[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / power / cpu.c

/*
 * Suspend support specific for i386/x86-64.
 *
 * Distribute under GPLv2
 *
 * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
 * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
 */

#include <linux/suspend.h>
#include <linux/export.h>
#include <linux/smp.h>
#include <linux/perf_event.h>

#include <asm/pgtable.h>
#include <asm/proto.h>
#include <asm/mtrr.h>
#include <asm/page.h>
#include <asm/mce.h>
#include <asm/xcr.h>
#include <asm/suspend.h>
#include <asm/debugreg.h>
#include <asm/fpu-internal.h> /* pcntxt_mask */
#include <asm/cpu.h>

#ifdef CONFIG_X86_32
unsigned long saved_context_ebx;
unsigned long saved_context_esp, saved_context_ebp;
unsigned long saved_context_esi, saved_context_edi;
unsigned long saved_context_eflags;
#endif
struct saved_context saved_context;

/**
 *	__save_processor_state - save CPU registers before creating a
 *		hibernation image and before restoring the memory state from it
 *	@ctxt - structure to store the registers contents in
 *
 *	NOTE: If there is a CPU register the modification of which by the
 *	boot kernel (ie. the kernel used for loading the hibernation image)
 *	might affect the operations of the restored target kernel (ie. the one
 *	saved in the hibernation image), then its contents must be saved by this
 *	function.  In other words, if kernel A is hibernated and different
 *	kernel B is used for loading the hibernation image into memory, the
 *	kernel A's __save_processor_state() function must save all registers
 *	needed by kernel A, so that it can operate correctly after the resume
 *	regardless of what kernel B does in the meantime.
 */
static void __save_processor_state(struct saved_context *ctxt)
{
#ifdef CONFIG_X86_32
	mtrr_save_fixed_ranges(NULL);
#endif
	kernel_fpu_begin();

	/*
	 * descriptor tables
	 */
#ifdef CONFIG_X86_32
	store_idt(&ctxt->idt);
#else
/* CONFIG_X86_64 */
	store_idt((struct desc_ptr *)&ctxt->idt_limit);
#endif
	/*
	 * We save it here, but restore it only in the hibernate case.
	 * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit
	 * mode in "secondary_startup_64". In 32-bit mode it is done via
	 * 'pmode_gdt' in wakeup_start.
	 */
	ctxt->gdt_desc.size = GDT_SIZE - 1;
	ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_table(smp_processor_id());

	store_tr(ctxt->tr);

	/* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
	/*
	 * segment registers
	 */
#ifdef CONFIG_X86_32
	savesegment(es, ctxt->es);
	savesegment(fs, ctxt->fs);
	savesegment(gs, ctxt->gs);
	savesegment(ss, ctxt->ss);
#else
/* CONFIG_X86_64 */
	asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
	asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
	asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
	asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
	asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));

	rdmsrl(MSR_FS_BASE, ctxt->fs_base);
	rdmsrl(MSR_GS_BASE, ctxt->gs_base);
	rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
	mtrr_save_fixed_ranges(NULL);

	rdmsrl(MSR_EFER, ctxt->efer);
#endif

	/*
	 * control registers
	 */
	ctxt->cr0 = read_cr0();
	ctxt->cr2 = read_cr2();
	ctxt->cr3 = read_cr3();
#ifdef CONFIG_X86_32
	ctxt->cr4 = read_cr4_safe();
#else
/* CONFIG_X86_64 */
	ctxt->cr4 = read_cr4();
	ctxt->cr8 = read_cr8();
#endif
	ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
					       &ctxt->misc_enable);
}

/* Needed by apm.c */
void save_processor_state(void)
{
	__save_processor_state(&saved_context);
	x86_platform.save_sched_clock_state();
}
EXPORT_SYMBOL(save_processor_state);

static void do_fpu_end(void)
{
	/*
	 * Restore FPU regs if necessary.
	 */
	kernel_fpu_end();
}

static void fix_processor_context(void)
{
	int cpu = smp_processor_id();
	struct tss_struct *t = &per_cpu(init_tss, cpu);
#ifdef CONFIG_X86_64
	struct desc_struct *desc = get_cpu_gdt_table(cpu);
	tss_desc tss;
#endif
	set_tss_desc(cpu, t);	/*
				 * This just modifies memory; should not be
				 * necessary. But... This is necessary, because
				 * 386 hardware has concept of busy TSS or some
				 * similar stupidity.
				 */

#ifdef CONFIG_X86_64
	memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
	tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */
	write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS);

	syscall_init();				/* This sets MSR_*STAR and related */
#endif
	load_TR_desc();				/* This does ltr */
	load_LDT(&current->active_mm->context);	/* This does lldt */
}

/**
 *	__restore_processor_state - restore the contents of CPU registers saved
 *		by __save_processor_state()
 *	@ctxt - structure to load the registers contents from
 */
static void __restore_processor_state(struct saved_context *ctxt)
{
	if (ctxt->misc_enable_saved)
		wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
	/*
	 * control registers
	 */
	/* cr4 was introduced in the Pentium CPU */
#ifdef CONFIG_X86_32
	if (ctxt->cr4)
		write_cr4(ctxt->cr4);
#else
/* CONFIG X86_64 */
	wrmsrl(MSR_EFER, ctxt->efer);
	write_cr8(ctxt->cr8);
	write_cr4(ctxt->cr4);
#endif
	write_cr3(ctxt->cr3);
	write_cr2(ctxt->cr2);
	write_cr0(ctxt->cr0);

	/*
	 * now restore the descriptor tables to their proper values
	 * ltr is done i fix_processor_context().
	 */
#ifdef CONFIG_X86_32
	load_idt(&ctxt->idt);
#else
/* CONFIG_X86_64 */
	load_idt((const struct desc_ptr *)&ctxt->idt_limit);
#endif

	/*
	 * segment registers
	 */
#ifdef CONFIG_X86_32
	loadsegment(es, ctxt->es);
	loadsegment(fs, ctxt->fs);
	loadsegment(gs, ctxt->gs);
	loadsegment(ss, ctxt->ss);

	/*
	 * sysenter MSRs
	 */
	if (boot_cpu_has(X86_FEATURE_SEP))
		enable_sep_cpu();
#else
/* CONFIG_X86_64 */
	asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
	asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
	asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
	load_gs_index(ctxt->gs);
	asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));

	wrmsrl(MSR_FS_BASE, ctxt->fs_base);
	wrmsrl(MSR_GS_BASE, ctxt->gs_base);
	wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
#endif

	/*
	 * restore XCR0 for xsave capable cpu's.
	 */
	if (cpu_has_xsave)
		xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask);

	fix_processor_context();

	do_fpu_end();
	x86_platform.restore_sched_clock_state();
	mtrr_bp_restore();
	perf_restore_debug_store();
}

/* Needed by apm.c */
void restore_processor_state(void)
{
	__restore_processor_state(&saved_context);
}
#ifdef CONFIG_X86_32
EXPORT_SYMBOL(restore_processor_state);
#endif

/*
 * When bsp_check() is called in hibernate and suspend, cpu hotplug
 * is disabled already. So it's unnessary to handle race condition between
 * cpumask query and cpu hotplug.
 */
static int bsp_check(void)
{
	if (cpumask_first(cpu_online_mask) != 0) {
		pr_warn("CPU0 is offline.\n");
		return -ENODEV;
	}

	return 0;
}

static int bsp_pm_callback(struct notifier_block *nb, unsigned long action,
			   void *ptr)
{
	int ret = 0;

	switch (action) {
	case PM_SUSPEND_PREPARE:
	case PM_HIBERNATION_PREPARE:
		ret = bsp_check();
		break;
#ifdef CONFIG_DEBUG_HOTPLUG_CPU0
	case PM_RESTORE_PREPARE:
		/*
		 * When system resumes from hibernation, online CPU0 because
		 * 1. it's required for resume and
		 * 2. the CPU was online before hibernation
		 */
		if (!cpu_online(0))
			_debug_hotplug_cpu(0, 1);
		break;
	case PM_POST_RESTORE:
		/*
		 * When a resume really happens, this code won't be called.
		 *
		 * This code is called only when user space hibernation software
		 * prepares for snapshot device during boot time. So we just
		 * call _debug_hotplug_cpu() to restore to CPU0's state prior to
		 * preparing the snapshot device.
		 *
		 * This works for normal boot case in our CPU0 hotplug debug
		 * mode, i.e. CPU0 is offline and user mode hibernation
		 * software initializes during boot time.
		 *
		 * If CPU0 is online and user application accesses snapshot
		 * device after boot time, this will offline CPU0 and user may
		 * see different CPU0 state before and after accessing
		 * the snapshot device. But hopefully this is not a case when
		 * user debugging CPU0 hotplug. Even if users hit this case,
		 * they can easily online CPU0 back.
		 *
		 * To simplify this debug code, we only consider normal boot
		 * case. Otherwise we need to remember CPU0's state and restore
		 * to that state and resolve racy conditions etc.
		 */
		_debug_hotplug_cpu(0, 0);
		break;
#endif
	default:
		break;
	}
	return notifier_from_errno(ret);
}

static int __init bsp_pm_check_init(void)
{
	/*
	 * Set this bsp_pm_callback as lower priority than
	 * cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called
	 * earlier to disable cpu hotplug before bsp online check.
	 */
	pm_notifier(bsp_pm_callback, -INT_MAX);
	return 0;
}

core_initcall(bsp_pm_check_init);
Commit	Line	Data
1da177e4	1	/*
6d48becd	2	* Suspend support specific for i386/x86-64.
1da177e4 LT	3	*
	4	* Distribute under GPLv2
	5	*
cf7700fe	6	* Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
a2531293	7	* Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
1da177e4 LT	8	* Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
	9	*/
	10
1da177e4	11	#include <linux/suspend.h>
69c60c88	12	#include <linux/export.h>
f6783d20	13	#include <linux/smp.h>
1d9d8639	14	#include <linux/perf_event.h>
f6783d20	15
3dd08325	16	#include <asm/pgtable.h>
f6783d20	17	#include <asm/proto.h>
3ebad590	18	#include <asm/mtrr.h>
f6783d20 SL	19	#include <asm/page.h>
f6783d20 SL	20	#include <asm/mce.h>
83b8e28b	21	#include <asm/xcr.h>
a8af7898	22	#include <asm/suspend.h>
1e350066	23	#include <asm/debugreg.h>
1361b83a	24	#include <asm/fpu-internal.h> /* pcntxt_mask */
a71c8bc5	25	#include <asm/cpu.h>
1da177e4	26
833b2ca0	27	#ifdef CONFIG_X86_32
833b2ca0 SL	28	unsigned long saved_context_ebx;
	29	unsigned long saved_context_esp, saved_context_ebp;
	30	unsigned long saved_context_esi, saved_context_edi;
	31	unsigned long saved_context_eflags;
833b2ca0	32	#endif
cc456c4e	33	struct saved_context saved_context;
1da177e4	34
5c9c9bec RW	35	/**
	36	* __save_processor_state - save CPU registers before creating a
	37	* hibernation image and before restoring the memory state from it
	38	* @ctxt - structure to store the registers contents in
	39	*
	40	* NOTE: If there is a CPU register the modification of which by the
	41	* boot kernel (ie. the kernel used for loading the hibernation image)
	42	* might affect the operations of the restored target kernel (ie. the one
	43	* saved in the hibernation image), then its contents must be saved by this
	44	* function. In other words, if kernel A is hibernated and different
	45	* kernel B is used for loading the hibernation image into memory, the
	46	* kernel A's __save_processor_state() function must save all registers
	47	* needed by kernel A, so that it can operate correctly after the resume
	48	* regardless of what kernel B does in the meantime.
	49	*/
cae45957	50	static void __save_processor_state(struct saved_context *ctxt)
1da177e4	51	{
f9ebbe53 SL	52	#ifdef CONFIG_X86_32
	53	mtrr_save_fixed_ranges(NULL);
	54	#endif
1da177e4 LT	55	kernel_fpu_begin();
	56
	57	/*
	58	* descriptor tables
	59	*/
f9ebbe53	60	#ifdef CONFIG_X86_32
f9ebbe53 SL	61	store_idt(&ctxt->idt);
	62	#else
	63	/* CONFIG_X86_64 */
9d1c6e7c	64	store_idt((struct desc_ptr *)&ctxt->idt_limit);
f9ebbe53	65	#endif
cc456c4e KRW	66	/*
	67	* We save it here, but restore it only in the hibernate case.
	68	* For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit
	69	* mode in "secondary_startup_64". In 32-bit mode it is done via
	70	* 'pmode_gdt' in wakeup_start.
	71	*/
	72	ctxt->gdt_desc.size = GDT_SIZE - 1;
	73	ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_table(smp_processor_id());
	74
9d1c6e7c	75	store_tr(ctxt->tr);
1da177e4 LT	76
1da177e4 LT	77	/* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
1da177e4 LT	78	/*
	79	* segment registers
	80	*/
f9ebbe53 SL	81	#ifdef CONFIG_X86_32
	82	savesegment(es, ctxt->es);
	83	savesegment(fs, ctxt->fs);
	84	savesegment(gs, ctxt->gs);
	85	savesegment(ss, ctxt->ss);
	86	#else
	87	/* CONFIG_X86_64 */
1da177e4 LT	88	asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
	89	asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
	90	asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
	91	asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
	92	asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
	93
	94	rdmsrl(MSR_FS_BASE, ctxt->fs_base);
	95	rdmsrl(MSR_GS_BASE, ctxt->gs_base);
	96	rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
3ebad590	97	mtrr_save_fixed_ranges(NULL);
1da177e4	98
f9ebbe53 SL	99	rdmsrl(MSR_EFER, ctxt->efer);
	100	#endif
	101
1da177e4	102	/*
cf7700fe	103	* control registers
1da177e4	104	*/
f51c9452 GOC	105	ctxt->cr0 = read_cr0();
	106	ctxt->cr2 = read_cr2();
	107	ctxt->cr3 = read_cr3();
f9ebbe53 SL	108	#ifdef CONFIG_X86_32
	109	ctxt->cr4 = read_cr4_safe();
	110	#else
	111	/* CONFIG_X86_64 */
f51c9452 GOC	112	ctxt->cr4 = read_cr4();
f51c9452 GOC	113	ctxt->cr8 = read_cr8();
f9ebbe53	114	#endif
85a0e753 OZ	115	ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
85a0e753 OZ	116	&ctxt->misc_enable);
1da177e4 LT	117	}
1da177e4 LT	118
f9ebbe53	119	/* Needed by apm.c */
1da177e4 LT	120	void save_processor_state(void)
	121	{
	122	__save_processor_state(&saved_context);
b74f05d6	123	x86_platform.save_sched_clock_state();
1da177e4	124	}
f9ebbe53	125	EXPORT_SYMBOL(save_processor_state);
1da177e4	126
08967f94	127	static void do_fpu_end(void)
1da177e4	128	{
08967f94	129	/*
3134d04b	130	* Restore FPU regs if necessary.
08967f94 SL	131	*/
08967f94 SL	132	kernel_fpu_end();
1da177e4 LT	133	}
1da177e4 LT	134
3134d04b SL	135	static void fix_processor_context(void)
	136	{
	137	int cpu = smp_processor_id();
	138	struct tss_struct *t = &per_cpu(init_tss, cpu);
4d681be3	139	#ifdef CONFIG_X86_64
	140	struct desc_struct *desc = get_cpu_gdt_table(cpu);
	141	tss_desc tss;
	142	#endif
3134d04b SL	143	set_tss_desc(cpu, t); /*
	144	* This just modifies memory; should not be
	145	* necessary. But... This is necessary, because
	146	* 386 hardware has concept of busy TSS or some
	147	* similar stupidity.
	148	*/
	149
	150	#ifdef CONFIG_X86_64
4d681be3	151	memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
	152	tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */
	153	write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS);
3134d04b SL	154
	155	syscall_init(); /* This sets MSR_STAR and related /
	156	#endif
	157	load_TR_desc(); /* This does ltr */
	158	load_LDT(&current->active_mm->context); /* This does lldt */
3134d04b SL	159	}
3134d04b SL	160
5c9c9bec RW	161	/**
	162	* __restore_processor_state - restore the contents of CPU registers saved
	163	* by __save_processor_state()
	164	* @ctxt - structure to load the registers contents from
	165	*/
cae45957	166	static void __restore_processor_state(struct saved_context *ctxt)
1da177e4	167	{
85a0e753 OZ	168	if (ctxt->misc_enable_saved)
85a0e753 OZ	169	wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
1da177e4 LT	170	/*
	171	* control registers
	172	*/
3134d04b SL	173	/* cr4 was introduced in the Pentium CPU */
	174	#ifdef CONFIG_X86_32
	175	if (ctxt->cr4)
	176	write_cr4(ctxt->cr4);
	177	#else
	178	/* CONFIG X86_64 */
3c321bce	179	wrmsrl(MSR_EFER, ctxt->efer);
f51c9452 GOC	180	write_cr8(ctxt->cr8);
f51c9452 GOC	181	write_cr4(ctxt->cr4);
3134d04b	182	#endif
f51c9452 GOC	183	write_cr3(ctxt->cr3);
	184	write_cr2(ctxt->cr2);
	185	write_cr0(ctxt->cr0);
1da177e4	186
8d783b3e PM	187	/*
	188	* now restore the descriptor tables to their proper values
	189	* ltr is done i fix_processor_context().
	190	*/
3134d04b	191	#ifdef CONFIG_X86_32
3134d04b SL	192	load_idt(&ctxt->idt);
	193	#else
	194	/* CONFIG_X86_64 */
9d1c6e7c	195	load_idt((const struct desc_ptr *)&ctxt->idt_limit);
3134d04b	196	#endif
8d783b3e	197
1da177e4 LT	198	/*
	199	* segment registers
	200	*/
3134d04b SL	201	#ifdef CONFIG_X86_32
	202	loadsegment(es, ctxt->es);
	203	loadsegment(fs, ctxt->fs);
	204	loadsegment(gs, ctxt->gs);
	205	loadsegment(ss, ctxt->ss);
	206
	207	/*
	208	* sysenter MSRs
	209	*/
	210	if (boot_cpu_has(X86_FEATURE_SEP))
	211	enable_sep_cpu();
	212	#else
	213	/* CONFIG_X86_64 */
1da177e4 LT	214	asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
	215	asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
	216	asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
	217	load_gs_index(ctxt->gs);
	218	asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
	219
	220	wrmsrl(MSR_FS_BASE, ctxt->fs_base);
	221	wrmsrl(MSR_GS_BASE, ctxt->gs_base);
	222	wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
3134d04b	223	#endif
1da177e4	224
83b8e28b SS	225	/*
	226	* restore XCR0 for xsave capable cpu's.
	227	*/
	228	if (cpu_has_xsave)
	229	xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask);
	230
1da177e4 LT	231	fix_processor_context();
	232
	233	do_fpu_end();
dba69d10	234	x86_platform.restore_sched_clock_state();
d0af9eed	235	mtrr_bp_restore();
1d9d8639	236	perf_restore_debug_store();
1da177e4 LT	237	}
1da177e4 LT	238
3134d04b	239	/* Needed by apm.c */
1da177e4 LT	240	void restore_processor_state(void)
	241	{
	242	__restore_processor_state(&saved_context);
	243	}
3134d04b SL	244	#ifdef CONFIG_X86_32
	245	EXPORT_SYMBOL(restore_processor_state);
	246	#endif
209efae1 FY	247
	248	/*
	249	* When bsp_check() is called in hibernate and suspend, cpu hotplug
	250	* is disabled already. So it's unnessary to handle race condition between
	251	* cpumask query and cpu hotplug.
	252	*/
	253	static int bsp_check(void)
	254	{
	255	if (cpumask_first(cpu_online_mask) != 0) {
	256	pr_warn("CPU0 is offline.\n");
	257	return -ENODEV;
	258	}
	259
	260	return 0;
	261	}
	262
	263	static int bsp_pm_callback(struct notifier_block *nb, unsigned long action,
	264	void *ptr)
	265	{
	266	int ret = 0;
	267
	268	switch (action) {
	269	case PM_SUSPEND_PREPARE:
	270	case PM_HIBERNATION_PREPARE:
	271	ret = bsp_check();
	272	break;
a71c8bc5 FY	273	#ifdef CONFIG_DEBUG_HOTPLUG_CPU0
	274	case PM_RESTORE_PREPARE:
	275	/*
	276	* When system resumes from hibernation, online CPU0 because
	277	* 1. it's required for resume and
	278	* 2. the CPU was online before hibernation
	279	*/
	280	if (!cpu_online(0))
	281	_debug_hotplug_cpu(0, 1);
	282	break;
	283	case PM_POST_RESTORE:
	284	/*
	285	* When a resume really happens, this code won't be called.
	286	*
	287	* This code is called only when user space hibernation software
	288	* prepares for snapshot device during boot time. So we just
	289	* call _debug_hotplug_cpu() to restore to CPU0's state prior to
	290	* preparing the snapshot device.
	291	*
	292	* This works for normal boot case in our CPU0 hotplug debug
	293	* mode, i.e. CPU0 is offline and user mode hibernation
	294	* software initializes during boot time.
	295	*
	296	* If CPU0 is online and user application accesses snapshot
	297	* device after boot time, this will offline CPU0 and user may
	298	* see different CPU0 state before and after accessing
	299	* the snapshot device. But hopefully this is not a case when
	300	* user debugging CPU0 hotplug. Even if users hit this case,
	301	* they can easily online CPU0 back.
	302	*
	303	* To simplify this debug code, we only consider normal boot
	304	* case. Otherwise we need to remember CPU0's state and restore
	305	* to that state and resolve racy conditions etc.
	306	*/
	307	_debug_hotplug_cpu(0, 0);
	308	break;
	309	#endif
209efae1 FY	310	default:
	311	break;
	312	}
	313	return notifier_from_errno(ret);
	314	}
	315
	316	static int __init bsp_pm_check_init(void)
	317	{
	318	/*
	319	* Set this bsp_pm_callback as lower priority than
	320	* cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called
	321	* earlier to disable cpu hotplug before bsp online check.
	322	*/
	323	pm_notifier(bsp_pm_callback, -INT_MAX);
	324	return 0;
	325	}
	326
	327	core_initcall(bsp_pm_check_init);