[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / platform / ce4100 / falconfalls.dts

/*
 * CE4100 on Falcon Falls
 *
 * (c) Copyright 2010 Intel Corporation
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; version 2 of the License.
 */
/dts-v1/;
/ {
	model = "intel,falconfalls";
	compatible = "intel,falconfalls";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "intel,ce4100";
			reg = <0>;
			lapic = <&lapic0>;
		};
	};

	soc@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "intel,ce4100-cp";
		ranges;

		ioapic1: interrupt-controller@fec00000 {
			#interrupt-cells = <2>;
			compatible = "intel,ce4100-ioapic";
			interrupt-controller;
			reg = <0xfec00000 0x1000>;
		};

		timer@fed00000 {
			compatible = "intel,ce4100-hpet";
			reg = <0xfed00000 0x200>;
		};

		lapic0: interrupt-controller@fee00000 {
			compatible = "intel,ce4100-lapic";
			reg = <0xfee00000 0x1000>;
		};

		pci@3fc {
			#address-cells = <3>;
			#size-cells = <2>;
			compatible = "intel,ce4100-pci", "pci";
			device_type = "pci";
			bus-range = <0 0>;
			ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000
				  0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000
				  0x0000000 0 0x0	 0x0	    0 0x100>;

			/* Secondary IO-APIC */
			ioapic2: interrupt-controller@0,1 {
				#interrupt-cells = <2>;
				compatible = "intel,ce4100-ioapic";
				interrupt-controller;
				reg = <0x100 0x0 0x0 0x0 0x0>;
				assigned-addresses = <0x02000000 0x0 0xbffff000 0x0 0x1000>;
			};

			pci@1,0 {
				#address-cells = <3>;
				#size-cells = <2>;
				compatible = "intel,ce4100-pci", "pci";
				device_type = "pci";
				bus-range = <1 1>;
				reg = <0x0800 0x0 0x0 0x0 0x0>;
				ranges = <0x2000000 0 0xdffe0000 0x2000000 0 0xdffe0000 0 0x1000>;

				interrupt-parent = <&ioapic2>;

				display@2,0 {
					compatible = "pci8086,2e5b.2",
						   "pci8086,2e5b",
						   "pciclass038000",
						   "pciclass0380";

					reg = <0x11000 0x0 0x0 0x0 0x0>;
					interrupts = <0 1>;
				};

				multimedia@3,0 {
					compatible = "pci8086,2e5c.2",
						   "pci8086,2e5c",
						   "pciclass048000",
						   "pciclass0480";

					reg = <0x11800 0x0 0x0 0x0 0x0>;
					interrupts = <2 1>;
				};

				multimedia@4,0 {
					compatible = "pci8086,2e5d.2",
						   "pci8086,2e5d",
						   "pciclass048000",
						   "pciclass0480";

					reg = <0x12000 0x0 0x0 0x0 0x0>;
					interrupts = <4 1>;
				};

				multimedia@4,1 {
					compatible = "pci8086,2e5e.2",
						   "pci8086,2e5e",
						   "pciclass048000",
						   "pciclass0480";

					reg = <0x12100 0x0 0x0 0x0 0x0>;
					interrupts = <5 1>;
				};

				sound@6,0 {
					compatible = "pci8086,2e5f.2",
						   "pci8086,2e5f",
						   "pciclass040100",
						   "pciclass0401";

					reg = <0x13000 0x0 0x0 0x0 0x0>;
					interrupts = <6 1>;
				};

				sound@6,1 {
					compatible = "pci8086,2e5f.2",
						   "pci8086,2e5f",
						   "pciclass040100",
						   "pciclass0401";

					reg = <0x13100 0x0 0x0 0x0 0x0>;
					interrupts = <7 1>;
				};

				sound@6,2 {
					compatible = "pci8086,2e60.2",
						   "pci8086,2e60",
						   "pciclass040100",
						   "pciclass0401";

					reg = <0x13200 0x0 0x0 0x0 0x0>;
					interrupts = <8 1>;
				};

				display@8,0 {
					compatible = "pci8086,2e61.2",
						   "pci8086,2e61",
						   "pciclass038000",
						   "pciclass0380";

					reg = <0x14000 0x0 0x0 0x0 0x0>;
					interrupts = <9 1>;
				};

				display@8,1 {
					compatible = "pci8086,2e62.2",
						   "pci8086,2e62",
						   "pciclass038000",
						   "pciclass0380";

					reg = <0x14100 0x0 0x0 0x0 0x0>;
					interrupts = <10 1>;
				};

				multimedia@8,2 {
					compatible = "pci8086,2e63.2",
						   "pci8086,2e63",
						   "pciclass048000",
						   "pciclass0480";

					reg = <0x14200 0x0 0x0 0x0 0x0>;
					interrupts = <11 1>;
				};

				entertainment-encryption@9,0 {
					compatible = "pci8086,2e64.2",
						   "pci8086,2e64",
						   "pciclass101000",
						   "pciclass1010";

					reg = <0x14800 0x0 0x0 0x0 0x0>;
					interrupts = <12 1>;
				};

				localbus@a,0 {
					compatible = "pci8086,2e65.2",
						   "pci8086,2e65",
						   "pciclassff0000",
						   "pciclassff00";

					reg = <0x15000 0x0 0x0 0x0 0x0>;
				};

				serial@b,0 {
					compatible = "pci8086,2e66.2",
						   "pci8086,2e66",
						   "pciclass070003",
						   "pciclass0700";

					reg = <0x15800 0x0 0x0 0x0 0x0>;
					interrupts = <14 1>;
				};

				gpio@b,1 {
					compatible = "pci8086,2e67.2",
						   "pci8086,2e67",
						   "pciclassff0000",
						   "pciclassff00";

					#gpio-cells = <2>;
					reg = <0x15900 0x0 0x0 0x0 0x0>;
					interrupts = <15 1>;
					gpio-controller;
				};

				i2c-controller@b,2 {
					#address-cells = <2>;
					#size-cells = <1>;
					compatible = "pci8086,2e68.2",
						   "pci8086,2e68",
						   "pciclass,ff0000",
						   "pciclass,ff00";

					reg = <0x15a00 0x0 0x0 0x0 0x0>;
					interrupts = <16 1>;
					ranges = <0 0	0x02000000 0 0xdffe0500	0x100
						  1 0	0x02000000 0 0xdffe0600	0x100
						  2 0	0x02000000 0 0xdffe0700	0x100>;

					i2c@0 {
						#address-cells = <1>;
						#size-cells = <0>;
						compatible = "intel,ce4100-i2c-controller";
						reg = <0 0 0x100>;
					};

					i2c@1 {
						#address-cells = <1>;
						#size-cells = <0>;
						compatible = "intel,ce4100-i2c-controller";
						reg = <1 0 0x100>;

						gpio@26 {
							#gpio-cells = <2>;
							compatible = "ti,pcf8575";
							reg = <0x26>;
							gpio-controller;
						};
					};

					i2c@2 {
						#address-cells = <1>;
						#size-cells = <0>;
						compatible = "intel,ce4100-i2c-controller";
						reg = <2 0 0x100>;

						gpio@26 {
							#gpio-cells = <2>;
							compatible = "ti,pcf8575";
							reg = <0x26>;
							gpio-controller;
						};
					};
				};

				smard-card@b,3 {
					compatible = "pci8086,2e69.2",
						   "pci8086,2e69",
						   "pciclass070500",
						   "pciclass0705";

					reg = <0x15b00 0x0 0x0 0x0 0x0>;
					interrupts = <15 1>;
				};

				spi-controller@b,4 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible =
						"pci8086,2e6a.2",
						"pci8086,2e6a",
						"pciclass,ff0000",
						"pciclass,ff00";

					reg = <0x15c00 0x0 0x0 0x0 0x0>;
					interrupts = <15 1>;

					dac@0 {
						compatible = "ti,pcm1755";
						reg = <0>;
						spi-max-frequency = <115200>;
					};

					dac@1 {
						compatible = "ti,pcm1609a";
						reg = <1>;
						spi-max-frequency = <115200>;
					};

					eeprom@2 {
						compatible = "atmel,at93c46";
						reg = <2>;
						spi-max-frequency = <115200>;
					};
				};

				multimedia@b,7 {
					compatible = "pci8086,2e6d.2",
						   "pci8086,2e6d",
						   "pciclassff0000",
						   "pciclassff00";

					reg = <0x15f00 0x0 0x0 0x0 0x0>;
				};

				ethernet@c,0 {
					compatible = "pci8086,2e6e.2",
						   "pci8086,2e6e",
						   "pciclass020000",
						   "pciclass0200";

					reg = <0x16000 0x0 0x0 0x0 0x0>;
					interrupts = <21 1>;
				};

				clock@c,1 {
					compatible = "pci8086,2e6f.2",
						   "pci8086,2e6f",
						   "pciclassff0000",
						   "pciclassff00";

					reg = <0x16100 0x0 0x0 0x0 0x0>;
					interrupts = <3 1>;
				};

				usb@d,0 {
					compatible = "pci8086,2e70.2",
						   "pci8086,2e70",
						   "pciclass0c0320",
						   "pciclass0c03";

					reg = <0x16800 0x0 0x0 0x0 0x0>;
					interrupts = <22 1>;
				};

				usb@d,1 {
					compatible = "pci8086,2e70.2",
						   "pci8086,2e70",
						   "pciclass0c0320",
						   "pciclass0c03";

					reg = <0x16900 0x0 0x0 0x0 0x0>;
					interrupts = <22 1>;
				};

				sata@e,0 {
					compatible = "pci8086,2e71.0",
						   "pci8086,2e71",
						   "pciclass010601",
						   "pciclass0106";

					reg = <0x17000 0x0 0x0 0x0 0x0>;
					interrupts = <23 1>;
				};

				flash@f,0 {
					compatible = "pci8086,701.1",
						   "pci8086,701",
						   "pciclass050100",
						   "pciclass0501";

					reg = <0x17800 0x0 0x0 0x0 0x0>;
					interrupts = <13 1>;
				};

				entertainment-encryption@10,0 {
					compatible = "pci8086,702.1",
						   "pci8086,702",
						   "pciclass101000",
						   "pciclass1010";

					reg = <0x18000 0x0 0x0 0x0 0x0>;
				};

				co-processor@11,0 {
					compatible = "pci8086,703.1",
						   "pci8086,703",
						   "pciclass0b4000",
						   "pciclass0b40";

					reg = <0x18800 0x0 0x0 0x0 0x0>;
					interrupts = <1 1>;
				};

				multimedia@12,0 {
					compatible = "pci8086,704.0",
						   "pci8086,704",
						   "pciclass048000",
						   "pciclass0480";

					reg = <0x19000 0x0 0x0 0x0 0x0>;
				};
			};

			isa@1f,0 {
				#address-cells = <2>;
				#size-cells = <1>;
				compatible = "isa";
				reg = <0xf800 0x0 0x0 0x0 0x0>;
				ranges = <1 0 0 0 0 0x100>;

				rtc@70 {
					compatible = "intel,ce4100-rtc", "motorola,mc146818";
					interrupts = <8 3>;
					interrupt-parent = <&ioapic1>;
					ctrl-reg = <2>;
					freq-reg = <0x26>;
					reg = <1 0x70 2>;
				};
			};
		};
	};
};
Commit	Line	Data
df2634f4 SAS	1	/*
	2	* CE4100 on Falcon Falls
	3	*
	4	* (c) Copyright 2010 Intel Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; version 2 of the License.
	9	*/
	10	/dts-v1/;
	11	/ {
	12	model = "intel,falconfalls";
	13	compatible = "intel,falconfalls";
	14	#address-cells = <1>;
	15	#size-cells = <1>;
	16
	17	cpus {
	18	#address-cells = <1>;
	19	#size-cells = <0>;
	20
	21	cpu@0 {
	22	device_type = "cpu";
	23	compatible = "intel,ce4100";
	24	reg = <0>;
	25	lapic = <&lapic0>;
	26	};
	27	};
	28
	29	soc@0 {
	30	#address-cells = <1>;
	31	#size-cells = <1>;
	32	compatible = "intel,ce4100-cp";
	33	ranges;
	34
	35	ioapic1: interrupt-controller@fec00000 {
	36	#interrupt-cells = <2>;
	37	compatible = "intel,ce4100-ioapic";
	38	interrupt-controller;
	39	reg = <0xfec00000 0x1000>;
	40	};
	41
	42	timer@fed00000 {
	43	compatible = "intel,ce4100-hpet";
	44	reg = <0xfed00000 0x200>;
	45	};
	46
	47	lapic0: interrupt-controller@fee00000 {
	48	compatible = "intel,ce4100-lapic";
	49	reg = <0xfee00000 0x1000>;
	50	};
	51
	52	pci@3fc {
	53	#address-cells = <3>;
	54	#size-cells = <2>;
	55	compatible = "intel,ce4100-pci", "pci";
	56	device_type = "pci";
	57	bus-range = <0 0>;
	58	ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000
	59	0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000
	60	0x0000000 0 0x0 0x0 0 0x100>;
	61
	62	/* Secondary IO-APIC */
	63	ioapic2: interrupt-controller@0,1 {
	64	#interrupt-cells = <2>;
65	compatible = "intel,ce4100-ioapic";
66	interrupt-controller;
67	reg = <0x100 0x0 0x0 0x0 0x0>;
68	assigned-addresses = <0x02000000 0x0 0xbffff000 0x0 0x1000>;
69	};
70
71	pci@1,0 {
72	#address-cells = <3>;
73	#size-cells = <2>;
74	compatible = "intel,ce4100-pci", "pci";
75	device_type = "pci";
76	bus-range = <1 1>;
30d746c6	77	reg = <0x0800 0x0 0x0 0x0 0x0>;
df2634f4 SAS	78	ranges = <0x2000000 0 0xdffe0000 0x2000000 0 0xdffe0000 0 0x1000>;
	79
	80	interrupt-parent = <&ioapic2>;
	81
	82	display@2,0 {
	83	compatible = "pci8086,2e5b.2",
	84	"pci8086,2e5b",
	85	"pciclass038000",
	86	"pciclass0380";
	87
	88	reg = <0x11000 0x0 0x0 0x0 0x0>;
	89	interrupts = <0 1>;
	90	};
	91
	92	multimedia@3,0 {
	93	compatible = "pci8086,2e5c.2",
	94	"pci8086,2e5c",
	95	"pciclass048000",
	96	"pciclass0480";
	97
	98	reg = <0x11800 0x0 0x0 0x0 0x0>;
	99	interrupts = <2 1>;
	100	};
	101
	102	multimedia@4,0 {
	103	compatible = "pci8086,2e5d.2",
	104	"pci8086,2e5d",
	105	"pciclass048000",
	106	"pciclass0480";
	107
	108	reg = <0x12000 0x0 0x0 0x0 0x0>;
	109	interrupts = <4 1>;
	110	};
	111
	112	multimedia@4,1 {
	113	compatible = "pci8086,2e5e.2",
	114	"pci8086,2e5e",
	115	"pciclass048000",
	116	"pciclass0480";
	117
	118	reg = <0x12100 0x0 0x0 0x0 0x0>;
	119	interrupts = <5 1>;
	120	};
	121
	122	sound@6,0 {
	123	compatible = "pci8086,2e5f.2",
	124	"pci8086,2e5f",
	125	"pciclass040100",
	126	"pciclass0401";
	127
	128	reg = <0x13000 0x0 0x0 0x0 0x0>;
	129	interrupts = <6 1>;
	130	};
	131
	132	sound@6,1 {
	133	compatible = "pci8086,2e5f.2",
	134	"pci8086,2e5f",
	135	"pciclass040100",
	136	"pciclass0401";
	137
	138	reg = <0x13100 0x0 0x0 0x0 0x0>;
	139	interrupts = <7 1>;
	140	};
	141
142	sound@6,2 {
143	compatible = "pci8086,2e60.2",
144	"pci8086,2e60",
145	"pciclass040100",
146	"pciclass0401";
147
148	reg = <0x13200 0x0 0x0 0x0 0x0>;
149	interrupts = <8 1>;
150	};
151
152	display@8,0 {
153	compatible = "pci8086,2e61.2",
154	"pci8086,2e61",
155	"pciclass038000",
156	"pciclass0380";
157
158	reg = <0x14000 0x0 0x0 0x0 0x0>;
159	interrupts = <9 1>;
160	};
161
162	display@8,1 {
163	compatible = "pci8086,2e62.2",
164	"pci8086,2e62",
165	"pciclass038000",
166	"pciclass0380";
167
168	reg = <0x14100 0x0 0x0 0x0 0x0>;
169	interrupts = <10 1>;
170	};
171
172	multimedia@8,2 {
173	compatible = "pci8086,2e63.2",
174	"pci8086,2e63",
175	"pciclass048000",
176	"pciclass0480";
177
178	reg = <0x14200 0x0 0x0 0x0 0x0>;
179	interrupts = <11 1>;
180	};
181
182	entertainment-encryption@9,0 {
183	compatible = "pci8086,2e64.2",
184	"pci8086,2e64",
185	"pciclass101000",
186	"pciclass1010";
187
188	reg = <0x14800 0x0 0x0 0x0 0x0>;
189	interrupts = <12 1>;
190	};
191
192	localbus@a,0 {
193	compatible = "pci8086,2e65.2",
194	"pci8086,2e65",
195	"pciclassff0000",
196	"pciclassff00";
197
198	reg = <0x15000 0x0 0x0 0x0 0x0>;
199	};
200
201	serial@b,0 {
202	compatible = "pci8086,2e66.2",
203	"pci8086,2e66",
204	"pciclass070003",
205	"pciclass0700";
206
207	reg = <0x15800 0x0 0x0 0x0 0x0>;
208	interrupts = <14 1>;
209	};
210
211	gpio@b,1 {
212	compatible = "pci8086,2e67.2",
213	"pci8086,2e67",
214	"pciclassff0000",
215	"pciclassff00";
216
217	#gpio-cells = <2>;
218	reg = <0x15900 0x0 0x0 0x0 0x0>;
219	interrupts = <15 1>;
220	gpio-controller;
221	};
222
223	i2c-controller@b,2 {
224	#address-cells = <2>;
225	#size-cells = <1>;
226	compatible = "pci8086,2e68.2",
227	"pci8086,2e68",
228	"pciclass,ff0000",
229	"pciclass,ff00";
230
231	reg = <0x15a00 0x0 0x0 0x0 0x0>;
232	interrupts = <16 1>;
233	ranges = <0 0 0x02000000 0 0xdffe0500 0x100
234	1 0 0x02000000 0 0xdffe0600 0x100
235	2 0 0x02000000 0 0xdffe0700 0x100>;
236
237	i2c@0 {
238	#address-cells = <1>;
239	#size-cells = <0>;
240	compatible = "intel,ce4100-i2c-controller";
241	reg = <0 0 0x100>;
242	};
243
244	i2c@1 {
245	#address-cells = <1>;
246	#size-cells = <0>;
247	compatible = "intel,ce4100-i2c-controller";
248	reg = <1 0 0x100>;
249
250	gpio@26 {
251	#gpio-cells = <2>;
252	compatible = "ti,pcf8575";
253	reg = <0x26>;
254	gpio-controller;
255	};
256	};
257
258	i2c@2 {
259	#address-cells = <1>;
260	#size-cells = <0>;
261	compatible = "intel,ce4100-i2c-controller";
262	reg = <2 0 0x100>;
263
264	gpio@26 {
265	#gpio-cells = <2>;
266	compatible = "ti,pcf8575";
267	reg = <0x26>;
268	gpio-controller;
269	};
270	};
271	};
272
273	smard-card@b,3 {
274	compatible = "pci8086,2e69.2",
275	"pci8086,2e69",
276	"pciclass070500",
277	"pciclass0705";
278
279	reg = <0x15b00 0x0 0x0 0x0 0x0>;
280	interrupts = <15 1>;
281	};
282
283	spi-controller@b,4 {
284	#address-cells = <1>;
285	#size-cells = <0>;
286	compatible =
287	"pci8086,2e6a.2",
288	"pci8086,2e6a",
289	"pciclass,ff0000",
290	"pciclass,ff00";
291
292	reg = <0x15c00 0x0 0x0 0x0 0x0>;
293	interrupts = <15 1>;
294
295	dac@0 {
296	compatible = "ti,pcm1755";
297	reg = <0>;
298	spi-max-frequency = <115200>;
299	};
300
301	dac@1 {
302	compatible = "ti,pcm1609a";
303	reg = <1>;
304	spi-max-frequency = <115200>;
305	};
306
307	eeprom@2 {
308	compatible = "atmel,at93c46";
309	reg = <2>;
310	spi-max-frequency = <115200>;
311	};
312	};
313
314	multimedia@b,7 {
315	compatible = "pci8086,2e6d.2",
316	"pci8086,2e6d",
317	"pciclassff0000",
318	"pciclassff00";
319
320	reg = <0x15f00 0x0 0x0 0x0 0x0>;
321	};
322
323	ethernet@c,0 {
324	compatible = "pci8086,2e6e.2",
325	"pci8086,2e6e",
326	"pciclass020000",
327	"pciclass0200";
328
329	reg = <0x16000 0x0 0x0 0x0 0x0>;
330	interrupts = <21 1>;
331	};
332
333	clock@c,1 {
334	compatible = "pci8086,2e6f.2",
335	"pci8086,2e6f",
336	"pciclassff0000",
337	"pciclassff00";
338
339	reg = <0x16100 0x0 0x0 0x0 0x0>;
340	interrupts = <3 1>;
341	};
342
343	usb@d,0 {
344	compatible = "pci8086,2e70.2",
345	"pci8086,2e70",
346	"pciclass0c0320",
347	"pciclass0c03";
348
349	reg = <0x16800 0x0 0x0 0x0 0x0>;
1ff42c32	350	interrupts = <22 1>;
df2634f4 SAS	351	};
	352
	353	usb@d,1 {
	354	compatible = "pci8086,2e70.2",
	355	"pci8086,2e70",
	356	"pciclass0c0320",
	357	"pciclass0c03";
	358
	359	reg = <0x16900 0x0 0x0 0x0 0x0>;
1ff42c32	360	interrupts = <22 1>;
df2634f4 SAS	361	};
	362
	363	sata@e,0 {
	364	compatible = "pci8086,2e71.0",
	365	"pci8086,2e71",
	366	"pciclass010601",
	367	"pciclass0106";
	368
	369	reg = <0x17000 0x0 0x0 0x0 0x0>;
1ff42c32	370	interrupts = <23 1>;
df2634f4 SAS	371	};
	372
	373	flash@f,0 {
	374	compatible = "pci8086,701.1",
	375	"pci8086,701",
	376	"pciclass050100",
	377	"pciclass0501";
	378
	379	reg = <0x17800 0x0 0x0 0x0 0x0>;
	380	interrupts = <13 1>;
	381	};
	382
	383	entertainment-encryption@10,0 {
	384	compatible = "pci8086,702.1",
	385	"pci8086,702",
	386	"pciclass101000",
	387	"pciclass1010";
	388
	389	reg = <0x18000 0x0 0x0 0x0 0x0>;
	390	};
	391
	392	co-processor@11,0 {
	393	compatible = "pci8086,703.1",
	394	"pci8086,703",
	395	"pciclass0b4000",
	396	"pciclass0b40";
	397
	398	reg = <0x18800 0x0 0x0 0x0 0x0>;
	399	interrupts = <1 1>;
	400	};
	401
	402	multimedia@12,0 {
	403	compatible = "pci8086,704.0",
	404	"pci8086,704",
	405	"pciclass048000",
	406	"pciclass0480";
	407
	408	reg = <0x19000 0x0 0x0 0x0 0x0>;
	409	};
	410	};
	411
	412	isa@1f,0 {
	413	#address-cells = <2>;
	414	#size-cells = <1>;
	415	compatible = "isa";
30d746c6	416	reg = <0xf800 0x0 0x0 0x0 0x0>;
df2634f4 SAS	417	ranges = <1 0 0 0 0 0x100>;
	418
	419	rtc@70 {
	420	compatible = "intel,ce4100-rtc", "motorola,mc146818";
	421	interrupts = <8 3>;
	422	interrupt-parent = <&ioapic1>;
	423	ctrl-reg = <2>;
	424	freq-reg = <0x26>;
	425	reg = <1 0x70 2>;
	426	};
	427	};
	428	};
	429	};
	430	};