[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / pci / numaq_32.c

/*
 * numaq_32.c - Low-level PCI access for NUMA-Q machines
 */

#include <linux/pci.h>
#include <linux/init.h>
#include <linux/nodemask.h>
#include <asm/apic.h>
#include <asm/mpspec.h>
#include <asm/pci_x86.h>
#include <asm/numaq.h>

#define BUS2QUAD(global) (mp_bus_id_to_node[global])

#define BUS2LOCAL(global) (mp_bus_id_to_local[global])

#define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])

#define PCI_CONF1_MQ_ADDRESS(bus, devfn, reg) \
	(0x80000000 | (BUS2LOCAL(bus) << 16) | (devfn << 8) | (reg & ~3))

static void write_cf8(unsigned bus, unsigned devfn, unsigned reg)
{
	unsigned val = PCI_CONF1_MQ_ADDRESS(bus, devfn, reg);
	if (xquad_portio)
		writel(val, XQUAD_PORT_ADDR(0xcf8, BUS2QUAD(bus)));
	else
		outl(val, 0xCF8);
}

static int pci_conf1_mq_read(unsigned int seg, unsigned int bus,
			     unsigned int devfn, int reg, int len, u32 *value)
{
	unsigned long flags;
	void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));

	WARN_ON(seg);
	if (!value || (bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
		return -EINVAL;

	raw_spin_lock_irqsave(&pci_config_lock, flags);

	write_cf8(bus, devfn, reg);

	switch (len) {
	case 1:
		if (xquad_portio)
			*value = readb(adr + (reg & 3));
		else
			*value = inb(0xCFC + (reg & 3));
		break;
	case 2:
		if (xquad_portio)
			*value = readw(adr + (reg & 2));
		else
			*value = inw(0xCFC + (reg & 2));
		break;
	case 4:
		if (xquad_portio)
			*value = readl(adr);
		else
			*value = inl(0xCFC);
		break;
	}

	raw_spin_unlock_irqrestore(&pci_config_lock, flags);

	return 0;
}

static int pci_conf1_mq_write(unsigned int seg, unsigned int bus,
			      unsigned int devfn, int reg, int len, u32 value)
{
	unsigned long flags;
	void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));

	WARN_ON(seg);
	if ((bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255)) 
		return -EINVAL;

	raw_spin_lock_irqsave(&pci_config_lock, flags);

	write_cf8(bus, devfn, reg);

	switch (len) {
	case 1:
		if (xquad_portio)
			writeb(value, adr + (reg & 3));
		else
			outb((u8)value, 0xCFC + (reg & 3));
		break;
	case 2:
		if (xquad_portio)
			writew(value, adr + (reg & 2));
		else
			outw((u16)value, 0xCFC + (reg & 2));
		break;
	case 4:
		if (xquad_portio)
			writel(value, adr + reg);
		else
			outl((u32)value, 0xCFC);
		break;
	}

	raw_spin_unlock_irqrestore(&pci_config_lock, flags);

	return 0;
}

#undef PCI_CONF1_MQ_ADDRESS

static const struct pci_raw_ops pci_direct_conf1_mq = {
	.read	= pci_conf1_mq_read,
	.write	= pci_conf1_mq_write
};


static void pci_fixup_i450nx(struct pci_dev *d)
{
	/*
	 * i450NX -- Find and scan all secondary buses on all PXB's.
	 */
	int pxb, reg;
	u8 busno, suba, subb;
	int quad = BUS2QUAD(d->bus->number);

	dev_info(&d->dev, "searching for i450NX host bridges\n");
	reg = 0xd0;
	for(pxb=0; pxb<2; pxb++) {
		pci_read_config_byte(d, reg++, &busno);
		pci_read_config_byte(d, reg++, &suba);
		pci_read_config_byte(d, reg++, &subb);
		dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n",
			pxb, busno, suba, subb);
		if (busno) {
			/* Bus A */
			pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, busno));
		}
		if (suba < subb) {
			/* Bus B */
			pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, suba+1));
		}
	}
	pcibios_last_bus = -1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);

int __init pci_numaq_init(void)
{
	int quad;

	raw_pci_ops = &pci_direct_conf1_mq;

	pcibios_scan_root(0);
	if (num_online_nodes() > 1)
		for_each_online_node(quad) {
			if (quad == 0)
				continue;
			printk("Scanning PCI bus %d for quad %d\n", 
				QUADLOCAL2BUS(quad,0), quad);
			pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, 0));
		}
	return 0;
}
Commit	Line	Data
1da177e4	1	/*
e27cf3a2	2	* numaq_32.c - Low-level PCI access for NUMA-Q machines
1da177e4 LT	3	*/
	4
	5	#include <linux/pci.h>
	6	#include <linux/init.h>
	7	#include <linux/nodemask.h>
7b6aa335	8	#include <asm/apic.h>
d49c4288	9	#include <asm/mpspec.h>
82487711	10	#include <asm/pci_x86.h>
5c64c701	11	#include <asm/numaq.h>
c7e844f0	12
1da177e4	13	#define BUS2QUAD(global) (mp_bus_id_to_node[global])
e129cb49	14
1da177e4	15	#define BUS2LOCAL(global) (mp_bus_id_to_local[global])
6079d2d5	16
1da177e4 LT	17	#define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])
	18
	19	#define PCI_CONF1_MQ_ADDRESS(bus, devfn, reg) \
	20	(0x80000000 \| (BUS2LOCAL(bus) << 16) \| (devfn << 8) \| (reg & ~3))
	21
c7e844f0 AK	22	static void write_cf8(unsigned bus, unsigned devfn, unsigned reg)
	23	{
	24	unsigned val = PCI_CONF1_MQ_ADDRESS(bus, devfn, reg);
	25	if (xquad_portio)
	26	writel(val, XQUAD_PORT_ADDR(0xcf8, BUS2QUAD(bus)));
	27	else
	28	outl(val, 0xCF8);
	29	}
	30
1da177e4 LT	31	static int pci_conf1_mq_read(unsigned int seg, unsigned int bus,
	32	unsigned int devfn, int reg, int len, u32 *value)
	33	{
	34	unsigned long flags;
c7e844f0	35	void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
1da177e4	36
db34a363	37	WARN_ON(seg);
1da177e4 LT	38	if (!value \|\| (bus >= MAX_MP_BUSSES) \|\| (devfn > 255) \|\| (reg > 255))
	39	return -EINVAL;
	40
d19f61f0	41	raw_spin_lock_irqsave(&pci_config_lock, flags);
1da177e4	42
c7e844f0	43	write_cf8(bus, devfn, reg);
1da177e4 LT	44
	45	switch (len) {
	46	case 1:
c7e844f0 AK	47	if (xquad_portio)
	48	*value = readb(adr + (reg & 3));
	49	else
	50	*value = inb(0xCFC + (reg & 3));
1da177e4 LT	51	break;
1da177e4 LT	52	case 2:
c7e844f0 AK	53	if (xquad_portio)
	54	*value = readw(adr + (reg & 2));
	55	else
	56	*value = inw(0xCFC + (reg & 2));
1da177e4 LT	57	break;
1da177e4 LT	58	case 4:
c7e844f0 AK	59	if (xquad_portio)
	60	*value = readl(adr);
	61	else
	62	*value = inl(0xCFC);
1da177e4 LT	63	break;
	64	}
	65
d19f61f0	66	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
1da177e4 LT	67
	68	return 0;
	69	}
	70
	71	static int pci_conf1_mq_write(unsigned int seg, unsigned int bus,
	72	unsigned int devfn, int reg, int len, u32 value)
	73	{
	74	unsigned long flags;
c7e844f0	75	void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
1da177e4	76
db34a363	77	WARN_ON(seg);
1da177e4 LT	78	if ((bus >= MAX_MP_BUSSES) \|\| (devfn > 255) \|\| (reg > 255))
	79	return -EINVAL;
	80
d19f61f0	81	raw_spin_lock_irqsave(&pci_config_lock, flags);
1da177e4	82
c7e844f0	83	write_cf8(bus, devfn, reg);
1da177e4 LT	84
	85	switch (len) {
	86	case 1:
c7e844f0 AK	87	if (xquad_portio)
	88	writeb(value, adr + (reg & 3));
	89	else
	90	outb((u8)value, 0xCFC + (reg & 3));
1da177e4 LT	91	break;
1da177e4 LT	92	case 2:
c7e844f0 AK	93	if (xquad_portio)
	94	writew(value, adr + (reg & 2));
	95	else
	96	outw((u16)value, 0xCFC + (reg & 2));
1da177e4 LT	97	break;
1da177e4 LT	98	case 4:
c7e844f0 AK	99	if (xquad_portio)
	100	writel(value, adr + reg);
	101	else
	102	outl((u32)value, 0xCFC);
1da177e4 LT	103	break;
	104	}
	105
d19f61f0	106	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
1da177e4 LT	107
	108	return 0;
	109	}
	110
	111	#undef PCI_CONF1_MQ_ADDRESS
	112
72da0b07	113	static const struct pci_raw_ops pci_direct_conf1_mq = {
1da177e4 LT	114	.read = pci_conf1_mq_read,
	115	.write = pci_conf1_mq_write
	116	};
	117
	118
a18e3690	119	static void pci_fixup_i450nx(struct pci_dev *d)
1da177e4 LT	120	{
	121	/*
	122	* i450NX -- Find and scan all secondary buses on all PXB's.
	123	*/
	124	int pxb, reg;
	125	u8 busno, suba, subb;
	126	int quad = BUS2QUAD(d->bus->number);
	127
12c0b20f	128	dev_info(&d->dev, "searching for i450NX host bridges\n");
1da177e4 LT	129	reg = 0xd0;
	130	for(pxb=0; pxb<2; pxb++) {
	131	pci_read_config_byte(d, reg++, &busno);
	132	pci_read_config_byte(d, reg++, &suba);
	133	pci_read_config_byte(d, reg++, &subb);
12c0b20f BH	134	dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n",
12c0b20f BH	135	pxb, busno, suba, subb);
73c59afc MBY	136	if (busno) {
	137	/* Bus A */
	138	pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, busno));
	139	}
	140	if (suba < subb) {
	141	/* Bus B */
	142	pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, suba+1));
	143	}
1da177e4 LT	144	}
	145	pcibios_last_bus = -1;
	146	}
	147	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
	148
e27cf3a2	149	int __init pci_numaq_init(void)
1da177e4 LT	150	{
	151	int quad;
	152
	153	raw_pci_ops = &pci_direct_conf1_mq;
	154
b7869ba1	155	pcibios_scan_root(0);
1da177e4 LT	156	if (num_online_nodes() > 1)
	157	for_each_online_node(quad) {
	158	if (quad == 0)
	159	continue;
	160	printk("Scanning PCI bus %d for quad %d\n",
	161	QUADLOCAL2BUS(quad,0), quad);
73c59afc	162	pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, 0));
1da177e4 LT	163	}
	164	return 0;
	165	}