[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / pci / numaq_32.c

/*
 * numaq_32.c - Low-level PCI access for NUMA-Q machines
 */

#include <linux/pci.h>
#include <linux/init.h>
#include <linux/nodemask.h>
#include <mach_apic.h>
#include <asm/mpspec.h>
#include <asm/pci_x86.h>

#define XQUAD_PORTIO_BASE 0xfe400000
#define XQUAD_PORTIO_QUAD 0x40000  /* 256k per quad. */

#define BUS2QUAD(global) (mp_bus_id_to_node[global])

#define BUS2LOCAL(global) (mp_bus_id_to_local[global])

#define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])

/* Where the IO area was mapped on multiquad, always 0 otherwise */
void *xquad_portio;
EXPORT_SYMBOL(xquad_portio);

#define XQUAD_PORT_ADDR(port, quad) (xquad_portio + (XQUAD_PORTIO_QUAD*quad) + port)

#define PCI_CONF1_MQ_ADDRESS(bus, devfn, reg) \
	(0x80000000 | (BUS2LOCAL(bus) << 16) | (devfn << 8) | (reg & ~3))

static void write_cf8(unsigned bus, unsigned devfn, unsigned reg)
{
	unsigned val = PCI_CONF1_MQ_ADDRESS(bus, devfn, reg);
	if (xquad_portio)
		writel(val, XQUAD_PORT_ADDR(0xcf8, BUS2QUAD(bus)));
	else
		outl(val, 0xCF8);
}

static int pci_conf1_mq_read(unsigned int seg, unsigned int bus,
			     unsigned int devfn, int reg, int len, u32 *value)
{
	unsigned long flags;
	void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));

	if (!value || (bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
		return -EINVAL;

	spin_lock_irqsave(&pci_config_lock, flags);

	write_cf8(bus, devfn, reg);

	switch (len) {
	case 1:
		if (xquad_portio)
			*value = readb(adr + (reg & 3));
		else
			*value = inb(0xCFC + (reg & 3));
		break;
	case 2:
		if (xquad_portio)
			*value = readw(adr + (reg & 2));
		else
			*value = inw(0xCFC + (reg & 2));
		break;
	case 4:
		if (xquad_portio)
			*value = readl(adr);
		else
			*value = inl(0xCFC);
		break;
	}

	spin_unlock_irqrestore(&pci_config_lock, flags);

	return 0;
}

static int pci_conf1_mq_write(unsigned int seg, unsigned int bus,
			      unsigned int devfn, int reg, int len, u32 value)
{
	unsigned long flags;
	void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));

	if ((bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255)) 
		return -EINVAL;

	spin_lock_irqsave(&pci_config_lock, flags);

	write_cf8(bus, devfn, reg);

	switch (len) {
	case 1:
		if (xquad_portio)
			writeb(value, adr + (reg & 3));
		else
			outb((u8)value, 0xCFC + (reg & 3));
		break;
	case 2:
		if (xquad_portio)
			writew(value, adr + (reg & 2));
		else
			outw((u16)value, 0xCFC + (reg & 2));
		break;
	case 4:
		if (xquad_portio)
			writel(value, adr + reg);
		else
			outl((u32)value, 0xCFC);
		break;
	}

	spin_unlock_irqrestore(&pci_config_lock, flags);

	return 0;
}

#undef PCI_CONF1_MQ_ADDRESS

static struct pci_raw_ops pci_direct_conf1_mq = {
	.read	= pci_conf1_mq_read,
	.write	= pci_conf1_mq_write
};


static void __devinit pci_fixup_i450nx(struct pci_dev *d)
{
	/*
	 * i450NX -- Find and scan all secondary buses on all PXB's.
	 */
	int pxb, reg;
	u8 busno, suba, subb;
	int quad = BUS2QUAD(d->bus->number);

	dev_info(&d->dev, "searching for i450NX host bridges\n");
	reg = 0xd0;
	for(pxb=0; pxb<2; pxb++) {
		pci_read_config_byte(d, reg++, &busno);
		pci_read_config_byte(d, reg++, &suba);
		pci_read_config_byte(d, reg++, &subb);
		dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n",
			pxb, busno, suba, subb);
		if (busno) {
			/* Bus A */
			pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, busno));
		}
		if (suba < subb) {
			/* Bus B */
			pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, suba+1));
		}
	}
	pcibios_last_bus = -1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);

int __init pci_numaq_init(void)
{
	int quad;

	if (!found_numaq)
		return 0;

	raw_pci_ops = &pci_direct_conf1_mq;

	if (pcibios_scanned++)
		return 0;

	pci_root_bus = pcibios_scan_root(0);
	if (pci_root_bus)
		pci_bus_add_devices(pci_root_bus);
	if (num_online_nodes() > 1)
		for_each_online_node(quad) {
			if (quad == 0)
				continue;
			printk("Scanning PCI bus %d for quad %d\n", 
				QUADLOCAL2BUS(quad,0), quad);
			pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, 0));
		}
	return 0;
}
Commit	Line	Data
1da177e4	1	/*
e27cf3a2	2	* numaq_32.c - Low-level PCI access for NUMA-Q machines
1da177e4 LT	3	*/
	4
	5	#include <linux/pci.h>
	6	#include <linux/init.h>
	7	#include <linux/nodemask.h>
c7e844f0	8	#include <mach_apic.h>
d49c4288	9	#include <asm/mpspec.h>
82487711	10	#include <asm/pci_x86.h>
1da177e4	11
c7e844f0 AK	12	#define XQUAD_PORTIO_BASE 0xfe400000
	13	#define XQUAD_PORTIO_QUAD 0x40000 /* 256k per quad. */
	14
1da177e4	15	#define BUS2QUAD(global) (mp_bus_id_to_node[global])
e129cb49	16
1da177e4	17	#define BUS2LOCAL(global) (mp_bus_id_to_local[global])
6079d2d5	18
1da177e4 LT	19	#define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])
1da177e4 LT	20
4cedb334 GOC	21	/* Where the IO area was mapped on multiquad, always 0 otherwise */
4cedb334 GOC	22	void *xquad_portio;
4cedb334	23	EXPORT_SYMBOL(xquad_portio);
4cedb334	24
c7e844f0 AK	25	#define XQUAD_PORT_ADDR(port, quad) (xquad_portio + (XQUAD_PORTIO_QUAD*quad) + port)
c7e844f0 AK	26
1da177e4 LT	27	#define PCI_CONF1_MQ_ADDRESS(bus, devfn, reg) \
	28	(0x80000000 \| (BUS2LOCAL(bus) << 16) \| (devfn << 8) \| (reg & ~3))
	29
c7e844f0 AK	30	static void write_cf8(unsigned bus, unsigned devfn, unsigned reg)
	31	{
	32	unsigned val = PCI_CONF1_MQ_ADDRESS(bus, devfn, reg);
	33	if (xquad_portio)
	34	writel(val, XQUAD_PORT_ADDR(0xcf8, BUS2QUAD(bus)));
	35	else
	36	outl(val, 0xCF8);
	37	}
	38
1da177e4 LT	39	static int pci_conf1_mq_read(unsigned int seg, unsigned int bus,
	40	unsigned int devfn, int reg, int len, u32 *value)
	41	{
	42	unsigned long flags;
c7e844f0	43	void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
1da177e4 LT	44
	45	if (!value \|\| (bus >= MAX_MP_BUSSES) \|\| (devfn > 255) \|\| (reg > 255))
	46	return -EINVAL;
	47
	48	spin_lock_irqsave(&pci_config_lock, flags);
	49
c7e844f0	50	write_cf8(bus, devfn, reg);
1da177e4 LT	51
	52	switch (len) {
	53	case 1:
c7e844f0 AK	54	if (xquad_portio)
	55	*value = readb(adr + (reg & 3));
	56	else
	57	*value = inb(0xCFC + (reg & 3));
1da177e4 LT	58	break;
1da177e4 LT	59	case 2:
c7e844f0 AK	60	if (xquad_portio)
	61	*value = readw(adr + (reg & 2));
	62	else
	63	*value = inw(0xCFC + (reg & 2));
1da177e4 LT	64	break;
1da177e4 LT	65	case 4:
c7e844f0 AK	66	if (xquad_portio)
	67	*value = readl(adr);
	68	else
	69	*value = inl(0xCFC);
1da177e4 LT	70	break;
	71	}
	72
	73	spin_unlock_irqrestore(&pci_config_lock, flags);
	74
	75	return 0;
	76	}
	77
	78	static int pci_conf1_mq_write(unsigned int seg, unsigned int bus,
	79	unsigned int devfn, int reg, int len, u32 value)
	80	{
	81	unsigned long flags;
c7e844f0	82	void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
1da177e4 LT	83
	84	if ((bus >= MAX_MP_BUSSES) \|\| (devfn > 255) \|\| (reg > 255))
	85	return -EINVAL;
	86
	87	spin_lock_irqsave(&pci_config_lock, flags);
	88
c7e844f0	89	write_cf8(bus, devfn, reg);
1da177e4 LT	90
	91	switch (len) {
	92	case 1:
c7e844f0 AK	93	if (xquad_portio)
	94	writeb(value, adr + (reg & 3));
	95	else
	96	outb((u8)value, 0xCFC + (reg & 3));
1da177e4 LT	97	break;
1da177e4 LT	98	case 2:
c7e844f0 AK	99	if (xquad_portio)
	100	writew(value, adr + (reg & 2));
	101	else
	102	outw((u16)value, 0xCFC + (reg & 2));
1da177e4 LT	103	break;
1da177e4 LT	104	case 4:
c7e844f0 AK	105	if (xquad_portio)
	106	writel(value, adr + reg);
	107	else
	108	outl((u32)value, 0xCFC);
1da177e4 LT	109	break;
	110	}
	111
	112	spin_unlock_irqrestore(&pci_config_lock, flags);
	113
	114	return 0;
	115	}
	116
	117	#undef PCI_CONF1_MQ_ADDRESS
	118
	119	static struct pci_raw_ops pci_direct_conf1_mq = {
	120	.read = pci_conf1_mq_read,
	121	.write = pci_conf1_mq_write
	122	};
	123
	124
	125	static void __devinit pci_fixup_i450nx(struct pci_dev *d)
	126	{
	127	/*
	128	* i450NX -- Find and scan all secondary buses on all PXB's.
	129	*/
	130	int pxb, reg;
	131	u8 busno, suba, subb;
	132	int quad = BUS2QUAD(d->bus->number);
	133
12c0b20f	134	dev_info(&d->dev, "searching for i450NX host bridges\n");
1da177e4 LT	135	reg = 0xd0;
	136	for(pxb=0; pxb<2; pxb++) {
	137	pci_read_config_byte(d, reg++, &busno);
	138	pci_read_config_byte(d, reg++, &suba);
	139	pci_read_config_byte(d, reg++, &subb);
12c0b20f BH	140	dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n",
12c0b20f BH	141	pxb, busno, suba, subb);
73c59afc MBY	142	if (busno) {
	143	/* Bus A */
	144	pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, busno));
	145	}
	146	if (suba < subb) {
	147	/* Bus B */
	148	pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, suba+1));
	149	}
1da177e4 LT	150	}
	151	pcibios_last_bus = -1;
	152	}
	153	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
	154
e27cf3a2	155	int __init pci_numaq_init(void)
1da177e4 LT	156	{
	157	int quad;
	158
d49c4288 YL	159	if (!found_numaq)
	160	return 0;
	161
1da177e4 LT	162	raw_pci_ops = &pci_direct_conf1_mq;
	163
	164	if (pcibios_scanned++)
	165	return 0;
	166
	167	pci_root_bus = pcibios_scan_root(0);
c431ada4 RS	168	if (pci_root_bus)
c431ada4 RS	169	pci_bus_add_devices(pci_root_bus);
1da177e4 LT	170	if (num_online_nodes() > 1)
	171	for_each_online_node(quad) {
	172	if (quad == 0)
	173	continue;
	174	printk("Scanning PCI bus %d for quad %d\n",
	175	QUADLOCAL2BUS(quad,0), quad);
73c59afc	176	pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, 0));
1da177e4 LT	177	}
	178	return 0;
	179	}