[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / arch / x86 / pci / mmconfig_32.c

/*
 * Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
 * Copyright (C) 2004 Intel Corp.
 *
 * This code is released under the GNU General Public License version 2.
 */

/*
 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
 */

#include <linux/pci.h>
#include <linux/init.h>
#include <asm/e820.h>
#include <asm/pci_x86.h>
#include <acpi/acpi.h>

/* Assume systems with more busses have correct MCFG */
#define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))

/* The base address of the last MMCONFIG device accessed */
static u32 mmcfg_last_accessed_device;
static int mmcfg_last_accessed_cpu;

/*
 * Functions for accessing PCI configuration space with MMCONFIG accesses
 */
static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
{
	struct acpi_mcfg_allocation *cfg;
	int cfg_num;

	for (cfg_num = 0; cfg_num < pci_mmcfg_config_num; cfg_num++) {
		cfg = &pci_mmcfg_config[cfg_num];
		if (cfg->pci_segment == seg &&
		    (cfg->start_bus_number <= bus) &&
		    (cfg->end_bus_number >= bus))
			return cfg->address;
	}

	/* Fall back to type 0 */
	return 0;
}

/*
 * This is always called under pci_config_lock
 */
static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
{
	u32 dev_base = base | (bus << 20) | (devfn << 12);
	int cpu = smp_processor_id();
	if (dev_base != mmcfg_last_accessed_device ||
	    cpu != mmcfg_last_accessed_cpu) {
		mmcfg_last_accessed_device = dev_base;
		mmcfg_last_accessed_cpu = cpu;
		set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
	}
}

static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
			  unsigned int devfn, int reg, int len, u32 *value)
{
	unsigned long flags;
	u32 base;

	if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
err:		*value = -1;
		return -EINVAL;
	}

	base = get_base_addr(seg, bus, devfn);
	if (!base)
		goto err;

	spin_lock_irqsave(&pci_config_lock, flags);

	pci_exp_set_dev_base(base, bus, devfn);

	switch (len) {
	case 1:
		*value = mmio_config_readb(mmcfg_virt_addr + reg);
		break;
	case 2:
		*value = mmio_config_readw(mmcfg_virt_addr + reg);
		break;
	case 4:
		*value = mmio_config_readl(mmcfg_virt_addr + reg);
		break;
	}
	spin_unlock_irqrestore(&pci_config_lock, flags);

	return 0;
}

static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
			   unsigned int devfn, int reg, int len, u32 value)
{
	unsigned long flags;
	u32 base;

	if ((bus > 255) || (devfn > 255) || (reg > 4095))
		return -EINVAL;

	base = get_base_addr(seg, bus, devfn);
	if (!base)
		return -EINVAL;

	spin_lock_irqsave(&pci_config_lock, flags);

	pci_exp_set_dev_base(base, bus, devfn);

	switch (len) {
	case 1:
		mmio_config_writeb(mmcfg_virt_addr + reg, value);
		break;
	case 2:
		mmio_config_writew(mmcfg_virt_addr + reg, value);
		break;
	case 4:
		mmio_config_writel(mmcfg_virt_addr + reg, value);
		break;
	}
	spin_unlock_irqrestore(&pci_config_lock, flags);

	return 0;
}

static struct pci_raw_ops pci_mmcfg = {
	.read =		pci_mmcfg_read,
	.write =	pci_mmcfg_write,
};

int __init pci_mmcfg_arch_init(void)
{
	printk(KERN_INFO "PCI: Using MMCONFIG for extended config space\n");
	raw_pci_ext_ops = &pci_mmcfg;
	return 1;
}

void __init pci_mmcfg_arch_free(void)
{
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
	3	* Copyright (C) 2004 Intel Corp.
	4	*
	5	* This code is released under the GNU General Public License version 2.
	6	*/
	7
	8	/*
	9	* mmconfig.c - Low-level direct PCI config space access via MMCONFIG
	10	*/
	11
	12	#include <linux/pci.h>
	13	#include <linux/init.h>
946f2ee5	14	#include <asm/e820.h>
82487711	15	#include <asm/pci_x86.h>
5f0db7a2	16	#include <acpi/acpi.h>
1da177e4	17
8c30b1a7	18	/* Assume systems with more busses have correct MCFG */
1da177e4 LT	19	#define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))
	20
	21	/* The base address of the last MMCONFIG device accessed */
	22	static u32 mmcfg_last_accessed_device;
8d1c4819	23	static int mmcfg_last_accessed_cpu;
1da177e4 LT	24
	25	/*
	26	* Functions for accessing PCI configuration space with MMCONFIG accesses
	27	*/
d6ece549	28	static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
d57e26ce	29	{
15a58ed1	30	struct acpi_mcfg_allocation *cfg;
429d512e	31	int cfg_num;
d57e26ce	32
429d512e	33	for (cfg_num = 0; cfg_num < pci_mmcfg_config_num; cfg_num++) {
d57e26ce	34	cfg = &pci_mmcfg_config[cfg_num];
429d512e OH	35	if (cfg->pci_segment == seg &&
429d512e OH	36	(cfg->start_bus_number <= bus) &&
d57e26ce	37	(cfg->end_bus_number >= bus))
15a58ed1	38	return cfg->address;
d57e26ce	39	}
3103039c	40
3103039c AK	41	/* Fall back to type 0 */
3103039c AK	42	return 0;
d57e26ce	43	}
1da177e4	44
be5b7a89 AM	45	/*
	46	* This is always called under pci_config_lock
	47	*/
	48	static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
1da177e4	49	{
928cf8c6	50	u32 dev_base = base \| (bus << 20) \| (devfn << 12);
8d1c4819 OH	51	int cpu = smp_processor_id();
	52	if (dev_base != mmcfg_last_accessed_device \|\|
	53	cpu != mmcfg_last_accessed_cpu) {
1da177e4	54	mmcfg_last_accessed_device = dev_base;
8d1c4819	55	mmcfg_last_accessed_cpu = cpu;
1da177e4 LT	56	set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
	57	}
	58	}
	59
	60	static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
	61	unsigned int devfn, int reg, int len, u32 *value)
	62	{
	63	unsigned long flags;
928cf8c6	64	u32 base;
1da177e4	65
ecc16ba9	66	if ((bus > 255) \|\| (devfn > 255) \|\| (reg > 4095)) {
a0ca9909	67	err: *value = -1;
1da177e4	68	return -EINVAL;
49c93e84	69	}
1da177e4	70
d6ece549	71	base = get_base_addr(seg, bus, devfn);
928cf8c6	72	if (!base)
a0ca9909	73	goto err;
928cf8c6	74
1da177e4 LT	75	spin_lock_irqsave(&pci_config_lock, flags);
1da177e4 LT	76
928cf8c6	77	pci_exp_set_dev_base(base, bus, devfn);
1da177e4 LT	78
	79	switch (len) {
	80	case 1:
3320ad99	81	*value = mmio_config_readb(mmcfg_virt_addr + reg);
1da177e4 LT	82	break;
1da177e4 LT	83	case 2:
3320ad99	84	*value = mmio_config_readw(mmcfg_virt_addr + reg);
1da177e4 LT	85	break;
1da177e4 LT	86	case 4:
3320ad99	87	*value = mmio_config_readl(mmcfg_virt_addr + reg);
1da177e4 LT	88	break;
1da177e4 LT	89	}
1da177e4 LT	90	spin_unlock_irqrestore(&pci_config_lock, flags);
	91
	92	return 0;
	93	}
	94
	95	static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
	96	unsigned int devfn, int reg, int len, u32 value)
	97	{
	98	unsigned long flags;
928cf8c6	99	u32 base;
1da177e4	100
15a58ed1	101	if ((bus > 255) \|\| (devfn > 255) \|\| (reg > 4095))
1da177e4 LT	102	return -EINVAL;
1da177e4 LT	103
d6ece549	104	base = get_base_addr(seg, bus, devfn);
928cf8c6	105	if (!base)
a0ca9909	106	return -EINVAL;
928cf8c6	107
1da177e4 LT	108	spin_lock_irqsave(&pci_config_lock, flags);
1da177e4 LT	109
928cf8c6	110	pci_exp_set_dev_base(base, bus, devfn);
1da177e4 LT	111
	112	switch (len) {
	113	case 1:
c1502e28	114	mmio_config_writeb(mmcfg_virt_addr + reg, value);
1da177e4 LT	115	break;
1da177e4 LT	116	case 2:
c1502e28	117	mmio_config_writew(mmcfg_virt_addr + reg, value);
1da177e4 LT	118	break;
1da177e4 LT	119	case 4:
c1502e28	120	mmio_config_writel(mmcfg_virt_addr + reg, value);
1da177e4 LT	121	break;
1da177e4 LT	122	}
1da177e4 LT	123	spin_unlock_irqrestore(&pci_config_lock, flags);
	124
	125	return 0;
	126	}
	127
	128	static struct pci_raw_ops pci_mmcfg = {
	129	.read = pci_mmcfg_read,
	130	.write = pci_mmcfg_write,
	131	};
	132
b7867394	133	int __init pci_mmcfg_arch_init(void)
d6ece549	134	{
b6ce068a MW	135	printk(KERN_INFO "PCI: Using MMCONFIG for extended config space\n");
b6ce068a MW	136	raw_pci_ext_ops = &pci_mmcfg;
b7867394	137	return 1;
1da177e4	138	}
0b64ad71 YL	139
	140	void __init pci_mmcfg_arch_free(void)
	141	{
	142	}