[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / pci / mmconfig_32.c

/*
 * Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
 * Copyright (C) 2004 Intel Corp.
 *
 * This code is released under the GNU General Public License version 2.
 */

/*
 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
 */

#include <linux/pci.h>
#include <linux/init.h>
#include <linux/rcupdate.h>
#include <asm/e820.h>
#include <asm/pci_x86.h>
#include <acpi/acpi.h>

/* Assume systems with more busses have correct MCFG */
#define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))

/* The base address of the last MMCONFIG device accessed */
static u32 mmcfg_last_accessed_device;
static int mmcfg_last_accessed_cpu;

/*
 * Functions for accessing PCI configuration space with MMCONFIG accesses
 */
static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
{
	struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus);

	if (cfg)
		return cfg->address;
	return 0;
}

/*
 * This is always called under pci_config_lock
 */
static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
{
	u32 dev_base = base | PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12);
	int cpu = smp_processor_id();
	if (dev_base != mmcfg_last_accessed_device ||
	    cpu != mmcfg_last_accessed_cpu) {
		mmcfg_last_accessed_device = dev_base;
		mmcfg_last_accessed_cpu = cpu;
		set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
	}
}

static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
			  unsigned int devfn, int reg, int len, u32 *value)
{
	unsigned long flags;
	u32 base;

	if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
err:		*value = -1;
		return -EINVAL;
	}

	rcu_read_lock();
	base = get_base_addr(seg, bus, devfn);
	if (!base) {
		rcu_read_unlock();
		goto err;
	}

	raw_spin_lock_irqsave(&pci_config_lock, flags);

	pci_exp_set_dev_base(base, bus, devfn);

	switch (len) {
	case 1:
		*value = mmio_config_readb(mmcfg_virt_addr + reg);
		break;
	case 2:
		*value = mmio_config_readw(mmcfg_virt_addr + reg);
		break;
	case 4:
		*value = mmio_config_readl(mmcfg_virt_addr + reg);
		break;
	}
	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
	rcu_read_unlock();

	return 0;
}

static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
			   unsigned int devfn, int reg, int len, u32 value)
{
	unsigned long flags;
	u32 base;

	if ((bus > 255) || (devfn > 255) || (reg > 4095))
		return -EINVAL;

	rcu_read_lock();
	base = get_base_addr(seg, bus, devfn);
	if (!base) {
		rcu_read_unlock();
		return -EINVAL;
	}

	raw_spin_lock_irqsave(&pci_config_lock, flags);

	pci_exp_set_dev_base(base, bus, devfn);

	switch (len) {
	case 1:
		mmio_config_writeb(mmcfg_virt_addr + reg, value);
		break;
	case 2:
		mmio_config_writew(mmcfg_virt_addr + reg, value);
		break;
	case 4:
		mmio_config_writel(mmcfg_virt_addr + reg, value);
		break;
	}
	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
	rcu_read_unlock();

	return 0;
}

const struct pci_raw_ops pci_mmcfg = {
	.read =		pci_mmcfg_read,
	.write =	pci_mmcfg_write,
};

int __init pci_mmcfg_arch_init(void)
{
	printk(KERN_INFO "PCI: Using MMCONFIG for extended config space\n");
	raw_pci_ext_ops = &pci_mmcfg;
	return 1;
}

void __init pci_mmcfg_arch_free(void)
{
}

int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg)
{
	return 0;
}

void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg)
{
	unsigned long flags;

	/* Invalidate the cached mmcfg map entry. */
	raw_spin_lock_irqsave(&pci_config_lock, flags);
	mmcfg_last_accessed_device = 0;
	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
	3	* Copyright (C) 2004 Intel Corp.
	4	*
	5	* This code is released under the GNU General Public License version 2.
	6	*/
	7
	8	/*
	9	* mmconfig.c - Low-level direct PCI config space access via MMCONFIG
	10	*/
	11
	12	#include <linux/pci.h>
	13	#include <linux/init.h>
376f70ac	14	#include <linux/rcupdate.h>
946f2ee5	15	#include <asm/e820.h>
82487711	16	#include <asm/pci_x86.h>
5f0db7a2	17	#include <acpi/acpi.h>
1da177e4	18
8c30b1a7	19	/* Assume systems with more busses have correct MCFG */
1da177e4 LT	20	#define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))
	21
	22	/* The base address of the last MMCONFIG device accessed */
	23	static u32 mmcfg_last_accessed_device;
8d1c4819	24	static int mmcfg_last_accessed_cpu;
1da177e4 LT	25
	26	/*
	27	* Functions for accessing PCI configuration space with MMCONFIG accesses
	28	*/
d6ece549	29	static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
d57e26ce	30	{
f6e1d8cc	31	struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus);
d57e26ce	32
f6e1d8cc BH	33	if (cfg)
f6e1d8cc BH	34	return cfg->address;
3103039c	35	return 0;
d57e26ce	36	}
1da177e4	37
be5b7a89 AM	38	/*
	39	* This is always called under pci_config_lock
	40	*/
	41	static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
1da177e4	42	{
df5eb1d6	43	u32 dev_base = base \| PCI_MMCFG_BUS_OFFSET(bus) \| (devfn << 12);
8d1c4819 OH	44	int cpu = smp_processor_id();
	45	if (dev_base != mmcfg_last_accessed_device \|\|
	46	cpu != mmcfg_last_accessed_cpu) {
1da177e4	47	mmcfg_last_accessed_device = dev_base;
8d1c4819	48	mmcfg_last_accessed_cpu = cpu;
1da177e4 LT	49	set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
	50	}
	51	}
	52
	53	static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
	54	unsigned int devfn, int reg, int len, u32 *value)
	55	{
	56	unsigned long flags;
928cf8c6	57	u32 base;
1da177e4	58
ecc16ba9	59	if ((bus > 255) \|\| (devfn > 255) \|\| (reg > 4095)) {
a0ca9909	60	err: *value = -1;
1da177e4	61	return -EINVAL;
49c93e84	62	}
1da177e4	63
376f70ac	64	rcu_read_lock();
d6ece549	65	base = get_base_addr(seg, bus, devfn);
376f70ac JL	66	if (!base) {
376f70ac JL	67	rcu_read_unlock();
a0ca9909	68	goto err;
376f70ac	69	}
928cf8c6	70
d19f61f0	71	raw_spin_lock_irqsave(&pci_config_lock, flags);
1da177e4	72
928cf8c6	73	pci_exp_set_dev_base(base, bus, devfn);
1da177e4 LT	74
	75	switch (len) {
	76	case 1:
3320ad99	77	*value = mmio_config_readb(mmcfg_virt_addr + reg);
1da177e4 LT	78	break;
1da177e4 LT	79	case 2:
3320ad99	80	*value = mmio_config_readw(mmcfg_virt_addr + reg);
1da177e4 LT	81	break;
1da177e4 LT	82	case 4:
3320ad99	83	*value = mmio_config_readl(mmcfg_virt_addr + reg);
1da177e4 LT	84	break;
1da177e4 LT	85	}
d19f61f0	86	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
376f70ac	87	rcu_read_unlock();
1da177e4 LT	88
	89	return 0;
	90	}
	91
	92	static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
	93	unsigned int devfn, int reg, int len, u32 value)
	94	{
	95	unsigned long flags;
928cf8c6	96	u32 base;
1da177e4	97
15a58ed1	98	if ((bus > 255) \|\| (devfn > 255) \|\| (reg > 4095))
1da177e4 LT	99	return -EINVAL;
1da177e4 LT	100
376f70ac	101	rcu_read_lock();
d6ece549	102	base = get_base_addr(seg, bus, devfn);
376f70ac JL	103	if (!base) {
376f70ac JL	104	rcu_read_unlock();
a0ca9909	105	return -EINVAL;
376f70ac	106	}
928cf8c6	107
d19f61f0	108	raw_spin_lock_irqsave(&pci_config_lock, flags);
1da177e4	109
928cf8c6	110	pci_exp_set_dev_base(base, bus, devfn);
1da177e4 LT	111
	112	switch (len) {
	113	case 1:
c1502e28	114	mmio_config_writeb(mmcfg_virt_addr + reg, value);
1da177e4 LT	115	break;
1da177e4 LT	116	case 2:
c1502e28	117	mmio_config_writew(mmcfg_virt_addr + reg, value);
1da177e4 LT	118	break;
1da177e4 LT	119	case 4:
c1502e28	120	mmio_config_writel(mmcfg_virt_addr + reg, value);
1da177e4 LT	121	break;
1da177e4 LT	122	}
d19f61f0	123	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
376f70ac	124	rcu_read_unlock();
1da177e4 LT	125
	126	return 0;
	127	}
	128
c0fa4078	129	const struct pci_raw_ops pci_mmcfg = {
1da177e4 LT	130	.read = pci_mmcfg_read,
	131	.write = pci_mmcfg_write,
	132	};
	133
b7867394	134	int __init pci_mmcfg_arch_init(void)
d6ece549	135	{
b6ce068a MW	136	printk(KERN_INFO "PCI: Using MMCONFIG for extended config space\n");
b6ce068a MW	137	raw_pci_ext_ops = &pci_mmcfg;
b7867394	138	return 1;
1da177e4	139	}
0b64ad71 YL	140
	141	void __init pci_mmcfg_arch_free(void)
	142	{
	143	}
9cf0105d	144
a18e3690	145	int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg)
9cf0105d JL	146	{
	147	return 0;
	148	}
	149
	150	void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg)
	151	{
	152	unsigned long flags;
	153
	154	/* Invalidate the cached mmcfg map entry. */
	155	raw_spin_lock_irqsave(&pci_config_lock, flags);
	156	mmcfg_last_accessed_device = 0;
	157	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
	158	}