[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / pci / mmconfig-shared.c

/*
 * mmconfig-shared.c - Low-level direct PCI config space access via
 *                     MMCONFIG - common code between i386 and x86-64.
 *
 * This code does:
 * - known chipset handling
 * - ACPI decoding and validation
 *
 * Per-architecture code takes care of the mappings and accesses
 * themselves.
 */

#include <linux/pci.h>
#include <linux/init.h>
#include <linux/acpi.h>
#include <linux/bitmap.h>
#include <linux/sort.h>
#include <asm/e820.h>
#include <asm/pci_x86.h>

/* aperture is up to 256MB but BIOS may reserve less */
#define MMCONFIG_APER_MIN	(2 * 1024*1024)
#define MMCONFIG_APER_MAX	(256 * 1024*1024)

/* Indicate if the mmcfg resources have been placed into the resource table. */
static int __initdata pci_mmcfg_resources_inserted;

static __init int extend_mmcfg(int num)
{
	struct acpi_mcfg_allocation *new;
	int new_num = pci_mmcfg_config_num + num;

	new = kzalloc(sizeof(pci_mmcfg_config[0]) * new_num, GFP_KERNEL);
	if (!new)
		return -1;

	if (pci_mmcfg_config) {
		memcpy(new, pci_mmcfg_config,
			 sizeof(pci_mmcfg_config[0]) * new_num);
		kfree(pci_mmcfg_config);
	}
	pci_mmcfg_config = new;

	return 0;
}

static __init void fill_one_mmcfg(u64 addr, int segment, int start, int end)
{
	int i = pci_mmcfg_config_num;

	pci_mmcfg_config_num++;
	pci_mmcfg_config[i].address = addr;
	pci_mmcfg_config[i].pci_segment = segment;
	pci_mmcfg_config[i].start_bus_number = start;
	pci_mmcfg_config[i].end_bus_number = end;
}

static const char __init *pci_mmcfg_e7520(void)
{
	u32 win;
	raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);

	win = win & 0xf000;
	if (win == 0x0000 || win == 0xf000)
		return NULL;

	if (extend_mmcfg(1) == -1)
		return NULL;

	fill_one_mmcfg(win << 16, 0, 0, 255);

	return "Intel Corporation E7520 Memory Controller Hub";
}

static const char __init *pci_mmcfg_intel_945(void)
{
	u32 pciexbar, mask = 0, len = 0;

	raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);

	/* Enable bit */
	if (!(pciexbar & 1))
		return NULL;

	/* Size bits */
	switch ((pciexbar >> 1) & 3) {
	case 0:
		mask = 0xf0000000U;
		len  = 0x10000000U;
		break;
	case 1:
		mask = 0xf8000000U;
		len  = 0x08000000U;
		break;
	case 2:
		mask = 0xfc000000U;
		len  = 0x04000000U;
		break;
	default:
		return NULL;
	}

	/* Errata #2, things break when not aligned on a 256Mb boundary */
	/* Can only happen in 64M/128M mode */

	if ((pciexbar & mask) & 0x0fffffffU)
		return NULL;

	/* Don't hit the APIC registers and their friends */
	if ((pciexbar & mask) >= 0xf0000000U)
		return NULL;

	if (extend_mmcfg(1) == -1)
		return NULL;

	fill_one_mmcfg(pciexbar & mask, 0, 0, (len >> 20) - 1);

	return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
}

static const char __init *pci_mmcfg_amd_fam10h(void)
{
	u32 low, high, address;
	u64 base, msr;
	int i;
	unsigned segnbits = 0, busnbits;

	if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
		return NULL;

	address = MSR_FAM10H_MMIO_CONF_BASE;
	if (rdmsr_safe(address, &low, &high))
		return NULL;

	msr = high;
	msr <<= 32;
	msr |= low;

	/* mmconfig is not enable */
	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
		return NULL;

	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);

	busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
			 FAM10H_MMIO_CONF_BUSRANGE_MASK;

	/*
	 * only handle bus 0 ?
	 * need to skip it
	 */
	if (!busnbits)
		return NULL;

	if (busnbits > 8) {
		segnbits = busnbits - 8;
		busnbits = 8;
	}

	if (extend_mmcfg(1 << segnbits) == -1)
		return NULL;

	for (i = 0; i < (1 << segnbits); i++)
		fill_one_mmcfg(base + (1<<28) * i, i, 0, (1 << busnbits) - 1);

	return "AMD Family 10h NB";
}

static bool __initdata mcp55_checked;
static const char __init *pci_mmcfg_nvidia_mcp55(void)
{
	int bus;
	int mcp55_mmconf_found = 0;

	static const u32 extcfg_regnum		= 0x90;
	static const u32 extcfg_regsize		= 4;
	static const u32 extcfg_enable_mask	= 1<<31;
	static const u32 extcfg_start_mask	= 0xff<<16;
	static const int extcfg_start_shift	= 16;
	static const u32 extcfg_size_mask	= 0x3<<28;
	static const int extcfg_size_shift	= 28;
	static const int extcfg_sizebus[]	= {0x100, 0x80, 0x40, 0x20};
	static const u32 extcfg_base_mask[]	= {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
	static const int extcfg_base_lshift	= 25;

	/*
	 * do check if amd fam10h already took over
	 */
	if (!acpi_disabled || pci_mmcfg_config_num || mcp55_checked)
		return NULL;

	mcp55_checked = true;
	for (bus = 0; bus < 256; bus++) {
		u64 base;
		u32 l, extcfg;
		u16 vendor, device;
		int start, size_index, end;

		raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
		vendor = l & 0xffff;
		device = (l >> 16) & 0xffff;

		if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
			continue;

		raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
				  extcfg_regsize, &extcfg);

		if (!(extcfg & extcfg_enable_mask))
			continue;

		if (extend_mmcfg(1) == -1)
			continue;

		size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
		base = extcfg & extcfg_base_mask[size_index];
		/* base could > 4G */
		base <<= extcfg_base_lshift;
		start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
		end = start + extcfg_sizebus[size_index] - 1;
		fill_one_mmcfg(base, 0, start, end);
		mcp55_mmconf_found++;
	}

	if (!mcp55_mmconf_found)
		return NULL;

	return "nVidia MCP55";
}

struct pci_mmcfg_hostbridge_probe {
	u32 bus;
	u32 devfn;
	u32 vendor;
	u32 device;
	const char *(*probe)(void);
};

static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
	  PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
	  PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
	{ 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
	  0x1200, pci_mmcfg_amd_fam10h },
	{ 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
	  0x1200, pci_mmcfg_amd_fam10h },
	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
	  0x0369, pci_mmcfg_nvidia_mcp55 },
};

static int __init cmp_mmcfg(const void *x1, const void *x2)
{
	const typeof(pci_mmcfg_config[0]) *m1 = x1;
	const typeof(pci_mmcfg_config[0]) *m2 = x2;
	int start1, start2;

	start1 = m1->start_bus_number;
	start2 = m2->start_bus_number;

	return start1 - start2;
}

static void __init pci_mmcfg_check_end_bus_number(void)
{
	int i;
	typeof(pci_mmcfg_config[0]) *cfg, *cfgx;

	/* sort them at first */
	sort(pci_mmcfg_config, pci_mmcfg_config_num,
		 sizeof(pci_mmcfg_config[0]), cmp_mmcfg, NULL);

	/* last one*/
	if (pci_mmcfg_config_num > 0) {
		i = pci_mmcfg_config_num - 1;
		cfg = &pci_mmcfg_config[i];
		if (cfg->end_bus_number < cfg->start_bus_number)
			cfg->end_bus_number = 255;
	}

	/* don't overlap please */
	for (i = 0; i < pci_mmcfg_config_num - 1; i++) {
		cfg = &pci_mmcfg_config[i];
		cfgx = &pci_mmcfg_config[i+1];

		if (cfg->end_bus_number < cfg->start_bus_number)
			cfg->end_bus_number = 255;

		if (cfg->end_bus_number >= cfgx->start_bus_number)
			cfg->end_bus_number = cfgx->start_bus_number - 1;
	}
}

static int __init pci_mmcfg_check_hostbridge(void)
{
	u32 l;
	u32 bus, devfn;
	u16 vendor, device;
	int i;
	const char *name;

	if (!raw_pci_ops)
		return 0;

	pci_mmcfg_config_num = 0;
	pci_mmcfg_config = NULL;

	for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
		bus =  pci_mmcfg_probes[i].bus;
		devfn = pci_mmcfg_probes[i].devfn;
		raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
		vendor = l & 0xffff;
		device = (l >> 16) & 0xffff;

		name = NULL;
		if (pci_mmcfg_probes[i].vendor == vendor &&
		    pci_mmcfg_probes[i].device == device)
			name = pci_mmcfg_probes[i].probe();

		if (name)
			printk(KERN_INFO "PCI: Found %s with MMCONFIG support.\n",
			       name);
	}

	/* some end_bus_number is crazy, fix it */
	pci_mmcfg_check_end_bus_number();

	return pci_mmcfg_config_num != 0;
}

static void __init pci_mmcfg_insert_resources(void)
{
#define PCI_MMCFG_RESOURCE_NAME_LEN 24
	int i;
	struct resource *res;
	char *names;
	unsigned num_buses;

	res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
			pci_mmcfg_config_num, GFP_KERNEL);
	if (!res) {
		printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
		return;
	}

	names = (void *)&res[pci_mmcfg_config_num];
	for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
		struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
		num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
		res->name = names;
		snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN,
			 "PCI MMCONFIG %u [%02x-%02x]", cfg->pci_segment,
			 cfg->start_bus_number, cfg->end_bus_number);
		res->start = cfg->address + (cfg->start_bus_number << 20);
		res->end = res->start + (num_buses << 20) - 1;
		res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
		insert_resource(&iomem_resource, res);
		names += PCI_MMCFG_RESOURCE_NAME_LEN;
	}

	/* Mark that the resources have been inserted. */
	pci_mmcfg_resources_inserted = 1;
}

static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
					      void *data)
{
	struct resource *mcfg_res = data;
	struct acpi_resource_address64 address;
	acpi_status status;

	if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
		struct acpi_resource_fixed_memory32 *fixmem32 =
			&res->data.fixed_memory32;
		if (!fixmem32)
			return AE_OK;
		if ((mcfg_res->start >= fixmem32->address) &&
		    (mcfg_res->end <= (fixmem32->address +
				      fixmem32->address_length))) {
			mcfg_res->flags = 1;
			return AE_CTRL_TERMINATE;
		}
	}
	if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
	    (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
		return AE_OK;

	status = acpi_resource_to_address64(res, &address);
	if (ACPI_FAILURE(status) ||
	   (address.address_length <= 0) ||
	   (address.resource_type != ACPI_MEMORY_RANGE))
		return AE_OK;

	if ((mcfg_res->start >= address.minimum) &&
	    (mcfg_res->end <= (address.minimum + address.address_length))) {
		mcfg_res->flags = 1;
		return AE_CTRL_TERMINATE;
	}
	return AE_OK;
}

static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
		void *context, void **rv)
{
	struct resource *mcfg_res = context;

	acpi_walk_resources(handle, METHOD_NAME__CRS,
			    check_mcfg_resource, context);

	if (mcfg_res->flags)
		return AE_CTRL_TERMINATE;

	return AE_OK;
}

static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
{
	struct resource mcfg_res;

	mcfg_res.start = start;
	mcfg_res.end = end;
	mcfg_res.flags = 0;

	acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);

	if (!mcfg_res.flags)
		acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
				 NULL);

	return mcfg_res.flags;
}

typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);

static int __init is_mmconf_reserved(check_reserved_t is_reserved,
		u64 addr, u64 size, int i,
		typeof(pci_mmcfg_config[0]) *cfg, int with_e820)
{
	u64 old_size = size;
	int valid = 0;

	while (!is_reserved(addr, addr + size, E820_RESERVED)) {
		size >>= 1;
		if (size < (16UL<<20))
			break;
	}

	if (size >= (16UL<<20) || size == old_size) {
		printk(KERN_NOTICE
		       "PCI: MCFG area at %Lx reserved in %s\n",
			addr, with_e820?"E820":"ACPI motherboard resources");
		valid = 1;

		if (old_size != size) {
			/* update end_bus_number */
			cfg->end_bus_number = cfg->start_bus_number + ((size>>20) - 1);
			printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx "
			       "segment %hu buses %u - %u\n",
			       i, (unsigned long)cfg->address, cfg->pci_segment,
			       (unsigned int)cfg->start_bus_number,
			       (unsigned int)cfg->end_bus_number);
		}
	}

	return valid;
}

static void __init pci_mmcfg_reject_broken(int early)
{
	typeof(pci_mmcfg_config[0]) *cfg;
	int i;

	if ((pci_mmcfg_config_num == 0) ||
	    (pci_mmcfg_config == NULL) ||
	    (pci_mmcfg_config[0].address == 0))
		return;

	for (i = 0; i < pci_mmcfg_config_num; i++) {
		int valid = 0;
		u64 addr, size;

		cfg = &pci_mmcfg_config[i];
		addr = cfg->start_bus_number;
		addr <<= 20;
		addr += cfg->address;
		size = cfg->end_bus_number + 1 - cfg->start_bus_number;
		size <<= 20;
		printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
		       "segment %hu buses %u - %u\n",
		       i, (unsigned long)cfg->address, cfg->pci_segment,
		       (unsigned int)cfg->start_bus_number,
		       (unsigned int)cfg->end_bus_number);

		if (!early)
			valid = is_mmconf_reserved(is_acpi_reserved, addr, size, i, cfg, 0);

		if (valid)
			continue;

		if (!early)
			printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
			       " reserved in ACPI motherboard resources\n",
			       cfg->address);

		/* Don't try to do this check unless configuration
		   type 1 is available. how about type 2 ?*/
		if (raw_pci_ops)
			valid = is_mmconf_reserved(e820_all_mapped, addr, size, i, cfg, 1);

		if (!valid)
			goto reject;
	}

	return;

reject:
	printk(KERN_INFO "PCI: Not using MMCONFIG.\n");
	pci_mmcfg_arch_free();
	kfree(pci_mmcfg_config);
	pci_mmcfg_config = NULL;
	pci_mmcfg_config_num = 0;
}

static int __initdata known_bridge;

static void __init __pci_mmcfg_init(int early)
{
	/* MMCONFIG disabled */
	if ((pci_probe & PCI_PROBE_MMCONF) == 0)
		return;

	/* MMCONFIG already enabled */
	if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
		return;

	/* for late to exit */
	if (known_bridge)
		return;

	if (early) {
		if (pci_mmcfg_check_hostbridge())
			known_bridge = 1;
	}

	if (!known_bridge)
		acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);

	pci_mmcfg_reject_broken(early);

	if ((pci_mmcfg_config_num == 0) ||
	    (pci_mmcfg_config == NULL) ||
	    (pci_mmcfg_config[0].address == 0))
		return;

	if (pci_mmcfg_arch_init())
		pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
	else {
		/*
		 * Signal not to attempt to insert mmcfg resources because
		 * the architecture mmcfg setup could not initialize.
		 */
		pci_mmcfg_resources_inserted = 1;
	}
}

void __init pci_mmcfg_early_init(void)
{
	__pci_mmcfg_init(1);
}

void __init pci_mmcfg_late_init(void)
{
	__pci_mmcfg_init(0);
}

static int __init pci_mmcfg_late_insert_resources(void)
{
	/*
	 * If resources are already inserted or we are not using MMCONFIG,
	 * don't insert the resources.
	 */
	if ((pci_mmcfg_resources_inserted == 1) ||
	    (pci_probe & PCI_PROBE_MMCONF) == 0 ||
	    (pci_mmcfg_config_num == 0) ||
	    (pci_mmcfg_config == NULL) ||
	    (pci_mmcfg_config[0].address == 0))
		return 1;

	/*
	 * Attempt to insert the mmcfg resources but not with the busy flag
	 * marked so it won't cause request errors when __request_region is
	 * called.
	 */
	pci_mmcfg_insert_resources();

	return 0;
}

/*
 * Perform MMCONFIG resource insertion after PCI initialization to allow for
 * misprogrammed MCFG tables that state larger sizes but actually conflict
 * with other system resources.
 */
late_initcall(pci_mmcfg_late_insert_resources);
Commit	Line	Data
b7867394 OG	1	/*
	2	* mmconfig-shared.c - Low-level direct PCI config space access via
	3	* MMCONFIG - common code between i386 and x86-64.
	4	*
	5	* This code does:
9358c693	6	* - known chipset handling
b7867394 OG	7	* - ACPI decoding and validation
	8	*
	9	* Per-architecture code takes care of the mappings and accesses
	10	* themselves.
	11	*/
	12
	13	#include <linux/pci.h>
	14	#include <linux/init.h>
	15	#include <linux/acpi.h>
	16	#include <linux/bitmap.h>
068258bc	17	#include <linux/sort.h>
b7867394	18	#include <asm/e820.h>
82487711	19	#include <asm/pci_x86.h>
b7867394 OG	20
	21	/* aperture is up to 256MB but BIOS may reserve less */
	22	#define MMCONFIG_APER_MIN (2 * 1024*1024)
	23	#define MMCONFIG_APER_MAX (256 * 1024*1024)
	24
a5ba7971 AD	25	/* Indicate if the mmcfg resources have been placed into the resource table. */
	26	static int __initdata pci_mmcfg_resources_inserted;
	27
068258bc YL	28	static __init int extend_mmcfg(int num)
	29	{
	30	struct acpi_mcfg_allocation *new;
	31	int new_num = pci_mmcfg_config_num + num;
	32
	33	new = kzalloc(sizeof(pci_mmcfg_config[0]) * new_num, GFP_KERNEL);
	34	if (!new)
	35	return -1;
	36
	37	if (pci_mmcfg_config) {
	38	memcpy(new, pci_mmcfg_config,
	39	sizeof(pci_mmcfg_config[0]) * new_num);
	40	kfree(pci_mmcfg_config);
	41	}
	42	pci_mmcfg_config = new;
	43
	44	return 0;
	45	}
	46
	47	static __init void fill_one_mmcfg(u64 addr, int segment, int start, int end)
	48	{
	49	int i = pci_mmcfg_config_num;
	50
	51	pci_mmcfg_config_num++;
	52	pci_mmcfg_config[i].address = addr;
	53	pci_mmcfg_config[i].pci_segment = segment;
	54	pci_mmcfg_config[i].start_bus_number = start;
	55	pci_mmcfg_config[i].end_bus_number = end;
	56	}
	57
429d512e	58	static const char __init *pci_mmcfg_e7520(void)
9358c693 OG	59	{
9358c693 OG	60	u32 win;
bb63b421	61	raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
9358c693	62
b5229dbb	63	win = win & 0xf000;
068258bc YL	64	if (win == 0x0000 \|\| win == 0xf000)
	65	return NULL;
	66
	67	if (extend_mmcfg(1) == -1)
	68	return NULL;
	69
	70	fill_one_mmcfg(win << 16, 0, 0, 255);
9358c693 OG	71
	72	return "Intel Corporation E7520 Memory Controller Hub";
	73	}
	74
429d512e	75	static const char __init *pci_mmcfg_intel_945(void)
9358c693 OG	76	{
	77	u32 pciexbar, mask = 0, len = 0;
	78
bb63b421	79	raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
9358c693 OG	80
	81	/* Enable bit */
	82	if (!(pciexbar & 1))
068258bc	83	return NULL;
9358c693 OG	84
	85	/* Size bits */
	86	switch ((pciexbar >> 1) & 3) {
	87	case 0:
	88	mask = 0xf0000000U;
	89	len = 0x10000000U;
	90	break;
	91	case 1:
	92	mask = 0xf8000000U;
	93	len = 0x08000000U;
	94	break;
	95	case 2:
	96	mask = 0xfc000000U;
	97	len = 0x04000000U;
	98	break;
	99	default:
068258bc	100	return NULL;
9358c693 OG	101	}
	102
	103	/* Errata #2, things break when not aligned on a 256Mb boundary */
	104	/* Can only happen in 64M/128M mode */
	105
	106	if ((pciexbar & mask) & 0x0fffffffU)
068258bc	107	return NULL;
9358c693	108
b5229dbb OG	109	/* Don't hit the APIC registers and their friends */
b5229dbb OG	110	if ((pciexbar & mask) >= 0xf0000000U)
068258bc YL	111	return NULL;
	112
	113	if (extend_mmcfg(1) == -1)
	114	return NULL;
	115
	116	fill_one_mmcfg(pciexbar & mask, 0, 0, (len >> 20) - 1);
9358c693 OG	117
	118	return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
	119	}
	120
7fd0da40 YL	121	static const char __init *pci_mmcfg_amd_fam10h(void)
	122	{
	123	u32 low, high, address;
	124	u64 base, msr;
	125	int i;
	126	unsigned segnbits = 0, busnbits;
	127
5f0b2976 YL	128	if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
	129	return NULL;
	130
7fd0da40 YL	131	address = MSR_FAM10H_MMIO_CONF_BASE;
	132	if (rdmsr_safe(address, &low, &high))
	133	return NULL;
	134
	135	msr = high;
	136	msr <<= 32;
	137	msr \|= low;
	138
	139	/* mmconfig is not enable */
	140	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
	141	return NULL;
	142
	143	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
	144
	145	busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
	146	FAM10H_MMIO_CONF_BUSRANGE_MASK;
	147
	148	/*
	149	* only handle bus 0 ?
	150	* need to skip it
	151	*/
	152	if (!busnbits)
	153	return NULL;
	154
	155	if (busnbits > 8) {
	156	segnbits = busnbits - 8;
	157	busnbits = 8;
	158	}
	159
068258bc	160	if (extend_mmcfg(1 << segnbits) == -1)
7fd0da40 YL	161	return NULL;
7fd0da40 YL	162
068258bc YL	163	for (i = 0; i < (1 << segnbits); i++)
068258bc YL	164	fill_one_mmcfg(base + (1<<28) * i, i, 0, (1 << busnbits) - 1);
7fd0da40 YL	165
	166	return "AMD Family 10h NB";
	167	}
	168
5546d6f5 ES	169	static bool __initdata mcp55_checked;
	170	static const char __init *pci_mmcfg_nvidia_mcp55(void)
	171	{
	172	int bus;
	173	int mcp55_mmconf_found = 0;
	174
	175	static const u32 extcfg_regnum = 0x90;
	176	static const u32 extcfg_regsize = 4;
	177	static const u32 extcfg_enable_mask = 1<<31;
	178	static const u32 extcfg_start_mask = 0xff<<16;
	179	static const int extcfg_start_shift = 16;
	180	static const u32 extcfg_size_mask = 0x3<<28;
	181	static const int extcfg_size_shift = 28;
	182	static const int extcfg_sizebus[] = {0x100, 0x80, 0x40, 0x20};
	183	static const u32 extcfg_base_mask[] = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
	184	static const int extcfg_base_lshift = 25;
	185
	186	/*
	187	* do check if amd fam10h already took over
	188	*/
	189	if (!acpi_disabled \|\| pci_mmcfg_config_num \|\| mcp55_checked)
	190	return NULL;
	191
	192	mcp55_checked = true;
	193	for (bus = 0; bus < 256; bus++) {
	194	u64 base;
	195	u32 l, extcfg;
	196	u16 vendor, device;
	197	int start, size_index, end;
	198
	199	raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
	200	vendor = l & 0xffff;
	201	device = (l >> 16) & 0xffff;
	202
	203	if (PCI_VENDOR_ID_NVIDIA != vendor \|\| 0x0369 != device)
	204	continue;
	205
	206	raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
	207	extcfg_regsize, &extcfg);
	208
	209	if (!(extcfg & extcfg_enable_mask))
	210	continue;
	211
	212	if (extend_mmcfg(1) == -1)
	213	continue;
	214
	215	size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
	216	base = extcfg & extcfg_base_mask[size_index];
	217	/* base could > 4G */
	218	base <<= extcfg_base_lshift;
	219	start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
	220	end = start + extcfg_sizebus[size_index] - 1;
	221	fill_one_mmcfg(base, 0, start, end);
	222	mcp55_mmconf_found++;
	223	}
	224
	225	if (!mcp55_mmconf_found)
	226	return NULL;
	227
	228	return "nVidia MCP55";
	229	}
	230
9358c693	231	struct pci_mmcfg_hostbridge_probe {
7fd0da40 YL	232	u32 bus;
7fd0da40 YL	233	u32 devfn;
9358c693 OG	234	u32 vendor;
	235	u32 device;
	236	const char (probe)(void);
	237	};
	238
429d512e	239	static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
7fd0da40 YL	240	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
	241	PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
	242	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
	243	PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
	244	{ 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
	245	0x1200, pci_mmcfg_amd_fam10h },
	246	{ 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
	247	0x1200, pci_mmcfg_amd_fam10h },
5546d6f5 ES	248	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
5546d6f5 ES	249	0x0369, pci_mmcfg_nvidia_mcp55 },
9358c693 OG	250	};
9358c693 OG	251
068258bc YL	252	static int __init cmp_mmcfg(const void x1, const void x2)
	253	{
	254	const typeof(pci_mmcfg_config[0]) *m1 = x1;
	255	const typeof(pci_mmcfg_config[0]) *m2 = x2;
	256	int start1, start2;
	257
	258	start1 = m1->start_bus_number;
	259	start2 = m2->start_bus_number;
	260
	261	return start1 - start2;
	262	}
	263
	264	static void __init pci_mmcfg_check_end_bus_number(void)
	265	{
	266	int i;
	267	typeof(pci_mmcfg_config[0]) cfg, cfgx;
	268
	269	/* sort them at first */
	270	sort(pci_mmcfg_config, pci_mmcfg_config_num,
	271	sizeof(pci_mmcfg_config[0]), cmp_mmcfg, NULL);
	272
	273	/* last one*/
	274	if (pci_mmcfg_config_num > 0) {
	275	i = pci_mmcfg_config_num - 1;
	276	cfg = &pci_mmcfg_config[i];
	277	if (cfg->end_bus_number < cfg->start_bus_number)
	278	cfg->end_bus_number = 255;
	279	}
	280
	281	/* don't overlap please */
	282	for (i = 0; i < pci_mmcfg_config_num - 1; i++) {
	283	cfg = &pci_mmcfg_config[i];
	284	cfgx = &pci_mmcfg_config[i+1];
	285
	286	if (cfg->end_bus_number < cfg->start_bus_number)
	287	cfg->end_bus_number = 255;
	288
	289	if (cfg->end_bus_number >= cfgx->start_bus_number)
	290	cfg->end_bus_number = cfgx->start_bus_number - 1;
	291	}
	292	}
	293
9358c693 OG	294	static int __init pci_mmcfg_check_hostbridge(void)
	295	{
	296	u32 l;
7fd0da40	297	u32 bus, devfn;
9358c693 OG	298	u16 vendor, device;
	299	int i;
	300	const char *name;
	301
bb63b421 YL	302	if (!raw_pci_ops)
	303	return 0;
	304
9358c693 OG	305	pci_mmcfg_config_num = 0;
9358c693 OG	306	pci_mmcfg_config = NULL;
9358c693	307
068258bc	308	for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
7fd0da40 YL	309	bus = pci_mmcfg_probes[i].bus;
7fd0da40 YL	310	devfn = pci_mmcfg_probes[i].devfn;
bb63b421	311	raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
7fd0da40 YL	312	vendor = l & 0xffff;
	313	device = (l >> 16) & 0xffff;
	314
068258bc	315	name = NULL;
429d512e OH	316	if (pci_mmcfg_probes[i].vendor == vendor &&
429d512e OH	317	pci_mmcfg_probes[i].device == device)
9358c693 OG	318	name = pci_mmcfg_probes[i].probe();
9358c693 OG	319
068258bc YL	320	if (name)
	321	printk(KERN_INFO "PCI: Found %s with MMCONFIG support.\n",
	322	name);
9358c693 OG	323	}
9358c693 OG	324
068258bc YL	325	/* some end_bus_number is crazy, fix it */
	326	pci_mmcfg_check_end_bus_number();
	327
	328	return pci_mmcfg_config_num != 0;
9358c693 OG	329	}
9358c693 OG	330
ebd60cd6	331	static void __init pci_mmcfg_insert_resources(void)
6a0668fc	332	{
068258bc	333	#define PCI_MMCFG_RESOURCE_NAME_LEN 24
6a0668fc OG	334	int i;
	335	struct resource *res;
	336	char *names;
	337	unsigned num_buses;
	338
	339	res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
	340	pci_mmcfg_config_num, GFP_KERNEL);
6a0668fc OG	341	if (!res) {
	342	printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
	343	return;
	344	}
	345
	346	names = (void *)&res[pci_mmcfg_config_num];
	347	for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
429d512e OH	348	struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
429d512e OH	349	num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
6a0668fc	350	res->name = names;
068258bc YL	351	snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN,
	352	"PCI MMCONFIG %u [%02x-%02x]", cfg->pci_segment,
	353	cfg->start_bus_number, cfg->end_bus_number);
	354	res->start = cfg->address + (cfg->start_bus_number << 20);
6a0668fc	355	res->end = res->start + (num_buses << 20) - 1;
ebd60cd6	356	res->flags = IORESOURCE_MEM \| IORESOURCE_BUSY;
6a0668fc OG	357	insert_resource(&iomem_resource, res);
	358	names += PCI_MMCFG_RESOURCE_NAME_LEN;
	359	}
a5ba7971 AD	360
	361	/* Mark that the resources have been inserted. */
	362	pci_mmcfg_resources_inserted = 1;
6a0668fc OG	363	}
6a0668fc OG	364
7752d5cf RH	365	static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
	366	void *data)
	367	{
	368	struct resource *mcfg_res = data;
	369	struct acpi_resource_address64 address;
	370	acpi_status status;
	371
	372	if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
	373	struct acpi_resource_fixed_memory32 *fixmem32 =
	374	&res->data.fixed_memory32;
	375	if (!fixmem32)
	376	return AE_OK;
	377	if ((mcfg_res->start >= fixmem32->address) &&
044cd809	378	(mcfg_res->end <= (fixmem32->address +
7752d5cf RH	379	fixmem32->address_length))) {
	380	mcfg_res->flags = 1;
	381	return AE_CTRL_TERMINATE;
	382	}
	383	}
	384	if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
	385	(res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
	386	return AE_OK;
	387
	388	status = acpi_resource_to_address64(res, &address);
	389	if (ACPI_FAILURE(status) \|\|
	390	(address.address_length <= 0) \|\|
	391	(address.resource_type != ACPI_MEMORY_RANGE))
	392	return AE_OK;
	393
	394	if ((mcfg_res->start >= address.minimum) &&
044cd809	395	(mcfg_res->end <= (address.minimum + address.address_length))) {
7752d5cf RH	396	mcfg_res->flags = 1;
	397	return AE_CTRL_TERMINATE;
	398	}
	399	return AE_OK;
	400	}
	401
	402	static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
	403	void context, void *rv)
	404	{
	405	struct resource *mcfg_res = context;
	406
	407	acpi_walk_resources(handle, METHOD_NAME__CRS,
	408	check_mcfg_resource, context);
	409
	410	if (mcfg_res->flags)
	411	return AE_CTRL_TERMINATE;
	412
	413	return AE_OK;
	414	}
	415
a83fe32f	416	static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
7752d5cf RH	417	{
	418	struct resource mcfg_res;
	419
	420	mcfg_res.start = start;
	421	mcfg_res.end = end;
	422	mcfg_res.flags = 0;
	423
	424	acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
	425
	426	if (!mcfg_res.flags)
	427	acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
	428	NULL);
	429
	430	return mcfg_res.flags;
	431	}
	432
a83fe32f YL	433	typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
	434
	435	static int __init is_mmconf_reserved(check_reserved_t is_reserved,
	436	u64 addr, u64 size, int i,
	437	typeof(pci_mmcfg_config[0]) *cfg, int with_e820)
	438	{
	439	u64 old_size = size;
	440	int valid = 0;
	441
044cd809	442	while (!is_reserved(addr, addr + size, E820_RESERVED)) {
a83fe32f YL	443	size >>= 1;
	444	if (size < (16UL<<20))
	445	break;
	446	}
	447
	448	if (size >= (16UL<<20) \|\| size == old_size) {
	449	printk(KERN_NOTICE
	450	"PCI: MCFG area at %Lx reserved in %s\n",
	451	addr, with_e820?"E820":"ACPI motherboard resources");
	452	valid = 1;
	453
	454	if (old_size != size) {
	455	/* update end_bus_number */
	456	cfg->end_bus_number = cfg->start_bus_number + ((size>>20) - 1);
	457	printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx "
	458	"segment %hu buses %u - %u\n",
	459	i, (unsigned long)cfg->address, cfg->pci_segment,
	460	(unsigned int)cfg->start_bus_number,
	461	(unsigned int)cfg->end_bus_number);
	462	}
	463	}
	464
	465	return valid;
	466	}
	467
bb63b421	468	static void __init pci_mmcfg_reject_broken(int early)
44de0203	469	{
26054ed0	470	typeof(pci_mmcfg_config[0]) *cfg;
7752d5cf	471	int i;
26054ed0 OH	472
	473	if ((pci_mmcfg_config_num == 0) \|\|
	474	(pci_mmcfg_config == NULL) \|\|
	475	(pci_mmcfg_config[0].address == 0))
	476	return;
	477
7752d5cf	478	for (i = 0; i < pci_mmcfg_config_num; i++) {
05c58b8a	479	int valid = 0;
a83fe32f YL	480	u64 addr, size;
a83fe32f YL	481
7752d5cf	482	cfg = &pci_mmcfg_config[i];
a83fe32f YL	483	addr = cfg->start_bus_number;
	484	addr <<= 20;
	485	addr += cfg->address;
	486	size = cfg->end_bus_number + 1 - cfg->start_bus_number;
	487	size <<= 20;
05c58b8a	488	printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
7752d5cf RH	489	"segment %hu buses %u - %u\n",
	490	i, (unsigned long)cfg->address, cfg->pci_segment,
	491	(unsigned int)cfg->start_bus_number,
	492	(unsigned int)cfg->end_bus_number);
05c58b8a	493
a83fe32f YL	494	if (!early)
a83fe32f YL	495	valid = is_mmconf_reserved(is_acpi_reserved, addr, size, i, cfg, 0);
05c58b8a YL	496
	497	if (valid)
	498	continue;
	499
	500	if (!early)
7752d5cf RH	501	printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
	502	" reserved in ACPI motherboard resources\n",
	503	cfg->address);
a83fe32f	504
05c58b8a	505	/* Don't try to do this check unless configuration
bb63b421	506	type 1 is available. how about type 2 ?*/
a83fe32f YL	507	if (raw_pci_ops)
a83fe32f YL	508	valid = is_mmconf_reserved(e820_all_mapped, addr, size, i, cfg, 1);
05c58b8a YL	509
	510	if (!valid)
	511	goto reject;
44de0203	512	}
7752d5cf	513
26054ed0 OH	514	return;
	515
	516	reject:
ef310237	517	printk(KERN_INFO "PCI: Not using MMCONFIG.\n");
0b64ad71	518	pci_mmcfg_arch_free();
26054ed0 OH	519	kfree(pci_mmcfg_config);
	520	pci_mmcfg_config = NULL;
	521	pci_mmcfg_config_num = 0;
44de0203 OH	522	}
44de0203 OH	523
05c58b8a	524	static int __initdata known_bridge;
7752d5cf	525
968cbfad	526	static void __init __pci_mmcfg_init(int early)
b7867394	527	{
7752d5cf	528	/* MMCONFIG disabled */
b7867394 OG	529	if ((pci_probe & PCI_PROBE_MMCONF) == 0)
	530	return;
	531
7752d5cf	532	/* MMCONFIG already enabled */
05c58b8a	533	if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
7752d5cf	534	return;
9358c693	535
05c58b8a YL	536	/* for late to exit */
	537	if (known_bridge)
	538	return;
7752d5cf	539
bb63b421	540	if (early) {
05c58b8a YL	541	if (pci_mmcfg_check_hostbridge())
	542	known_bridge = 1;
	543	}
	544
068258bc	545	if (!known_bridge)
05c58b8a	546	acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);
068258bc YL	547
068258bc YL	548	pci_mmcfg_reject_broken(early);
b7867394 OG	549
	550	if ((pci_mmcfg_config_num == 0) \|\|
	551	(pci_mmcfg_config == NULL) \|\|
	552	(pci_mmcfg_config[0].address == 0))
	553	return;
	554
ebd60cd6	555	if (pci_mmcfg_arch_init())
b7867394	556	pci_probe = (pci_probe & ~PCI_PROBE_MASK) \| PCI_PROBE_MMCONF;
ebd60cd6	557	else {
a5ba7971 AD	558	/*
	559	* Signal not to attempt to insert mmcfg resources because
	560	* the architecture mmcfg setup could not initialize.
	561	*/
	562	pci_mmcfg_resources_inserted = 1;
b7867394 OG	563	}
b7867394 OG	564	}
a5ba7971	565
bb63b421	566	void __init pci_mmcfg_early_init(void)
05c58b8a	567	{
bb63b421	568	__pci_mmcfg_init(1);
05c58b8a YL	569	}
	570
	571	void __init pci_mmcfg_late_init(void)
	572	{
bb63b421	573	__pci_mmcfg_init(0);
05c58b8a YL	574	}
05c58b8a YL	575
a5ba7971 AD	576	static int __init pci_mmcfg_late_insert_resources(void)
	577	{
	578	/*
	579	* If resources are already inserted or we are not using MMCONFIG,
	580	* don't insert the resources.
	581	*/
	582	if ((pci_mmcfg_resources_inserted == 1) \|\|
	583	(pci_probe & PCI_PROBE_MMCONF) == 0 \|\|
	584	(pci_mmcfg_config_num == 0) \|\|
	585	(pci_mmcfg_config == NULL) \|\|
	586	(pci_mmcfg_config[0].address == 0))
	587	return 1;
	588
	589	/*
	590	* Attempt to insert the mmcfg resources but not with the busy flag
	591	* marked so it won't cause request errors when __request_region is
	592	* called.
	593	*/
ebd60cd6	594	pci_mmcfg_insert_resources();
a5ba7971 AD	595
	596	return 0;
	597	}
	598
	599	/*
	600	* Perform MMCONFIG resource insertion after PCI initialization to allow for
	601	* misprogrammed MCFG tables that state larger sizes but actually conflict
	602	* with other system resources.
	603	*/
	604	late_initcall(pci_mmcfg_late_insert_resources);