[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / pci / mmconfig-shared.c

/*
 * mmconfig-shared.c - Low-level direct PCI config space access via
 *                     MMCONFIG - common code between i386 and x86-64.
 *
 * This code does:
 * - known chipset handling
 * - ACPI decoding and validation
 *
 * Per-architecture code takes care of the mappings and accesses
 * themselves.
 */

#include <linux/pci.h>
#include <linux/init.h>
#include <linux/acpi.h>
#include <linux/bitmap.h>
#include <asm/e820.h>

#include "pci.h"

/* aperture is up to 256MB but BIOS may reserve less */
#define MMCONFIG_APER_MIN	(2 * 1024*1024)
#define MMCONFIG_APER_MAX	(256 * 1024*1024)

/* Indicate if the mmcfg resources have been placed into the resource table. */
static int __initdata pci_mmcfg_resources_inserted;

static const char __init *pci_mmcfg_e7520(void)
{
	u32 win;
	pci_direct_conf1.read(0, 0, PCI_DEVFN(0,0), 0xce, 2, &win);

	win = win & 0xf000;
	if(win == 0x0000 || win == 0xf000)
		pci_mmcfg_config_num = 0;
	else {
		pci_mmcfg_config_num = 1;
		pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
		if (!pci_mmcfg_config)
			return NULL;
		pci_mmcfg_config[0].address = win << 16;
		pci_mmcfg_config[0].pci_segment = 0;
		pci_mmcfg_config[0].start_bus_number = 0;
		pci_mmcfg_config[0].end_bus_number = 255;
	}

	return "Intel Corporation E7520 Memory Controller Hub";
}

static const char __init *pci_mmcfg_intel_945(void)
{
	u32 pciexbar, mask = 0, len = 0;

	pci_mmcfg_config_num = 1;

	pci_direct_conf1.read(0, 0, PCI_DEVFN(0,0), 0x48, 4, &pciexbar);

	/* Enable bit */
	if (!(pciexbar & 1))
		pci_mmcfg_config_num = 0;

	/* Size bits */
	switch ((pciexbar >> 1) & 3) {
	case 0:
		mask = 0xf0000000U;
		len  = 0x10000000U;
		break;
	case 1:
		mask = 0xf8000000U;
		len  = 0x08000000U;
		break;
	case 2:
		mask = 0xfc000000U;
		len  = 0x04000000U;
		break;
	default:
		pci_mmcfg_config_num = 0;
	}

	/* Errata #2, things break when not aligned on a 256Mb boundary */
	/* Can only happen in 64M/128M mode */

	if ((pciexbar & mask) & 0x0fffffffU)
		pci_mmcfg_config_num = 0;

	/* Don't hit the APIC registers and their friends */
	if ((pciexbar & mask) >= 0xf0000000U)
		pci_mmcfg_config_num = 0;

	if (pci_mmcfg_config_num) {
		pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
		if (!pci_mmcfg_config)
			return NULL;
		pci_mmcfg_config[0].address = pciexbar & mask;
		pci_mmcfg_config[0].pci_segment = 0;
		pci_mmcfg_config[0].start_bus_number = 0;
		pci_mmcfg_config[0].end_bus_number = (len >> 20) - 1;
	}

	return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
}

static const char __init *pci_mmcfg_amd_fam10h(void)
{
	u32 low, high, address;
	u64 base, msr;
	int i;
	unsigned segnbits = 0, busnbits;

	address = MSR_FAM10H_MMIO_CONF_BASE;
	if (rdmsr_safe(address, &low, &high))
		return NULL;

	msr = high;
	msr <<= 32;
	msr |= low;

	/* mmconfig is not enable */
	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
		return NULL;

	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);

	busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
			 FAM10H_MMIO_CONF_BUSRANGE_MASK;

	/*
	 * only handle bus 0 ?
	 * need to skip it
	 */
	if (!busnbits)
		return NULL;

	if (busnbits > 8) {
		segnbits = busnbits - 8;
		busnbits = 8;
	}

	pci_mmcfg_config_num = (1 << segnbits);
	pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]) *
				   pci_mmcfg_config_num, GFP_KERNEL);
	if (!pci_mmcfg_config)
		return NULL;

	for (i = 0; i < (1 << segnbits); i++) {
		pci_mmcfg_config[i].address = base + (1<<28) * i;
		pci_mmcfg_config[i].pci_segment = i;
		pci_mmcfg_config[i].start_bus_number = 0;
		pci_mmcfg_config[i].end_bus_number = (1 << busnbits) - 1;
	}

	return "AMD Family 10h NB";
}

struct pci_mmcfg_hostbridge_probe {
	u32 bus;
	u32 devfn;
	u32 vendor;
	u32 device;
	const char *(*probe)(void);
};

static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
	  PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
	  PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
	{ 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
	  0x1200, pci_mmcfg_amd_fam10h },
	{ 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
	  0x1200, pci_mmcfg_amd_fam10h },
};

static int __init pci_mmcfg_check_hostbridge(void)
{
	u32 l;
	u32 bus, devfn;
	u16 vendor, device;
	int i;
	const char *name;

	pci_mmcfg_config_num = 0;
	pci_mmcfg_config = NULL;
	name = NULL;

	for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
		bus =  pci_mmcfg_probes[i].bus;
		devfn = pci_mmcfg_probes[i].devfn;
		pci_direct_conf1.read(0, bus, devfn, 0, 4, &l);
		vendor = l & 0xffff;
		device = (l >> 16) & 0xffff;

		if (pci_mmcfg_probes[i].vendor == vendor &&
		    pci_mmcfg_probes[i].device == device)
			name = pci_mmcfg_probes[i].probe();
	}

	if (name) {
		printk(KERN_INFO "PCI: Found %s %s MMCONFIG support.\n",
		       name, pci_mmcfg_config_num ? "with" : "without");
	}

	return name != NULL;
}

static void __init pci_mmcfg_insert_resources(unsigned long resource_flags)
{
#define PCI_MMCFG_RESOURCE_NAME_LEN 19
	int i;
	struct resource *res;
	char *names;
	unsigned num_buses;

	res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
			pci_mmcfg_config_num, GFP_KERNEL);
	if (!res) {
		printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
		return;
	}

	names = (void *)&res[pci_mmcfg_config_num];
	for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
		struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
		num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
		res->name = names;
		snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, "PCI MMCONFIG %u",
			 cfg->pci_segment);
		res->start = cfg->address;
		res->end = res->start + (num_buses << 20) - 1;
		res->flags = IORESOURCE_MEM | resource_flags;
		insert_resource(&iomem_resource, res);
		names += PCI_MMCFG_RESOURCE_NAME_LEN;
	}

	/* Mark that the resources have been inserted. */
	pci_mmcfg_resources_inserted = 1;
}

static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
					      void *data)
{
	struct resource *mcfg_res = data;
	struct acpi_resource_address64 address;
	acpi_status status;

	if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
		struct acpi_resource_fixed_memory32 *fixmem32 =
			&res->data.fixed_memory32;
		if (!fixmem32)
			return AE_OK;
		if ((mcfg_res->start >= fixmem32->address) &&
		    (mcfg_res->end < (fixmem32->address +
				      fixmem32->address_length))) {
			mcfg_res->flags = 1;
			return AE_CTRL_TERMINATE;
		}
	}
	if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
	    (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
		return AE_OK;

	status = acpi_resource_to_address64(res, &address);
	if (ACPI_FAILURE(status) ||
	   (address.address_length <= 0) ||
	   (address.resource_type != ACPI_MEMORY_RANGE))
		return AE_OK;

	if ((mcfg_res->start >= address.minimum) &&
	    (mcfg_res->end < (address.minimum + address.address_length))) {
		mcfg_res->flags = 1;
		return AE_CTRL_TERMINATE;
	}
	return AE_OK;
}

static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
		void *context, void **rv)
{
	struct resource *mcfg_res = context;

	acpi_walk_resources(handle, METHOD_NAME__CRS,
			    check_mcfg_resource, context);

	if (mcfg_res->flags)
		return AE_CTRL_TERMINATE;

	return AE_OK;
}

static int __init is_acpi_reserved(unsigned long start, unsigned long end)
{
	struct resource mcfg_res;

	mcfg_res.start = start;
	mcfg_res.end = end;
	mcfg_res.flags = 0;

	acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);

	if (!mcfg_res.flags)
		acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
				 NULL);

	return mcfg_res.flags;
}

static void __init pci_mmcfg_reject_broken(int type, int early)
{
	typeof(pci_mmcfg_config[0]) *cfg;
	int i;

	if ((pci_mmcfg_config_num == 0) ||
	    (pci_mmcfg_config == NULL) ||
	    (pci_mmcfg_config[0].address == 0))
		return;

	cfg = &pci_mmcfg_config[0];

	for (i = 0; i < pci_mmcfg_config_num; i++) {
		int valid = 0;
		u32 size = (cfg->end_bus_number + 1) << 20;
		cfg = &pci_mmcfg_config[i];
		printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
		       "segment %hu buses %u - %u\n",
		       i, (unsigned long)cfg->address, cfg->pci_segment,
		       (unsigned int)cfg->start_bus_number,
		       (unsigned int)cfg->end_bus_number);

		if (!early &&
		    is_acpi_reserved(cfg->address, cfg->address + size - 1)) {
			printk(KERN_NOTICE "PCI: MCFG area at %Lx reserved "
			       "in ACPI motherboard resources\n",
			       cfg->address);
			valid = 1;
		}

		if (valid)
			continue;

		if (!early)
			printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
			       " reserved in ACPI motherboard resources\n",
			       cfg->address);
		/* Don't try to do this check unless configuration
		   type 1 is available. */
		if (type == 1 && e820_all_mapped(cfg->address,
						  cfg->address + size - 1,
						  E820_RESERVED)) {
			printk(KERN_NOTICE
			       "PCI: MCFG area at %Lx reserved in E820\n",
			       cfg->address);
			valid = 1;
		}

		if (!valid)
			goto reject;
	}

	return;

reject:
	printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
	pci_mmcfg_arch_free();
	kfree(pci_mmcfg_config);
	pci_mmcfg_config = NULL;
	pci_mmcfg_config_num = 0;
}

static int __initdata known_bridge;

void __init __pci_mmcfg_init(int type, int early)
{
	/* MMCONFIG disabled */
	if ((pci_probe & PCI_PROBE_MMCONF) == 0)
		return;

	/* MMCONFIG already enabled */
	if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
		return;

	/* for late to exit */
	if (known_bridge)
		return;

	if (early && type == 1) {
		if (pci_mmcfg_check_hostbridge())
			known_bridge = 1;
	}

	if (!known_bridge) {
		acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);
		pci_mmcfg_reject_broken(type, early);
	}

	if ((pci_mmcfg_config_num == 0) ||
	    (pci_mmcfg_config == NULL) ||
	    (pci_mmcfg_config[0].address == 0))
		return;

	if (pci_mmcfg_arch_init()) {
		if (known_bridge)
			pci_mmcfg_insert_resources(IORESOURCE_BUSY);
		pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
	} else {
		/*
		 * Signal not to attempt to insert mmcfg resources because
		 * the architecture mmcfg setup could not initialize.
		 */
		pci_mmcfg_resources_inserted = 1;
	}
}

void __init pci_mmcfg_early_init(int type)
{
	__pci_mmcfg_init(type, 1);
}

void __init pci_mmcfg_late_init(void)
{
	int type = 0;

	if (pci_probe & PCI_PROBE_CONF1)
		type = 1;

	__pci_mmcfg_init(type, 0);
}

static int __init pci_mmcfg_late_insert_resources(void)
{
	/*
	 * If resources are already inserted or we are not using MMCONFIG,
	 * don't insert the resources.
	 */
	if ((pci_mmcfg_resources_inserted == 1) ||
	    (pci_probe & PCI_PROBE_MMCONF) == 0 ||
	    (pci_mmcfg_config_num == 0) ||
	    (pci_mmcfg_config == NULL) ||
	    (pci_mmcfg_config[0].address == 0))
		return 1;

	/*
	 * Attempt to insert the mmcfg resources but not with the busy flag
	 * marked so it won't cause request errors when __request_region is
	 * called.
	 */
	pci_mmcfg_insert_resources(0);

	return 0;
}

/*
 * Perform MMCONFIG resource insertion after PCI initialization to allow for
 * misprogrammed MCFG tables that state larger sizes but actually conflict
 * with other system resources.
 */
late_initcall(pci_mmcfg_late_insert_resources);
Commit	Line	Data
b7867394 OG	1	/*
	2	* mmconfig-shared.c - Low-level direct PCI config space access via
	3	* MMCONFIG - common code between i386 and x86-64.
	4	*
	5	* This code does:
9358c693	6	* - known chipset handling
b7867394 OG	7	* - ACPI decoding and validation
	8	*
	9	* Per-architecture code takes care of the mappings and accesses
	10	* themselves.
	11	*/
	12
	13	#include <linux/pci.h>
	14	#include <linux/init.h>
	15	#include <linux/acpi.h>
	16	#include <linux/bitmap.h>
	17	#include <asm/e820.h>
	18
	19	#include "pci.h"
	20
	21	/* aperture is up to 256MB but BIOS may reserve less */
	22	#define MMCONFIG_APER_MIN (2 * 1024*1024)
	23	#define MMCONFIG_APER_MAX (256 * 1024*1024)
	24
a5ba7971 AD	25	/* Indicate if the mmcfg resources have been placed into the resource table. */
	26	static int __initdata pci_mmcfg_resources_inserted;
	27
429d512e	28	static const char __init *pci_mmcfg_e7520(void)
9358c693 OG	29	{
9358c693 OG	30	u32 win;
b6ce068a	31	pci_direct_conf1.read(0, 0, PCI_DEVFN(0,0), 0xce, 2, &win);
9358c693	32
b5229dbb OG	33	win = win & 0xf000;
	34	if(win == 0x0000 \|\| win == 0xf000)
	35	pci_mmcfg_config_num = 0;
	36	else {
	37	pci_mmcfg_config_num = 1;
	38	pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
	39	if (!pci_mmcfg_config)
	40	return NULL;
	41	pci_mmcfg_config[0].address = win << 16;
	42	pci_mmcfg_config[0].pci_segment = 0;
	43	pci_mmcfg_config[0].start_bus_number = 0;
	44	pci_mmcfg_config[0].end_bus_number = 255;
	45	}
9358c693 OG	46
	47	return "Intel Corporation E7520 Memory Controller Hub";
	48	}
	49
429d512e	50	static const char __init *pci_mmcfg_intel_945(void)
9358c693 OG	51	{
	52	u32 pciexbar, mask = 0, len = 0;
	53
	54	pci_mmcfg_config_num = 1;
	55
b6ce068a	56	pci_direct_conf1.read(0, 0, PCI_DEVFN(0,0), 0x48, 4, &pciexbar);
9358c693 OG	57
	58	/* Enable bit */
	59	if (!(pciexbar & 1))
	60	pci_mmcfg_config_num = 0;
	61
	62	/* Size bits */
	63	switch ((pciexbar >> 1) & 3) {
	64	case 0:
	65	mask = 0xf0000000U;
	66	len = 0x10000000U;
	67	break;
	68	case 1:
	69	mask = 0xf8000000U;
	70	len = 0x08000000U;
	71	break;
	72	case 2:
	73	mask = 0xfc000000U;
	74	len = 0x04000000U;
	75	break;
	76	default:
	77	pci_mmcfg_config_num = 0;
	78	}
	79
	80	/* Errata #2, things break when not aligned on a 256Mb boundary */
	81	/* Can only happen in 64M/128M mode */
	82
	83	if ((pciexbar & mask) & 0x0fffffffU)
	84	pci_mmcfg_config_num = 0;
	85
b5229dbb OG	86	/* Don't hit the APIC registers and their friends */
	87	if ((pciexbar & mask) >= 0xf0000000U)
	88	pci_mmcfg_config_num = 0;
	89
9358c693 OG	90	if (pci_mmcfg_config_num) {
	91	pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
	92	if (!pci_mmcfg_config)
	93	return NULL;
	94	pci_mmcfg_config[0].address = pciexbar & mask;
	95	pci_mmcfg_config[0].pci_segment = 0;
	96	pci_mmcfg_config[0].start_bus_number = 0;
	97	pci_mmcfg_config[0].end_bus_number = (len >> 20) - 1;
	98	}
	99
	100	return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
	101	}
	102
7fd0da40 YL	103	static const char __init *pci_mmcfg_amd_fam10h(void)
	104	{
	105	u32 low, high, address;
	106	u64 base, msr;
	107	int i;
	108	unsigned segnbits = 0, busnbits;
	109
	110	address = MSR_FAM10H_MMIO_CONF_BASE;
	111	if (rdmsr_safe(address, &low, &high))
	112	return NULL;
	113
	114	msr = high;
	115	msr <<= 32;
	116	msr \|= low;
	117
	118	/* mmconfig is not enable */
	119	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
	120	return NULL;
	121
	122	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
	123
	124	busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
	125	FAM10H_MMIO_CONF_BUSRANGE_MASK;
	126
	127	/*
	128	* only handle bus 0 ?
	129	* need to skip it
	130	*/
	131	if (!busnbits)
	132	return NULL;
	133
	134	if (busnbits > 8) {
	135	segnbits = busnbits - 8;
	136	busnbits = 8;
	137	}
	138
	139	pci_mmcfg_config_num = (1 << segnbits);
	140	pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]) *
	141	pci_mmcfg_config_num, GFP_KERNEL);
	142	if (!pci_mmcfg_config)
	143	return NULL;
	144
	145	for (i = 0; i < (1 << segnbits); i++) {
	146	pci_mmcfg_config[i].address = base + (1<<28) * i;
	147	pci_mmcfg_config[i].pci_segment = i;
	148	pci_mmcfg_config[i].start_bus_number = 0;
	149	pci_mmcfg_config[i].end_bus_number = (1 << busnbits) - 1;
	150	}
	151
	152	return "AMD Family 10h NB";
	153	}
	154
9358c693	155	struct pci_mmcfg_hostbridge_probe {
7fd0da40 YL	156	u32 bus;
7fd0da40 YL	157	u32 devfn;
9358c693 OG	158	u32 vendor;
	159	u32 device;
	160	const char (probe)(void);
	161	};
	162
429d512e	163	static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
7fd0da40 YL	164	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
	165	PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
	166	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
	167	PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
	168	{ 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
	169	0x1200, pci_mmcfg_amd_fam10h },
	170	{ 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
	171	0x1200, pci_mmcfg_amd_fam10h },
9358c693 OG	172	};
	173
	174	static int __init pci_mmcfg_check_hostbridge(void)
	175	{
	176	u32 l;
7fd0da40	177	u32 bus, devfn;
9358c693 OG	178	u16 vendor, device;
	179	int i;
	180	const char *name;
	181
9358c693 OG	182	pci_mmcfg_config_num = 0;
	183	pci_mmcfg_config = NULL;
	184	name = NULL;
	185
429d512e	186	for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
7fd0da40 YL	187	bus = pci_mmcfg_probes[i].bus;
	188	devfn = pci_mmcfg_probes[i].devfn;
	189	pci_direct_conf1.read(0, bus, devfn, 0, 4, &l);
	190	vendor = l & 0xffff;
	191	device = (l >> 16) & 0xffff;
	192
429d512e OH	193	if (pci_mmcfg_probes[i].vendor == vendor &&
429d512e OH	194	pci_mmcfg_probes[i].device == device)
9358c693	195	name = pci_mmcfg_probes[i].probe();
429d512e	196	}
9358c693 OG	197
9358c693 OG	198	if (name) {
429d512e OH	199	printk(KERN_INFO "PCI: Found %s %s MMCONFIG support.\n",
429d512e OH	200	name, pci_mmcfg_config_num ? "with" : "without");
9358c693 OG	201	}
	202
	203	return name != NULL;
	204	}
	205
a5ba7971	206	static void __init pci_mmcfg_insert_resources(unsigned long resource_flags)
6a0668fc OG	207	{
	208	#define PCI_MMCFG_RESOURCE_NAME_LEN 19
	209	int i;
	210	struct resource *res;
	211	char *names;
	212	unsigned num_buses;
	213
	214	res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
	215	pci_mmcfg_config_num, GFP_KERNEL);
6a0668fc OG	216	if (!res) {
	217	printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
	218	return;
	219	}
	220
	221	names = (void *)&res[pci_mmcfg_config_num];
	222	for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
429d512e OH	223	struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
429d512e OH	224	num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
6a0668fc OG	225	res->name = names;
6a0668fc OG	226	snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, "PCI MMCONFIG %u",
429d512e OH	227	cfg->pci_segment);
429d512e OH	228	res->start = cfg->address;
6a0668fc	229	res->end = res->start + (num_buses << 20) - 1;
a5ba7971	230	res->flags = IORESOURCE_MEM \| resource_flags;
6a0668fc OG	231	insert_resource(&iomem_resource, res);
	232	names += PCI_MMCFG_RESOURCE_NAME_LEN;
	233	}
a5ba7971 AD	234
	235	/* Mark that the resources have been inserted. */
	236	pci_mmcfg_resources_inserted = 1;
6a0668fc OG	237	}
6a0668fc OG	238
7752d5cf RH	239	static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
	240	void *data)
	241	{
	242	struct resource *mcfg_res = data;
	243	struct acpi_resource_address64 address;
	244	acpi_status status;
	245
	246	if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
	247	struct acpi_resource_fixed_memory32 *fixmem32 =
	248	&res->data.fixed_memory32;
	249	if (!fixmem32)
	250	return AE_OK;
	251	if ((mcfg_res->start >= fixmem32->address) &&
	252	(mcfg_res->end < (fixmem32->address +
	253	fixmem32->address_length))) {
	254	mcfg_res->flags = 1;
	255	return AE_CTRL_TERMINATE;
	256	}
	257	}
	258	if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
	259	(res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
	260	return AE_OK;
	261
	262	status = acpi_resource_to_address64(res, &address);
	263	if (ACPI_FAILURE(status) \|\|
	264	(address.address_length <= 0) \|\|
	265	(address.resource_type != ACPI_MEMORY_RANGE))
	266	return AE_OK;
	267
	268	if ((mcfg_res->start >= address.minimum) &&
	269	(mcfg_res->end < (address.minimum + address.address_length))) {
	270	mcfg_res->flags = 1;
	271	return AE_CTRL_TERMINATE;
	272	}
	273	return AE_OK;
	274	}
	275
	276	static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
	277	void context, void *rv)
	278	{
	279	struct resource *mcfg_res = context;
	280
	281	acpi_walk_resources(handle, METHOD_NAME__CRS,
	282	check_mcfg_resource, context);
	283
	284	if (mcfg_res->flags)
	285	return AE_CTRL_TERMINATE;
	286
	287	return AE_OK;
	288	}
	289
	290	static int __init is_acpi_reserved(unsigned long start, unsigned long end)
	291	{
	292	struct resource mcfg_res;
	293
	294	mcfg_res.start = start;
	295	mcfg_res.end = end;
	296	mcfg_res.flags = 0;
	297
	298	acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
	299
	300	if (!mcfg_res.flags)
	301	acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
	302	NULL);
303
304	return mcfg_res.flags;
305	}
306
05c58b8a	307	static void __init pci_mmcfg_reject_broken(int type, int early)
44de0203	308	{
26054ed0	309	typeof(pci_mmcfg_config[0]) *cfg;
7752d5cf	310	int i;
26054ed0 OH	311
	312	if ((pci_mmcfg_config_num == 0) \|\|
	313	(pci_mmcfg_config == NULL) \|\|
	314	(pci_mmcfg_config[0].address == 0))
	315	return;
	316
	317	cfg = &pci_mmcfg_config[0];
44de0203	318
7752d5cf	319	for (i = 0; i < pci_mmcfg_config_num; i++) {
05c58b8a	320	int valid = 0;
7752d5cf RH	321	u32 size = (cfg->end_bus_number + 1) << 20;
7752d5cf RH	322	cfg = &pci_mmcfg_config[i];
05c58b8a	323	printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
7752d5cf RH	324	"segment %hu buses %u - %u\n",
	325	i, (unsigned long)cfg->address, cfg->pci_segment,
	326	(unsigned int)cfg->start_bus_number,
	327	(unsigned int)cfg->end_bus_number);
05c58b8a YL	328
	329	if (!early &&
	330	is_acpi_reserved(cfg->address, cfg->address + size - 1)) {
7752d5cf RH	331	printk(KERN_NOTICE "PCI: MCFG area at %Lx reserved "
	332	"in ACPI motherboard resources\n",
	333	cfg->address);
05c58b8a YL	334	valid = 1;
	335	}
	336
	337	if (valid)
	338	continue;
	339
	340	if (!early)
7752d5cf RH	341	printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
	342	" reserved in ACPI motherboard resources\n",
	343	cfg->address);
05c58b8a YL	344	/* Don't try to do this check unless configuration
	345	type 1 is available. */
	346	if (type == 1 && e820_all_mapped(cfg->address,
	347	cfg->address + size - 1,
	348	E820_RESERVED)) {
	349	printk(KERN_NOTICE
	350	"PCI: MCFG area at %Lx reserved in E820\n",
	351	cfg->address);
	352	valid = 1;
7752d5cf	353	}
05c58b8a YL	354
	355	if (!valid)
	356	goto reject;
44de0203	357	}
7752d5cf	358
26054ed0 OH	359	return;
	360
	361	reject:
	362	printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
0b64ad71	363	pci_mmcfg_arch_free();
26054ed0 OH	364	kfree(pci_mmcfg_config);
	365	pci_mmcfg_config = NULL;
	366	pci_mmcfg_config_num = 0;
44de0203 OH	367	}
44de0203 OH	368
05c58b8a	369	static int __initdata known_bridge;
7752d5cf	370
05c58b8a	371	void __init __pci_mmcfg_init(int type, int early)
b7867394	372	{
7752d5cf	373	/* MMCONFIG disabled */
b7867394 OG	374	if ((pci_probe & PCI_PROBE_MMCONF) == 0)
	375	return;
	376
7752d5cf	377	/* MMCONFIG already enabled */
05c58b8a	378	if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
7752d5cf	379	return;
9358c693	380
05c58b8a YL	381	/* for late to exit */
	382	if (known_bridge)
	383	return;
7752d5cf	384
05c58b8a YL	385	if (early && type == 1) {
	386	if (pci_mmcfg_check_hostbridge())
	387	known_bridge = 1;
	388	}
	389
	390	if (!known_bridge) {
	391	acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);
	392	pci_mmcfg_reject_broken(type, early);
	393	}
b7867394 OG	394
	395	if ((pci_mmcfg_config_num == 0) \|\|
	396	(pci_mmcfg_config == NULL) \|\|
	397	(pci_mmcfg_config[0].address == 0))
	398	return;
	399
b7867394	400	if (pci_mmcfg_arch_init()) {
6a0668fc	401	if (known_bridge)
a5ba7971	402	pci_mmcfg_insert_resources(IORESOURCE_BUSY);
b7867394	403	pci_probe = (pci_probe & ~PCI_PROBE_MASK) \| PCI_PROBE_MMCONF;
a5ba7971 AD	404	} else {
	405	/*
	406	* Signal not to attempt to insert mmcfg resources because
	407	* the architecture mmcfg setup could not initialize.
	408	*/
	409	pci_mmcfg_resources_inserted = 1;
b7867394 OG	410	}
b7867394 OG	411	}
a5ba7971	412
05c58b8a YL	413	void __init pci_mmcfg_early_init(int type)
	414	{
	415	__pci_mmcfg_init(type, 1);
	416	}
	417
	418	void __init pci_mmcfg_late_init(void)
	419	{
	420	int type = 0;
	421
	422	if (pci_probe & PCI_PROBE_CONF1)
	423	type = 1;
	424
	425	__pci_mmcfg_init(type, 0);
	426	}
	427
a5ba7971 AD	428	static int __init pci_mmcfg_late_insert_resources(void)
	429	{
	430	/*
	431	* If resources are already inserted or we are not using MMCONFIG,
	432	* don't insert the resources.
	433	*/
	434	if ((pci_mmcfg_resources_inserted == 1) \|\|
	435	(pci_probe & PCI_PROBE_MMCONF) == 0 \|\|
	436	(pci_mmcfg_config_num == 0) \|\|
	437	(pci_mmcfg_config == NULL) \|\|
	438	(pci_mmcfg_config[0].address == 0))
	439	return 1;
	440
	441	/*
	442	* Attempt to insert the mmcfg resources but not with the busy flag
	443	* marked so it won't cause request errors when __request_region is
	444	* called.
	445	*/
	446	pci_mmcfg_insert_resources(0);
	447
	448	return 0;
	449	}
	450
	451	/*
	452	* Perform MMCONFIG resource insertion after PCI initialization to allow for
	453	* misprogrammed MCFG tables that state larger sizes but actually conflict
	454	* with other system resources.
	455	*/
	456	late_initcall(pci_mmcfg_late_insert_resources);