Commit | Line | Data |
---|---|---|
b7867394 OG |
1 | /* |
2 | * mmconfig-shared.c - Low-level direct PCI config space access via | |
3 | * MMCONFIG - common code between i386 and x86-64. | |
4 | * | |
5 | * This code does: | |
9358c693 | 6 | * - known chipset handling |
b7867394 OG |
7 | * - ACPI decoding and validation |
8 | * | |
9 | * Per-architecture code takes care of the mappings and accesses | |
10 | * themselves. | |
11 | */ | |
12 | ||
13 | #include <linux/pci.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/acpi.h> | |
16 | #include <linux/bitmap.h> | |
068258bc | 17 | #include <linux/sort.h> |
b7867394 | 18 | #include <asm/e820.h> |
82487711 | 19 | #include <asm/pci_x86.h> |
b7867394 | 20 | |
a192a958 LB |
21 | #define PREFIX "ACPI: " |
22 | ||
b7867394 OG |
23 | /* aperture is up to 256MB but BIOS may reserve less */ |
24 | #define MMCONFIG_APER_MIN (2 * 1024*1024) | |
25 | #define MMCONFIG_APER_MAX (256 * 1024*1024) | |
26 | ||
a5ba7971 AD |
27 | /* Indicate if the mmcfg resources have been placed into the resource table. */ |
28 | static int __initdata pci_mmcfg_resources_inserted; | |
29 | ||
068258bc YL |
30 | static __init int extend_mmcfg(int num) |
31 | { | |
32 | struct acpi_mcfg_allocation *new; | |
33 | int new_num = pci_mmcfg_config_num + num; | |
34 | ||
35 | new = kzalloc(sizeof(pci_mmcfg_config[0]) * new_num, GFP_KERNEL); | |
36 | if (!new) | |
37 | return -1; | |
38 | ||
39 | if (pci_mmcfg_config) { | |
40 | memcpy(new, pci_mmcfg_config, | |
41 | sizeof(pci_mmcfg_config[0]) * new_num); | |
42 | kfree(pci_mmcfg_config); | |
43 | } | |
44 | pci_mmcfg_config = new; | |
45 | ||
46 | return 0; | |
47 | } | |
48 | ||
49 | static __init void fill_one_mmcfg(u64 addr, int segment, int start, int end) | |
50 | { | |
51 | int i = pci_mmcfg_config_num; | |
52 | ||
53 | pci_mmcfg_config_num++; | |
54 | pci_mmcfg_config[i].address = addr; | |
55 | pci_mmcfg_config[i].pci_segment = segment; | |
56 | pci_mmcfg_config[i].start_bus_number = start; | |
57 | pci_mmcfg_config[i].end_bus_number = end; | |
58 | } | |
59 | ||
429d512e | 60 | static const char __init *pci_mmcfg_e7520(void) |
9358c693 OG |
61 | { |
62 | u32 win; | |
bb63b421 | 63 | raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win); |
9358c693 | 64 | |
b5229dbb | 65 | win = win & 0xf000; |
068258bc YL |
66 | if (win == 0x0000 || win == 0xf000) |
67 | return NULL; | |
68 | ||
69 | if (extend_mmcfg(1) == -1) | |
70 | return NULL; | |
71 | ||
72 | fill_one_mmcfg(win << 16, 0, 0, 255); | |
9358c693 OG |
73 | |
74 | return "Intel Corporation E7520 Memory Controller Hub"; | |
75 | } | |
76 | ||
429d512e | 77 | static const char __init *pci_mmcfg_intel_945(void) |
9358c693 OG |
78 | { |
79 | u32 pciexbar, mask = 0, len = 0; | |
80 | ||
bb63b421 | 81 | raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar); |
9358c693 OG |
82 | |
83 | /* Enable bit */ | |
84 | if (!(pciexbar & 1)) | |
068258bc | 85 | return NULL; |
9358c693 OG |
86 | |
87 | /* Size bits */ | |
88 | switch ((pciexbar >> 1) & 3) { | |
89 | case 0: | |
90 | mask = 0xf0000000U; | |
91 | len = 0x10000000U; | |
92 | break; | |
93 | case 1: | |
94 | mask = 0xf8000000U; | |
95 | len = 0x08000000U; | |
96 | break; | |
97 | case 2: | |
98 | mask = 0xfc000000U; | |
99 | len = 0x04000000U; | |
100 | break; | |
101 | default: | |
068258bc | 102 | return NULL; |
9358c693 OG |
103 | } |
104 | ||
105 | /* Errata #2, things break when not aligned on a 256Mb boundary */ | |
106 | /* Can only happen in 64M/128M mode */ | |
107 | ||
108 | if ((pciexbar & mask) & 0x0fffffffU) | |
068258bc | 109 | return NULL; |
9358c693 | 110 | |
b5229dbb OG |
111 | /* Don't hit the APIC registers and their friends */ |
112 | if ((pciexbar & mask) >= 0xf0000000U) | |
068258bc YL |
113 | return NULL; |
114 | ||
115 | if (extend_mmcfg(1) == -1) | |
116 | return NULL; | |
117 | ||
118 | fill_one_mmcfg(pciexbar & mask, 0, 0, (len >> 20) - 1); | |
9358c693 OG |
119 | |
120 | return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub"; | |
121 | } | |
122 | ||
7fd0da40 YL |
123 | static const char __init *pci_mmcfg_amd_fam10h(void) |
124 | { | |
125 | u32 low, high, address; | |
126 | u64 base, msr; | |
127 | int i; | |
128 | unsigned segnbits = 0, busnbits; | |
129 | ||
5f0b2976 YL |
130 | if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF)) |
131 | return NULL; | |
132 | ||
7fd0da40 YL |
133 | address = MSR_FAM10H_MMIO_CONF_BASE; |
134 | if (rdmsr_safe(address, &low, &high)) | |
135 | return NULL; | |
136 | ||
137 | msr = high; | |
138 | msr <<= 32; | |
139 | msr |= low; | |
140 | ||
141 | /* mmconfig is not enable */ | |
142 | if (!(msr & FAM10H_MMIO_CONF_ENABLE)) | |
143 | return NULL; | |
144 | ||
145 | base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT); | |
146 | ||
147 | busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) & | |
148 | FAM10H_MMIO_CONF_BUSRANGE_MASK; | |
149 | ||
150 | /* | |
151 | * only handle bus 0 ? | |
152 | * need to skip it | |
153 | */ | |
154 | if (!busnbits) | |
155 | return NULL; | |
156 | ||
157 | if (busnbits > 8) { | |
158 | segnbits = busnbits - 8; | |
159 | busnbits = 8; | |
160 | } | |
161 | ||
068258bc | 162 | if (extend_mmcfg(1 << segnbits) == -1) |
7fd0da40 YL |
163 | return NULL; |
164 | ||
068258bc YL |
165 | for (i = 0; i < (1 << segnbits); i++) |
166 | fill_one_mmcfg(base + (1<<28) * i, i, 0, (1 << busnbits) - 1); | |
7fd0da40 YL |
167 | |
168 | return "AMD Family 10h NB"; | |
169 | } | |
170 | ||
5546d6f5 ES |
171 | static bool __initdata mcp55_checked; |
172 | static const char __init *pci_mmcfg_nvidia_mcp55(void) | |
173 | { | |
174 | int bus; | |
175 | int mcp55_mmconf_found = 0; | |
176 | ||
177 | static const u32 extcfg_regnum = 0x90; | |
178 | static const u32 extcfg_regsize = 4; | |
179 | static const u32 extcfg_enable_mask = 1<<31; | |
180 | static const u32 extcfg_start_mask = 0xff<<16; | |
181 | static const int extcfg_start_shift = 16; | |
182 | static const u32 extcfg_size_mask = 0x3<<28; | |
183 | static const int extcfg_size_shift = 28; | |
184 | static const int extcfg_sizebus[] = {0x100, 0x80, 0x40, 0x20}; | |
185 | static const u32 extcfg_base_mask[] = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff}; | |
186 | static const int extcfg_base_lshift = 25; | |
187 | ||
188 | /* | |
189 | * do check if amd fam10h already took over | |
190 | */ | |
191 | if (!acpi_disabled || pci_mmcfg_config_num || mcp55_checked) | |
192 | return NULL; | |
193 | ||
194 | mcp55_checked = true; | |
195 | for (bus = 0; bus < 256; bus++) { | |
196 | u64 base; | |
197 | u32 l, extcfg; | |
198 | u16 vendor, device; | |
199 | int start, size_index, end; | |
200 | ||
201 | raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l); | |
202 | vendor = l & 0xffff; | |
203 | device = (l >> 16) & 0xffff; | |
204 | ||
205 | if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device) | |
206 | continue; | |
207 | ||
208 | raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum, | |
209 | extcfg_regsize, &extcfg); | |
210 | ||
211 | if (!(extcfg & extcfg_enable_mask)) | |
212 | continue; | |
213 | ||
214 | if (extend_mmcfg(1) == -1) | |
215 | continue; | |
216 | ||
217 | size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift; | |
218 | base = extcfg & extcfg_base_mask[size_index]; | |
219 | /* base could > 4G */ | |
220 | base <<= extcfg_base_lshift; | |
221 | start = (extcfg & extcfg_start_mask) >> extcfg_start_shift; | |
222 | end = start + extcfg_sizebus[size_index] - 1; | |
223 | fill_one_mmcfg(base, 0, start, end); | |
224 | mcp55_mmconf_found++; | |
225 | } | |
226 | ||
227 | if (!mcp55_mmconf_found) | |
228 | return NULL; | |
229 | ||
230 | return "nVidia MCP55"; | |
231 | } | |
232 | ||
9358c693 | 233 | struct pci_mmcfg_hostbridge_probe { |
7fd0da40 YL |
234 | u32 bus; |
235 | u32 devfn; | |
9358c693 OG |
236 | u32 vendor; |
237 | u32 device; | |
238 | const char *(*probe)(void); | |
239 | }; | |
240 | ||
429d512e | 241 | static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = { |
7fd0da40 YL |
242 | { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL, |
243 | PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 }, | |
244 | { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL, | |
245 | PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 }, | |
246 | { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD, | |
247 | 0x1200, pci_mmcfg_amd_fam10h }, | |
248 | { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD, | |
249 | 0x1200, pci_mmcfg_amd_fam10h }, | |
5546d6f5 ES |
250 | { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA, |
251 | 0x0369, pci_mmcfg_nvidia_mcp55 }, | |
9358c693 OG |
252 | }; |
253 | ||
068258bc YL |
254 | static int __init cmp_mmcfg(const void *x1, const void *x2) |
255 | { | |
256 | const typeof(pci_mmcfg_config[0]) *m1 = x1; | |
257 | const typeof(pci_mmcfg_config[0]) *m2 = x2; | |
258 | int start1, start2; | |
259 | ||
260 | start1 = m1->start_bus_number; | |
261 | start2 = m2->start_bus_number; | |
262 | ||
263 | return start1 - start2; | |
264 | } | |
265 | ||
266 | static void __init pci_mmcfg_check_end_bus_number(void) | |
267 | { | |
268 | int i; | |
269 | typeof(pci_mmcfg_config[0]) *cfg, *cfgx; | |
270 | ||
271 | /* sort them at first */ | |
272 | sort(pci_mmcfg_config, pci_mmcfg_config_num, | |
273 | sizeof(pci_mmcfg_config[0]), cmp_mmcfg, NULL); | |
274 | ||
275 | /* last one*/ | |
276 | if (pci_mmcfg_config_num > 0) { | |
277 | i = pci_mmcfg_config_num - 1; | |
278 | cfg = &pci_mmcfg_config[i]; | |
279 | if (cfg->end_bus_number < cfg->start_bus_number) | |
280 | cfg->end_bus_number = 255; | |
281 | } | |
282 | ||
283 | /* don't overlap please */ | |
284 | for (i = 0; i < pci_mmcfg_config_num - 1; i++) { | |
285 | cfg = &pci_mmcfg_config[i]; | |
286 | cfgx = &pci_mmcfg_config[i+1]; | |
287 | ||
288 | if (cfg->end_bus_number < cfg->start_bus_number) | |
289 | cfg->end_bus_number = 255; | |
290 | ||
291 | if (cfg->end_bus_number >= cfgx->start_bus_number) | |
292 | cfg->end_bus_number = cfgx->start_bus_number - 1; | |
293 | } | |
294 | } | |
295 | ||
9358c693 OG |
296 | static int __init pci_mmcfg_check_hostbridge(void) |
297 | { | |
298 | u32 l; | |
7fd0da40 | 299 | u32 bus, devfn; |
9358c693 OG |
300 | u16 vendor, device; |
301 | int i; | |
302 | const char *name; | |
303 | ||
bb63b421 YL |
304 | if (!raw_pci_ops) |
305 | return 0; | |
306 | ||
9358c693 OG |
307 | pci_mmcfg_config_num = 0; |
308 | pci_mmcfg_config = NULL; | |
9358c693 | 309 | |
068258bc | 310 | for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) { |
7fd0da40 YL |
311 | bus = pci_mmcfg_probes[i].bus; |
312 | devfn = pci_mmcfg_probes[i].devfn; | |
bb63b421 | 313 | raw_pci_ops->read(0, bus, devfn, 0, 4, &l); |
7fd0da40 YL |
314 | vendor = l & 0xffff; |
315 | device = (l >> 16) & 0xffff; | |
316 | ||
068258bc | 317 | name = NULL; |
429d512e OH |
318 | if (pci_mmcfg_probes[i].vendor == vendor && |
319 | pci_mmcfg_probes[i].device == device) | |
9358c693 OG |
320 | name = pci_mmcfg_probes[i].probe(); |
321 | ||
068258bc YL |
322 | if (name) |
323 | printk(KERN_INFO "PCI: Found %s with MMCONFIG support.\n", | |
324 | name); | |
9358c693 OG |
325 | } |
326 | ||
068258bc YL |
327 | /* some end_bus_number is crazy, fix it */ |
328 | pci_mmcfg_check_end_bus_number(); | |
329 | ||
330 | return pci_mmcfg_config_num != 0; | |
9358c693 OG |
331 | } |
332 | ||
ebd60cd6 | 333 | static void __init pci_mmcfg_insert_resources(void) |
6a0668fc | 334 | { |
068258bc | 335 | #define PCI_MMCFG_RESOURCE_NAME_LEN 24 |
6a0668fc OG |
336 | int i; |
337 | struct resource *res; | |
338 | char *names; | |
339 | unsigned num_buses; | |
340 | ||
341 | res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res), | |
342 | pci_mmcfg_config_num, GFP_KERNEL); | |
6a0668fc OG |
343 | if (!res) { |
344 | printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n"); | |
345 | return; | |
346 | } | |
347 | ||
348 | names = (void *)&res[pci_mmcfg_config_num]; | |
349 | for (i = 0; i < pci_mmcfg_config_num; i++, res++) { | |
429d512e OH |
350 | struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i]; |
351 | num_buses = cfg->end_bus_number - cfg->start_bus_number + 1; | |
6a0668fc | 352 | res->name = names; |
068258bc YL |
353 | snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, |
354 | "PCI MMCONFIG %u [%02x-%02x]", cfg->pci_segment, | |
355 | cfg->start_bus_number, cfg->end_bus_number); | |
356 | res->start = cfg->address + (cfg->start_bus_number << 20); | |
6a0668fc | 357 | res->end = res->start + (num_buses << 20) - 1; |
ebd60cd6 | 358 | res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; |
6a0668fc OG |
359 | insert_resource(&iomem_resource, res); |
360 | names += PCI_MMCFG_RESOURCE_NAME_LEN; | |
361 | } | |
a5ba7971 AD |
362 | |
363 | /* Mark that the resources have been inserted. */ | |
364 | pci_mmcfg_resources_inserted = 1; | |
6a0668fc OG |
365 | } |
366 | ||
7752d5cf RH |
367 | static acpi_status __init check_mcfg_resource(struct acpi_resource *res, |
368 | void *data) | |
369 | { | |
370 | struct resource *mcfg_res = data; | |
371 | struct acpi_resource_address64 address; | |
372 | acpi_status status; | |
373 | ||
374 | if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) { | |
375 | struct acpi_resource_fixed_memory32 *fixmem32 = | |
376 | &res->data.fixed_memory32; | |
377 | if (!fixmem32) | |
378 | return AE_OK; | |
379 | if ((mcfg_res->start >= fixmem32->address) && | |
75e613cd | 380 | (mcfg_res->end < (fixmem32->address + |
7752d5cf RH |
381 | fixmem32->address_length))) { |
382 | mcfg_res->flags = 1; | |
383 | return AE_CTRL_TERMINATE; | |
384 | } | |
385 | } | |
386 | if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) && | |
387 | (res->type != ACPI_RESOURCE_TYPE_ADDRESS64)) | |
388 | return AE_OK; | |
389 | ||
390 | status = acpi_resource_to_address64(res, &address); | |
391 | if (ACPI_FAILURE(status) || | |
392 | (address.address_length <= 0) || | |
393 | (address.resource_type != ACPI_MEMORY_RANGE)) | |
394 | return AE_OK; | |
395 | ||
396 | if ((mcfg_res->start >= address.minimum) && | |
75e613cd | 397 | (mcfg_res->end < (address.minimum + address.address_length))) { |
7752d5cf RH |
398 | mcfg_res->flags = 1; |
399 | return AE_CTRL_TERMINATE; | |
400 | } | |
401 | return AE_OK; | |
402 | } | |
403 | ||
404 | static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl, | |
405 | void *context, void **rv) | |
406 | { | |
407 | struct resource *mcfg_res = context; | |
408 | ||
409 | acpi_walk_resources(handle, METHOD_NAME__CRS, | |
410 | check_mcfg_resource, context); | |
411 | ||
412 | if (mcfg_res->flags) | |
413 | return AE_CTRL_TERMINATE; | |
414 | ||
415 | return AE_OK; | |
416 | } | |
417 | ||
a83fe32f | 418 | static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used) |
7752d5cf RH |
419 | { |
420 | struct resource mcfg_res; | |
421 | ||
422 | mcfg_res.start = start; | |
75e613cd | 423 | mcfg_res.end = end - 1; |
7752d5cf RH |
424 | mcfg_res.flags = 0; |
425 | ||
426 | acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL); | |
427 | ||
428 | if (!mcfg_res.flags) | |
429 | acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res, | |
430 | NULL); | |
431 | ||
432 | return mcfg_res.flags; | |
433 | } | |
434 | ||
a83fe32f YL |
435 | typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type); |
436 | ||
437 | static int __init is_mmconf_reserved(check_reserved_t is_reserved, | |
438 | u64 addr, u64 size, int i, | |
439 | typeof(pci_mmcfg_config[0]) *cfg, int with_e820) | |
440 | { | |
441 | u64 old_size = size; | |
442 | int valid = 0; | |
443 | ||
044cd809 | 444 | while (!is_reserved(addr, addr + size, E820_RESERVED)) { |
a83fe32f YL |
445 | size >>= 1; |
446 | if (size < (16UL<<20)) | |
447 | break; | |
448 | } | |
449 | ||
450 | if (size >= (16UL<<20) || size == old_size) { | |
451 | printk(KERN_NOTICE | |
452 | "PCI: MCFG area at %Lx reserved in %s\n", | |
453 | addr, with_e820?"E820":"ACPI motherboard resources"); | |
454 | valid = 1; | |
455 | ||
456 | if (old_size != size) { | |
457 | /* update end_bus_number */ | |
458 | cfg->end_bus_number = cfg->start_bus_number + ((size>>20) - 1); | |
459 | printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx " | |
460 | "segment %hu buses %u - %u\n", | |
461 | i, (unsigned long)cfg->address, cfg->pci_segment, | |
462 | (unsigned int)cfg->start_bus_number, | |
463 | (unsigned int)cfg->end_bus_number); | |
464 | } | |
465 | } | |
466 | ||
467 | return valid; | |
468 | } | |
469 | ||
bb63b421 | 470 | static void __init pci_mmcfg_reject_broken(int early) |
44de0203 | 471 | { |
26054ed0 | 472 | typeof(pci_mmcfg_config[0]) *cfg; |
7752d5cf | 473 | int i; |
26054ed0 OH |
474 | |
475 | if ((pci_mmcfg_config_num == 0) || | |
476 | (pci_mmcfg_config == NULL) || | |
477 | (pci_mmcfg_config[0].address == 0)) | |
478 | return; | |
479 | ||
7752d5cf | 480 | for (i = 0; i < pci_mmcfg_config_num; i++) { |
05c58b8a | 481 | int valid = 0; |
a83fe32f YL |
482 | u64 addr, size; |
483 | ||
7752d5cf | 484 | cfg = &pci_mmcfg_config[i]; |
a83fe32f YL |
485 | addr = cfg->start_bus_number; |
486 | addr <<= 20; | |
487 | addr += cfg->address; | |
488 | size = cfg->end_bus_number + 1 - cfg->start_bus_number; | |
489 | size <<= 20; | |
05c58b8a | 490 | printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx " |
7752d5cf RH |
491 | "segment %hu buses %u - %u\n", |
492 | i, (unsigned long)cfg->address, cfg->pci_segment, | |
493 | (unsigned int)cfg->start_bus_number, | |
494 | (unsigned int)cfg->end_bus_number); | |
05c58b8a | 495 | |
a83fe32f YL |
496 | if (!early) |
497 | valid = is_mmconf_reserved(is_acpi_reserved, addr, size, i, cfg, 0); | |
05c58b8a YL |
498 | |
499 | if (valid) | |
500 | continue; | |
501 | ||
502 | if (!early) | |
7752d5cf RH |
503 | printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not" |
504 | " reserved in ACPI motherboard resources\n", | |
505 | cfg->address); | |
a83fe32f | 506 | |
05c58b8a | 507 | /* Don't try to do this check unless configuration |
bb63b421 | 508 | type 1 is available. how about type 2 ?*/ |
a83fe32f YL |
509 | if (raw_pci_ops) |
510 | valid = is_mmconf_reserved(e820_all_mapped, addr, size, i, cfg, 1); | |
05c58b8a YL |
511 | |
512 | if (!valid) | |
513 | goto reject; | |
44de0203 | 514 | } |
7752d5cf | 515 | |
26054ed0 OH |
516 | return; |
517 | ||
518 | reject: | |
ef310237 | 519 | printk(KERN_INFO "PCI: Not using MMCONFIG.\n"); |
0b64ad71 | 520 | pci_mmcfg_arch_free(); |
26054ed0 OH |
521 | kfree(pci_mmcfg_config); |
522 | pci_mmcfg_config = NULL; | |
523 | pci_mmcfg_config_num = 0; | |
44de0203 OH |
524 | } |
525 | ||
05c58b8a | 526 | static int __initdata known_bridge; |
7752d5cf | 527 | |
c4bf2f37 LB |
528 | static int acpi_mcfg_64bit_base_addr __initdata = FALSE; |
529 | ||
530 | /* The physical address of the MMCONFIG aperture. Set from ACPI tables. */ | |
531 | struct acpi_mcfg_allocation *pci_mmcfg_config; | |
532 | int pci_mmcfg_config_num; | |
533 | ||
534 | static int __init acpi_mcfg_oem_check(struct acpi_table_mcfg *mcfg) | |
535 | { | |
536 | if (!strcmp(mcfg->header.oem_id, "SGI")) | |
537 | acpi_mcfg_64bit_base_addr = TRUE; | |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
542 | static int __init pci_parse_mcfg(struct acpi_table_header *header) | |
543 | { | |
544 | struct acpi_table_mcfg *mcfg; | |
545 | unsigned long i; | |
546 | int config_size; | |
547 | ||
548 | if (!header) | |
549 | return -EINVAL; | |
550 | ||
551 | mcfg = (struct acpi_table_mcfg *)header; | |
552 | ||
553 | /* how many config structures do we have */ | |
554 | pci_mmcfg_config_num = 0; | |
555 | i = header->length - sizeof(struct acpi_table_mcfg); | |
556 | while (i >= sizeof(struct acpi_mcfg_allocation)) { | |
557 | ++pci_mmcfg_config_num; | |
558 | i -= sizeof(struct acpi_mcfg_allocation); | |
559 | }; | |
560 | if (pci_mmcfg_config_num == 0) { | |
561 | printk(KERN_ERR PREFIX "MMCONFIG has no entries\n"); | |
562 | return -ENODEV; | |
563 | } | |
564 | ||
565 | config_size = pci_mmcfg_config_num * sizeof(*pci_mmcfg_config); | |
566 | pci_mmcfg_config = kmalloc(config_size, GFP_KERNEL); | |
567 | if (!pci_mmcfg_config) { | |
568 | printk(KERN_WARNING PREFIX | |
569 | "No memory for MCFG config tables\n"); | |
570 | return -ENOMEM; | |
571 | } | |
572 | ||
573 | memcpy(pci_mmcfg_config, &mcfg[1], config_size); | |
574 | ||
575 | acpi_mcfg_oem_check(mcfg); | |
576 | ||
577 | for (i = 0; i < pci_mmcfg_config_num; ++i) { | |
578 | if ((pci_mmcfg_config[i].address > 0xFFFFFFFF) && | |
579 | !acpi_mcfg_64bit_base_addr) { | |
580 | printk(KERN_ERR PREFIX | |
581 | "MMCONFIG not in low 4GB of memory\n"); | |
582 | kfree(pci_mmcfg_config); | |
583 | pci_mmcfg_config_num = 0; | |
584 | return -ENODEV; | |
585 | } | |
586 | } | |
587 | ||
588 | return 0; | |
589 | } | |
590 | ||
968cbfad | 591 | static void __init __pci_mmcfg_init(int early) |
b7867394 | 592 | { |
7752d5cf | 593 | /* MMCONFIG disabled */ |
b7867394 OG |
594 | if ((pci_probe & PCI_PROBE_MMCONF) == 0) |
595 | return; | |
596 | ||
7752d5cf | 597 | /* MMCONFIG already enabled */ |
05c58b8a | 598 | if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF)) |
7752d5cf | 599 | return; |
9358c693 | 600 | |
05c58b8a YL |
601 | /* for late to exit */ |
602 | if (known_bridge) | |
603 | return; | |
7752d5cf | 604 | |
bb63b421 | 605 | if (early) { |
05c58b8a YL |
606 | if (pci_mmcfg_check_hostbridge()) |
607 | known_bridge = 1; | |
608 | } | |
609 | ||
068258bc | 610 | if (!known_bridge) |
c4bf2f37 | 611 | acpi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg); |
068258bc YL |
612 | |
613 | pci_mmcfg_reject_broken(early); | |
b7867394 OG |
614 | |
615 | if ((pci_mmcfg_config_num == 0) || | |
616 | (pci_mmcfg_config == NULL) || | |
617 | (pci_mmcfg_config[0].address == 0)) | |
618 | return; | |
619 | ||
ebd60cd6 | 620 | if (pci_mmcfg_arch_init()) |
b7867394 | 621 | pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF; |
ebd60cd6 | 622 | else { |
a5ba7971 AD |
623 | /* |
624 | * Signal not to attempt to insert mmcfg resources because | |
625 | * the architecture mmcfg setup could not initialize. | |
626 | */ | |
627 | pci_mmcfg_resources_inserted = 1; | |
b7867394 OG |
628 | } |
629 | } | |
a5ba7971 | 630 | |
bb63b421 | 631 | void __init pci_mmcfg_early_init(void) |
05c58b8a | 632 | { |
bb63b421 | 633 | __pci_mmcfg_init(1); |
05c58b8a YL |
634 | } |
635 | ||
636 | void __init pci_mmcfg_late_init(void) | |
637 | { | |
bb63b421 | 638 | __pci_mmcfg_init(0); |
05c58b8a YL |
639 | } |
640 | ||
a5ba7971 AD |
641 | static int __init pci_mmcfg_late_insert_resources(void) |
642 | { | |
643 | /* | |
644 | * If resources are already inserted or we are not using MMCONFIG, | |
645 | * don't insert the resources. | |
646 | */ | |
647 | if ((pci_mmcfg_resources_inserted == 1) || | |
648 | (pci_probe & PCI_PROBE_MMCONF) == 0 || | |
649 | (pci_mmcfg_config_num == 0) || | |
650 | (pci_mmcfg_config == NULL) || | |
651 | (pci_mmcfg_config[0].address == 0)) | |
652 | return 1; | |
653 | ||
654 | /* | |
655 | * Attempt to insert the mmcfg resources but not with the busy flag | |
656 | * marked so it won't cause request errors when __request_region is | |
657 | * called. | |
658 | */ | |
ebd60cd6 | 659 | pci_mmcfg_insert_resources(); |
a5ba7971 AD |
660 | |
661 | return 0; | |
662 | } | |
663 | ||
664 | /* | |
665 | * Perform MMCONFIG resource insertion after PCI initialization to allow for | |
666 | * misprogrammed MCFG tables that state larger sizes but actually conflict | |
667 | * with other system resources. | |
668 | */ | |
669 | late_initcall(pci_mmcfg_late_insert_resources); |