[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / pci / mmconfig-shared.c

/*
 * mmconfig-shared.c - Low-level direct PCI config space access via
 *                     MMCONFIG - common code between i386 and x86-64.
 *
 * This code does:
 * - known chipset handling
 * - ACPI decoding and validation
 *
 * Per-architecture code takes care of the mappings and accesses
 * themselves.
 */

#include <linux/pci.h>
#include <linux/init.h>
#include <linux/acpi.h>
#include <linux/bitmap.h>
#include <asm/e820.h>

#include "pci.h"

/* aperture is up to 256MB but BIOS may reserve less */
#define MMCONFIG_APER_MIN	(2 * 1024*1024)
#define MMCONFIG_APER_MAX	(256 * 1024*1024)

/* Indicate if the mmcfg resources have been placed into the resource table. */
static int __initdata pci_mmcfg_resources_inserted;

static const char __init *pci_mmcfg_e7520(void)
{
	u32 win;
	pci_direct_conf1.read(0, 0, PCI_DEVFN(0,0), 0xce, 2, &win);

	win = win & 0xf000;
	if(win == 0x0000 || win == 0xf000)
		pci_mmcfg_config_num = 0;
	else {
		pci_mmcfg_config_num = 1;
		pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
		if (!pci_mmcfg_config)
			return NULL;
		pci_mmcfg_config[0].address = win << 16;
		pci_mmcfg_config[0].pci_segment = 0;
		pci_mmcfg_config[0].start_bus_number = 0;
		pci_mmcfg_config[0].end_bus_number = 255;
	}

	return "Intel Corporation E7520 Memory Controller Hub";
}

static const char __init *pci_mmcfg_intel_945(void)
{
	u32 pciexbar, mask = 0, len = 0;

	pci_mmcfg_config_num = 1;

	pci_direct_conf1.read(0, 0, PCI_DEVFN(0,0), 0x48, 4, &pciexbar);

	/* Enable bit */
	if (!(pciexbar & 1))
		pci_mmcfg_config_num = 0;

	/* Size bits */
	switch ((pciexbar >> 1) & 3) {
	case 0:
		mask = 0xf0000000U;
		len  = 0x10000000U;
		break;
	case 1:
		mask = 0xf8000000U;
		len  = 0x08000000U;
		break;
	case 2:
		mask = 0xfc000000U;
		len  = 0x04000000U;
		break;
	default:
		pci_mmcfg_config_num = 0;
	}

	/* Errata #2, things break when not aligned on a 256Mb boundary */
	/* Can only happen in 64M/128M mode */

	if ((pciexbar & mask) & 0x0fffffffU)
		pci_mmcfg_config_num = 0;

	/* Don't hit the APIC registers and their friends */
	if ((pciexbar & mask) >= 0xf0000000U)
		pci_mmcfg_config_num = 0;

	if (pci_mmcfg_config_num) {
		pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
		if (!pci_mmcfg_config)
			return NULL;
		pci_mmcfg_config[0].address = pciexbar & mask;
		pci_mmcfg_config[0].pci_segment = 0;
		pci_mmcfg_config[0].start_bus_number = 0;
		pci_mmcfg_config[0].end_bus_number = (len >> 20) - 1;
	}

	return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
}

struct pci_mmcfg_hostbridge_probe {
	u32 vendor;
	u32 device;
	const char *(*probe)(void);
};

static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
};

static int __init pci_mmcfg_check_hostbridge(void)
{
	u32 l;
	u16 vendor, device;
	int i;
	const char *name;

	pci_direct_conf1.read(0, 0, PCI_DEVFN(0,0), 0, 4, &l);
	vendor = l & 0xffff;
	device = (l >> 16) & 0xffff;

	pci_mmcfg_config_num = 0;
	pci_mmcfg_config = NULL;
	name = NULL;

	for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
		if (pci_mmcfg_probes[i].vendor == vendor &&
		    pci_mmcfg_probes[i].device == device)
			name = pci_mmcfg_probes[i].probe();
	}

	if (name) {
		printk(KERN_INFO "PCI: Found %s %s MMCONFIG support.\n",
		       name, pci_mmcfg_config_num ? "with" : "without");
	}

	return name != NULL;
}

static void __init pci_mmcfg_insert_resources(unsigned long resource_flags)
{
#define PCI_MMCFG_RESOURCE_NAME_LEN 19
	int i;
	struct resource *res;
	char *names;
	unsigned num_buses;

	res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
			pci_mmcfg_config_num, GFP_KERNEL);
	if (!res) {
		printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
		return;
	}

	names = (void *)&res[pci_mmcfg_config_num];
	for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
		struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
		num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
		res->name = names;
		snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, "PCI MMCONFIG %u",
			 cfg->pci_segment);
		res->start = cfg->address;
		res->end = res->start + (num_buses << 20) - 1;
		res->flags = IORESOURCE_MEM | resource_flags;
		insert_resource(&iomem_resource, res);
		names += PCI_MMCFG_RESOURCE_NAME_LEN;
	}

	/* Mark that the resources have been inserted. */
	pci_mmcfg_resources_inserted = 1;
}

static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
					      void *data)
{
	struct resource *mcfg_res = data;
	struct acpi_resource_address64 address;
	acpi_status status;

	if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
		struct acpi_resource_fixed_memory32 *fixmem32 =
			&res->data.fixed_memory32;
		if (!fixmem32)
			return AE_OK;
		if ((mcfg_res->start >= fixmem32->address) &&
		    (mcfg_res->end < (fixmem32->address +
				      fixmem32->address_length))) {
			mcfg_res->flags = 1;
			return AE_CTRL_TERMINATE;
		}
	}
	if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
	    (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
		return AE_OK;

	status = acpi_resource_to_address64(res, &address);
	if (ACPI_FAILURE(status) ||
	   (address.address_length <= 0) ||
	   (address.resource_type != ACPI_MEMORY_RANGE))
		return AE_OK;

	if ((mcfg_res->start >= address.minimum) &&
	    (mcfg_res->end < (address.minimum + address.address_length))) {
		mcfg_res->flags = 1;
		return AE_CTRL_TERMINATE;
	}
	return AE_OK;
}

static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
		void *context, void **rv)
{
	struct resource *mcfg_res = context;

	acpi_walk_resources(handle, METHOD_NAME__CRS,
			    check_mcfg_resource, context);

	if (mcfg_res->flags)
		return AE_CTRL_TERMINATE;

	return AE_OK;
}

static int __init is_acpi_reserved(unsigned long start, unsigned long end)
{
	struct resource mcfg_res;

	mcfg_res.start = start;
	mcfg_res.end = end;
	mcfg_res.flags = 0;

	acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);

	if (!mcfg_res.flags)
		acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
				 NULL);

	return mcfg_res.flags;
}

static void __init pci_mmcfg_reject_broken(void)
{
	typeof(pci_mmcfg_config[0]) *cfg;
	int i;

	if ((pci_mmcfg_config_num == 0) ||
	    (pci_mmcfg_config == NULL) ||
	    (pci_mmcfg_config[0].address == 0))
		return;

	cfg = &pci_mmcfg_config[0];

	/*
	 * Handle more broken MCFG tables on Asus etc.
	 * They only contain a single entry for bus 0-0.
	 */
	if (pci_mmcfg_config_num == 1 &&
	    cfg->pci_segment == 0 &&
	    (cfg->start_bus_number | cfg->end_bus_number) == 0) {
		printk(KERN_ERR "PCI: start and end of bus number is 0. "
		       "Rejected as broken MCFG.\n");
		goto reject;
	}

	for (i = 0; i < pci_mmcfg_config_num; i++) {
		u32 size = (cfg->end_bus_number + 1) << 20;
		cfg = &pci_mmcfg_config[i];
		printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lu "
		       "segment %hu buses %u - %u\n",
		       i, (unsigned long)cfg->address, cfg->pci_segment,
		       (unsigned int)cfg->start_bus_number,
		       (unsigned int)cfg->end_bus_number);
		if (is_acpi_reserved(cfg->address, cfg->address + size - 1)) {
			printk(KERN_NOTICE "PCI: MCFG area at %Lx reserved "
			       "in ACPI motherboard resources\n",
			       cfg->address);
		} else {
			printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
			       " reserved in ACPI motherboard resources\n",
			       cfg->address);
			/* Don't try to do this check unless configuration
			   type 1 is available. */
			if ((pci_probe & PCI_PROBE_CONF1) &&
			    e820_all_mapped(cfg->address,
					    cfg->address + size - 1,
					    E820_RESERVED))
				printk(KERN_NOTICE
				       "PCI: MCFG area at %Lx reserved in "
				       "E820\n",
				       cfg->address);
			else
				goto reject;
		}
	}

	return;

reject:
	printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
	kfree(pci_mmcfg_config);
	pci_mmcfg_config = NULL;
	pci_mmcfg_config_num = 0;
}

void __init pci_mmcfg_early_init(int type)
{
	if ((pci_probe & PCI_PROBE_MMCONF) == 0)
		return;

	/* If type 1 access is available, no need to enable MMCONFIG yet, we can
	   defer until later when the ACPI interpreter is available to better
	   validate things. */
	if (type == 1)
		return;

	acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);

	if ((pci_mmcfg_config_num == 0) ||
	    (pci_mmcfg_config == NULL) ||
	    (pci_mmcfg_config[0].address == 0))
		return;

	if (pci_mmcfg_arch_init())
		pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
}

void __init pci_mmcfg_late_init(void)
{
	int known_bridge = 0;

	/* MMCONFIG disabled */
	if ((pci_probe & PCI_PROBE_MMCONF) == 0)
		return;

	/* MMCONFIG already enabled */
	if (!(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
		return;

	if ((pci_probe & PCI_PROBE_CONF1) && pci_mmcfg_check_hostbridge())
		known_bridge = 1;
	else
		acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);

	pci_mmcfg_reject_broken();

	if ((pci_mmcfg_config_num == 0) ||
	    (pci_mmcfg_config == NULL) ||
	    (pci_mmcfg_config[0].address == 0))
		return;

	if (pci_mmcfg_arch_init()) {
		if (known_bridge)
			pci_mmcfg_insert_resources(IORESOURCE_BUSY);
		pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
	} else {
		/*
		 * Signal not to attempt to insert mmcfg resources because
		 * the architecture mmcfg setup could not initialize.
		 */
		pci_mmcfg_resources_inserted = 1;
	}
}

static int __init pci_mmcfg_late_insert_resources(void)
{
	/*
	 * If resources are already inserted or we are not using MMCONFIG,
	 * don't insert the resources.
	 */
	if ((pci_mmcfg_resources_inserted == 1) ||
	    (pci_probe & PCI_PROBE_MMCONF) == 0 ||
	    (pci_mmcfg_config_num == 0) ||
	    (pci_mmcfg_config == NULL) ||
	    (pci_mmcfg_config[0].address == 0))
		return 1;

	/*
	 * Attempt to insert the mmcfg resources but not with the busy flag
	 * marked so it won't cause request errors when __request_region is
	 * called.
	 */
	pci_mmcfg_insert_resources(0);

	return 0;
}

/*
 * Perform MMCONFIG resource insertion after PCI initialization to allow for
 * misprogrammed MCFG tables that state larger sizes but actually conflict
 * with other system resources.
 */
late_initcall(pci_mmcfg_late_insert_resources);
Commit	Line	Data
b7867394 OG	1	/*
	2	* mmconfig-shared.c - Low-level direct PCI config space access via
	3	* MMCONFIG - common code between i386 and x86-64.
	4	*
	5	* This code does:
9358c693	6	* - known chipset handling
b7867394 OG	7	* - ACPI decoding and validation
	8	*
	9	* Per-architecture code takes care of the mappings and accesses
	10	* themselves.
	11	*/
	12
	13	#include <linux/pci.h>
	14	#include <linux/init.h>
	15	#include <linux/acpi.h>
	16	#include <linux/bitmap.h>
	17	#include <asm/e820.h>
	18
	19	#include "pci.h"
	20
	21	/* aperture is up to 256MB but BIOS may reserve less */
	22	#define MMCONFIG_APER_MIN (2 * 1024*1024)
	23	#define MMCONFIG_APER_MAX (256 * 1024*1024)
	24
a5ba7971 AD	25	/* Indicate if the mmcfg resources have been placed into the resource table. */
	26	static int __initdata pci_mmcfg_resources_inserted;
	27
429d512e	28	static const char __init *pci_mmcfg_e7520(void)
9358c693 OG	29	{
9358c693 OG	30	u32 win;
b6ce068a	31	pci_direct_conf1.read(0, 0, PCI_DEVFN(0,0), 0xce, 2, &win);
9358c693	32
b5229dbb OG	33	win = win & 0xf000;
	34	if(win == 0x0000 \|\| win == 0xf000)
	35	pci_mmcfg_config_num = 0;
	36	else {
	37	pci_mmcfg_config_num = 1;
	38	pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
	39	if (!pci_mmcfg_config)
	40	return NULL;
	41	pci_mmcfg_config[0].address = win << 16;
	42	pci_mmcfg_config[0].pci_segment = 0;
	43	pci_mmcfg_config[0].start_bus_number = 0;
	44	pci_mmcfg_config[0].end_bus_number = 255;
	45	}
9358c693 OG	46
	47	return "Intel Corporation E7520 Memory Controller Hub";
	48	}
	49
429d512e	50	static const char __init *pci_mmcfg_intel_945(void)
9358c693 OG	51	{
	52	u32 pciexbar, mask = 0, len = 0;
	53
	54	pci_mmcfg_config_num = 1;
	55
b6ce068a	56	pci_direct_conf1.read(0, 0, PCI_DEVFN(0,0), 0x48, 4, &pciexbar);
9358c693 OG	57
	58	/* Enable bit */
	59	if (!(pciexbar & 1))
	60	pci_mmcfg_config_num = 0;
	61
	62	/* Size bits */
	63	switch ((pciexbar >> 1) & 3) {
	64	case 0:
	65	mask = 0xf0000000U;
	66	len = 0x10000000U;
	67	break;
	68	case 1:
	69	mask = 0xf8000000U;
	70	len = 0x08000000U;
	71	break;
	72	case 2:
	73	mask = 0xfc000000U;
	74	len = 0x04000000U;
	75	break;
	76	default:
	77	pci_mmcfg_config_num = 0;
	78	}
	79
	80	/* Errata #2, things break when not aligned on a 256Mb boundary */
	81	/* Can only happen in 64M/128M mode */
	82
	83	if ((pciexbar & mask) & 0x0fffffffU)
	84	pci_mmcfg_config_num = 0;
	85
b5229dbb OG	86	/* Don't hit the APIC registers and their friends */
	87	if ((pciexbar & mask) >= 0xf0000000U)
	88	pci_mmcfg_config_num = 0;
	89
9358c693 OG	90	if (pci_mmcfg_config_num) {
	91	pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
	92	if (!pci_mmcfg_config)
	93	return NULL;
	94	pci_mmcfg_config[0].address = pciexbar & mask;
	95	pci_mmcfg_config[0].pci_segment = 0;
	96	pci_mmcfg_config[0].start_bus_number = 0;
	97	pci_mmcfg_config[0].end_bus_number = (len >> 20) - 1;
	98	}
	99
	100	return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
	101	}
	102
	103	struct pci_mmcfg_hostbridge_probe {
	104	u32 vendor;
	105	u32 device;
	106	const char (probe)(void);
	107	};
	108
429d512e	109	static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
9358c693 OG	110	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
	111	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
	112	};
	113
	114	static int __init pci_mmcfg_check_hostbridge(void)
	115	{
	116	u32 l;
	117	u16 vendor, device;
	118	int i;
	119	const char *name;
	120
b6ce068a	121	pci_direct_conf1.read(0, 0, PCI_DEVFN(0,0), 0, 4, &l);
9358c693 OG	122	vendor = l & 0xffff;
	123	device = (l >> 16) & 0xffff;
	124
	125	pci_mmcfg_config_num = 0;
	126	pci_mmcfg_config = NULL;
	127	name = NULL;
	128
429d512e OH	129	for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
	130	if (pci_mmcfg_probes[i].vendor == vendor &&
	131	pci_mmcfg_probes[i].device == device)
9358c693	132	name = pci_mmcfg_probes[i].probe();
429d512e	133	}
9358c693 OG	134
9358c693 OG	135	if (name) {
429d512e OH	136	printk(KERN_INFO "PCI: Found %s %s MMCONFIG support.\n",
429d512e OH	137	name, pci_mmcfg_config_num ? "with" : "without");
9358c693 OG	138	}
	139
	140	return name != NULL;
	141	}
	142
a5ba7971	143	static void __init pci_mmcfg_insert_resources(unsigned long resource_flags)
6a0668fc OG	144	{
	145	#define PCI_MMCFG_RESOURCE_NAME_LEN 19
	146	int i;
	147	struct resource *res;
	148	char *names;
	149	unsigned num_buses;
	150
	151	res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
	152	pci_mmcfg_config_num, GFP_KERNEL);
6a0668fc OG	153	if (!res) {
	154	printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
	155	return;
	156	}
	157
	158	names = (void *)&res[pci_mmcfg_config_num];
	159	for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
429d512e OH	160	struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
429d512e OH	161	num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
6a0668fc OG	162	res->name = names;
6a0668fc OG	163	snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, "PCI MMCONFIG %u",
429d512e OH	164	cfg->pci_segment);
429d512e OH	165	res->start = cfg->address;
6a0668fc	166	res->end = res->start + (num_buses << 20) - 1;
a5ba7971	167	res->flags = IORESOURCE_MEM \| resource_flags;
6a0668fc OG	168	insert_resource(&iomem_resource, res);
	169	names += PCI_MMCFG_RESOURCE_NAME_LEN;
	170	}
a5ba7971 AD	171
	172	/* Mark that the resources have been inserted. */
	173	pci_mmcfg_resources_inserted = 1;
6a0668fc OG	174	}
6a0668fc OG	175
7752d5cf RH	176	static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
	177	void *data)
	178	{
	179	struct resource *mcfg_res = data;
	180	struct acpi_resource_address64 address;
	181	acpi_status status;
	182
	183	if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
	184	struct acpi_resource_fixed_memory32 *fixmem32 =
	185	&res->data.fixed_memory32;
	186	if (!fixmem32)
	187	return AE_OK;
	188	if ((mcfg_res->start >= fixmem32->address) &&
	189	(mcfg_res->end < (fixmem32->address +
	190	fixmem32->address_length))) {
	191	mcfg_res->flags = 1;
	192	return AE_CTRL_TERMINATE;
	193	}
	194	}
	195	if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
	196	(res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
	197	return AE_OK;
	198
	199	status = acpi_resource_to_address64(res, &address);
	200	if (ACPI_FAILURE(status) \|\|
	201	(address.address_length <= 0) \|\|
	202	(address.resource_type != ACPI_MEMORY_RANGE))
	203	return AE_OK;
	204
	205	if ((mcfg_res->start >= address.minimum) &&
	206	(mcfg_res->end < (address.minimum + address.address_length))) {
	207	mcfg_res->flags = 1;
	208	return AE_CTRL_TERMINATE;
	209	}
	210	return AE_OK;
	211	}
	212
	213	static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
	214	void context, void *rv)
	215	{
	216	struct resource *mcfg_res = context;
	217
	218	acpi_walk_resources(handle, METHOD_NAME__CRS,
	219	check_mcfg_resource, context);
	220
	221	if (mcfg_res->flags)
	222	return AE_CTRL_TERMINATE;
	223
	224	return AE_OK;
	225	}
	226
	227	static int __init is_acpi_reserved(unsigned long start, unsigned long end)
	228	{
	229	struct resource mcfg_res;
	230
	231	mcfg_res.start = start;
	232	mcfg_res.end = end;
	233	mcfg_res.flags = 0;
	234
	235	acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
	236
	237	if (!mcfg_res.flags)
	238	acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
	239	NULL);
240
241	return mcfg_res.flags;
242	}
243
244	static void __init pci_mmcfg_reject_broken(void)
44de0203	245	{
26054ed0	246	typeof(pci_mmcfg_config[0]) *cfg;
7752d5cf	247	int i;
26054ed0 OH	248
	249	if ((pci_mmcfg_config_num == 0) \|\|
	250	(pci_mmcfg_config == NULL) \|\|
	251	(pci_mmcfg_config[0].address == 0))
	252	return;
	253
	254	cfg = &pci_mmcfg_config[0];
44de0203 OH	255
	256	/*
	257	* Handle more broken MCFG tables on Asus etc.
	258	* They only contain a single entry for bus 0-0.
	259	*/
	260	if (pci_mmcfg_config_num == 1 &&
	261	cfg->pci_segment == 0 &&
	262	(cfg->start_bus_number \| cfg->end_bus_number) == 0) {
44de0203	263	printk(KERN_ERR "PCI: start and end of bus number is 0. "
26054ed0 OH	264	"Rejected as broken MCFG.\n");
	265	goto reject;
	266	}
	267
7752d5cf RH	268	for (i = 0; i < pci_mmcfg_config_num; i++) {
	269	u32 size = (cfg->end_bus_number + 1) << 20;
	270	cfg = &pci_mmcfg_config[i];
	271	printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lu "
	272	"segment %hu buses %u - %u\n",
	273	i, (unsigned long)cfg->address, cfg->pci_segment,
	274	(unsigned int)cfg->start_bus_number,
	275	(unsigned int)cfg->end_bus_number);
	276	if (is_acpi_reserved(cfg->address, cfg->address + size - 1)) {
	277	printk(KERN_NOTICE "PCI: MCFG area at %Lx reserved "
	278	"in ACPI motherboard resources\n",
	279	cfg->address);
	280	} else {
	281	printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
	282	" reserved in ACPI motherboard resources\n",
	283	cfg->address);
	284	/* Don't try to do this check unless configuration
	285	type 1 is available. */
	286	if ((pci_probe & PCI_PROBE_CONF1) &&
	287	e820_all_mapped(cfg->address,
	288	cfg->address + size - 1,
	289	E820_RESERVED))
	290	printk(KERN_NOTICE
	291	"PCI: MCFG area at %Lx reserved in "
	292	"E820\n",
	293	cfg->address);
	294	else
	295	goto reject;
	296	}
44de0203	297	}
7752d5cf	298
26054ed0 OH	299	return;
	300
	301	reject:
	302	printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
	303	kfree(pci_mmcfg_config);
	304	pci_mmcfg_config = NULL;
	305	pci_mmcfg_config_num = 0;
44de0203 OH	306	}
44de0203 OH	307
7752d5cf RH	308	void __init pci_mmcfg_early_init(int type)
	309	{
	310	if ((pci_probe & PCI_PROBE_MMCONF) == 0)
	311	return;
	312
	313	/* If type 1 access is available, no need to enable MMCONFIG yet, we can
	314	defer until later when the ACPI interpreter is available to better
	315	validate things. */
	316	if (type == 1)
	317	return;
	318
	319	acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);
	320
	321	if ((pci_mmcfg_config_num == 0) \|\|
	322	(pci_mmcfg_config == NULL) \|\|
	323	(pci_mmcfg_config[0].address == 0))
	324	return;
	325
	326	if (pci_mmcfg_arch_init())
	327	pci_probe = (pci_probe & ~PCI_PROBE_MASK) \| PCI_PROBE_MMCONF;
	328	}
	329
	330	void __init pci_mmcfg_late_init(void)
b7867394	331	{
9358c693 OG	332	int known_bridge = 0;
9358c693 OG	333
7752d5cf	334	/* MMCONFIG disabled */
b7867394 OG	335	if ((pci_probe & PCI_PROBE_MMCONF) == 0)
	336	return;
	337
7752d5cf RH	338	/* MMCONFIG already enabled */
	339	if (!(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
	340	return;
9358c693	341
7752d5cf RH	342	if ((pci_probe & PCI_PROBE_CONF1) && pci_mmcfg_check_hostbridge())
	343	known_bridge = 1;
	344	else
9358c693	345	acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);
7752d5cf RH	346
7752d5cf RH	347	pci_mmcfg_reject_broken();
b7867394 OG	348
	349	if ((pci_mmcfg_config_num == 0) \|\|
	350	(pci_mmcfg_config == NULL) \|\|
	351	(pci_mmcfg_config[0].address == 0))
	352	return;
	353
b7867394	354	if (pci_mmcfg_arch_init()) {
6a0668fc	355	if (known_bridge)
a5ba7971	356	pci_mmcfg_insert_resources(IORESOURCE_BUSY);
b7867394	357	pci_probe = (pci_probe & ~PCI_PROBE_MASK) \| PCI_PROBE_MMCONF;
a5ba7971 AD	358	} else {
	359	/*
	360	* Signal not to attempt to insert mmcfg resources because
	361	* the architecture mmcfg setup could not initialize.
	362	*/
	363	pci_mmcfg_resources_inserted = 1;
b7867394 OG	364	}
b7867394 OG	365	}
a5ba7971 AD	366
	367	static int __init pci_mmcfg_late_insert_resources(void)
	368	{
	369	/*
	370	* If resources are already inserted or we are not using MMCONFIG,
	371	* don't insert the resources.
	372	*/
	373	if ((pci_mmcfg_resources_inserted == 1) \|\|
	374	(pci_probe & PCI_PROBE_MMCONF) == 0 \|\|
	375	(pci_mmcfg_config_num == 0) \|\|
	376	(pci_mmcfg_config == NULL) \|\|
	377	(pci_mmcfg_config[0].address == 0))
	378	return 1;
	379
	380	/*
	381	* Attempt to insert the mmcfg resources but not with the busy flag
	382	* marked so it won't cause request errors when __request_region is
	383	* called.
	384	*/
	385	pci_mmcfg_insert_resources(0);
	386
	387	return 0;
	388	}
	389
	390	/*
	391	* Perform MMCONFIG resource insertion after PCI initialization to allow for
	392	* misprogrammed MCFG tables that state larger sizes but actually conflict
	393	* with other system resources.
	394	*/
	395	late_initcall(pci_mmcfg_late_insert_resources);