[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / pci / mmconfig-shared.c

/*
 * mmconfig-shared.c - Low-level direct PCI config space access via
 *                     MMCONFIG - common code between i386 and x86-64.
 *
 * This code does:
 * - known chipset handling
 * - ACPI decoding and validation
 *
 * Per-architecture code takes care of the mappings and accesses
 * themselves.
 */

#include <linux/pci.h>
#include <linux/init.h>
#include <linux/acpi.h>
#include <linux/bitmap.h>
#include <asm/e820.h>
#include <asm/pci_x86.h>

/* aperture is up to 256MB but BIOS may reserve less */
#define MMCONFIG_APER_MIN	(2 * 1024*1024)
#define MMCONFIG_APER_MAX	(256 * 1024*1024)

/* Indicate if the mmcfg resources have been placed into the resource table. */
static int __initdata pci_mmcfg_resources_inserted;

static const char __init *pci_mmcfg_e7520(void)
{
	u32 win;
	raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);

	win = win & 0xf000;
	if(win == 0x0000 || win == 0xf000)
		pci_mmcfg_config_num = 0;
	else {
		pci_mmcfg_config_num = 1;
		pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
		if (!pci_mmcfg_config)
			return NULL;
		pci_mmcfg_config[0].address = win << 16;
		pci_mmcfg_config[0].pci_segment = 0;
		pci_mmcfg_config[0].start_bus_number = 0;
		pci_mmcfg_config[0].end_bus_number = 255;
	}

	return "Intel Corporation E7520 Memory Controller Hub";
}

static const char __init *pci_mmcfg_intel_945(void)
{
	u32 pciexbar, mask = 0, len = 0;

	pci_mmcfg_config_num = 1;

	raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);

	/* Enable bit */
	if (!(pciexbar & 1))
		pci_mmcfg_config_num = 0;

	/* Size bits */
	switch ((pciexbar >> 1) & 3) {
	case 0:
		mask = 0xf0000000U;
		len  = 0x10000000U;
		break;
	case 1:
		mask = 0xf8000000U;
		len  = 0x08000000U;
		break;
	case 2:
		mask = 0xfc000000U;
		len  = 0x04000000U;
		break;
	default:
		pci_mmcfg_config_num = 0;
	}

	/* Errata #2, things break when not aligned on a 256Mb boundary */
	/* Can only happen in 64M/128M mode */

	if ((pciexbar & mask) & 0x0fffffffU)
		pci_mmcfg_config_num = 0;

	/* Don't hit the APIC registers and their friends */
	if ((pciexbar & mask) >= 0xf0000000U)
		pci_mmcfg_config_num = 0;

	if (pci_mmcfg_config_num) {
		pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
		if (!pci_mmcfg_config)
			return NULL;
		pci_mmcfg_config[0].address = pciexbar & mask;
		pci_mmcfg_config[0].pci_segment = 0;
		pci_mmcfg_config[0].start_bus_number = 0;
		pci_mmcfg_config[0].end_bus_number = (len >> 20) - 1;
	}

	return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
}

static const char __init *pci_mmcfg_amd_fam10h(void)
{
	u32 low, high, address;
	u64 base, msr;
	int i;
	unsigned segnbits = 0, busnbits;

	if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
		return NULL;

	address = MSR_FAM10H_MMIO_CONF_BASE;
	if (rdmsr_safe(address, &low, &high))
		return NULL;

	msr = high;
	msr <<= 32;
	msr |= low;

	/* mmconfig is not enable */
	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
		return NULL;

	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);

	busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
			 FAM10H_MMIO_CONF_BUSRANGE_MASK;

	/*
	 * only handle bus 0 ?
	 * need to skip it
	 */
	if (!busnbits)
		return NULL;

	if (busnbits > 8) {
		segnbits = busnbits - 8;
		busnbits = 8;
	}

	pci_mmcfg_config_num = (1 << segnbits);
	pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]) *
				   pci_mmcfg_config_num, GFP_KERNEL);
	if (!pci_mmcfg_config)
		return NULL;

	for (i = 0; i < (1 << segnbits); i++) {
		pci_mmcfg_config[i].address = base + (1<<28) * i;
		pci_mmcfg_config[i].pci_segment = i;
		pci_mmcfg_config[i].start_bus_number = 0;
		pci_mmcfg_config[i].end_bus_number = (1 << busnbits) - 1;
	}

	return "AMD Family 10h NB";
}

struct pci_mmcfg_hostbridge_probe {
	u32 bus;
	u32 devfn;
	u32 vendor;
	u32 device;
	const char *(*probe)(void);
};

static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
	  PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
	  PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
	{ 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
	  0x1200, pci_mmcfg_amd_fam10h },
	{ 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
	  0x1200, pci_mmcfg_amd_fam10h },
};

static int __init pci_mmcfg_check_hostbridge(void)
{
	u32 l;
	u32 bus, devfn;
	u16 vendor, device;
	int i;
	const char *name;

	if (!raw_pci_ops)
		return 0;

	pci_mmcfg_config_num = 0;
	pci_mmcfg_config = NULL;
	name = NULL;

	for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
		bus =  pci_mmcfg_probes[i].bus;
		devfn = pci_mmcfg_probes[i].devfn;
		raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
		vendor = l & 0xffff;
		device = (l >> 16) & 0xffff;

		if (pci_mmcfg_probes[i].vendor == vendor &&
		    pci_mmcfg_probes[i].device == device)
			name = pci_mmcfg_probes[i].probe();
	}

	if (name) {
		printk(KERN_INFO "PCI: Found %s %s MMCONFIG support.\n",
		       name, pci_mmcfg_config_num ? "with" : "without");
	}

	return name != NULL;
}

static void __init pci_mmcfg_insert_resources(void)
{
#define PCI_MMCFG_RESOURCE_NAME_LEN 19
	int i;
	struct resource *res;
	char *names;
	unsigned num_buses;

	res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
			pci_mmcfg_config_num, GFP_KERNEL);
	if (!res) {
		printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
		return;
	}

	names = (void *)&res[pci_mmcfg_config_num];
	for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
		struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
		num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
		res->name = names;
		snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, "PCI MMCONFIG %u",
			 cfg->pci_segment);
		res->start = cfg->address;
		res->end = res->start + (num_buses << 20) - 1;
		res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
		insert_resource(&iomem_resource, res);
		names += PCI_MMCFG_RESOURCE_NAME_LEN;
	}

	/* Mark that the resources have been inserted. */
	pci_mmcfg_resources_inserted = 1;
}

static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
					      void *data)
{
	struct resource *mcfg_res = data;
	struct acpi_resource_address64 address;
	acpi_status status;

	if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
		struct acpi_resource_fixed_memory32 *fixmem32 =
			&res->data.fixed_memory32;
		if (!fixmem32)
			return AE_OK;
		if ((mcfg_res->start >= fixmem32->address) &&
		    (mcfg_res->end < (fixmem32->address +
				      fixmem32->address_length))) {
			mcfg_res->flags = 1;
			return AE_CTRL_TERMINATE;
		}
	}
	if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
	    (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
		return AE_OK;

	status = acpi_resource_to_address64(res, &address);
	if (ACPI_FAILURE(status) ||
	   (address.address_length <= 0) ||
	   (address.resource_type != ACPI_MEMORY_RANGE))
		return AE_OK;

	if ((mcfg_res->start >= address.minimum) &&
	    (mcfg_res->end < (address.minimum + address.address_length))) {
		mcfg_res->flags = 1;
		return AE_CTRL_TERMINATE;
	}
	return AE_OK;
}

static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
		void *context, void **rv)
{
	struct resource *mcfg_res = context;

	acpi_walk_resources(handle, METHOD_NAME__CRS,
			    check_mcfg_resource, context);

	if (mcfg_res->flags)
		return AE_CTRL_TERMINATE;

	return AE_OK;
}

static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
{
	struct resource mcfg_res;

	mcfg_res.start = start;
	mcfg_res.end = end;
	mcfg_res.flags = 0;

	acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);

	if (!mcfg_res.flags)
		acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
				 NULL);

	return mcfg_res.flags;
}

typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);

static int __init is_mmconf_reserved(check_reserved_t is_reserved,
		u64 addr, u64 size, int i,
		typeof(pci_mmcfg_config[0]) *cfg, int with_e820)
{
	u64 old_size = size;
	int valid = 0;

	while (!is_reserved(addr, addr + size - 1, E820_RESERVED)) {
		size >>= 1;
		if (size < (16UL<<20))
			break;
	}

	if (size >= (16UL<<20) || size == old_size) {
		printk(KERN_NOTICE
		       "PCI: MCFG area at %Lx reserved in %s\n",
			addr, with_e820?"E820":"ACPI motherboard resources");
		valid = 1;

		if (old_size != size) {
			/* update end_bus_number */
			cfg->end_bus_number = cfg->start_bus_number + ((size>>20) - 1);
			printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx "
			       "segment %hu buses %u - %u\n",
			       i, (unsigned long)cfg->address, cfg->pci_segment,
			       (unsigned int)cfg->start_bus_number,
			       (unsigned int)cfg->end_bus_number);
		}
	}

	return valid;
}

static void __init pci_mmcfg_reject_broken(int early)
{
	typeof(pci_mmcfg_config[0]) *cfg;
	int i;

	if ((pci_mmcfg_config_num == 0) ||
	    (pci_mmcfg_config == NULL) ||
	    (pci_mmcfg_config[0].address == 0))
		return;

	cfg = &pci_mmcfg_config[0];

	for (i = 0; i < pci_mmcfg_config_num; i++) {
		int valid = 0;
		u64 addr, size;

		cfg = &pci_mmcfg_config[i];
		addr = cfg->start_bus_number;
		addr <<= 20;
		addr += cfg->address;
		size = cfg->end_bus_number + 1 - cfg->start_bus_number;
		size <<= 20;
		printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
		       "segment %hu buses %u - %u\n",
		       i, (unsigned long)cfg->address, cfg->pci_segment,
		       (unsigned int)cfg->start_bus_number,
		       (unsigned int)cfg->end_bus_number);

		if (!early)
			valid = is_mmconf_reserved(is_acpi_reserved, addr, size, i, cfg, 0);

		if (valid)
			continue;

		if (!early)
			printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
			       " reserved in ACPI motherboard resources\n",
			       cfg->address);

		/* Don't try to do this check unless configuration
		   type 1 is available. how about type 2 ?*/
		if (raw_pci_ops)
			valid = is_mmconf_reserved(e820_all_mapped, addr, size, i, cfg, 1);

		if (!valid)
			goto reject;
	}

	return;

reject:
	printk(KERN_INFO "PCI: Not using MMCONFIG.\n");
	pci_mmcfg_arch_free();
	kfree(pci_mmcfg_config);
	pci_mmcfg_config = NULL;
	pci_mmcfg_config_num = 0;
}

static int __initdata known_bridge;

static void __init __pci_mmcfg_init(int early)
{
	/* MMCONFIG disabled */
	if ((pci_probe & PCI_PROBE_MMCONF) == 0)
		return;

	/* MMCONFIG already enabled */
	if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
		return;

	/* for late to exit */
	if (known_bridge)
		return;

	if (early) {
		if (pci_mmcfg_check_hostbridge())
			known_bridge = 1;
	}

	if (!known_bridge) {
		acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);
		pci_mmcfg_reject_broken(early);
	}

	if ((pci_mmcfg_config_num == 0) ||
	    (pci_mmcfg_config == NULL) ||
	    (pci_mmcfg_config[0].address == 0))
		return;

	if (pci_mmcfg_arch_init())
		pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
	else {
		/*
		 * Signal not to attempt to insert mmcfg resources because
		 * the architecture mmcfg setup could not initialize.
		 */
		pci_mmcfg_resources_inserted = 1;
	}
}

void __init pci_mmcfg_early_init(void)
{
	__pci_mmcfg_init(1);
}

void __init pci_mmcfg_late_init(void)
{
	__pci_mmcfg_init(0);
}

static int __init pci_mmcfg_late_insert_resources(void)
{
	/*
	 * If resources are already inserted or we are not using MMCONFIG,
	 * don't insert the resources.
	 */
	if ((pci_mmcfg_resources_inserted == 1) ||
	    (pci_probe & PCI_PROBE_MMCONF) == 0 ||
	    (pci_mmcfg_config_num == 0) ||
	    (pci_mmcfg_config == NULL) ||
	    (pci_mmcfg_config[0].address == 0))
		return 1;

	/*
	 * Attempt to insert the mmcfg resources but not with the busy flag
	 * marked so it won't cause request errors when __request_region is
	 * called.
	 */
	pci_mmcfg_insert_resources();

	return 0;
}

/*
 * Perform MMCONFIG resource insertion after PCI initialization to allow for
 * misprogrammed MCFG tables that state larger sizes but actually conflict
 * with other system resources.
 */
late_initcall(pci_mmcfg_late_insert_resources);
Commit	Line	Data
b7867394 OG	1	/*
	2	* mmconfig-shared.c - Low-level direct PCI config space access via
	3	* MMCONFIG - common code between i386 and x86-64.
	4	*
	5	* This code does:
9358c693	6	* - known chipset handling
b7867394 OG	7	* - ACPI decoding and validation
	8	*
	9	* Per-architecture code takes care of the mappings and accesses
	10	* themselves.
	11	*/
	12
	13	#include <linux/pci.h>
	14	#include <linux/init.h>
	15	#include <linux/acpi.h>
	16	#include <linux/bitmap.h>
	17	#include <asm/e820.h>
82487711	18	#include <asm/pci_x86.h>
b7867394 OG	19
	20	/* aperture is up to 256MB but BIOS may reserve less */
	21	#define MMCONFIG_APER_MIN (2 * 1024*1024)
	22	#define MMCONFIG_APER_MAX (256 * 1024*1024)
	23
a5ba7971 AD	24	/* Indicate if the mmcfg resources have been placed into the resource table. */
	25	static int __initdata pci_mmcfg_resources_inserted;
	26
429d512e	27	static const char __init *pci_mmcfg_e7520(void)
9358c693 OG	28	{
9358c693 OG	29	u32 win;
bb63b421	30	raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
9358c693	31
b5229dbb OG	32	win = win & 0xf000;
	33	if(win == 0x0000 \|\| win == 0xf000)
	34	pci_mmcfg_config_num = 0;
	35	else {
	36	pci_mmcfg_config_num = 1;
	37	pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
	38	if (!pci_mmcfg_config)
	39	return NULL;
	40	pci_mmcfg_config[0].address = win << 16;
	41	pci_mmcfg_config[0].pci_segment = 0;
	42	pci_mmcfg_config[0].start_bus_number = 0;
	43	pci_mmcfg_config[0].end_bus_number = 255;
	44	}
9358c693 OG	45
	46	return "Intel Corporation E7520 Memory Controller Hub";
	47	}
	48
429d512e	49	static const char __init *pci_mmcfg_intel_945(void)
9358c693 OG	50	{
	51	u32 pciexbar, mask = 0, len = 0;
	52
	53	pci_mmcfg_config_num = 1;
	54
bb63b421	55	raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
9358c693 OG	56
	57	/* Enable bit */
	58	if (!(pciexbar & 1))
	59	pci_mmcfg_config_num = 0;
	60
	61	/* Size bits */
	62	switch ((pciexbar >> 1) & 3) {
	63	case 0:
	64	mask = 0xf0000000U;
	65	len = 0x10000000U;
	66	break;
	67	case 1:
	68	mask = 0xf8000000U;
	69	len = 0x08000000U;
	70	break;
	71	case 2:
	72	mask = 0xfc000000U;
	73	len = 0x04000000U;
	74	break;
	75	default:
	76	pci_mmcfg_config_num = 0;
	77	}
	78
	79	/* Errata #2, things break when not aligned on a 256Mb boundary */
	80	/* Can only happen in 64M/128M mode */
	81
	82	if ((pciexbar & mask) & 0x0fffffffU)
	83	pci_mmcfg_config_num = 0;
	84
b5229dbb OG	85	/* Don't hit the APIC registers and their friends */
	86	if ((pciexbar & mask) >= 0xf0000000U)
	87	pci_mmcfg_config_num = 0;
	88
9358c693 OG	89	if (pci_mmcfg_config_num) {
	90	pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
	91	if (!pci_mmcfg_config)
	92	return NULL;
	93	pci_mmcfg_config[0].address = pciexbar & mask;
	94	pci_mmcfg_config[0].pci_segment = 0;
	95	pci_mmcfg_config[0].start_bus_number = 0;
	96	pci_mmcfg_config[0].end_bus_number = (len >> 20) - 1;
	97	}
	98
	99	return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
	100	}
	101
7fd0da40 YL	102	static const char __init *pci_mmcfg_amd_fam10h(void)
	103	{
	104	u32 low, high, address;
	105	u64 base, msr;
	106	int i;
	107	unsigned segnbits = 0, busnbits;
	108
5f0b2976 YL	109	if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
	110	return NULL;
	111
7fd0da40 YL	112	address = MSR_FAM10H_MMIO_CONF_BASE;
	113	if (rdmsr_safe(address, &low, &high))
	114	return NULL;
	115
	116	msr = high;
	117	msr <<= 32;
	118	msr \|= low;
	119
	120	/* mmconfig is not enable */
	121	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
	122	return NULL;
	123
	124	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
	125
	126	busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
	127	FAM10H_MMIO_CONF_BUSRANGE_MASK;
	128
	129	/*
	130	* only handle bus 0 ?
	131	* need to skip it
	132	*/
	133	if (!busnbits)
	134	return NULL;
	135
	136	if (busnbits > 8) {
	137	segnbits = busnbits - 8;
	138	busnbits = 8;
	139	}
	140
	141	pci_mmcfg_config_num = (1 << segnbits);
	142	pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]) *
	143	pci_mmcfg_config_num, GFP_KERNEL);
	144	if (!pci_mmcfg_config)
	145	return NULL;
	146
	147	for (i = 0; i < (1 << segnbits); i++) {
	148	pci_mmcfg_config[i].address = base + (1<<28) * i;
	149	pci_mmcfg_config[i].pci_segment = i;
	150	pci_mmcfg_config[i].start_bus_number = 0;
	151	pci_mmcfg_config[i].end_bus_number = (1 << busnbits) - 1;
	152	}
	153
	154	return "AMD Family 10h NB";
	155	}
	156
9358c693	157	struct pci_mmcfg_hostbridge_probe {
7fd0da40 YL	158	u32 bus;
7fd0da40 YL	159	u32 devfn;
9358c693 OG	160	u32 vendor;
	161	u32 device;
	162	const char (probe)(void);
	163	};
	164
429d512e	165	static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
7fd0da40 YL	166	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
	167	PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
	168	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
	169	PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
	170	{ 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
	171	0x1200, pci_mmcfg_amd_fam10h },
	172	{ 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
	173	0x1200, pci_mmcfg_amd_fam10h },
9358c693 OG	174	};
	175
	176	static int __init pci_mmcfg_check_hostbridge(void)
	177	{
	178	u32 l;
7fd0da40	179	u32 bus, devfn;
9358c693 OG	180	u16 vendor, device;
	181	int i;
	182	const char *name;
	183
bb63b421 YL	184	if (!raw_pci_ops)
	185	return 0;
	186
9358c693 OG	187	pci_mmcfg_config_num = 0;
	188	pci_mmcfg_config = NULL;
	189	name = NULL;
	190
429d512e	191	for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
7fd0da40 YL	192	bus = pci_mmcfg_probes[i].bus;
7fd0da40 YL	193	devfn = pci_mmcfg_probes[i].devfn;
bb63b421	194	raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
7fd0da40 YL	195	vendor = l & 0xffff;
	196	device = (l >> 16) & 0xffff;
	197
429d512e OH	198	if (pci_mmcfg_probes[i].vendor == vendor &&
429d512e OH	199	pci_mmcfg_probes[i].device == device)
9358c693	200	name = pci_mmcfg_probes[i].probe();
429d512e	201	}
9358c693 OG	202
9358c693 OG	203	if (name) {
429d512e OH	204	printk(KERN_INFO "PCI: Found %s %s MMCONFIG support.\n",
429d512e OH	205	name, pci_mmcfg_config_num ? "with" : "without");
9358c693 OG	206	}
	207
	208	return name != NULL;
	209	}
	210
ebd60cd6	211	static void __init pci_mmcfg_insert_resources(void)
6a0668fc OG	212	{
	213	#define PCI_MMCFG_RESOURCE_NAME_LEN 19
	214	int i;
	215	struct resource *res;
	216	char *names;
	217	unsigned num_buses;
	218
	219	res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
	220	pci_mmcfg_config_num, GFP_KERNEL);
6a0668fc OG	221	if (!res) {
	222	printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
	223	return;
	224	}
	225
	226	names = (void *)&res[pci_mmcfg_config_num];
	227	for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
429d512e OH	228	struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
429d512e OH	229	num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
6a0668fc OG	230	res->name = names;
6a0668fc OG	231	snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, "PCI MMCONFIG %u",
429d512e OH	232	cfg->pci_segment);
429d512e OH	233	res->start = cfg->address;
6a0668fc	234	res->end = res->start + (num_buses << 20) - 1;
ebd60cd6	235	res->flags = IORESOURCE_MEM \| IORESOURCE_BUSY;
6a0668fc OG	236	insert_resource(&iomem_resource, res);
	237	names += PCI_MMCFG_RESOURCE_NAME_LEN;
	238	}
a5ba7971 AD	239
	240	/* Mark that the resources have been inserted. */
	241	pci_mmcfg_resources_inserted = 1;
6a0668fc OG	242	}
6a0668fc OG	243
7752d5cf RH	244	static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
	245	void *data)
	246	{
	247	struct resource *mcfg_res = data;
	248	struct acpi_resource_address64 address;
	249	acpi_status status;
	250
	251	if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
	252	struct acpi_resource_fixed_memory32 *fixmem32 =
	253	&res->data.fixed_memory32;
	254	if (!fixmem32)
	255	return AE_OK;
	256	if ((mcfg_res->start >= fixmem32->address) &&
	257	(mcfg_res->end < (fixmem32->address +
	258	fixmem32->address_length))) {
	259	mcfg_res->flags = 1;
	260	return AE_CTRL_TERMINATE;
	261	}
	262	}
	263	if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
	264	(res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
	265	return AE_OK;
	266
	267	status = acpi_resource_to_address64(res, &address);
	268	if (ACPI_FAILURE(status) \|\|
	269	(address.address_length <= 0) \|\|
	270	(address.resource_type != ACPI_MEMORY_RANGE))
	271	return AE_OK;
	272
	273	if ((mcfg_res->start >= address.minimum) &&
	274	(mcfg_res->end < (address.minimum + address.address_length))) {
	275	mcfg_res->flags = 1;
	276	return AE_CTRL_TERMINATE;
	277	}
	278	return AE_OK;
	279	}
	280
	281	static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
	282	void context, void *rv)
	283	{
	284	struct resource *mcfg_res = context;
	285
	286	acpi_walk_resources(handle, METHOD_NAME__CRS,
	287	check_mcfg_resource, context);
	288
	289	if (mcfg_res->flags)
	290	return AE_CTRL_TERMINATE;
	291
	292	return AE_OK;
	293	}
	294
a83fe32f	295	static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
7752d5cf RH	296	{
	297	struct resource mcfg_res;
	298
	299	mcfg_res.start = start;
	300	mcfg_res.end = end;
	301	mcfg_res.flags = 0;
	302
	303	acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
	304
	305	if (!mcfg_res.flags)
	306	acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
	307	NULL);
	308
	309	return mcfg_res.flags;
	310	}
	311
a83fe32f YL	312	typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
	313
	314	static int __init is_mmconf_reserved(check_reserved_t is_reserved,
	315	u64 addr, u64 size, int i,
	316	typeof(pci_mmcfg_config[0]) *cfg, int with_e820)
	317	{
	318	u64 old_size = size;
	319	int valid = 0;
	320
	321	while (!is_reserved(addr, addr + size - 1, E820_RESERVED)) {
	322	size >>= 1;
	323	if (size < (16UL<<20))
	324	break;
	325	}
	326
	327	if (size >= (16UL<<20) \|\| size == old_size) {
	328	printk(KERN_NOTICE
	329	"PCI: MCFG area at %Lx reserved in %s\n",
	330	addr, with_e820?"E820":"ACPI motherboard resources");
	331	valid = 1;
	332
	333	if (old_size != size) {
	334	/* update end_bus_number */
	335	cfg->end_bus_number = cfg->start_bus_number + ((size>>20) - 1);
	336	printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx "
	337	"segment %hu buses %u - %u\n",
	338	i, (unsigned long)cfg->address, cfg->pci_segment,
	339	(unsigned int)cfg->start_bus_number,
	340	(unsigned int)cfg->end_bus_number);
	341	}
	342	}
	343
	344	return valid;
	345	}
	346
bb63b421	347	static void __init pci_mmcfg_reject_broken(int early)
44de0203	348	{
26054ed0	349	typeof(pci_mmcfg_config[0]) *cfg;
7752d5cf	350	int i;
26054ed0 OH	351
	352	if ((pci_mmcfg_config_num == 0) \|\|
	353	(pci_mmcfg_config == NULL) \|\|
	354	(pci_mmcfg_config[0].address == 0))
	355	return;
	356
	357	cfg = &pci_mmcfg_config[0];
44de0203	358
7752d5cf	359	for (i = 0; i < pci_mmcfg_config_num; i++) {
05c58b8a	360	int valid = 0;
a83fe32f YL	361	u64 addr, size;
a83fe32f YL	362
7752d5cf	363	cfg = &pci_mmcfg_config[i];
a83fe32f YL	364	addr = cfg->start_bus_number;
	365	addr <<= 20;
	366	addr += cfg->address;
	367	size = cfg->end_bus_number + 1 - cfg->start_bus_number;
	368	size <<= 20;
05c58b8a	369	printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
7752d5cf RH	370	"segment %hu buses %u - %u\n",
	371	i, (unsigned long)cfg->address, cfg->pci_segment,
	372	(unsigned int)cfg->start_bus_number,
	373	(unsigned int)cfg->end_bus_number);
05c58b8a	374
a83fe32f YL	375	if (!early)
a83fe32f YL	376	valid = is_mmconf_reserved(is_acpi_reserved, addr, size, i, cfg, 0);
05c58b8a YL	377
	378	if (valid)
	379	continue;
	380
	381	if (!early)
7752d5cf RH	382	printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
	383	" reserved in ACPI motherboard resources\n",
	384	cfg->address);
a83fe32f	385
05c58b8a	386	/* Don't try to do this check unless configuration
bb63b421	387	type 1 is available. how about type 2 ?*/
a83fe32f YL	388	if (raw_pci_ops)
a83fe32f YL	389	valid = is_mmconf_reserved(e820_all_mapped, addr, size, i, cfg, 1);
05c58b8a YL	390
	391	if (!valid)
	392	goto reject;
44de0203	393	}
7752d5cf	394
26054ed0 OH	395	return;
	396
	397	reject:
ef310237	398	printk(KERN_INFO "PCI: Not using MMCONFIG.\n");
0b64ad71	399	pci_mmcfg_arch_free();
26054ed0 OH	400	kfree(pci_mmcfg_config);
	401	pci_mmcfg_config = NULL;
	402	pci_mmcfg_config_num = 0;
44de0203 OH	403	}
44de0203 OH	404
05c58b8a	405	static int __initdata known_bridge;
7752d5cf	406
968cbfad	407	static void __init __pci_mmcfg_init(int early)
b7867394	408	{
7752d5cf	409	/* MMCONFIG disabled */
b7867394 OG	410	if ((pci_probe & PCI_PROBE_MMCONF) == 0)
	411	return;
	412
7752d5cf	413	/* MMCONFIG already enabled */
05c58b8a	414	if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
7752d5cf	415	return;
9358c693	416
05c58b8a YL	417	/* for late to exit */
	418	if (known_bridge)
	419	return;
7752d5cf	420
bb63b421	421	if (early) {
05c58b8a YL	422	if (pci_mmcfg_check_hostbridge())
	423	known_bridge = 1;
	424	}
	425
	426	if (!known_bridge) {
	427	acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);
bb63b421	428	pci_mmcfg_reject_broken(early);
05c58b8a	429	}
b7867394 OG	430
	431	if ((pci_mmcfg_config_num == 0) \|\|
	432	(pci_mmcfg_config == NULL) \|\|
	433	(pci_mmcfg_config[0].address == 0))
	434	return;
	435
ebd60cd6	436	if (pci_mmcfg_arch_init())
b7867394	437	pci_probe = (pci_probe & ~PCI_PROBE_MASK) \| PCI_PROBE_MMCONF;
ebd60cd6	438	else {
a5ba7971 AD	439	/*
	440	* Signal not to attempt to insert mmcfg resources because
	441	* the architecture mmcfg setup could not initialize.
	442	*/
	443	pci_mmcfg_resources_inserted = 1;
b7867394 OG	444	}
b7867394 OG	445	}
a5ba7971	446
bb63b421	447	void __init pci_mmcfg_early_init(void)
05c58b8a	448	{
bb63b421	449	__pci_mmcfg_init(1);
05c58b8a YL	450	}
	451
	452	void __init pci_mmcfg_late_init(void)
	453	{
bb63b421	454	__pci_mmcfg_init(0);
05c58b8a YL	455	}
05c58b8a YL	456
a5ba7971 AD	457	static int __init pci_mmcfg_late_insert_resources(void)
	458	{
	459	/*
	460	* If resources are already inserted or we are not using MMCONFIG,
	461	* don't insert the resources.
	462	*/
	463	if ((pci_mmcfg_resources_inserted == 1) \|\|
	464	(pci_probe & PCI_PROBE_MMCONF) == 0 \|\|
	465	(pci_mmcfg_config_num == 0) \|\|
	466	(pci_mmcfg_config == NULL) \|\|
	467	(pci_mmcfg_config[0].address == 0))
	468	return 1;
	469
	470	/*
	471	* Attempt to insert the mmcfg resources but not with the busy flag
	472	* marked so it won't cause request errors when __request_region is
	473	* called.
	474	*/
ebd60cd6	475	pci_mmcfg_insert_resources();
a5ba7971 AD	476
	477	return 0;
	478	}
	479
	480	/*
	481	* Perform MMCONFIG resource insertion after PCI initialization to allow for
	482	* misprogrammed MCFG tables that state larger sizes but actually conflict
	483	* with other system resources.
	484	*/
	485	late_initcall(pci_mmcfg_late_insert_resources);