[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / pci / fixup.c

/*
 * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
 */

#include <linux/delay.h>
#include <linux/dmi.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/vgaarb.h>
#include <asm/pci_x86.h>

static void pci_fixup_i450nx(struct pci_dev *d)
{
	/*
	 * i450NX -- Find and scan all secondary buses on all PXB's.
	 */
	int pxb, reg;
	u8 busno, suba, subb;

	dev_warn(&d->dev, "Searching for i450NX host bridges\n");
	reg = 0xd0;
	for(pxb = 0; pxb < 2; pxb++) {
		pci_read_config_byte(d, reg++, &busno);
		pci_read_config_byte(d, reg++, &suba);
		pci_read_config_byte(d, reg++, &subb);
		dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno,
			suba, subb);
		if (busno)
			pci_scan_bus_with_sysdata(busno);	/* Bus A */
		if (suba < subb)
			pci_scan_bus_with_sysdata(suba+1);	/* Bus B */
	}
	pcibios_last_bus = -1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);

static void pci_fixup_i450gx(struct pci_dev *d)
{
	/*
	 * i450GX and i450KX -- Find and scan all secondary buses.
	 * (called separately for each PCI bridge found)
	 */
	u8 busno;
	pci_read_config_byte(d, 0x4a, &busno);
	dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno);
	pci_scan_bus_with_sysdata(busno);
	pcibios_last_bus = -1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx);

static void pci_fixup_umc_ide(struct pci_dev *d)
{
	/*
	 * UM8886BF IDE controller sets region type bits incorrectly,
	 * therefore they look like memory despite of them being I/O.
	 */
	int i;

	dev_warn(&d->dev, "Fixing base address flags\n");
	for(i = 0; i < 4; i++)
		d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);

static void pci_fixup_ncr53c810(struct pci_dev *d)
{
	/*
	 * NCR 53C810 returns class code 0 (at least on some systems).
	 * Fix class to be PCI_CLASS_STORAGE_SCSI
	 */
	if (!d->class) {
		dev_warn(&d->dev, "Fixing NCR 53C810 class code\n");
		d->class = PCI_CLASS_STORAGE_SCSI << 8;
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810);

static void pci_fixup_latency(struct pci_dev *d)
{
	/*
	 *  SiS 5597 and 5598 chipsets require latency timer set to
	 *  at most 32 to avoid lockups.
	 */
	dev_dbg(&d->dev, "Setting max latency to 32\n");
	pcibios_max_latency = 32;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);

static void pci_fixup_piix4_acpi(struct pci_dev *d)
{
	/*
	 * PIIX4 ACPI device: hardwired IRQ9
	 */
	d->irq = 9;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi);

/*
 * Addresses issues with problems in the memory write queue timer in
 * certain VIA Northbridges.  This bugfix is per VIA's specifications,
 * except for the KL133/KM133: clearing bit 5 on those Northbridges seems
 * to trigger a bug in its integrated ProSavage video card, which
 * causes screen corruption.  We only clear bits 6 and 7 for that chipset,
 * until VIA can provide us with definitive information on why screen
 * corruption occurs, and what exactly those bits do.
 *
 * VIA 8363,8622,8361 Northbridges:
 *  - bits  5, 6, 7 at offset 0x55 need to be turned off
 * VIA 8367 (KT266x) Northbridges:
 *  - bits  5, 6, 7 at offset 0x95 need to be turned off
 * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
 *  - bits     6, 7 at offset 0x55 need to be turned off
 */

#define VIA_8363_KL133_REVISION_ID 0x81
#define VIA_8363_KM133_REVISION_ID 0x84

static void pci_fixup_via_northbridge_bug(struct pci_dev *d)
{
	u8 v;
	int where = 0x55;
	int mask = 0x1f; /* clear bits 5, 6, 7 by default */

	if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
		/* fix pci bus latency issues resulted by NB bios error
		   it appears on bug free^Wreduced kt266x's bios forces
		   NB latency to zero */
		pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);

		where = 0x95; /* the memory write queue timer register is
				different for the KT266x's: 0x95 not 0x55 */
	} else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
			(d->revision == VIA_8363_KL133_REVISION_ID ||
			d->revision == VIA_8363_KM133_REVISION_ID)) {
			mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
					causes screen corruption on the KL133/KM133 */
	}

	pci_read_config_byte(d, where, &v);
	if (v & ~mask) {
		dev_warn(&d->dev, "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
			d->device, d->revision, where, v, mask, v & mask);
		v &= mask;
		pci_write_config_byte(d, where, v);
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);

/*
 * For some reasons Intel decided that certain parts of their
 * 815, 845 and some other chipsets must look like PCI-to-PCI bridges
 * while they are obviously not. The 82801 family (AA, AB, BAM/CAM,
 * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according
 * to Intel terminology. These devices do forward all addresses from
 * system to PCI bus no matter what are their window settings, so they are
 * "transparent" (or subtractive decoding) from programmers point of view.
 */
static void pci_fixup_transparent_bridge(struct pci_dev *dev)
{
	if ((dev->device & 0xff00) == 0x2400)
		dev->transparent = 1;
}
DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
			 PCI_CLASS_BRIDGE_PCI, 8, pci_fixup_transparent_bridge);

/*
 * Fixup for C1 Halt Disconnect problem on nForce2 systems.
 *
 * From information provided by "Allen Martin" <AMartin@nvidia.com>:
 *
 * A hang is caused when the CPU generates a very fast CONNECT/HALT cycle
 * sequence.  Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns.
 * This allows the state-machine and timer to return to a proper state within
 * 80 ns of the CONNECT and probe appearing together.  Since the CPU will not
 * issue another HALT within 80 ns of the initial HALT, the failure condition
 * is avoided.
 */
static void pci_fixup_nforce2(struct pci_dev *dev)
{
	u32 val;

	/*
	 * Chip  Old value   New value
	 * C17   0x1F0FFF01  0x1F01FF01
	 * C18D  0x9F0FFF01  0x9F01FF01
	 *
	 * Northbridge chip version may be determined by
	 * reading the PCI revision ID (0xC1 or greater is C18D).
	 */
	pci_read_config_dword(dev, 0x6c, &val);

	/*
	 * Apply fixup if needed, but don't touch disconnect state
	 */
	if ((val & 0x00FF0000) != 0x00010000) {
		dev_warn(&dev->dev, "nForce2 C1 Halt Disconnect fixup\n");
		pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000);
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);

/* Max PCI Express root ports */
#define MAX_PCIEROOT	6
static int quirk_aspm_offset[MAX_PCIEROOT << 3];

#define GET_INDEX(a, b) ((((a) - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + ((b) & 7))

static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
{
	return raw_pci_read(pci_domain_nr(bus), bus->number,
						devfn, where, size, value);
}

/*
 * Replace the original pci bus ops for write with a new one that will filter
 * the request to insure ASPM cannot be enabled.
 */
static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
{
	u8 offset;

	offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)];

	if ((offset) && (where == offset))
		value = value & 0xfffffffc;

	return raw_pci_write(pci_domain_nr(bus), bus->number,
						devfn, where, size, value);
}

static struct pci_ops quirk_pcie_aspm_ops = {
	.read = quirk_pcie_aspm_read,
	.write = quirk_pcie_aspm_write,
};

/*
 * Prevents PCI Express ASPM (Active State Power Management) being enabled.
 *
 * Save the register offset, where the ASPM control bits are located,
 * for each PCI Express device that is in the device list of
 * the root port in an array for fast indexing. Replace the bus ops
 * with the modified one.
 */
static void pcie_rootport_aspm_quirk(struct pci_dev *pdev)
{
	int cap_base, i;
	struct pci_bus  *pbus;
	struct pci_dev *dev;

	if ((pbus = pdev->subordinate) == NULL)
		return;

	/*
	 * Check if the DID of pdev matches one of the six root ports. This
	 * check is needed in the case this function is called directly by the
	 * hot-plug driver.
	 */
	if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) ||
	    (pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1))
		return;

	if (list_empty(&pbus->devices)) {
		/*
		 * If no device is attached to the root port at power-up or
		 * after hot-remove, the pbus->devices is empty and this code
		 * will set the offsets to zero and the bus ops to parent's bus
		 * ops, which is unmodified.
		 */
		for (i = GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i)
			quirk_aspm_offset[i] = 0;

		pbus->ops = pbus->parent->ops;
	} else {
		/*
		 * If devices are attached to the root port at power-up or
		 * after hot-add, the code loops through the device list of
		 * each root port to save the register offsets and replace the
		 * bus ops.
		 */
		list_for_each_entry(dev, &pbus->devices, bus_list) {
			/* There are 0 to 8 devices attached to this bus */
			cap_base = pci_find_capability(dev, PCI_CAP_ID_EXP);
			quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)] = cap_base + 0x10;
		}
		pbus->ops = &quirk_pcie_aspm_ops;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PA,	pcie_rootport_aspm_quirk);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PA1,	pcie_rootport_aspm_quirk);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PB,	pcie_rootport_aspm_quirk);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PB1,	pcie_rootport_aspm_quirk);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PC,	pcie_rootport_aspm_quirk);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PC1,	pcie_rootport_aspm_quirk);

/*
 * Fixup to mark boot BIOS video selected by BIOS before it changes
 *
 * From information provided by "Jon Smirl" <jonsmirl@gmail.com>
 *
 * The standard boot ROM sequence for an x86 machine uses the BIOS
 * to select an initial video card for boot display. This boot video
 * card will have it's BIOS copied to C0000 in system RAM.
 * IORESOURCE_ROM_SHADOW is used to associate the boot video
 * card with this copy. On laptops this copy has to be used since
 * the main ROM may be compressed or combined with another image.
 * See pci_map_rom() for use of this flag. IORESOURCE_ROM_SHADOW
 * is marked here since the boot video device will be the only enabled
 * video device at this point.
 */

static void pci_fixup_video(struct pci_dev *pdev)
{
	struct pci_dev *bridge;
	struct pci_bus *bus;
	u16 config;

	/* Is VGA routed to us? */
	bus = pdev->bus;
	while (bus) {
		bridge = bus->self;

		/*
		 * From information provided by
		 * "David Miller" <davem@davemloft.net>
		 * The bridge control register is valid for PCI header
		 * type BRIDGE, or CARDBUS. Host to PCI controllers use
		 * PCI header type NORMAL.
		 */
		if (bridge
		    && ((bridge->hdr_type == PCI_HEADER_TYPE_BRIDGE)
		       || (bridge->hdr_type == PCI_HEADER_TYPE_CARDBUS))) {
			pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
						&config);
			if (!(config & PCI_BRIDGE_CTL_VGA))
				return;
		}
		bus = bus->parent;
	}
	pci_read_config_word(pdev, PCI_COMMAND, &config);
	if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
		pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW;
		dev_printk(KERN_DEBUG, &pdev->dev, "Boot video device\n");
		if (!vga_default_device())
			vga_set_default_device(pdev);
	}
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
				PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_video);


static const struct dmi_system_id msi_k8t_dmi_table[] = {
	{
		.ident = "MSI-K8T-Neo2Fir",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
			DMI_MATCH(DMI_PRODUCT_NAME, "MS-6702E"),
		},
	},
	{}
};

/*
 * The AMD-Athlon64 board MSI "K8T Neo2-FIR" disables the onboard sound
 * card if a PCI-soundcard is added.
 *
 * The BIOS only gives options "DISABLED" and "AUTO". This code sets
 * the corresponding register-value to enable the soundcard.
 *
 * The soundcard is only enabled, if the mainborad is identified
 * via DMI-tables and the soundcard is detected to be off.
 */
static void pci_fixup_msi_k8t_onboard_sound(struct pci_dev *dev)
{
	unsigned char val;
	if (!dmi_check_system(msi_k8t_dmi_table))
		return; /* only applies to MSI K8T Neo2-FIR */

	pci_read_config_byte(dev, 0x50, &val);
	if (val & 0x40) {
		pci_write_config_byte(dev, 0x50, val & (~0x40));

		/* verify the change for status output */
		pci_read_config_byte(dev, 0x50, &val);
		if (val & 0x40)
			dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
					"can't enable onboard soundcard!\n");
		else
			dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
					"enabled onboard soundcard\n");
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
		pci_fixup_msi_k8t_onboard_sound);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
		pci_fixup_msi_k8t_onboard_sound);

/*
 * Some Toshiba laptops need extra code to enable their TI TSB43AB22/A.
 *
 * We pretend to bring them out of full D3 state, and restore the proper
 * IRQ, PCI cache line size, and BARs, otherwise the device won't function
 * properly.  In some cases, the device will generate an interrupt on
 * the wrong IRQ line, causing any devices sharing the line it's
 * *supposed* to use to be disabled by the kernel's IRQ debug code.
 */
static u16 toshiba_line_size;

static const struct dmi_system_id toshiba_ohci1394_dmi_table[] = {
	{
		.ident = "Toshiba PS5 based laptop",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
			DMI_MATCH(DMI_PRODUCT_VERSION, "PS5"),
		},
	},
	{
		.ident = "Toshiba PSM4 based laptop",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
			DMI_MATCH(DMI_PRODUCT_VERSION, "PSM4"),
		},
	},
	{
		.ident = "Toshiba A40 based laptop",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
			DMI_MATCH(DMI_PRODUCT_VERSION, "PSA40U"),
		},
	},
	{ }
};

static void pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev)
{
	if (!dmi_check_system(toshiba_ohci1394_dmi_table))
		return; /* only applies to certain Toshibas (so far) */

	dev->current_state = PCI_D3cold;
	pci_read_config_word(dev, PCI_CACHE_LINE_SIZE, &toshiba_line_size);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032,
			 pci_pre_fixup_toshiba_ohci1394);

static void pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev)
{
	if (!dmi_check_system(toshiba_ohci1394_dmi_table))
		return; /* only applies to certain Toshibas (so far) */

	/* Restore config space on Toshiba laptops */
	pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size);
	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, (u8 *)&dev->irq);
	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
			       pci_resource_start(dev, 0));
	pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
			       pci_resource_start(dev, 1));
}
DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032,
			 pci_post_fixup_toshiba_ohci1394);


/*
 * Prevent the BIOS trapping accesses to the Cyrix CS5530A video device
 * configuration space.
 */
static void pci_early_fixup_cyrix_5530(struct pci_dev *dev)
{
	u8 r;
	/* clear 'F4 Video Configuration Trap' bit */
	pci_read_config_byte(dev, 0x42, &r);
	r &= 0xfd;
	pci_write_config_byte(dev, 0x42, r);
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
			pci_early_fixup_cyrix_5530);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
			pci_early_fixup_cyrix_5530);

/*
 * Siemens Nixdorf AG FSC Multiprocessor Interrupt Controller:
 * prevent update of the BAR0, which doesn't look like a normal BAR.
 */
static void pci_siemens_interrupt_controller(struct pci_dev *dev)
{
	dev->resource[0].flags |= IORESOURCE_PCI_FIXED;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015,
			  pci_siemens_interrupt_controller);

/*
 * SB600: Disable BAR1 on device 14.0 to avoid HPET resources from
 * confusing the PCI engine:
 */
static void sb600_disable_hpet_bar(struct pci_dev *dev)
{
	u8 val;

	/*
	 * The SB600 and SB700 both share the same device
	 * ID, but the PM register 0x55 does something different
	 * for the SB700, so make sure we are dealing with the
	 * SB600 before touching the bit:
	 */

	pci_read_config_byte(dev, 0x08, &val);

	if (val < 0x2F) {
		outb(0x55, 0xCD6);
		val = inb(0xCD7);

		/* Set bit 7 in PM register 0x55 */
		outb(0x55, 0xCD6);
		outb(val | 0x80, 0xCD7);
	}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4385, sb600_disable_hpet_bar);

/*
 * Twinhead H12Y needs us to block out a region otherwise we map devices
 * there and any access kills the box.
 *
 *   See: https://bugzilla.kernel.org/show_bug.cgi?id=10231
 *
 * Match off the LPC and svid/sdid (older kernels lose the bridge subvendor)
 */
static void twinhead_reserve_killing_zone(struct pci_dev *dev)
{
        if (dev->subsystem_vendor == 0x14FF && dev->subsystem_device == 0xA003) {
                pr_info("Reserving memory on Twinhead H12Y\n");
                request_mem_region(0xFFB00000, 0x100000, "twinhead");
        }
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x27B9, twinhead_reserve_killing_zone);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Exceptions for specific devices. Usually work-arounds for fatal design flaws.
	3	*/
	4
f8977d0a JB	5	#include <linux/delay.h>
f8977d0a JB	6	#include <linux/dmi.h>
1da177e4 LT	7	#include <linux/pci.h>
1da177e4 LT	8	#include <linux/init.h>
db2e034d	9	#include <linux/vgaarb.h>
82487711	10	#include <asm/pci_x86.h>
1da177e4	11
a18e3690	12	static void pci_fixup_i450nx(struct pci_dev *d)
1da177e4 LT	13	{
	14	/*
	15	* i450NX -- Find and scan all secondary buses on all PXB's.
	16	*/
	17	int pxb, reg;
	18	u8 busno, suba, subb;
	19
9ed88554	20	dev_warn(&d->dev, "Searching for i450NX host bridges\n");
1da177e4	21	reg = 0xd0;
938f6671	22	for(pxb = 0; pxb < 2; pxb++) {
1da177e4 LT	23	pci_read_config_byte(d, reg++, &busno);
	24	pci_read_config_byte(d, reg++, &suba);
	25	pci_read_config_byte(d, reg++, &subb);
12c0b20f BH	26	dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno,
12c0b20f BH	27	suba, subb);
1da177e4	28	if (busno)
73c59afc	29	pci_scan_bus_with_sysdata(busno); /* Bus A */
1da177e4	30	if (suba < subb)
73c59afc	31	pci_scan_bus_with_sysdata(suba+1); /* Bus B */
1da177e4 LT	32	}
	33	pcibios_last_bus = -1;
	34	}
	35	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
	36
a18e3690	37	static void pci_fixup_i450gx(struct pci_dev *d)
1da177e4 LT	38	{
	39	/*
	40	* i450GX and i450KX -- Find and scan all secondary buses.
	41	* (called separately for each PCI bridge found)
	42	*/
	43	u8 busno;
	44	pci_read_config_byte(d, 0x4a, &busno);
9ed88554	45	dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno);
73c59afc	46	pci_scan_bus_with_sysdata(busno);
1da177e4 LT	47	pcibios_last_bus = -1;
	48	}
	49	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx);
	50
a18e3690	51	static void pci_fixup_umc_ide(struct pci_dev *d)
1da177e4 LT	52	{
	53	/*
	54	* UM8886BF IDE controller sets region type bits incorrectly,
	55	* therefore they look like memory despite of them being I/O.
	56	*/
	57	int i;
	58
9ed88554	59	dev_warn(&d->dev, "Fixing base address flags\n");
938f6671	60	for(i = 0; i < 4; i++)
1da177e4 LT	61	d->resource[i].flags \|= PCI_BASE_ADDRESS_SPACE_IO;
	62	}
	63	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
	64
a18e3690	65	static void pci_fixup_ncr53c810(struct pci_dev *d)
1da177e4 LT	66	{
	67	/*
	68	* NCR 53C810 returns class code 0 (at least on some systems).
	69	* Fix class to be PCI_CLASS_STORAGE_SCSI
	70	*/
	71	if (!d->class) {
9ed88554	72	dev_warn(&d->dev, "Fixing NCR 53C810 class code\n");
1da177e4 LT	73	d->class = PCI_CLASS_STORAGE_SCSI << 8;
	74	}
	75	}
	76	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810);
	77
a18e3690	78	static void pci_fixup_latency(struct pci_dev *d)
1da177e4 LT	79	{
	80	/*
	81	* SiS 5597 and 5598 chipsets require latency timer set to
	82	* at most 32 to avoid lockups.
	83	*/
9ed88554	84	dev_dbg(&d->dev, "Setting max latency to 32\n");
1da177e4 LT	85	pcibios_max_latency = 32;
	86	}
	87	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
	88	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
	89
a18e3690	90	static void pci_fixup_piix4_acpi(struct pci_dev *d)
1da177e4 LT	91	{
	92	/*
	93	* PIIX4 ACPI device: hardwired IRQ9
	94	*/
	95	d->irq = 9;
	96	}
	97	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi);
	98
	99	/*
	100	* Addresses issues with problems in the memory write queue timer in
	101	* certain VIA Northbridges. This bugfix is per VIA's specifications,
	102	* except for the KL133/KM133: clearing bit 5 on those Northbridges seems
	103	* to trigger a bug in its integrated ProSavage video card, which
	104	* causes screen corruption. We only clear bits 6 and 7 for that chipset,
	105	* until VIA can provide us with definitive information on why screen
	106	* corruption occurs, and what exactly those bits do.
	107	*
	108	* VIA 8363,8622,8361 Northbridges:
	109	* - bits 5, 6, 7 at offset 0x55 need to be turned off
	110	* VIA 8367 (KT266x) Northbridges:
	111	* - bits 5, 6, 7 at offset 0x95 need to be turned off
	112	* VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
	113	* - bits 6, 7 at offset 0x55 need to be turned off
	114	*/
	115
	116	#define VIA_8363_KL133_REVISION_ID 0x81
	117	#define VIA_8363_KM133_REVISION_ID 0x84
	118
1597cacb	119	static void pci_fixup_via_northbridge_bug(struct pci_dev *d)
1da177e4 LT	120	{
1da177e4 LT	121	u8 v;
1da177e4 LT	122	int where = 0x55;
	123	int mask = 0x1f; /* clear bits 5, 6, 7 by default */
	124
1da177e4 LT	125	if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
	126	/* fix pci bus latency issues resulted by NB bios error
	127	it appears on bug free^Wreduced kt266x's bios forces
	128	NB latency to zero */
	129	pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
	130
938f6671	131	where = 0x95; /* the memory write queue timer register is
1da177e4 LT	132	different for the KT266x's: 0x95 not 0x55 */
1da177e4 LT	133	} else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
44c10138 AK	134	(d->revision == VIA_8363_KL133_REVISION_ID \|\|
44c10138 AK	135	d->revision == VIA_8363_KM133_REVISION_ID)) {
1da177e4 LT	136	mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
	137	causes screen corruption on the KL133/KM133 */
	138	}
	139
	140	pci_read_config_byte(d, where, &v);
	141	if (v & ~mask) {
9ed88554	142	dev_warn(&d->dev, "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
44c10138	143	d->device, d->revision, where, v, mask, v & mask);
1da177e4 LT	144	v &= mask;
	145	pci_write_config_byte(d, where, v);
	146	}
	147	}
	148	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
	149	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
	150	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
	151	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
1597cacb AC	152	DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
	153	DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
	154	DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
	155	DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
1da177e4 LT	156
	157	/*
	158	* For some reasons Intel decided that certain parts of their
	159	* 815, 845 and some other chipsets must look like PCI-to-PCI bridges
	160	* while they are obviously not. The 82801 family (AA, AB, BAM/CAM,
	161	* BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according
	162	* to Intel terminology. These devices do forward all addresses from
	163	* system to PCI bus no matter what are their window settings, so they are
	164	* "transparent" (or subtractive decoding) from programmers point of view.
	165	*/
a18e3690	166	static void pci_fixup_transparent_bridge(struct pci_dev *dev)
1da177e4	167	{
4082cf2d	168	if ((dev->device & 0xff00) == 0x2400)
1da177e4 LT	169	dev->transparent = 1;
1da177e4 LT	170	}
4082cf2d YL	171	DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
4082cf2d YL	172	PCI_CLASS_BRIDGE_PCI, 8, pci_fixup_transparent_bridge);
1da177e4 LT	173
	174	/*
	175	* Fixup for C1 Halt Disconnect problem on nForce2 systems.
	176	*
	177	* From information provided by "Allen Martin" <AMartin@nvidia.com>:
	178	*
	179	* A hang is caused when the CPU generates a very fast CONNECT/HALT cycle
	180	* sequence. Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns.
	181	* This allows the state-machine and timer to return to a proper state within
	182	* 80 ns of the CONNECT and probe appearing together. Since the CPU will not
	183	* issue another HALT within 80 ns of the initial HALT, the failure condition
	184	* is avoided.
	185	*/
1597cacb	186	static void pci_fixup_nforce2(struct pci_dev *dev)
1da177e4 LT	187	{
	188	u32 val;
	189
	190	/*
	191	* Chip Old value New value
	192	* C17 0x1F0FFF01 0x1F01FF01
	193	* C18D 0x9F0FFF01 0x9F01FF01
	194	*
	195	* Northbridge chip version may be determined by
	196	* reading the PCI revision ID (0xC1 or greater is C18D).
	197	*/
	198	pci_read_config_dword(dev, 0x6c, &val);
	199
	200	/*
	201	* Apply fixup if needed, but don't touch disconnect state
	202	*/
	203	if ((val & 0x00FF0000) != 0x00010000) {
9ed88554	204	dev_warn(&dev->dev, "nForce2 C1 Halt Disconnect fixup\n");
1da177e4 LT	205	pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) \| 0x00010000);
	206	}
	207	}
	208	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
1597cacb	209	DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
1da177e4 LT	210
	211	/* Max PCI Express root ports */
	212	#define MAX_PCIEROOT 6
	213	static int quirk_aspm_offset[MAX_PCIEROOT << 3];
	214
ff0d2f90	215	#define GET_INDEX(a, b) ((((a) - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + ((b) & 7))
1da177e4 LT	216
	217	static int quirk_pcie_aspm_read(struct pci_bus bus, unsigned int devfn, int where, int size, u32 value)
	218	{
b6ce068a MW	219	return raw_pci_read(pci_domain_nr(bus), bus->number,
b6ce068a MW	220	devfn, where, size, value);
1da177e4 LT	221	}
	222
	223	/*
	224	* Replace the original pci bus ops for write with a new one that will filter
	225	* the request to insure ASPM cannot be enabled.
	226	*/
	227	static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
	228	{
	229	u8 offset;
	230
	231	offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)];
	232
	233	if ((offset) && (where == offset))
	234	value = value & 0xfffffffc;
938f6671	235
b6ce068a MW	236	return raw_pci_write(pci_domain_nr(bus), bus->number,
b6ce068a MW	237	devfn, where, size, value);
1da177e4 LT	238	}
	239
	240	static struct pci_ops quirk_pcie_aspm_ops = {
	241	.read = quirk_pcie_aspm_read,
	242	.write = quirk_pcie_aspm_write,
	243	};
	244
	245	/*
	246	* Prevents PCI Express ASPM (Active State Power Management) being enabled.
	247	*
	248	* Save the register offset, where the ASPM control bits are located,
	249	* for each PCI Express device that is in the device list of
	250	* the root port in an array for fast indexing. Replace the bus ops
	251	* with the modified one.
	252	*/
	253	static void pcie_rootport_aspm_quirk(struct pci_dev *pdev)
	254	{
	255	int cap_base, i;
	256	struct pci_bus *pbus;
	257	struct pci_dev *dev;
	258
	259	if ((pbus = pdev->subordinate) == NULL)
	260	return;
	261
	262	/*
	263	* Check if the DID of pdev matches one of the six root ports. This
	264	* check is needed in the case this function is called directly by the
	265	* hot-plug driver.
	266	*/
	267	if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) \|\|
	268	(pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1))
	269	return;
	270
	271	if (list_empty(&pbus->devices)) {
	272	/*
	273	* If no device is attached to the root port at power-up or
	274	* after hot-remove, the pbus->devices is empty and this code
	275	* will set the offsets to zero and the bus ops to parent's bus
	276	* ops, which is unmodified.
938f6671 PC	277	*/
938f6671 PC	278	for (i = GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i)
1da177e4 LT	279	quirk_aspm_offset[i] = 0;
	280
	281	pbus->ops = pbus->parent->ops;
	282	} else {
	283	/*
	284	* If devices are attached to the root port at power-up or
	285	* after hot-add, the code loops through the device list of
	286	* each root port to save the register offsets and replace the
	287	* bus ops.
	288	*/
	289	list_for_each_entry(dev, &pbus->devices, bus_list) {
	290	/* There are 0 to 8 devices attached to this bus */
	291	cap_base = pci_find_capability(dev, PCI_CAP_ID_EXP);
938f6671	292	quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)] = cap_base + 0x10;
1da177e4 LT	293	}
	294	pbus->ops = &quirk_pcie_aspm_ops;
	295	}
	296	}
938f6671 PC	297	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA, pcie_rootport_aspm_quirk);
	298	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA1, pcie_rootport_aspm_quirk);
	299	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB, pcie_rootport_aspm_quirk);
	300	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB1, pcie_rootport_aspm_quirk);
	301	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC, pcie_rootport_aspm_quirk);
	302	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC1, pcie_rootport_aspm_quirk);
1da177e4	303
6b5c76b8 EO	304	/*
	305	* Fixup to mark boot BIOS video selected by BIOS before it changes
	306	*
	307	* From information provided by "Jon Smirl" <jonsmirl@gmail.com>
	308	*
	309	* The standard boot ROM sequence for an x86 machine uses the BIOS
	310	* to select an initial video card for boot display. This boot video
	311	* card will have it's BIOS copied to C0000 in system RAM.
	312	* IORESOURCE_ROM_SHADOW is used to associate the boot video
	313	* card with this copy. On laptops this copy has to be used since
	314	* the main ROM may be compressed or combined with another image.
	315	* See pci_map_rom() for use of this flag. IORESOURCE_ROM_SHADOW
	316	* is marked here since the boot video device will be the only enabled
	317	* video device at this point.
	318	*/
	319
a18e3690	320	static void pci_fixup_video(struct pci_dev *pdev)
6b5c76b8 EO	321	{
	322	struct pci_dev *bridge;
	323	struct pci_bus *bus;
	324	u16 config;
	325
6b5c76b8 EO	326	/* Is VGA routed to us? */
	327	bus = pdev->bus;
	328	while (bus) {
	329	bridge = bus->self;
	330
	331	/*
	332	* From information provided by
	333	* "David Miller" <davem@davemloft.net>
	334	* The bridge control register is valid for PCI header
	335	* type BRIDGE, or CARDBUS. Host to PCI controllers use
	336	* PCI header type NORMAL.
	337	*/
	338	if (bridge
938f6671 PC	339	&& ((bridge->hdr_type == PCI_HEADER_TYPE_BRIDGE)
938f6671 PC	340	\|\| (bridge->hdr_type == PCI_HEADER_TYPE_CARDBUS))) {
6b5c76b8 EO	341	pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
	342	&config);
	343	if (!(config & PCI_BRIDGE_CTL_VGA))
	344	return;
	345	}
	346	bus = bus->parent;
	347	}
	348	pci_read_config_word(pdev, PCI_COMMAND, &config);
	349	if (config & (PCI_COMMAND_IO \| PCI_COMMAND_MEMORY)) {
	350	pdev->resource[PCI_ROM_RESOURCE].flags \|= IORESOURCE_ROM_SHADOW;
9ed88554	351	dev_printk(KERN_DEBUG, &pdev->dev, "Boot video device\n");
6cf20bee DA	352	if (!vga_default_device())
6cf20bee DA	353	vga_set_default_device(pdev);
6b5c76b8 EO	354	}
6b5c76b8 EO	355	}
73e3b590 YL	356	DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
73e3b590 YL	357	PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_video);
6b5c76b8	358
346ca04d	359
a18e3690	360	static const struct dmi_system_id msi_k8t_dmi_table[] = {
346ca04d JG	361	{
	362	.ident = "MSI-K8T-Neo2Fir",
	363	.matches = {
	364	DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
	365	DMI_MATCH(DMI_PRODUCT_NAME, "MS-6702E"),
	366	},
	367	},
	368	{}
	369	};
	370
	371	/*
	372	* The AMD-Athlon64 board MSI "K8T Neo2-FIR" disables the onboard sound
	373	* card if a PCI-soundcard is added.
	374	*
	375	* The BIOS only gives options "DISABLED" and "AUTO". This code sets
	376	* the corresponding register-value to enable the soundcard.
	377	*
	378	* The soundcard is only enabled, if the mainborad is identified
	379	* via DMI-tables and the soundcard is detected to be off.
	380	*/
a18e3690	381	static void pci_fixup_msi_k8t_onboard_sound(struct pci_dev *dev)
346ca04d JG	382	{
	383	unsigned char val;
	384	if (!dmi_check_system(msi_k8t_dmi_table))
	385	return; /* only applies to MSI K8T Neo2-FIR */
	386
	387	pci_read_config_byte(dev, 0x50, &val);
	388	if (val & 0x40) {
	389	pci_write_config_byte(dev, 0x50, val & (~0x40));
	390
	391	/* verify the change for status output */
	392	pci_read_config_byte(dev, 0x50, &val);
	393	if (val & 0x40)
9ed88554	394	dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
346ca04d JG	395	"can't enable onboard soundcard!\n");
346ca04d JG	396	else
9ed88554	397	dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
9ed88554	398	"enabled onboard soundcard\n");
346ca04d JG	399	}
	400	}
	401	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
	402	pci_fixup_msi_k8t_onboard_sound);
	403	DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
	404	pci_fixup_msi_k8t_onboard_sound);
	405
f8977d0a JB	406	/*
	407	* Some Toshiba laptops need extra code to enable their TI TSB43AB22/A.
	408	*
	409	* We pretend to bring them out of full D3 state, and restore the proper
	410	* IRQ, PCI cache line size, and BARs, otherwise the device won't function
	411	* properly. In some cases, the device will generate an interrupt on
4b3f686d	412	* the wrong IRQ line, causing any devices sharing the line it's
f8977d0a JB	413	* supposed to use to be disabled by the kernel's IRQ debug code.
	414	*/
	415	static u16 toshiba_line_size;
	416
a18e3690	417	static const struct dmi_system_id toshiba_ohci1394_dmi_table[] = {
f8977d0a JB	418	{
	419	.ident = "Toshiba PS5 based laptop",
	420	.matches = {
	421	DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
	422	DMI_MATCH(DMI_PRODUCT_VERSION, "PS5"),
	423	},
	424	},
	425	{
	426	.ident = "Toshiba PSM4 based laptop",
	427	.matches = {
	428	DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
	429	DMI_MATCH(DMI_PRODUCT_VERSION, "PSM4"),
	430	},
	431	},
19272684 JB	432	{
	433	.ident = "Toshiba A40 based laptop",
	434	.matches = {
	435	DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
	436	DMI_MATCH(DMI_PRODUCT_VERSION, "PSA40U"),
	437	},
	438	},
f8977d0a JB	439	{ }
	440	};
	441
a18e3690	442	static void pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev)
f8977d0a JB	443	{
	444	if (!dmi_check_system(toshiba_ohci1394_dmi_table))
	445	return; /* only applies to certain Toshibas (so far) */
	446
	447	dev->current_state = PCI_D3cold;
	448	pci_read_config_word(dev, PCI_CACHE_LINE_SIZE, &toshiba_line_size);
	449	}
	450	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032,
	451	pci_pre_fixup_toshiba_ohci1394);
	452
a18e3690	453	static void pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev)
f8977d0a JB	454	{
	455	if (!dmi_check_system(toshiba_ohci1394_dmi_table))
	456	return; /* only applies to certain Toshibas (so far) */
	457
	458	/* Restore config space on Toshiba laptops */
f8977d0a	459	pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size);
6e6ece5d	460	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, (u8 *)&dev->irq);
f8977d0a JB	461	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
	462	pci_resource_start(dev, 0));
	463	pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
	464	pci_resource_start(dev, 1));
	465	}
	466	DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032,
	467	pci_post_fixup_toshiba_ohci1394);
a80da738 DV	468
	469
	470	/*
	471	* Prevent the BIOS trapping accesses to the Cyrix CS5530A video device
	472	* configuration space.
	473	*/
1597cacb	474	static void pci_early_fixup_cyrix_5530(struct pci_dev *dev)
a80da738 DV	475	{
	476	u8 r;
	477	/* clear 'F4 Video Configuration Trap' bit */
	478	pci_read_config_byte(dev, 0x42, &r);
	479	r &= 0xfd;
	480	pci_write_config_byte(dev, 0x42, r);
	481	}
	482	DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
	483	pci_early_fixup_cyrix_5530);
1597cacb AC	484	DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
1597cacb AC	485	pci_early_fixup_cyrix_5530);
73a74ed3 IK	486
	487	/*
	488	* Siemens Nixdorf AG FSC Multiprocessor Interrupt Controller:
	489	* prevent update of the BAR0, which doesn't look like a normal BAR.
	490	*/
a18e3690	491	static void pci_siemens_interrupt_controller(struct pci_dev *dev)
73a74ed3 IK	492	{
	493	dev->resource[0].flags \|= IORESOURCE_PCI_FIXED;
	494	}
	495	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015,
	496	pci_siemens_interrupt_controller);
57741a77	497
d7451fca JC	498	/*
	499	* SB600: Disable BAR1 on device 14.0 to avoid HPET resources from
	500	* confusing the PCI engine:
	501	*/
	502	static void sb600_disable_hpet_bar(struct pci_dev *dev)
	503	{
	504	u8 val;
	505
	506	/*
	507	* The SB600 and SB700 both share the same device
	508	* ID, but the PM register 0x55 does something different
	509	* for the SB700, so make sure we are dealing with the
	510	* SB600 before touching the bit:
	511	*/
	512
	513	pci_read_config_byte(dev, 0x08, &val);
	514
	515	if (val < 0x2F) {
	516	outb(0x55, 0xCD6);
	517	val = inb(0xCD7);
	518
	519	/* Set bit 7 in PM register 0x55 */
	520	outb(0x55, 0xCD6);
	521	outb(val \| 0x80, 0xCD7);
	522	}
	523	}
	524	DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4385, sb600_disable_hpet_bar);
80b3e557 AC	525
	526	/*
	527	* Twinhead H12Y needs us to block out a region otherwise we map devices
	528	* there and any access kills the box.
	529	*
	530	* See: https://bugzilla.kernel.org/show_bug.cgi?id=10231
	531	*
	532	* Match off the LPC and svid/sdid (older kernels lose the bridge subvendor)
	533	*/
a18e3690	534	static void twinhead_reserve_killing_zone(struct pci_dev *dev)
80b3e557 AC	535	{
	536	if (dev->subsystem_vendor == 0x14FF && dev->subsystem_device == 0xA003) {
	537	pr_info("Reserving memory on Twinhead H12Y\n");
	538	request_mem_region(0xFFB00000, 0x100000, "twinhead");
	539	}
	540	}
	541	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x27B9, twinhead_reserve_killing_zone);