lguest: optimize by coding restore_flags and irq_enable in assembler.
[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / arch / x86 / lguest / boot.c
CommitLineData
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1/*P:010
2 * A hypervisor allows multiple Operating Systems to run on a single machine.
3 * To quote David Wheeler: "Any problem in computer science can be solved with
4 * another layer of indirection."
5 *
6 * We keep things simple in two ways. First, we start with a normal Linux
7 * kernel and insert a module (lg.ko) which allows us to run other Linux
8 * kernels the same way we'd run processes. We call the first kernel the Host,
9 * and the others the Guests. The program which sets up and configures Guests
10 * (such as the example in Documentation/lguest/lguest.c) is called the
11 * Launcher.
12 *
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13 * Secondly, we only run specially modified Guests, not normal kernels: setting
14 * CONFIG_LGUEST_GUEST to "y" compiles this file into the kernel so it knows
15 * how to be a Guest at boot time. This means that you can use the same kernel
16 * you boot normally (ie. as a Host) as a Guest.
07ad157f 17 *
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18 * These Guests know that they cannot do privileged operations, such as disable
19 * interrupts, and that they have to ask the Host to do such things explicitly.
20 * This file consists of all the replacements for such low-level native
21 * hardware operations: these special Guest versions call the Host.
22 *
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23 * So how does the kernel know it's a Guest? We'll see that later, but let's
24 * just say that we end up here where we replace the native functions various
25 * "paravirt" structures with our Guest versions, then boot like normal. :*/
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26
27/*
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28 * Copyright (C) 2006, Rusty Russell <rusty@rustcorp.com.au> IBM Corporation.
29 *
30 * This program is free software; you can redistribute it and/or modify
31 * it under the terms of the GNU General Public License as published by
32 * the Free Software Foundation; either version 2 of the License, or
33 * (at your option) any later version.
34 *
35 * This program is distributed in the hope that it will be useful, but
36 * WITHOUT ANY WARRANTY; without even the implied warranty of
37 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
38 * NON INFRINGEMENT. See the GNU General Public License for more
39 * details.
40 *
41 * You should have received a copy of the GNU General Public License
42 * along with this program; if not, write to the Free Software
43 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
44 */
45#include <linux/kernel.h>
46#include <linux/start_kernel.h>
47#include <linux/string.h>
48#include <linux/console.h>
49#include <linux/screen_info.h>
50#include <linux/irq.h>
51#include <linux/interrupt.h>
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52#include <linux/clocksource.h>
53#include <linux/clockchips.h>
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54#include <linux/lguest.h>
55#include <linux/lguest_launcher.h>
19f1537b 56#include <linux/virtio_console.h>
4cfe6c3c 57#include <linux/pm.h>
7b6aa335 58#include <asm/apic.h>
cbc34973 59#include <asm/lguest.h>
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60#include <asm/paravirt.h>
61#include <asm/param.h>
62#include <asm/page.h>
63#include <asm/pgtable.h>
64#include <asm/desc.h>
65#include <asm/setup.h>
66#include <asm/e820.h>
67#include <asm/mce.h>
68#include <asm/io.h>
625efab1 69#include <asm/i387.h>
2cb7878a 70#include <asm/stackprotector.h>
ec04b13f 71#include <asm/reboot.h> /* for struct machine_ops */
07ad157f 72
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73/*G:010 Welcome to the Guest!
74 *
75 * The Guest in our tale is a simple creature: identical to the Host but
76 * behaving in simplified but equivalent ways. In particular, the Guest is the
77 * same kernel as the Host (or at least, built from the same source code). :*/
78
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79struct lguest_data lguest_data = {
80 .hcall_status = { [0 ... LHCALL_RING_SIZE-1] = 0xFF },
81 .noirq_start = (u32)lguest_noirq_start,
82 .noirq_end = (u32)lguest_noirq_end,
47436aa4 83 .kernel_address = PAGE_OFFSET,
07ad157f 84 .blocked_interrupts = { 1 }, /* Block timer interrupts */
c18acd73 85 .syscall_vec = SYSCALL_VECTOR,
07ad157f 86};
07ad157f 87
633872b9 88/*G:037 async_hcall() is pretty simple: I'm quite proud of it really. We have a
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89 * ring buffer of stored hypercalls which the Host will run though next time we
90 * do a normal hypercall. Each entry in the ring has 4 slots for the hypercall
91 * arguments, and a "hcall_status" word which is 0 if the call is ready to go,
92 * and 255 once the Host has finished with it.
93 *
94 * If we come around to a slot which hasn't been finished, then the table is
95 * full and we just make the hypercall directly. This has the nice side
96 * effect of causing the Host to run all the stored calls in the ring buffer
97 * which empties it for next time! */
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98static void async_hcall(unsigned long call, unsigned long arg1,
99 unsigned long arg2, unsigned long arg3)
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100{
101 /* Note: This code assumes we're uniprocessor. */
102 static unsigned int next_call;
103 unsigned long flags;
104
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105 /* Disable interrupts if not already disabled: we don't want an
106 * interrupt handler making a hypercall while we're already doing
107 * one! */
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108 local_irq_save(flags);
109 if (lguest_data.hcall_status[next_call] != 0xFF) {
110 /* Table full, so do normal hcall which will flush table. */
4cd8b5e2 111 kvm_hypercall3(call, arg1, arg2, arg3);
07ad157f 112 } else {
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113 lguest_data.hcalls[next_call].arg0 = call;
114 lguest_data.hcalls[next_call].arg1 = arg1;
115 lguest_data.hcalls[next_call].arg2 = arg2;
116 lguest_data.hcalls[next_call].arg3 = arg3;
b2b47c21 117 /* Arguments must all be written before we mark it to go */
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118 wmb();
119 lguest_data.hcall_status[next_call] = 0;
120 if (++next_call == LHCALL_RING_SIZE)
121 next_call = 0;
122 }
123 local_irq_restore(flags);
124}
9b56fdb4 125
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126/*G:035 Notice the lazy_hcall() above, rather than hcall(). This is our first
127 * real optimization trick!
128 *
129 * When lazy_mode is set, it means we're allowed to defer all hypercalls and do
130 * them as a batch when lazy_mode is eventually turned off. Because hypercalls
131 * are reasonably expensive, batching them up makes sense. For example, a
132 * large munmap might update dozens of page table entries: that code calls
133 * paravirt_enter_lazy_mmu(), does the dozen updates, then calls
134 * lguest_leave_lazy_mode().
135 *
136 * So, when we're in lazy mode, we call async_hcall() to store the call for
a6bd8e13 137 * future processing: */
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138static void lazy_hcall1(unsigned long call,
139 unsigned long arg1)
140{
141 if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_NONE)
142 kvm_hypercall1(call, arg1);
143 else
144 async_hcall(call, arg1, 0, 0);
145}
146
147static void lazy_hcall2(unsigned long call,
148 unsigned long arg1,
149 unsigned long arg2)
150{
151 if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_NONE)
152 kvm_hypercall2(call, arg1, arg2);
153 else
154 async_hcall(call, arg1, arg2, 0);
155}
156
157static void lazy_hcall3(unsigned long call,
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158 unsigned long arg1,
159 unsigned long arg2,
160 unsigned long arg3)
161{
162 if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_NONE)
4cd8b5e2 163 kvm_hypercall3(call, arg1, arg2, arg3);
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164 else
165 async_hcall(call, arg1, arg2, arg3);
166}
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167
168/* When lazy mode is turned off reset the per-cpu lazy mode variable and then
a6bd8e13 169 * issue the do-nothing hypercall to flush any stored calls. */
b407fc57 170static void lguest_leave_lazy_mmu_mode(void)
633872b9 171{
4cd8b5e2 172 kvm_hypercall0(LHCALL_FLUSH_ASYNC);
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173 paravirt_leave_lazy_mmu();
174}
175
224101ed 176static void lguest_end_context_switch(struct task_struct *next)
b407fc57 177{
4cd8b5e2 178 kvm_hypercall0(LHCALL_FLUSH_ASYNC);
224101ed 179 paravirt_end_context_switch(next);
633872b9 180}
07ad157f 181
61f4bc83 182/*G:032
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183 * After that diversion we return to our first native-instruction
184 * replacements: four functions for interrupt control.
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185 *
186 * The simplest way of implementing these would be to have "turn interrupts
187 * off" and "turn interrupts on" hypercalls. Unfortunately, this is too slow:
188 * these are by far the most commonly called functions of those we override.
189 *
190 * So instead we keep an "irq_enabled" field inside our "struct lguest_data",
191 * which the Guest can update with a single instruction. The Host knows to
a6bd8e13 192 * check there before it tries to deliver an interrupt.
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193 */
194
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195/* save_flags() is expected to return the processor state (ie. "flags"). The
196 * flags word contains all kind of stuff, but in practice Linux only cares
b2b47c21 197 * about the interrupt flag. Our "save_flags()" just returns that. */
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198static unsigned long save_fl(void)
199{
200 return lguest_data.irq_enabled;
201}
07ad157f 202
b2b47c21 203/* Interrupts go off... */
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204static void irq_disable(void)
205{
206 lguest_data.irq_enabled = 0;
207}
208
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209/* Let's pause a moment. Remember how I said these are called so often?
210 * Jeremy Fitzhardinge optimized them so hard early in 2009 that he had to
211 * break some rules. In particular, these functions are assumed to save their
212 * own registers if they need to: normal C functions assume they can trash the
213 * eax register. To use normal C functions, we use
214 * PV_CALLEE_SAVE_REGS_THUNK(), which pushes %eax onto the stack, calls the
215 * C function, then restores it. */
216PV_CALLEE_SAVE_REGS_THUNK(save_fl);
217PV_CALLEE_SAVE_REGS_THUNK(irq_disable);
218/*:*/
a32a8813 219
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220/* These are in i386_head.S */
221extern void lg_irq_enable(void);
222extern void lg_restore_fl(unsigned long flags);
ecb93d1c 223
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224/*M:003 Note that we don't check for outstanding interrupts when we re-enable
225 * them (or when we unmask an interrupt). This seems to work for the moment,
226 * since interrupts are rare and we'll just get the interrupt on the next timer
a6bd8e13 227 * tick, but now we can run with CONFIG_NO_HZ, we should revisit this. One way
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228 * would be to put the "irq_enabled" field in a page by itself, and have the
229 * Host write-protect it when an interrupt comes in when irqs are disabled.
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230 * There will then be a page fault as soon as interrupts are re-enabled.
231 *
232 * A better method is to implement soft interrupt disable generally for x86:
233 * instead of disabling interrupts, we set a flag. If an interrupt does come
234 * in, we then disable them for real. This is uncommon, so we could simply use
235 * a hypercall for interrupt control and not worry about efficiency. :*/
07ad157f 236
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237/*G:034
238 * The Interrupt Descriptor Table (IDT).
239 *
240 * The IDT tells the processor what to do when an interrupt comes in. Each
241 * entry in the table is a 64-bit descriptor: this holds the privilege level,
242 * address of the handler, and... well, who cares? The Guest just asks the
243 * Host to make the change anyway, because the Host controls the real IDT.
244 */
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245static void lguest_write_idt_entry(gate_desc *dt,
246 int entrynum, const gate_desc *g)
07ad157f 247{
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248 /* The gate_desc structure is 8 bytes long: we hand it to the Host in
249 * two 32-bit chunks. The whole 32-bit kernel used to hand descriptors
250 * around like this; typesafety wasn't a big concern in Linux's early
251 * years. */
8d947344 252 u32 *desc = (u32 *)g;
b2b47c21 253 /* Keep the local copy up to date. */
8d947344 254 native_write_idt_entry(dt, entrynum, g);
b2b47c21 255 /* Tell Host about this new entry. */
4cd8b5e2 256 kvm_hypercall3(LHCALL_LOAD_IDT_ENTRY, entrynum, desc[0], desc[1]);
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257}
258
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259/* Changing to a different IDT is very rare: we keep the IDT up-to-date every
260 * time it is written, so we can simply loop through all entries and tell the
261 * Host about them. */
6b68f01b 262static void lguest_load_idt(const struct desc_ptr *desc)
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263{
264 unsigned int i;
265 struct desc_struct *idt = (void *)desc->address;
266
267 for (i = 0; i < (desc->size+1)/8; i++)
4cd8b5e2 268 kvm_hypercall3(LHCALL_LOAD_IDT_ENTRY, i, idt[i].a, idt[i].b);
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269}
270
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271/*
272 * The Global Descriptor Table.
273 *
274 * The Intel architecture defines another table, called the Global Descriptor
275 * Table (GDT). You tell the CPU where it is (and its size) using the "lgdt"
276 * instruction, and then several other instructions refer to entries in the
277 * table. There are three entries which the Switcher needs, so the Host simply
278 * controls the entire thing and the Guest asks it to make changes using the
279 * LOAD_GDT hypercall.
280 *
a489f0b5 281 * This is the exactly like the IDT code.
b2b47c21 282 */
6b68f01b 283static void lguest_load_gdt(const struct desc_ptr *desc)
07ad157f 284{
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285 unsigned int i;
286 struct desc_struct *gdt = (void *)desc->address;
287
288 for (i = 0; i < (desc->size+1)/8; i++)
289 kvm_hypercall3(LHCALL_LOAD_GDT_ENTRY, i, gdt[i].a, gdt[i].b);
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290}
291
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292/* For a single GDT entry which changes, we do the lazy thing: alter our GDT,
293 * then tell the Host to reload the entire thing. This operation is so rare
294 * that this naive implementation is reasonable. */
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295static void lguest_write_gdt_entry(struct desc_struct *dt, int entrynum,
296 const void *desc, int type)
07ad157f 297{
014b15be 298 native_write_gdt_entry(dt, entrynum, desc, type);
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299 /* Tell Host about this new entry. */
300 kvm_hypercall3(LHCALL_LOAD_GDT_ENTRY, entrynum,
301 dt[entrynum].a, dt[entrynum].b);
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302}
303
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304/* OK, I lied. There are three "thread local storage" GDT entries which change
305 * on every context switch (these three entries are how glibc implements
306 * __thread variables). So we have a hypercall specifically for this case. */
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307static void lguest_load_tls(struct thread_struct *t, unsigned int cpu)
308{
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309 /* There's one problem which normal hardware doesn't have: the Host
310 * can't handle us removing entries we're currently using. So we clear
311 * the GS register here: if it's needed it'll be reloaded anyway. */
ccbeed3a 312 lazy_load_gs(0);
4cd8b5e2 313 lazy_hcall2(LHCALL_LOAD_TLS, __pa(&t->tls_array), cpu);
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314}
315
b2b47c21 316/*G:038 That's enough excitement for now, back to ploughing through each of
93b1eab3 317 * the different pv_ops structures (we're about 1/3 of the way through).
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318 *
319 * This is the Local Descriptor Table, another weird Intel thingy. Linux only
320 * uses this for some strange applications like Wine. We don't do anything
321 * here, so they'll get an informative and friendly Segmentation Fault. */
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322static void lguest_set_ldt(const void *addr, unsigned entries)
323{
324}
325
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326/* This loads a GDT entry into the "Task Register": that entry points to a
327 * structure called the Task State Segment. Some comments scattered though the
328 * kernel code indicate that this used for task switching in ages past, along
329 * with blood sacrifice and astrology.
330 *
331 * Now there's nothing interesting in here that we don't get told elsewhere.
332 * But the native version uses the "ltr" instruction, which makes the Host
333 * complain to the Guest about a Segmentation Fault and it'll oops. So we
334 * override the native version with a do-nothing version. */
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335static void lguest_load_tr_desc(void)
336{
337}
338
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339/* The "cpuid" instruction is a way of querying both the CPU identity
340 * (manufacturer, model, etc) and its features. It was introduced before the
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341 * Pentium in 1993 and keeps getting extended by both Intel, AMD and others.
342 * As you might imagine, after a decade and a half this treatment, it is now a
343 * giant ball of hair. Its entry in the current Intel manual runs to 28 pages.
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344 *
345 * This instruction even it has its own Wikipedia entry. The Wikipedia entry
346 * has been translated into 4 languages. I am not making this up!
347 *
348 * We could get funky here and identify ourselves as "GenuineLguest", but
349 * instead we just use the real "cpuid" instruction. Then I pretty much turned
350 * off feature bits until the Guest booted. (Don't say that: you'll damage
351 * lguest sales!) Shut up, inner voice! (Hey, just pointing out that this is
352 * hardly future proof.) Noone's listening! They don't like you anyway,
353 * parenthetic weirdo!
354 *
355 * Replacing the cpuid so we can turn features off is great for the kernel, but
356 * anyone (including userspace) can just use the raw "cpuid" instruction and
357 * the Host won't even notice since it isn't privileged. So we try not to get
358 * too worked up about it. */
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359static void lguest_cpuid(unsigned int *ax, unsigned int *bx,
360 unsigned int *cx, unsigned int *dx)
07ad157f 361{
65ea5b03 362 int function = *ax;
07ad157f 363
65ea5b03 364 native_cpuid(ax, bx, cx, dx);
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365 switch (function) {
366 case 1: /* Basic feature request. */
367 /* We only allow kernel to see SSE3, CMPXCHG16B and SSSE3 */
65ea5b03 368 *cx &= 0x00002201;
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369 /* SSE, SSE2, FXSR, MMX, CMOV, CMPXCHG8B, TSC, FPU. */
370 *dx &= 0x07808111;
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371 /* The Host can do a nice optimization if it knows that the
372 * kernel mappings (addresses above 0xC0000000 or whatever
373 * PAGE_OFFSET is set to) haven't changed. But Linux calls
374 * flush_tlb_user() for both user and kernel mappings unless
375 * the Page Global Enable (PGE) feature bit is set. */
65ea5b03 376 *dx |= 0x00002000;
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377 /* We also lie, and say we're family id 5. 6 or greater
378 * leads to a rdmsr in early_init_intel which we can't handle.
379 * Family ID is returned as bits 8-12 in ax. */
380 *ax &= 0xFFFFF0FF;
381 *ax |= 0x00000500;
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382 break;
383 case 0x80000000:
384 /* Futureproof this a little: if they ask how much extended
b2b47c21 385 * processor information there is, limit it to known fields. */
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386 if (*ax > 0x80000008)
387 *ax = 0x80000008;
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388 break;
389 }
390}
391
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392/* Intel has four control registers, imaginatively named cr0, cr2, cr3 and cr4.
393 * I assume there's a cr1, but it hasn't bothered us yet, so we'll not bother
394 * it. The Host needs to know when the Guest wants to change them, so we have
395 * a whole series of functions like read_cr0() and write_cr0().
396 *
e1e72965 397 * We start with cr0. cr0 allows you to turn on and off all kinds of basic
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398 * features, but Linux only really cares about one: the horrifically-named Task
399 * Switched (TS) bit at bit 3 (ie. 8)
400 *
401 * What does the TS bit do? Well, it causes the CPU to trap (interrupt 7) if
402 * the floating point unit is used. Which allows us to restore FPU state
403 * lazily after a task switch, and Linux uses that gratefully, but wouldn't a
404 * name like "FPUTRAP bit" be a little less cryptic?
405 *
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406 * We store cr0 locally because the Host never changes it. The Guest sometimes
407 * wants to read it and we'd prefer not to bother the Host unnecessarily. */
408static unsigned long current_cr0;
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409static void lguest_write_cr0(unsigned long val)
410{
4cd8b5e2 411 lazy_hcall1(LHCALL_TS, val & X86_CR0_TS);
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412 current_cr0 = val;
413}
414
415static unsigned long lguest_read_cr0(void)
416{
417 return current_cr0;
418}
419
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420/* Intel provided a special instruction to clear the TS bit for people too cool
421 * to use write_cr0() to do it. This "clts" instruction is faster, because all
422 * the vowels have been optimized out. */
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423static void lguest_clts(void)
424{
4cd8b5e2 425 lazy_hcall1(LHCALL_TS, 0);
25c47bb3 426 current_cr0 &= ~X86_CR0_TS;
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427}
428
e1e72965 429/* cr2 is the virtual address of the last page fault, which the Guest only ever
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430 * reads. The Host kindly writes this into our "struct lguest_data", so we
431 * just read it out of there. */
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432static unsigned long lguest_read_cr2(void)
433{
434 return lguest_data.cr2;
435}
436
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437/* See lguest_set_pte() below. */
438static bool cr3_changed = false;
439
e1e72965 440/* cr3 is the current toplevel pagetable page: the principle is the same as
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441 * cr0. Keep a local copy, and tell the Host when it changes. The only
442 * difference is that our local copy is in lguest_data because the Host needs
443 * to set it upon our initial hypercall. */
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444static void lguest_write_cr3(unsigned long cr3)
445{
ad5173ff 446 lguest_data.pgdir = cr3;
4cd8b5e2 447 lazy_hcall1(LHCALL_NEW_PGTABLE, cr3);
ad5173ff 448 cr3_changed = true;
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449}
450
451static unsigned long lguest_read_cr3(void)
452{
ad5173ff 453 return lguest_data.pgdir;
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454}
455
e1e72965 456/* cr4 is used to enable and disable PGE, but we don't care. */
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457static unsigned long lguest_read_cr4(void)
458{
459 return 0;
460}
461
462static void lguest_write_cr4(unsigned long val)
463{
464}
465
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466/*
467 * Page Table Handling.
468 *
469 * Now would be a good time to take a rest and grab a coffee or similarly
470 * relaxing stimulant. The easy parts are behind us, and the trek gradually
471 * winds uphill from here.
472 *
473 * Quick refresher: memory is divided into "pages" of 4096 bytes each. The CPU
474 * maps virtual addresses to physical addresses using "page tables". We could
475 * use one huge index of 1 million entries: each address is 4 bytes, so that's
476 * 1024 pages just to hold the page tables. But since most virtual addresses
e1e72965 477 * are unused, we use a two level index which saves space. The cr3 register
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478 * contains the physical address of the top level "page directory" page, which
479 * contains physical addresses of up to 1024 second-level pages. Each of these
480 * second level pages contains up to 1024 physical addresses of actual pages,
481 * or Page Table Entries (PTEs).
482 *
483 * Here's a diagram, where arrows indicate physical addresses:
484 *
e1e72965 485 * cr3 ---> +---------+
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486 * | --------->+---------+
487 * | | | PADDR1 |
488 * Top-level | | PADDR2 |
489 * (PMD) page | | |
490 * | | Lower-level |
491 * | | (PTE) page |
492 * | | | |
493 * .... ....
494 *
495 * So to convert a virtual address to a physical address, we look up the top
496 * level, which points us to the second level, which gives us the physical
497 * address of that page. If the top level entry was not present, or the second
498 * level entry was not present, then the virtual address is invalid (we
499 * say "the page was not mapped").
500 *
501 * Put another way, a 32-bit virtual address is divided up like so:
502 *
503 * 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
504 * |<---- 10 bits ---->|<---- 10 bits ---->|<------ 12 bits ------>|
505 * Index into top Index into second Offset within page
506 * page directory page pagetable page
507 *
508 * The kernel spends a lot of time changing both the top-level page directory
509 * and lower-level pagetable pages. The Guest doesn't know physical addresses,
510 * so while it maintains these page tables exactly like normal, it also needs
511 * to keep the Host informed whenever it makes a change: the Host will create
512 * the real page tables based on the Guests'.
513 */
514
515/* The Guest calls this to set a second-level entry (pte), ie. to map a page
516 * into a process' address space. We set the entry then tell the Host the
517 * toplevel and address this corresponds to. The Guest uses one pagetable per
518 * process, so we need to tell the Host which one we're changing (mm->pgd). */
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519static void lguest_pte_update(struct mm_struct *mm, unsigned long addr,
520 pte_t *ptep)
521{
4cd8b5e2 522 lazy_hcall3(LHCALL_SET_PTE, __pa(mm->pgd), addr, ptep->pte_low);
b7ff99ea
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523}
524
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525static void lguest_set_pte_at(struct mm_struct *mm, unsigned long addr,
526 pte_t *ptep, pte_t pteval)
527{
528 *ptep = pteval;
b7ff99ea 529 lguest_pte_update(mm, addr, ptep);
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530}
531
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532/* The Guest calls this to set a top-level entry. Again, we set the entry then
533 * tell the Host which top-level page we changed, and the index of the entry we
534 * changed. */
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535static void lguest_set_pmd(pmd_t *pmdp, pmd_t pmdval)
536{
537 *pmdp = pmdval;
4cd8b5e2
MZ
538 lazy_hcall2(LHCALL_SET_PMD, __pa(pmdp) & PAGE_MASK,
539 (__pa(pmdp) & (PAGE_SIZE - 1)) / 4);
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540}
541
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542/* There are a couple of legacy places where the kernel sets a PTE, but we
543 * don't know the top level any more. This is useless for us, since we don't
544 * know which pagetable is changing or what address, so we just tell the Host
545 * to forget all of them. Fortunately, this is very rare.
546 *
547 * ... except in early boot when the kernel sets up the initial pagetables,
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548 * which makes booting astonishingly slow: 1.83 seconds! So we don't even tell
549 * the Host anything changed until we've done the first page table switch,
550 * which brings boot back to 0.25 seconds. */
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551static void lguest_set_pte(pte_t *ptep, pte_t pteval)
552{
553 *ptep = pteval;
ad5173ff 554 if (cr3_changed)
4cd8b5e2 555 lazy_hcall1(LHCALL_FLUSH_TLB, 1);
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556}
557
93b1eab3 558/* Unfortunately for Lguest, the pv_mmu_ops for page tables were based on
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559 * native page table operations. On native hardware you can set a new page
560 * table entry whenever you want, but if you want to remove one you have to do
561 * a TLB flush (a TLB is a little cache of page table entries kept by the CPU).
562 *
563 * So the lguest_set_pte_at() and lguest_set_pmd() functions above are only
564 * called when a valid entry is written, not when it's removed (ie. marked not
565 * present). Instead, this is where we come when the Guest wants to remove a
566 * page table entry: we tell the Host to set that entry to 0 (ie. the present
567 * bit is zero). */
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568static void lguest_flush_tlb_single(unsigned long addr)
569{
b2b47c21 570 /* Simply set it to zero: if it was not, it will fault back in. */
4cd8b5e2 571 lazy_hcall3(LHCALL_SET_PTE, lguest_data.pgdir, addr, 0);
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572}
573
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574/* This is what happens after the Guest has removed a large number of entries.
575 * This tells the Host that any of the page table entries for userspace might
576 * have changed, ie. virtual addresses below PAGE_OFFSET. */
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577static void lguest_flush_tlb_user(void)
578{
4cd8b5e2 579 lazy_hcall1(LHCALL_FLUSH_TLB, 0);
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580}
581
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582/* This is called when the kernel page tables have changed. That's not very
583 * common (unless the Guest is using highmem, which makes the Guest extremely
584 * slow), so it's worth separating this from the user flushing above. */
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585static void lguest_flush_tlb_kernel(void)
586{
4cd8b5e2 587 lazy_hcall1(LHCALL_FLUSH_TLB, 1);
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588}
589
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590/*
591 * The Unadvanced Programmable Interrupt Controller.
592 *
593 * This is an attempt to implement the simplest possible interrupt controller.
594 * I spent some time looking though routines like set_irq_chip_and_handler,
595 * set_irq_chip_and_handler_name, set_irq_chip_data and set_phasers_to_stun and
596 * I *think* this is as simple as it gets.
597 *
598 * We can tell the Host what interrupts we want blocked ready for using the
599 * lguest_data.interrupts bitmap, so disabling (aka "masking") them is as
600 * simple as setting a bit. We don't actually "ack" interrupts as such, we
601 * just mask and unmask them. I wonder if we should be cleverer?
602 */
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603static void disable_lguest_irq(unsigned int irq)
604{
605 set_bit(irq, lguest_data.blocked_interrupts);
606}
607
608static void enable_lguest_irq(unsigned int irq)
609{
610 clear_bit(irq, lguest_data.blocked_interrupts);
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611}
612
b2b47c21 613/* This structure describes the lguest IRQ controller. */
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614static struct irq_chip lguest_irq_controller = {
615 .name = "lguest",
616 .mask = disable_lguest_irq,
617 .mask_ack = disable_lguest_irq,
618 .unmask = enable_lguest_irq,
619};
620
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621/* This sets up the Interrupt Descriptor Table (IDT) entry for each hardware
622 * interrupt (except 128, which is used for system calls), and then tells the
623 * Linux infrastructure that each interrupt is controlled by our level-based
624 * lguest interrupt controller. */
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625static void __init lguest_init_IRQ(void)
626{
627 unsigned int i;
628
1028375e 629 for (i = FIRST_EXTERNAL_VECTOR; i < NR_VECTORS; i++) {
526e5ab2
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630 /* Some systems map "vectors" to interrupts weirdly. Lguest has
631 * a straightforward 1 to 1 mapping, so force that here. */
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632 __get_cpu_var(vector_irq)[i] = i - FIRST_EXTERNAL_VECTOR;
633 if (i != SYSCALL_VECTOR)
634 set_intr_gate(i, interrupt[i - FIRST_EXTERNAL_VECTOR]);
07ad157f 635 }
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636 /* This call is required to set up for 4k stacks, where we have
637 * separate stacks for hard and soft interrupts. */
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638 irq_ctx_init(smp_processor_id());
639}
640
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641void lguest_setup_irq(unsigned int irq)
642{
85ac16d0 643 irq_to_desc_alloc_node(irq, 0);
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644 set_irq_chip_and_handler_name(irq, &lguest_irq_controller,
645 handle_level_irq, "level");
646}
647
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648/*
649 * Time.
650 *
651 * It would be far better for everyone if the Guest had its own clock, but
6c8dca5d 652 * until then the Host gives us the time on every interrupt.
b2b47c21 653 */
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654static unsigned long lguest_get_wallclock(void)
655{
6c8dca5d 656 return lguest_data.time.tv_sec;
07ad157f
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657}
658
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659/* The TSC is an Intel thing called the Time Stamp Counter. The Host tells us
660 * what speed it runs at, or 0 if it's unusable as a reliable clock source.
661 * This matches what we want here: if we return 0 from this function, the x86
662 * TSC clock will give up and not register itself. */
e93ef949 663static unsigned long lguest_tsc_khz(void)
3fabc55f
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664{
665 return lguest_data.tsc_khz;
666}
667
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668/* If we can't use the TSC, the kernel falls back to our lower-priority
669 * "lguest_clock", where we read the time value given to us by the Host. */
8e19608e 670static cycle_t lguest_clock_read(struct clocksource *cs)
d7e28ffe 671{
6c8dca5d
RR
672 unsigned long sec, nsec;
673
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674 /* Since the time is in two parts (seconds and nanoseconds), we risk
675 * reading it just as it's changing from 99 & 0.999999999 to 100 and 0,
676 * and getting 99 and 0. As Linux tends to come apart under the stress
677 * of time travel, we must be careful: */
6c8dca5d
RR
678 do {
679 /* First we read the seconds part. */
680 sec = lguest_data.time.tv_sec;
681 /* This read memory barrier tells the compiler and the CPU that
682 * this can't be reordered: we have to complete the above
683 * before going on. */
684 rmb();
685 /* Now we read the nanoseconds part. */
686 nsec = lguest_data.time.tv_nsec;
687 /* Make sure we've done that. */
688 rmb();
689 /* Now if the seconds part has changed, try again. */
690 } while (unlikely(lguest_data.time.tv_sec != sec));
691
3fabc55f 692 /* Our lguest clock is in real nanoseconds. */
6c8dca5d 693 return sec*1000000000ULL + nsec;
d7e28ffe
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694}
695
3fabc55f 696/* This is the fallback clocksource: lower priority than the TSC clocksource. */
d7e28ffe
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697static struct clocksource lguest_clock = {
698 .name = "lguest",
3fabc55f 699 .rating = 200,
d7e28ffe 700 .read = lguest_clock_read,
6c8dca5d 701 .mask = CLOCKSOURCE_MASK(64),
37250097
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702 .mult = 1 << 22,
703 .shift = 22,
05aa026a 704 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
d7e28ffe
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705};
706
707/* We also need a "struct clock_event_device": Linux asks us to set it to go
708 * off some time in the future. Actually, James Morris figured all this out, I
709 * just applied the patch. */
710static int lguest_clockevent_set_next_event(unsigned long delta,
711 struct clock_event_device *evt)
712{
a6bd8e13
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713 /* FIXME: I don't think this can ever happen, but James tells me he had
714 * to put this code in. Maybe we should remove it now. Anyone? */
d7e28ffe
RR
715 if (delta < LG_CLOCK_MIN_DELTA) {
716 if (printk_ratelimit())
717 printk(KERN_DEBUG "%s: small delta %lu ns\n",
77bf90ed 718 __func__, delta);
d7e28ffe
RR
719 return -ETIME;
720 }
a6bd8e13
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721
722 /* Please wake us this far in the future. */
4cd8b5e2 723 kvm_hypercall1(LHCALL_SET_CLOCKEVENT, delta);
d7e28ffe
RR
724 return 0;
725}
726
727static void lguest_clockevent_set_mode(enum clock_event_mode mode,
728 struct clock_event_device *evt)
729{
730 switch (mode) {
731 case CLOCK_EVT_MODE_UNUSED:
732 case CLOCK_EVT_MODE_SHUTDOWN:
733 /* A 0 argument shuts the clock down. */
4cd8b5e2 734 kvm_hypercall0(LHCALL_SET_CLOCKEVENT);
d7e28ffe
RR
735 break;
736 case CLOCK_EVT_MODE_ONESHOT:
737 /* This is what we expect. */
738 break;
739 case CLOCK_EVT_MODE_PERIODIC:
740 BUG();
18de5bc4
TG
741 case CLOCK_EVT_MODE_RESUME:
742 break;
d7e28ffe
RR
743 }
744}
745
746/* This describes our primitive timer chip. */
747static struct clock_event_device lguest_clockevent = {
748 .name = "lguest",
749 .features = CLOCK_EVT_FEAT_ONESHOT,
750 .set_next_event = lguest_clockevent_set_next_event,
751 .set_mode = lguest_clockevent_set_mode,
752 .rating = INT_MAX,
753 .mult = 1,
754 .shift = 0,
755 .min_delta_ns = LG_CLOCK_MIN_DELTA,
756 .max_delta_ns = LG_CLOCK_MAX_DELTA,
757};
758
759/* This is the Guest timer interrupt handler (hardware interrupt 0). We just
760 * call the clockevent infrastructure and it does whatever needs doing. */
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761static void lguest_time_irq(unsigned int irq, struct irq_desc *desc)
762{
d7e28ffe
RR
763 unsigned long flags;
764
765 /* Don't interrupt us while this is running. */
766 local_irq_save(flags);
767 lguest_clockevent.event_handler(&lguest_clockevent);
768 local_irq_restore(flags);
07ad157f
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769}
770
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771/* At some point in the boot process, we get asked to set up our timing
772 * infrastructure. The kernel doesn't expect timer interrupts before this, but
773 * we cleverly initialized the "blocked_interrupts" field of "struct
774 * lguest_data" so that timer interrupts were blocked until now. */
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775static void lguest_time_init(void)
776{
b2b47c21 777 /* Set up the timer interrupt (0) to go to our simple timer routine */
07ad157f 778 set_irq_handler(0, lguest_time_irq);
07ad157f 779
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780 clocksource_register(&lguest_clock);
781
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782 /* We can't set cpumask in the initializer: damn C limitations! Set it
783 * here and register our timer device. */
320ab2b0 784 lguest_clockevent.cpumask = cpumask_of(0);
d7e28ffe
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785 clockevents_register_device(&lguest_clockevent);
786
b2b47c21 787 /* Finally, we unblock the timer interrupt. */
d7e28ffe 788 enable_lguest_irq(0);
07ad157f
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789}
790
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791/*
792 * Miscellaneous bits and pieces.
793 *
794 * Here is an oddball collection of functions which the Guest needs for things
795 * to work. They're pretty simple.
796 */
797
e1e72965 798/* The Guest needs to tell the Host what stack it expects traps to use. For
b2b47c21
RR
799 * native hardware, this is part of the Task State Segment mentioned above in
800 * lguest_load_tr_desc(), but to help hypervisors there's this special call.
801 *
802 * We tell the Host the segment we want to use (__KERNEL_DS is the kernel data
803 * segment), the privilege level (we're privilege level 1, the Host is 0 and
804 * will not tolerate us trying to use that), the stack pointer, and the number
805 * of pages in the stack. */
faca6227 806static void lguest_load_sp0(struct tss_struct *tss,
a6bd8e13 807 struct thread_struct *thread)
07ad157f 808{
4cd8b5e2
MZ
809 lazy_hcall3(LHCALL_SET_STACK, __KERNEL_DS | 0x1, thread->sp0,
810 THREAD_SIZE / PAGE_SIZE);
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811}
812
b2b47c21 813/* Let's just say, I wouldn't do debugging under a Guest. */
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814static void lguest_set_debugreg(int regno, unsigned long value)
815{
816 /* FIXME: Implement */
817}
818
b2b47c21
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819/* There are times when the kernel wants to make sure that no memory writes are
820 * caught in the cache (that they've all reached real hardware devices). This
821 * doesn't matter for the Guest which has virtual hardware.
822 *
823 * On the Pentium 4 and above, cpuid() indicates that the Cache Line Flush
824 * (clflush) instruction is available and the kernel uses that. Otherwise, it
825 * uses the older "Write Back and Invalidate Cache" (wbinvd) instruction.
826 * Unlike clflush, wbinvd can only be run at privilege level 0. So we can
827 * ignore clflush, but replace wbinvd.
828 */
07ad157f
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829static void lguest_wbinvd(void)
830{
831}
832
b2b47c21
RR
833/* If the Guest expects to have an Advanced Programmable Interrupt Controller,
834 * we play dumb by ignoring writes and returning 0 for reads. So it's no
835 * longer Programmable nor Controlling anything, and I don't think 8 lines of
836 * code qualifies for Advanced. It will also never interrupt anything. It
837 * does, however, allow us to get through the Linux boot code. */
07ad157f 838#ifdef CONFIG_X86_LOCAL_APIC
ad66dd34 839static void lguest_apic_write(u32 reg, u32 v)
07ad157f
RR
840{
841}
842
ad66dd34 843static u32 lguest_apic_read(u32 reg)
07ad157f
RR
844{
845 return 0;
846}
511d9d34
SS
847
848static u64 lguest_apic_icr_read(void)
849{
850 return 0;
851}
852
853static void lguest_apic_icr_write(u32 low, u32 id)
854{
855 /* Warn to see if there's any stray references */
856 WARN_ON(1);
857}
858
859static void lguest_apic_wait_icr_idle(void)
860{
861 return;
862}
863
864static u32 lguest_apic_safe_wait_icr_idle(void)
865{
866 return 0;
867}
868
c1eeb2de
YL
869static void set_lguest_basic_apic_ops(void)
870{
871 apic->read = lguest_apic_read;
872 apic->write = lguest_apic_write;
873 apic->icr_read = lguest_apic_icr_read;
874 apic->icr_write = lguest_apic_icr_write;
875 apic->wait_icr_idle = lguest_apic_wait_icr_idle;
876 apic->safe_wait_icr_idle = lguest_apic_safe_wait_icr_idle;
511d9d34 877};
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878#endif
879
b2b47c21 880/* STOP! Until an interrupt comes in. */
07ad157f
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881static void lguest_safe_halt(void)
882{
4cd8b5e2 883 kvm_hypercall0(LHCALL_HALT);
07ad157f
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884}
885
a6bd8e13
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886/* The SHUTDOWN hypercall takes a string to describe what's happening, and
887 * an argument which says whether this to restart (reboot) the Guest or not.
b2b47c21
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888 *
889 * Note that the Host always prefers that the Guest speak in physical addresses
890 * rather than virtual addresses, so we use __pa() here. */
07ad157f
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891static void lguest_power_off(void)
892{
4cd8b5e2
MZ
893 kvm_hypercall2(LHCALL_SHUTDOWN, __pa("Power down"),
894 LGUEST_SHUTDOWN_POWEROFF);
07ad157f
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895}
896
b2b47c21
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897/*
898 * Panicing.
899 *
900 * Don't. But if you did, this is what happens.
901 */
07ad157f
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902static int lguest_panic(struct notifier_block *nb, unsigned long l, void *p)
903{
4cd8b5e2 904 kvm_hypercall2(LHCALL_SHUTDOWN, __pa(p), LGUEST_SHUTDOWN_POWEROFF);
b2b47c21 905 /* The hcall won't return, but to keep gcc happy, we're "done". */
07ad157f
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906 return NOTIFY_DONE;
907}
908
909static struct notifier_block paniced = {
910 .notifier_call = lguest_panic
911};
912
b2b47c21 913/* Setting up memory is fairly easy. */
07ad157f
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914static __init char *lguest_memory_setup(void)
915{
a6bd8e13
RR
916 /* We do this here and not earlier because lockcheck used to barf if we
917 * did it before start_kernel(). I think we fixed that, so it'd be
918 * nice to move it back to lguest_init. Patch welcome... */
07ad157f
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919 atomic_notifier_chain_register(&panic_notifier_list, &paniced);
920
b2b47c21
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921 /* The Linux bootloader header contains an "e820" memory map: the
922 * Launcher populated the first entry with our memory limit. */
d0be6bde 923 e820_add_region(boot_params.e820_map[0].addr,
30c82645
PA
924 boot_params.e820_map[0].size,
925 boot_params.e820_map[0].type);
b2b47c21
RR
926
927 /* This string is for the boot messages. */
07ad157f
RR
928 return "LGUEST";
929}
930
e1e72965
RR
931/* We will eventually use the virtio console device to produce console output,
932 * but before that is set up we use LHCALL_NOTIFY on normal memory to produce
933 * console output. */
19f1537b
RR
934static __init int early_put_chars(u32 vtermno, const char *buf, int count)
935{
936 char scratch[17];
937 unsigned int len = count;
938
e1e72965
RR
939 /* We use a nul-terminated string, so we have to make a copy. Icky,
940 * huh? */
19f1537b
RR
941 if (len > sizeof(scratch) - 1)
942 len = sizeof(scratch) - 1;
943 scratch[len] = '\0';
944 memcpy(scratch, buf, len);
4cd8b5e2 945 kvm_hypercall1(LHCALL_NOTIFY, __pa(scratch));
19f1537b
RR
946
947 /* This routine returns the number of bytes actually written. */
948 return len;
949}
950
a6bd8e13
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951/* Rebooting also tells the Host we're finished, but the RESTART flag tells the
952 * Launcher to reboot us. */
953static void lguest_restart(char *reason)
954{
4cd8b5e2 955 kvm_hypercall2(LHCALL_SHUTDOWN, __pa(reason), LGUEST_SHUTDOWN_RESTART);
a6bd8e13
RR
956}
957
b2b47c21
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958/*G:050
959 * Patching (Powerfully Placating Performance Pedants)
960 *
a6bd8e13
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961 * We have already seen that pv_ops structures let us replace simple native
962 * instructions with calls to the appropriate back end all throughout the
963 * kernel. This allows the same kernel to run as a Guest and as a native
b2b47c21
RR
964 * kernel, but it's slow because of all the indirect branches.
965 *
966 * Remember that David Wheeler quote about "Any problem in computer science can
967 * be solved with another layer of indirection"? The rest of that quote is
968 * "... But that usually will create another problem." This is the first of
969 * those problems.
970 *
971 * Our current solution is to allow the paravirt back end to optionally patch
972 * over the indirect calls to replace them with something more efficient. We
a32a8813
RR
973 * patch two of the simplest of the most commonly called functions: disable
974 * interrupts and save interrupts. We usually have 6 or 10 bytes to patch
975 * into: the Guest versions of these operations are small enough that we can
976 * fit comfortably.
b2b47c21
RR
977 *
978 * First we need assembly templates of each of the patchable Guest operations,
72410af9 979 * and these are in i386_head.S. */
b2b47c21
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980
981/*G:060 We construct a table from the assembler templates: */
07ad157f
RR
982static const struct lguest_insns
983{
984 const char *start, *end;
985} lguest_insns[] = {
93b1eab3 986 [PARAVIRT_PATCH(pv_irq_ops.irq_disable)] = { lgstart_cli, lgend_cli },
93b1eab3 987 [PARAVIRT_PATCH(pv_irq_ops.save_fl)] = { lgstart_pushf, lgend_pushf },
07ad157f 988};
b2b47c21
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989
990/* Now our patch routine is fairly simple (based on the native one in
991 * paravirt.c). If we have a replacement, we copy it in and return how much of
992 * the available space we used. */
ab144f5e
AK
993static unsigned lguest_patch(u8 type, u16 clobber, void *ibuf,
994 unsigned long addr, unsigned len)
07ad157f
RR
995{
996 unsigned int insn_len;
997
b2b47c21 998 /* Don't do anything special if we don't have a replacement */
07ad157f 999 if (type >= ARRAY_SIZE(lguest_insns) || !lguest_insns[type].start)
ab144f5e 1000 return paravirt_patch_default(type, clobber, ibuf, addr, len);
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1001
1002 insn_len = lguest_insns[type].end - lguest_insns[type].start;
1003
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1004 /* Similarly if we can't fit replacement (shouldn't happen, but let's
1005 * be thorough). */
07ad157f 1006 if (len < insn_len)
ab144f5e 1007 return paravirt_patch_default(type, clobber, ibuf, addr, len);
07ad157f 1008
b2b47c21 1009 /* Copy in our instructions. */
ab144f5e 1010 memcpy(ibuf, lguest_insns[type].start, insn_len);
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1011 return insn_len;
1012}
1013
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1014/*G:030 Once we get to lguest_init(), we know we're a Guest. The various
1015 * pv_ops structures in the kernel provide points for (almost) every routine we
1016 * have to override to avoid privileged instructions. */
814a0e5c 1017__init void lguest_init(void)
07ad157f 1018{
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RR
1019 /* We're under lguest, paravirt is enabled, and we're running at
1020 * privilege level 1, not 0 as normal. */
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1021 pv_info.name = "lguest";
1022 pv_info.paravirt_enabled = 1;
1023 pv_info.kernel_rpl = 1;
07ad157f 1024
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1025 /* We set up all the lguest overrides for sensitive operations. These
1026 * are detailed with the operations themselves. */
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JF
1027
1028 /* interrupt-related operations */
1029 pv_irq_ops.init_IRQ = lguest_init_IRQ;
ecb93d1c 1030 pv_irq_ops.save_fl = PV_CALLEE_SAVE(save_fl);
61f4bc83 1031 pv_irq_ops.restore_fl = __PV_IS_CALLEE_SAVE(lg_restore_fl);
ecb93d1c 1032 pv_irq_ops.irq_disable = PV_CALLEE_SAVE(irq_disable);
61f4bc83 1033 pv_irq_ops.irq_enable = __PV_IS_CALLEE_SAVE(lg_irq_enable);
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1034 pv_irq_ops.safe_halt = lguest_safe_halt;
1035
1036 /* init-time operations */
1037 pv_init_ops.memory_setup = lguest_memory_setup;
1038 pv_init_ops.patch = lguest_patch;
1039
1040 /* Intercepts of various cpu instructions */
1041 pv_cpu_ops.load_gdt = lguest_load_gdt;
1042 pv_cpu_ops.cpuid = lguest_cpuid;
1043 pv_cpu_ops.load_idt = lguest_load_idt;
1044 pv_cpu_ops.iret = lguest_iret;
faca6227 1045 pv_cpu_ops.load_sp0 = lguest_load_sp0;
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1046 pv_cpu_ops.load_tr_desc = lguest_load_tr_desc;
1047 pv_cpu_ops.set_ldt = lguest_set_ldt;
1048 pv_cpu_ops.load_tls = lguest_load_tls;
1049 pv_cpu_ops.set_debugreg = lguest_set_debugreg;
1050 pv_cpu_ops.clts = lguest_clts;
1051 pv_cpu_ops.read_cr0 = lguest_read_cr0;
1052 pv_cpu_ops.write_cr0 = lguest_write_cr0;
1053 pv_cpu_ops.read_cr4 = lguest_read_cr4;
1054 pv_cpu_ops.write_cr4 = lguest_write_cr4;
1055 pv_cpu_ops.write_gdt_entry = lguest_write_gdt_entry;
1056 pv_cpu_ops.write_idt_entry = lguest_write_idt_entry;
1057 pv_cpu_ops.wbinvd = lguest_wbinvd;
224101ed
JF
1058 pv_cpu_ops.start_context_switch = paravirt_start_context_switch;
1059 pv_cpu_ops.end_context_switch = lguest_end_context_switch;
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1060
1061 /* pagetable management */
1062 pv_mmu_ops.write_cr3 = lguest_write_cr3;
1063 pv_mmu_ops.flush_tlb_user = lguest_flush_tlb_user;
1064 pv_mmu_ops.flush_tlb_single = lguest_flush_tlb_single;
1065 pv_mmu_ops.flush_tlb_kernel = lguest_flush_tlb_kernel;
1066 pv_mmu_ops.set_pte = lguest_set_pte;
1067 pv_mmu_ops.set_pte_at = lguest_set_pte_at;
1068 pv_mmu_ops.set_pmd = lguest_set_pmd;
1069 pv_mmu_ops.read_cr2 = lguest_read_cr2;
1070 pv_mmu_ops.read_cr3 = lguest_read_cr3;
8965c1c0 1071 pv_mmu_ops.lazy_mode.enter = paravirt_enter_lazy_mmu;
b407fc57 1072 pv_mmu_ops.lazy_mode.leave = lguest_leave_lazy_mmu_mode;
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1073 pv_mmu_ops.pte_update = lguest_pte_update;
1074 pv_mmu_ops.pte_update_defer = lguest_pte_update;
93b1eab3 1075
07ad157f 1076#ifdef CONFIG_X86_LOCAL_APIC
93b1eab3 1077 /* apic read/write intercepts */
c1eeb2de 1078 set_lguest_basic_apic_ops();
07ad157f 1079#endif
93b1eab3
JF
1080
1081 /* time operations */
1082 pv_time_ops.get_wallclock = lguest_get_wallclock;
1083 pv_time_ops.time_init = lguest_time_init;
e93ef949 1084 pv_time_ops.get_tsc_khz = lguest_tsc_khz;
93b1eab3 1085
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1086 /* Now is a good time to look at the implementations of these functions
1087 * before returning to the rest of lguest_init(). */
1088
1089 /*G:070 Now we've seen all the paravirt_ops, we return to
1090 * lguest_init() where the rest of the fairly chaotic boot setup
47436aa4 1091 * occurs. */
07ad157f 1092
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1093 /* The stack protector is a weird thing where gcc places a canary
1094 * value on the stack and then checks it on return. This file is
1095 * compiled with -fno-stack-protector it, so we got this far without
1096 * problems. The value of the canary is kept at offset 20 from the
1097 * %gs register, so we need to set that up before calling C functions
1098 * in other files. */
1099 setup_stack_canary_segment(0);
1100 /* We could just call load_stack_canary_segment(), but we might as
1101 * call switch_to_new_gdt() which loads the whole table and sets up
1102 * the per-cpu segment descriptor register %fs as well. */
1103 switch_to_new_gdt(0);
1104
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1105 /* As described in head_32.S, we map the first 128M of memory. */
1106 max_pfn_mapped = (128*1024*1024) >> PAGE_SHIFT;
1107
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1108 /* The Host<->Guest Switcher lives at the top of our address space, and
1109 * the Host told us how big it is when we made LGUEST_INIT hypercall:
1110 * it put the answer in lguest_data.reserve_mem */
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RR
1111 reserve_top_address(lguest_data.reserve_mem);
1112
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1113 /* If we don't initialize the lock dependency checker now, it crashes
1114 * paravirt_disable_iospace. */
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1115 lockdep_init();
1116
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1117 /* The IDE code spends about 3 seconds probing for disks: if we reserve
1118 * all the I/O ports up front it can't get them and so doesn't probe.
1119 * Other device drivers are similar (but less severe). This cuts the
1120 * kernel boot time on my machine from 4.1 seconds to 0.45 seconds. */
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1121 paravirt_disable_iospace();
1122
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1123 /* This is messy CPU setup stuff which the native boot code does before
1124 * start_kernel, so we have to do, too: */
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RR
1125 cpu_detect(&new_cpu_data);
1126 /* head.S usually sets up the first capability word, so do it here. */
1127 new_cpu_data.x86_capability[0] = cpuid_edx(1);
1128
1129 /* Math is always hard! */
1130 new_cpu_data.hard_math = 1;
1131
a6bd8e13 1132 /* We don't have features. We have puppies! Puppies! */
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1133#ifdef CONFIG_X86_MCE
1134 mce_disabled = 1;
1135#endif
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1136#ifdef CONFIG_ACPI
1137 acpi_disabled = 1;
1138 acpi_ht = 0;
1139#endif
1140
72410af9 1141 /* We set the preferred console to "hvc". This is the "hypervisor
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1142 * virtual console" driver written by the PowerPC people, which we also
1143 * adapted for lguest's use. */
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RR
1144 add_preferred_console("hvc", 0, NULL);
1145
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RR
1146 /* Register our very early console. */
1147 virtio_cons_early_init(early_put_chars);
1148
b2b47c21 1149 /* Last of all, we set the power management poweroff hook to point to
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RR
1150 * the Guest routine to power off, and the reboot hook to our restart
1151 * routine. */
07ad157f 1152 pm_power_off = lguest_power_off;
ec04b13f 1153 machine_ops.restart = lguest_restart;
a6bd8e13 1154
f0d43100 1155 /* Now we're set up, call i386_start_kernel() in head32.c and we proceed
b2b47c21 1156 * to boot as normal. It never returns. */
f0d43100 1157 i386_start_kernel();
07ad157f 1158}
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1159/*
1160 * This marks the end of stage II of our journey, The Guest.
1161 *
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1162 * It is now time for us to explore the layer of virtual drivers and complete
1163 * our understanding of the Guest in "make Drivers".
b2b47c21 1164 */