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KVM: remove in_range from io devices
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
229456fc
MT		 40#define CREATE_TRACE_POINTS
41#include "trace.h"
043405e1
CO		 42
43#include <asm/uaccess.h>
d825ed0a 44#include <asm/msr.h>
a5f61300 45#include <asm/desc.h>
0bed3b56 46#include <asm/mtrr.h>
890ca9ae 47#include <asm/mce.h>
043405e1 48
313a3dc7 49#define MAX_IO_MSRS 256
a03490ed
CO		 50#define CR0_RESERVED_BITS \
51 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
52 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
53 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
54#define CR4_RESERVED_BITS \
55 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
56 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
57 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
58 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
59
60#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 61
62#define KVM_MAX_MCE_BANKS 32
63#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
64
50a37eb4
JR		 65/* EFER defaults:
66 * - enable syscall per default because its emulated by KVM
67 * - enable LME and LMA per default on 64 bit KVM
68 */
69#ifdef CONFIG_X86_64
70static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
71#else
72static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
73#endif
313a3dc7 74
ba1389b7
AK		 75#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
76#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 77
674eea0f
AK		 78static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
79 struct kvm_cpuid_entry2 __user *entries);
d8017474
AG		 80struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
81 u32 function, u32 index);
674eea0f 82
97896d04 83struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 84EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 85
ed85c068
AP		 86int ignore_msrs = 0;
87module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
88
417bc304 89struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 90 { "pf_fixed", VCPU_STAT(pf_fixed) },
91 { "pf_guest", VCPU_STAT(pf_guest) },
92 { "tlb_flush", VCPU_STAT(tlb_flush) },
93 { "invlpg", VCPU_STAT(invlpg) },
94 { "exits", VCPU_STAT(exits) },
95 { "io_exits", VCPU_STAT(io_exits) },
96 { "mmio_exits", VCPU_STAT(mmio_exits) },
97 { "signal_exits", VCPU_STAT(signal_exits) },
98 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 99 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 100 { "halt_exits", VCPU_STAT(halt_exits) },
101 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 102 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 103 { "request_irq", VCPU_STAT(request_irq_exits) },
104 { "irq_exits", VCPU_STAT(irq_exits) },
105 { "host_state_reload", VCPU_STAT(host_state_reload) },
106 { "efer_reload", VCPU_STAT(efer_reload) },
107 { "fpu_reload", VCPU_STAT(fpu_reload) },
108 { "insn_emulation", VCPU_STAT(insn_emulation) },
109 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 110 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 111 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 112 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
113 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
114 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
115 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
116 { "mmu_flooded", VM_STAT(mmu_flooded) },
117 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 118 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 119 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 120 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 121 { "largepages", VM_STAT(lpages) },
417bc304
HB		 122 { NULL }
123};
124
5fb76f9b
CO		 125unsigned long segment_base(u16 selector)
126{
127 struct descriptor_table gdt;
a5f61300 128 struct desc_struct *d;
5fb76f9b
CO		 129 unsigned long table_base;
130 unsigned long v;
131
132 if (selector == 0)
133 return 0;
134
135 asm("sgdt %0" : "=m"(gdt));
136 table_base = gdt.base;
137
138 if (selector & 4) { /* from ldt */
139 u16 ldt_selector;
140
141 asm("sldt %0" : "=g"(ldt_selector));
142 table_base = segment_base(ldt_selector);
143 }
a5f61300
AK		 144 d = (struct desc_struct *)(table_base + (selector & ~7));
145 v = d->base0 | ((unsigned long)d->base1 << 16) |
146 ((unsigned long)d->base2 << 24);
5fb76f9b 147#ifdef CONFIG_X86_64
a5f61300
AK		 148 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
149 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 150#endif
151 return v;
152}
153EXPORT_SYMBOL_GPL(segment_base);
154
6866b83e
CO		 155u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
156{
157 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 158 return vcpu->arch.apic_base;
6866b83e 159 else
ad312c7c 160 return vcpu->arch.apic_base;
6866b83e
CO		 161}
162EXPORT_SYMBOL_GPL(kvm_get_apic_base);
163
164void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
165{
166 /* TODO: reserve bits check */
167 if (irqchip_in_kernel(vcpu->kvm))
168 kvm_lapic_set_base(vcpu, data);
169 else
ad312c7c 170 vcpu->arch.apic_base = data;
6866b83e
CO		 171}
172EXPORT_SYMBOL_GPL(kvm_set_apic_base);
173
298101da
AK		 174void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
175{
ad312c7c
ZX		 176 WARN_ON(vcpu->arch.exception.pending);
177 vcpu->arch.exception.pending = true;
178 vcpu->arch.exception.has_error_code = false;
179 vcpu->arch.exception.nr = nr;
298101da
AK		 180}
181EXPORT_SYMBOL_GPL(kvm_queue_exception);
182
c3c91fee
AK		 183void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
184 u32 error_code)
185{
186 ++vcpu->stat.pf_guest;
d8017474 187
71c4dfaf 188 if (vcpu->arch.exception.pending) {
6edf14d8
GN		 189 switch(vcpu->arch.exception.nr) {
190 case DF_VECTOR:
71c4dfaf
JR		 191 /* triple fault -> shutdown */
192 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
6edf14d8
GN		 193 return;
194 case PF_VECTOR:
195 vcpu->arch.exception.nr = DF_VECTOR;
196 vcpu->arch.exception.error_code = 0;
197 return;
198 default:
199 /* replace previous exception with a new one in a hope
200 that instruction re-execution will regenerate lost
201 exception */
202 vcpu->arch.exception.pending = false;
203 break;
71c4dfaf 204 }
c3c91fee 205 }
ad312c7c 206 vcpu->arch.cr2 = addr;
c3c91fee
AK		 207 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
208}
209
3419ffc8
SY		 210void kvm_inject_nmi(struct kvm_vcpu *vcpu)
211{
212 vcpu->arch.nmi_pending = 1;
213}
214EXPORT_SYMBOL_GPL(kvm_inject_nmi);
215
298101da
AK		 216void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
217{
ad312c7c
ZX		 218 WARN_ON(vcpu->arch.exception.pending);
219 vcpu->arch.exception.pending = true;
220 vcpu->arch.exception.has_error_code = true;
221 vcpu->arch.exception.nr = nr;
222 vcpu->arch.exception.error_code = error_code;
298101da
AK		 223}
224EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
225
226static void __queue_exception(struct kvm_vcpu *vcpu)
227{
ad312c7c
ZX		 228 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
229 vcpu->arch.exception.has_error_code,
230 vcpu->arch.exception.error_code);
298101da
AK		 231}
232
a03490ed
CO		 233/*
234 * Load the pae pdptrs. Return true is they are all valid.
235 */
236int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
237{
238 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
239 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
240 int i;
241 int ret;
ad312c7c 242 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 243
a03490ed
CO		 244 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
245 offset * sizeof(u64), sizeof(pdpte));
246 if (ret < 0) {
247 ret = 0;
248 goto out;
249 }
250 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 251 if (is_present_gpte(pdpte[i]) &&
20c466b5 252 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 253 ret = 0;
254 goto out;
255 }
256 }
257 ret = 1;
258
ad312c7c 259 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 260 __set_bit(VCPU_EXREG_PDPTR,
261 (unsigned long *)&vcpu->arch.regs_avail);
262 __set_bit(VCPU_EXREG_PDPTR,
263 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 264out:
a03490ed
CO		 265
266 return ret;
267}
cc4b6871 268EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 269
d835dfec
AK		 270static bool pdptrs_changed(struct kvm_vcpu *vcpu)
271{
ad312c7c 272 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 273 bool changed = true;
274 int r;
275
276 if (is_long_mode(vcpu) || !is_pae(vcpu))
277 return false;
278
6de4f3ad
AK		 279 if (!test_bit(VCPU_EXREG_PDPTR,
280 (unsigned long *)&vcpu->arch.regs_avail))
281 return true;
282
ad312c7c 283 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 284 if (r < 0)
285 goto out;
ad312c7c 286 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 287out:
d835dfec
AK		 288
289 return changed;
290}
291
2d3ad1f4 292void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 293{
294 if (cr0 & CR0_RESERVED_BITS) {
295 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 296 cr0, vcpu->arch.cr0);
c1a5d4f9 297 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 298 return;
299 }
300
301 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
302 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 303 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 304 return;
305 }
306
307 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
308 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
309 "and a clear PE flag\n");
c1a5d4f9 310 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 311 return;
312 }
313
314 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
315#ifdef CONFIG_X86_64
ad312c7c 316 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 317 int cs_db, cs_l;
318
319 if (!is_pae(vcpu)) {
320 printk(KERN_DEBUG "set_cr0: #GP, start paging "
321 "in long mode while PAE is disabled\n");
c1a5d4f9 322 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 323 return;
324 }
325 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
326 if (cs_l) {
327 printk(KERN_DEBUG "set_cr0: #GP, start paging "
328 "in long mode while CS.L == 1\n");
c1a5d4f9 329 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 330 return;
331
332 }
333 } else
334#endif
ad312c7c 335 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 336 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
337 "reserved bits\n");
c1a5d4f9 338 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 339 return;
340 }
341
342 }
343
344 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 345 vcpu->arch.cr0 = cr0;
a03490ed 346
a03490ed 347 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 348 return;
349}
2d3ad1f4 350EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 351
2d3ad1f4 352void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 353{
2d3ad1f4 354 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
a03490ed 355}
2d3ad1f4 356EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 357
2d3ad1f4 358void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 359{
a2edf57f
AK		 360 unsigned long old_cr4 = vcpu->arch.cr4;
361 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
362
a03490ed
CO		 363 if (cr4 & CR4_RESERVED_BITS) {
364 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 365 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 366 return;
367 }
368
369 if (is_long_mode(vcpu)) {
370 if (!(cr4 & X86_CR4_PAE)) {
371 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
372 "in long mode\n");
c1a5d4f9 373 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 374 return;
375 }
a2edf57f
AK		 376 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
377 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 378 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 379 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 380 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 381 return;
382 }
383
384 if (cr4 & X86_CR4_VMXE) {
385 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 386 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 387 return;
388 }
389 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 390 vcpu->arch.cr4 = cr4;
5a41accd 391 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 392 kvm_mmu_reset_context(vcpu);
a03490ed 393}
2d3ad1f4 394EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 395
2d3ad1f4 396void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 397{
ad312c7c 398 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 399 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 400 kvm_mmu_flush_tlb(vcpu);
401 return;
402 }
403
a03490ed
CO		 404 if (is_long_mode(vcpu)) {
405 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
406 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 407 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 408 return;
409 }
410 } else {
411 if (is_pae(vcpu)) {
412 if (cr3 & CR3_PAE_RESERVED_BITS) {
413 printk(KERN_DEBUG
414 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 415 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 416 return;
417 }
418 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
419 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
420 "reserved bits\n");
c1a5d4f9 421 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 422 return;
423 }
424 }
425 /*
426 * We don't check reserved bits in nonpae mode, because
427 * this isn't enforced, and VMware depends on this.
428 */
429 }
430
a03490ed
CO		 431 /*
432 * Does the new cr3 value map to physical memory? (Note, we
433 * catch an invalid cr3 even in real-mode, because it would
434 * cause trouble later on when we turn on paging anyway.)
435 *
436 * A real CPU would silently accept an invalid cr3 and would
437 * attempt to use it - with largely undefined (and often hard
438 * to debug) behavior on the guest side.
439 */
440 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 441 kvm_inject_gp(vcpu, 0);
a03490ed 442 else {
ad312c7c
ZX		 443 vcpu->arch.cr3 = cr3;
444 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 445 }
a03490ed 446}
2d3ad1f4 447EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 448
2d3ad1f4 449void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 450{
451 if (cr8 & CR8_RESERVED_BITS) {
452 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 453 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 454 return;
455 }
456 if (irqchip_in_kernel(vcpu->kvm))
457 kvm_lapic_set_tpr(vcpu, cr8);
458 else
ad312c7c 459 vcpu->arch.cr8 = cr8;
a03490ed 460}
2d3ad1f4 461EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 462
2d3ad1f4 463unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 464{
465 if (irqchip_in_kernel(vcpu->kvm))
466 return kvm_lapic_get_cr8(vcpu);
467 else
ad312c7c 468 return vcpu->arch.cr8;
a03490ed 469}
2d3ad1f4 470EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 471
d8017474
AG		 472static inline u32 bit(int bitno)
473{
474 return 1 << (bitno & 31);
475}
476
043405e1
CO		 477/*
478 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
479 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
480 *
481 * This list is modified at module load time to reflect the
482 * capabilities of the host cpu.
483 */
484static u32 msrs_to_save[] = {
485 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
486 MSR_K6_STAR,
487#ifdef CONFIG_X86_64
488 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
489#endif
af24a4e4 490 MSR_IA32_TSC, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 491 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 492};
493
494static unsigned num_msrs_to_save;
495
496static u32 emulated_msrs[] = {
497 MSR_IA32_MISC_ENABLE,
498};
499
15c4a640
CO		 500static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
501{
f2b4b7dd 502 if (efer & efer_reserved_bits) {
15c4a640
CO		 503 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
504 efer);
c1a5d4f9 505 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 506 return;
507 }
508
509 if (is_paging(vcpu)
ad312c7c 510 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 511 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 512 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 513 return;
514 }
515
1b2fd70c
AG		 516 if (efer & EFER_FFXSR) {
517 struct kvm_cpuid_entry2 *feat;
518
519 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
520 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
521 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
522 kvm_inject_gp(vcpu, 0);
523 return;
524 }
525 }
526
d8017474
AG		 527 if (efer & EFER_SVME) {
528 struct kvm_cpuid_entry2 *feat;
529
530 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
531 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
532 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
533 kvm_inject_gp(vcpu, 0);
534 return;
535 }
536 }
537
15c4a640
CO		 538 kvm_x86_ops->set_efer(vcpu, efer);
539
540 efer &= ~EFER_LMA;
ad312c7c 541 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 542
ad312c7c 543 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 544
545 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
546 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 547}
548
f2b4b7dd
JR		 549void kvm_enable_efer_bits(u64 mask)
550{
551 efer_reserved_bits &= ~mask;
552}
553EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
554
555
15c4a640
CO		 556/*
557 * Writes msr value into into the appropriate "register".
558 * Returns 0 on success, non-0 otherwise.
559 * Assumes vcpu_load() was already called.
560 */
561int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
562{
563 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
564}
565
313a3dc7
CO		 566/*
567 * Adapt set_msr() to msr_io()'s calling convention
568 */
569static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
570{
571 return kvm_set_msr(vcpu, index, *data);
572}
573
18068523
GOC		 574static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
575{
576 static int version;
50d0a0f9
GH		 577 struct pvclock_wall_clock wc;
578 struct timespec now, sys, boot;
18068523
GOC		 579
580 if (!wall_clock)
581 return;
582
583 version++;
584
18068523
GOC		 585 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
586
50d0a0f9
GH		 587 /*
588 * The guest calculates current wall clock time by adding
589 * system time (updated by kvm_write_guest_time below) to the
590 * wall clock specified here. guest system time equals host
591 * system time for us, thus we must fill in host boot time here.
592 */
593 now = current_kernel_time();
594 ktime_get_ts(&sys);
595 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
596
597 wc.sec = boot.tv_sec;
598 wc.nsec = boot.tv_nsec;
599 wc.version = version;
18068523
GOC		 600
601 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
602
603 version++;
604 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 605}
606
50d0a0f9
GH		 607static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
608{
609 uint32_t quotient, remainder;
610
611 /* Don't try to replace with do_div(), this one calculates
612 * "(dividend << 32) / divisor" */
613 __asm__ ( "divl %4"
614 : "=a" (quotient), "=d" (remainder)
615 : "0" (0), "1" (dividend), "r" (divisor) );
616 return quotient;
617}
618
619static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
620{
621 uint64_t nsecs = 1000000000LL;
622 int32_t shift = 0;
623 uint64_t tps64;
624 uint32_t tps32;
625
626 tps64 = tsc_khz * 1000LL;
627 while (tps64 > nsecs*2) {
628 tps64 >>= 1;
629 shift--;
630 }
631
632 tps32 = (uint32_t)tps64;
633 while (tps32 <= (uint32_t)nsecs) {
634 tps32 <<= 1;
635 shift++;
636 }
637
638 hv_clock->tsc_shift = shift;
639 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
640
641 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 642 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 643 hv_clock->tsc_to_system_mul);
644}
645
c8076604
GH		 646static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
647
18068523
GOC		 648static void kvm_write_guest_time(struct kvm_vcpu *v)
649{
650 struct timespec ts;
651 unsigned long flags;
652 struct kvm_vcpu_arch *vcpu = &v->arch;
653 void *shared_kaddr;
463656c0 654 unsigned long this_tsc_khz;
18068523
GOC		 655
656 if ((!vcpu->time_page))
657 return;
658
463656c0
AK		 659 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
660 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
661 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
662 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 663 }
463656c0 664 put_cpu_var(cpu_tsc_khz);
50d0a0f9 665
18068523
GOC		 666 /* Keep irq disabled to prevent changes to the clock */
667 local_irq_save(flags);
af24a4e4 668 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523
GOC		 669 ktime_get_ts(&ts);
670 local_irq_restore(flags);
671
672 /* With all the info we got, fill in the values */
673
674 vcpu->hv_clock.system_time = ts.tv_nsec +
675 (NSEC_PER_SEC * (u64)ts.tv_sec);
676 /*
677 * The interface expects us to write an even number signaling that the
678 * update is finished. Since the guest won't see the intermediate
50d0a0f9 679 * state, we just increase by 2 at the end.
18068523 680 */
50d0a0f9 681 vcpu->hv_clock.version += 2;
18068523
GOC		 682
683 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
684
685 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 686 sizeof(vcpu->hv_clock));
18068523
GOC		 687
688 kunmap_atomic(shared_kaddr, KM_USER0);
689
690 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
691}
692
c8076604
GH		 693static int kvm_request_guest_time_update(struct kvm_vcpu *v)
694{
695 struct kvm_vcpu_arch *vcpu = &v->arch;
696
697 if (!vcpu->time_page)
698 return 0;
699 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
700 return 1;
701}
702
9ba075a6
AK		 703static bool msr_mtrr_valid(unsigned msr)
704{
705 switch (msr) {
706 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
707 case MSR_MTRRfix64K_00000:
708 case MSR_MTRRfix16K_80000:
709 case MSR_MTRRfix16K_A0000:
710 case MSR_MTRRfix4K_C0000:
711 case MSR_MTRRfix4K_C8000:
712 case MSR_MTRRfix4K_D0000:
713 case MSR_MTRRfix4K_D8000:
714 case MSR_MTRRfix4K_E0000:
715 case MSR_MTRRfix4K_E8000:
716 case MSR_MTRRfix4K_F0000:
717 case MSR_MTRRfix4K_F8000:
718 case MSR_MTRRdefType:
719 case MSR_IA32_CR_PAT:
720 return true;
721 case 0x2f8:
722 return true;
723 }
724 return false;
725}
726
d6289b93
MT		 727static bool valid_pat_type(unsigned t)
728{
729 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
730}
731
732static bool valid_mtrr_type(unsigned t)
733{
734 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
735}
736
737static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
738{
739 int i;
740
741 if (!msr_mtrr_valid(msr))
742 return false;
743
744 if (msr == MSR_IA32_CR_PAT) {
745 for (i = 0; i < 8; i++)
746 if (!valid_pat_type((data >> (i * 8)) & 0xff))
747 return false;
748 return true;
749 } else if (msr == MSR_MTRRdefType) {
750 if (data & ~0xcff)
751 return false;
752 return valid_mtrr_type(data & 0xff);
753 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
754 for (i = 0; i < 8 ; i++)
755 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
756 return false;
757 return true;
758 }
759
760 /* variable MTRRs */
761 return valid_mtrr_type(data & 0xff);
762}
763
9ba075a6
AK		 764static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
765{
0bed3b56
SY		 766 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
767
d6289b93 768 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 769 return 1;
770
0bed3b56
SY		 771 if (msr == MSR_MTRRdefType) {
772 vcpu->arch.mtrr_state.def_type = data;
773 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
774 } else if (msr == MSR_MTRRfix64K_00000)
775 p[0] = data;
776 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
777 p[1 + msr - MSR_MTRRfix16K_80000] = data;
778 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
779 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
780 else if (msr == MSR_IA32_CR_PAT)
781 vcpu->arch.pat = data;
782 else { /* Variable MTRRs */
783 int idx, is_mtrr_mask;
784 u64 *pt;
785
786 idx = (msr - 0x200) / 2;
787 is_mtrr_mask = msr - 0x200 - 2 * idx;
788 if (!is_mtrr_mask)
789 pt =
790 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
791 else
792 pt =
793 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
794 *pt = data;
795 }
796
797 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 798 return 0;
799}
15c4a640 800
890ca9ae 801static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 802{
890ca9ae
HY		 803 u64 mcg_cap = vcpu->arch.mcg_cap;
804 unsigned bank_num = mcg_cap & 0xff;
805
15c4a640 806 switch (msr) {
15c4a640 807 case MSR_IA32_MCG_STATUS:
890ca9ae 808 vcpu->arch.mcg_status = data;
15c4a640 809 break;
c7ac679c 810 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 811 if (!(mcg_cap & MCG_CTL_P))
812 return 1;
813 if (data != 0 && data != ~(u64)0)
814 return -1;
815 vcpu->arch.mcg_ctl = data;
816 break;
817 default:
818 if (msr >= MSR_IA32_MC0_CTL &&
819 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
820 u32 offset = msr - MSR_IA32_MC0_CTL;
821 /* only 0 or all 1s can be written to IA32_MCi_CTL */
822 if ((offset & 0x3) == 0 &&
823 data != 0 && data != ~(u64)0)
824 return -1;
825 vcpu->arch.mce_banks[offset] = data;
826 break;
827 }
828 return 1;
829 }
830 return 0;
831}
832
833int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
834{
835 switch (msr) {
836 case MSR_EFER:
837 set_efer(vcpu, data);
c7ac679c 838 break;
8f1589d9
AP		 839 case MSR_K7_HWCR:
840 data &= ~(u64)0x40; /* ignore flush filter disable */
841 if (data != 0) {
842 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
843 data);
844 return 1;
845 }
846 break;
b5e2fec0
AG		 847 case MSR_IA32_DEBUGCTLMSR:
848 if (!data) {
849 /* We support the non-activated case already */
850 break;
851 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
852 /* Values other than LBR and BTF are vendor-specific,
853 thus reserved and should throw a #GP */
854 return 1;
855 }
856 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
857 __func__, data);
858 break;
15c4a640
CO		 859 case MSR_IA32_UCODE_REV:
860 case MSR_IA32_UCODE_WRITE:
61a6bd67 861 case MSR_VM_HSAVE_PA:
15c4a640 862 break;
9ba075a6
AK		 863 case 0x200 ... 0x2ff:
864 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 865 case MSR_IA32_APICBASE:
866 kvm_set_apic_base(vcpu, data);
867 break;
868 case MSR_IA32_MISC_ENABLE:
ad312c7c 869 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 870 break;
18068523
GOC		 871 case MSR_KVM_WALL_CLOCK:
872 vcpu->kvm->arch.wall_clock = data;
873 kvm_write_wall_clock(vcpu->kvm, data);
874 break;
875 case MSR_KVM_SYSTEM_TIME: {
876 if (vcpu->arch.time_page) {
877 kvm_release_page_dirty(vcpu->arch.time_page);
878 vcpu->arch.time_page = NULL;
879 }
880
881 vcpu->arch.time = data;
882
883 /* we verify if the enable bit is set... */
884 if (!(data & 1))
885 break;
886
887 /* ...but clean it before doing the actual write */
888 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
889
18068523
GOC		 890 vcpu->arch.time_page =
891 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 892
893 if (is_error_page(vcpu->arch.time_page)) {
894 kvm_release_page_clean(vcpu->arch.time_page);
895 vcpu->arch.time_page = NULL;
896 }
897
c8076604 898 kvm_request_guest_time_update(vcpu);
18068523
GOC		 899 break;
900 }
890ca9ae
HY		 901 case MSR_IA32_MCG_CTL:
902 case MSR_IA32_MCG_STATUS:
903 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
904 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 905
906 /* Performance counters are not protected by a CPUID bit,
907 * so we should check all of them in the generic path for the sake of
908 * cross vendor migration.
909 * Writing a zero into the event select MSRs disables them,
910 * which we perfectly emulate ;-). Any other value should be at least
911 * reported, some guests depend on them.
912 */
913 case MSR_P6_EVNTSEL0:
914 case MSR_P6_EVNTSEL1:
915 case MSR_K7_EVNTSEL0:
916 case MSR_K7_EVNTSEL1:
917 case MSR_K7_EVNTSEL2:
918 case MSR_K7_EVNTSEL3:
919 if (data != 0)
920 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
921 "0x%x data 0x%llx\n", msr, data);
922 break;
923 /* at least RHEL 4 unconditionally writes to the perfctr registers,
924 * so we ignore writes to make it happy.
925 */
926 case MSR_P6_PERFCTR0:
927 case MSR_P6_PERFCTR1:
928 case MSR_K7_PERFCTR0:
929 case MSR_K7_PERFCTR1:
930 case MSR_K7_PERFCTR2:
931 case MSR_K7_PERFCTR3:
932 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
933 "0x%x data 0x%llx\n", msr, data);
934 break;
15c4a640 935 default:
ed85c068
AP		 936 if (!ignore_msrs) {
937 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
938 msr, data);
939 return 1;
940 } else {
941 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
942 msr, data);
943 break;
944 }
15c4a640
CO		 945 }
946 return 0;
947}
948EXPORT_SYMBOL_GPL(kvm_set_msr_common);
949
950
951/*
952 * Reads an msr value (of 'msr_index') into 'pdata'.
953 * Returns 0 on success, non-0 otherwise.
954 * Assumes vcpu_load() was already called.
955 */
956int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
957{
958 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
959}
960
9ba075a6
AK		 961static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
962{
0bed3b56
SY		 963 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
964
9ba075a6
AK		 965 if (!msr_mtrr_valid(msr))
966 return 1;
967
0bed3b56
SY		 968 if (msr == MSR_MTRRdefType)
969 *pdata = vcpu->arch.mtrr_state.def_type +
970 (vcpu->arch.mtrr_state.enabled << 10);
971 else if (msr == MSR_MTRRfix64K_00000)
972 *pdata = p[0];
973 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
974 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
975 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
976 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
977 else if (msr == MSR_IA32_CR_PAT)
978 *pdata = vcpu->arch.pat;
979 else { /* Variable MTRRs */
980 int idx, is_mtrr_mask;
981 u64 *pt;
982
983 idx = (msr - 0x200) / 2;
984 is_mtrr_mask = msr - 0x200 - 2 * idx;
985 if (!is_mtrr_mask)
986 pt =
987 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
988 else
989 pt =
990 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
991 *pdata = *pt;
992 }
993
9ba075a6
AK		 994 return 0;
995}
996
890ca9ae 997static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 998{
999 u64 data;
890ca9ae
HY		 1000 u64 mcg_cap = vcpu->arch.mcg_cap;
1001 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1002
1003 switch (msr) {
15c4a640
CO		 1004 case MSR_IA32_P5_MC_ADDR:
1005 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1006 data = 0;
1007 break;
15c4a640 1008 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1009 data = vcpu->arch.mcg_cap;
1010 break;
c7ac679c 1011 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1012 if (!(mcg_cap & MCG_CTL_P))
1013 return 1;
1014 data = vcpu->arch.mcg_ctl;
1015 break;
1016 case MSR_IA32_MCG_STATUS:
1017 data = vcpu->arch.mcg_status;
1018 break;
1019 default:
1020 if (msr >= MSR_IA32_MC0_CTL &&
1021 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1022 u32 offset = msr - MSR_IA32_MC0_CTL;
1023 data = vcpu->arch.mce_banks[offset];
1024 break;
1025 }
1026 return 1;
1027 }
1028 *pdata = data;
1029 return 0;
1030}
1031
1032int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1033{
1034 u64 data;
1035
1036 switch (msr) {
890ca9ae 1037 case MSR_IA32_PLATFORM_ID:
15c4a640 1038 case MSR_IA32_UCODE_REV:
15c4a640 1039 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1040 case MSR_IA32_DEBUGCTLMSR:
1041 case MSR_IA32_LASTBRANCHFROMIP:
1042 case MSR_IA32_LASTBRANCHTOIP:
1043 case MSR_IA32_LASTINTFROMIP:
1044 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1045 case MSR_K8_SYSCFG:
1046 case MSR_K7_HWCR:
61a6bd67 1047 case MSR_VM_HSAVE_PA:
7fe29e0f
AS		 1048 case MSR_P6_EVNTSEL0:
1049 case MSR_P6_EVNTSEL1:
9e699624 1050 case MSR_K7_EVNTSEL0:
1fdbd48c 1051 case MSR_K8_INT_PENDING_MSG:
15c4a640
CO		 1052 data = 0;
1053 break;
9ba075a6
AK		 1054 case MSR_MTRRcap:
1055 data = 0x500 | KVM_NR_VAR_MTRR;
1056 break;
1057 case 0x200 ... 0x2ff:
1058 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1059 case 0xcd: /* fsb frequency */
1060 data = 3;
1061 break;
1062 case MSR_IA32_APICBASE:
1063 data = kvm_get_apic_base(vcpu);
1064 break;
1065 case MSR_IA32_MISC_ENABLE:
ad312c7c 1066 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1067 break;
847f0ad8
AG		 1068 case MSR_IA32_PERF_STATUS:
1069 /* TSC increment by tick */
1070 data = 1000ULL;
1071 /* CPU multiplier */
1072 data |= (((uint64_t)4ULL) << 40);
1073 break;
15c4a640 1074 case MSR_EFER:
ad312c7c 1075 data = vcpu->arch.shadow_efer;
15c4a640 1076 break;
18068523
GOC		 1077 case MSR_KVM_WALL_CLOCK:
1078 data = vcpu->kvm->arch.wall_clock;
1079 break;
1080 case MSR_KVM_SYSTEM_TIME:
1081 data = vcpu->arch.time;
1082 break;
890ca9ae
HY		 1083 case MSR_IA32_P5_MC_ADDR:
1084 case MSR_IA32_P5_MC_TYPE:
1085 case MSR_IA32_MCG_CAP:
1086 case MSR_IA32_MCG_CTL:
1087 case MSR_IA32_MCG_STATUS:
1088 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1089 return get_msr_mce(vcpu, msr, pdata);
15c4a640 1090 default:
ed85c068
AP		 1091 if (!ignore_msrs) {
1092 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1093 return 1;
1094 } else {
1095 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1096 data = 0;
1097 }
1098 break;
15c4a640
CO		 1099 }
1100 *pdata = data;
1101 return 0;
1102}
1103EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1104
313a3dc7
CO		 1105/*
1106 * Read or write a bunch of msrs. All parameters are kernel addresses.
1107 *
1108 * @return number of msrs set successfully.
1109 */
1110static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1111 struct kvm_msr_entry *entries,
1112 int (*do_msr)(struct kvm_vcpu *vcpu,
1113 unsigned index, u64 *data))
1114{
1115 int i;
1116
1117 vcpu_load(vcpu);
1118
3200f405 1119 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1120 for (i = 0; i < msrs->nmsrs; ++i)
1121 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1122 break;
3200f405 1123 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1124
1125 vcpu_put(vcpu);
1126
1127 return i;
1128}
1129
1130/*
1131 * Read or write a bunch of msrs. Parameters are user addresses.
1132 *
1133 * @return number of msrs set successfully.
1134 */
1135static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1136 int (*do_msr)(struct kvm_vcpu *vcpu,
1137 unsigned index, u64 *data),
1138 int writeback)
1139{
1140 struct kvm_msrs msrs;
1141 struct kvm_msr_entry *entries;
1142 int r, n;
1143 unsigned size;
1144
1145 r = -EFAULT;
1146 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1147 goto out;
1148
1149 r = -E2BIG;
1150 if (msrs.nmsrs >= MAX_IO_MSRS)
1151 goto out;
1152
1153 r = -ENOMEM;
1154 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1155 entries = vmalloc(size);
1156 if (!entries)
1157 goto out;
1158
1159 r = -EFAULT;
1160 if (copy_from_user(entries, user_msrs->entries, size))
1161 goto out_free;
1162
1163 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1164 if (r < 0)
1165 goto out_free;
1166
1167 r = -EFAULT;
1168 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1169 goto out_free;
1170
1171 r = n;
1172
1173out_free:
1174 vfree(entries);
1175out:
1176 return r;
1177}
1178
018d00d2
ZX		 1179int kvm_dev_ioctl_check_extension(long ext)
1180{
1181 int r;
1182
1183 switch (ext) {
1184 case KVM_CAP_IRQCHIP:
1185 case KVM_CAP_HLT:
1186 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1187 case KVM_CAP_SET_TSS_ADDR:
07716717 1188 case KVM_CAP_EXT_CPUID:
c8076604 1189 case KVM_CAP_CLOCKSOURCE:
7837699f 1190 case KVM_CAP_PIT:
a28e4f5a 1191 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1192 case KVM_CAP_MP_STATE:
ed848624 1193 case KVM_CAP_SYNC_MMU:
52d939a0 1194 case KVM_CAP_REINJECT_CONTROL:
4925663a 1195 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1196 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1197 case KVM_CAP_IRQFD:
c5ff41ce 1198 case KVM_CAP_PIT2:
018d00d2
ZX		 1199 r = 1;
1200 break;
542472b5
LV		 1201 case KVM_CAP_COALESCED_MMIO:
1202 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1203 break;
774ead3a
AK		 1204 case KVM_CAP_VAPIC:
1205 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1206 break;
f725230a
AK		 1207 case KVM_CAP_NR_VCPUS:
1208 r = KVM_MAX_VCPUS;
1209 break;
a988b910
AK		 1210 case KVM_CAP_NR_MEMSLOTS:
1211 r = KVM_MEMORY_SLOTS;
1212 break;
2f333bcb
MT		 1213 case KVM_CAP_PV_MMU:
1214 r = !tdp_enabled;
1215 break;
62c476c7 1216 case KVM_CAP_IOMMU:
19de40a8 1217 r = iommu_found();
62c476c7 1218 break;
890ca9ae
HY		 1219 case KVM_CAP_MCE:
1220 r = KVM_MAX_MCE_BANKS;
1221 break;
018d00d2
ZX		 1222 default:
1223 r = 0;
1224 break;
1225 }
1226 return r;
1227
1228}
1229
043405e1
CO		 1230long kvm_arch_dev_ioctl(struct file *filp,
1231 unsigned int ioctl, unsigned long arg)
1232{
1233 void __user *argp = (void __user *)arg;
1234 long r;
1235
1236 switch (ioctl) {
1237 case KVM_GET_MSR_INDEX_LIST: {
1238 struct kvm_msr_list __user *user_msr_list = argp;
1239 struct kvm_msr_list msr_list;
1240 unsigned n;
1241
1242 r = -EFAULT;
1243 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1244 goto out;
1245 n = msr_list.nmsrs;
1246 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1247 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1248 goto out;
1249 r = -E2BIG;
e125e7b6 1250 if (n < msr_list.nmsrs)
043405e1
CO		 1251 goto out;
1252 r = -EFAULT;
1253 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1254 num_msrs_to_save * sizeof(u32)))
1255 goto out;
e125e7b6 1256 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1257 &emulated_msrs,
1258 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1259 goto out;
1260 r = 0;
1261 break;
1262 }
674eea0f
AK		 1263 case KVM_GET_SUPPORTED_CPUID: {
1264 struct kvm_cpuid2 __user *cpuid_arg = argp;
1265 struct kvm_cpuid2 cpuid;
1266
1267 r = -EFAULT;
1268 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1269 goto out;
1270 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1271 cpuid_arg->entries);
674eea0f
AK		 1272 if (r)
1273 goto out;
1274
1275 r = -EFAULT;
1276 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1277 goto out;
1278 r = 0;
1279 break;
1280 }
890ca9ae
HY		 1281 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1282 u64 mce_cap;
1283
1284 mce_cap = KVM_MCE_CAP_SUPPORTED;
1285 r = -EFAULT;
1286 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1287 goto out;
1288 r = 0;
1289 break;
1290 }
043405e1
CO		 1291 default:
1292 r = -EINVAL;
1293 }
1294out:
1295 return r;
1296}
1297
313a3dc7
CO		 1298void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1299{
1300 kvm_x86_ops->vcpu_load(vcpu, cpu);
c8076604 1301 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1302}
1303
1304void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1305{
1306 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1307 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1308}
1309
07716717 1310static int is_efer_nx(void)
313a3dc7 1311{
e286e86e 1312 unsigned long long efer = 0;
313a3dc7 1313
e286e86e 1314 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1315 return efer & EFER_NX;
1316}
1317
1318static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1319{
1320 int i;
1321 struct kvm_cpuid_entry2 *e, *entry;
1322
313a3dc7 1323 entry = NULL;
ad312c7c
ZX		 1324 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1325 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1326 if (e->function == 0x80000001) {
1327 entry = e;
1328 break;
1329 }
1330 }
07716717 1331 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1332 entry->edx &= ~(1 << 20);
1333 printk(KERN_INFO "kvm: guest NX capability removed\n");
1334 }
1335}
1336
07716717 1337/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1338static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1339 struct kvm_cpuid *cpuid,
1340 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1341{
1342 int r, i;
1343 struct kvm_cpuid_entry *cpuid_entries;
1344
1345 r = -E2BIG;
1346 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1347 goto out;
1348 r = -ENOMEM;
1349 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1350 if (!cpuid_entries)
1351 goto out;
1352 r = -EFAULT;
1353 if (copy_from_user(cpuid_entries, entries,
1354 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1355 goto out_free;
1356 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1357 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1358 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1359 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1360 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1361 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1362 vcpu->arch.cpuid_entries[i].index = 0;
1363 vcpu->arch.cpuid_entries[i].flags = 0;
1364 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1365 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1366 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1367 }
1368 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1369 cpuid_fix_nx_cap(vcpu);
1370 r = 0;
1371
1372out_free:
1373 vfree(cpuid_entries);
1374out:
1375 return r;
1376}
1377
1378static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1379 struct kvm_cpuid2 *cpuid,
1380 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1381{
1382 int r;
1383
1384 r = -E2BIG;
1385 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1386 goto out;
1387 r = -EFAULT;
ad312c7c 1388 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1389 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1390 goto out;
ad312c7c 1391 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1392 return 0;
1393
1394out:
1395 return r;
1396}
1397
07716717 1398static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1399 struct kvm_cpuid2 *cpuid,
1400 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1401{
1402 int r;
1403
1404 r = -E2BIG;
ad312c7c 1405 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1406 goto out;
1407 r = -EFAULT;
ad312c7c 1408 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1409 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1410 goto out;
1411 return 0;
1412
1413out:
ad312c7c 1414 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1415 return r;
1416}
1417
07716717 1418static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1419 u32 index)
07716717
DK		 1420{
1421 entry->function = function;
1422 entry->index = index;
1423 cpuid_count(entry->function, entry->index,
19355475 1424 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1425 entry->flags = 0;
1426}
1427
7faa4ee1
AK		 1428#define F(x) bit(X86_FEATURE_##x)
1429
07716717
DK		 1430static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1431 u32 index, int *nent, int maxnent)
1432{
7faa4ee1 1433 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1434#ifdef CONFIG_X86_64
7faa4ee1
AK		 1435 unsigned f_lm = F(LM);
1436#else
1437 unsigned f_lm = 0;
07716717 1438#endif
7faa4ee1
AK		 1439
1440 /* cpuid 1.edx */
1441 const u32 kvm_supported_word0_x86_features =
1442 F(FPU) | F(VME) | F(DE) | F(PSE) |
1443 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1444 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1445 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1446 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1447 0 /* Reserved, DS, ACPI */ | F(MMX) |
1448 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1449 0 /* HTT, TM, Reserved, PBE */;
1450 /* cpuid 0x80000001.edx */
1451 const u32 kvm_supported_word1_x86_features =
1452 F(FPU) | F(VME) | F(DE) | F(PSE) |
1453 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1454 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1455 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1456 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1457 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
1458 F(FXSR) | F(FXSR_OPT) | 0 /* GBPAGES */ | 0 /* RDTSCP */ |
1459 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1460 /* cpuid 1.ecx */
1461 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1462 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1463 0 /* DS-CPL, VMX, SMX, EST */ |
1464 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1465 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1466 0 /* Reserved, DCA */ | F(XMM4_1) |
1467 F(XMM4_2) | 0 /* x2APIC */ | F(MOVBE) | F(POPCNT) |
1468 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1469 /* cpuid 0x80000001.ecx */
07716717 1470 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1471 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1472 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1473 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1474 0 /* SKINIT */ | 0 /* WDT */;
07716717 1475
19355475 1476 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1477 get_cpu();
1478 do_cpuid_1_ent(entry, function, index);
1479 ++*nent;
1480
1481 switch (function) {
1482 case 0:
1483 entry->eax = min(entry->eax, (u32)0xb);
1484 break;
1485 case 1:
1486 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1487 entry->ecx &= kvm_supported_word4_x86_features;
07716717
DK		 1488 break;
1489 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1490 * may return different values. This forces us to get_cpu() before
1491 * issuing the first command, and also to emulate this annoying behavior
1492 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1493 case 2: {
1494 int t, times = entry->eax & 0xff;
1495
1496 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1497 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1498 for (t = 1; t < times && *nent < maxnent; ++t) {
1499 do_cpuid_1_ent(&entry[t], function, 0);
1500 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1501 ++*nent;
1502 }
1503 break;
1504 }
1505 /* function 4 and 0xb have additional index. */
1506 case 4: {
14af3f3c 1507 int i, cache_type;
07716717
DK		 1508
1509 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1510 /* read more entries until cache_type is zero */
14af3f3c
HH		 1511 for (i = 1; *nent < maxnent; ++i) {
1512 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1513 if (!cache_type)
1514 break;
14af3f3c
HH		 1515 do_cpuid_1_ent(&entry[i], function, i);
1516 entry[i].flags |=
07716717
DK		 1517 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1518 ++*nent;
1519 }
1520 break;
1521 }
1522 case 0xb: {
14af3f3c 1523 int i, level_type;
07716717
DK		 1524
1525 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1526 /* read more entries until level_type is zero */
14af3f3c 1527 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1528 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1529 if (!level_type)
1530 break;
14af3f3c
HH		 1531 do_cpuid_1_ent(&entry[i], function, i);
1532 entry[i].flags |=
07716717
DK		 1533 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1534 ++*nent;
1535 }
1536 break;
1537 }
1538 case 0x80000000:
1539 entry->eax = min(entry->eax, 0x8000001a);
1540 break;
1541 case 0x80000001:
1542 entry->edx &= kvm_supported_word1_x86_features;
1543 entry->ecx &= kvm_supported_word6_x86_features;
1544 break;
1545 }
1546 put_cpu();
1547}
1548
7faa4ee1
AK		 1549#undef F
1550
674eea0f 1551static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1552 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1553{
1554 struct kvm_cpuid_entry2 *cpuid_entries;
1555 int limit, nent = 0, r = -E2BIG;
1556 u32 func;
1557
1558 if (cpuid->nent < 1)
1559 goto out;
1560 r = -ENOMEM;
1561 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1562 if (!cpuid_entries)
1563 goto out;
1564
1565 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1566 limit = cpuid_entries[0].eax;
1567 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1568 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1569 &nent, cpuid->nent);
07716717
DK		 1570 r = -E2BIG;
1571 if (nent >= cpuid->nent)
1572 goto out_free;
1573
1574 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1575 limit = cpuid_entries[nent - 1].eax;
1576 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1577 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1578 &nent, cpuid->nent);
cb007648
MM		 1579 r = -E2BIG;
1580 if (nent >= cpuid->nent)
1581 goto out_free;
1582
07716717
DK		 1583 r = -EFAULT;
1584 if (copy_to_user(entries, cpuid_entries,
19355475 1585 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1586 goto out_free;
1587 cpuid->nent = nent;
1588 r = 0;
1589
1590out_free:
1591 vfree(cpuid_entries);
1592out:
1593 return r;
1594}
1595
313a3dc7
CO		 1596static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1597 struct kvm_lapic_state *s)
1598{
1599 vcpu_load(vcpu);
ad312c7c 1600 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1601 vcpu_put(vcpu);
1602
1603 return 0;
1604}
1605
1606static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1607 struct kvm_lapic_state *s)
1608{
1609 vcpu_load(vcpu);
ad312c7c 1610 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1611 kvm_apic_post_state_restore(vcpu);
1612 vcpu_put(vcpu);
1613
1614 return 0;
1615}
1616
f77bc6a4
ZX		 1617static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1618 struct kvm_interrupt *irq)
1619{
1620 if (irq->irq < 0 || irq->irq >= 256)
1621 return -EINVAL;
1622 if (irqchip_in_kernel(vcpu->kvm))
1623 return -ENXIO;
1624 vcpu_load(vcpu);
1625
66fd3f7f 1626 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1627
1628 vcpu_put(vcpu);
1629
1630 return 0;
1631}
1632
c4abb7c9
JK		 1633static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1634{
1635 vcpu_load(vcpu);
1636 kvm_inject_nmi(vcpu);
1637 vcpu_put(vcpu);
1638
1639 return 0;
1640}
1641
b209749f
AK		 1642static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1643 struct kvm_tpr_access_ctl *tac)
1644{
1645 if (tac->flags)
1646 return -EINVAL;
1647 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1648 return 0;
1649}
1650
890ca9ae
HY		 1651static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1652 u64 mcg_cap)
1653{
1654 int r;
1655 unsigned bank_num = mcg_cap & 0xff, bank;
1656
1657 r = -EINVAL;
1658 if (!bank_num)
1659 goto out;
1660 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1661 goto out;
1662 r = 0;
1663 vcpu->arch.mcg_cap = mcg_cap;
1664 /* Init IA32_MCG_CTL to all 1s */
1665 if (mcg_cap & MCG_CTL_P)
1666 vcpu->arch.mcg_ctl = ~(u64)0;
1667 /* Init IA32_MCi_CTL to all 1s */
1668 for (bank = 0; bank < bank_num; bank++)
1669 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1670out:
1671 return r;
1672}
1673
1674static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1675 struct kvm_x86_mce *mce)
1676{
1677 u64 mcg_cap = vcpu->arch.mcg_cap;
1678 unsigned bank_num = mcg_cap & 0xff;
1679 u64 *banks = vcpu->arch.mce_banks;
1680
1681 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1682 return -EINVAL;
1683 /*
1684 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1685 * reporting is disabled
1686 */
1687 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1688 vcpu->arch.mcg_ctl != ~(u64)0)
1689 return 0;
1690 banks += 4 * mce->bank;
1691 /*
1692 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1693 * reporting is disabled for the bank
1694 */
1695 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1696 return 0;
1697 if (mce->status & MCI_STATUS_UC) {
1698 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1699 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1700 printk(KERN_DEBUG "kvm: set_mce: "
1701 "injects mce exception while "
1702 "previous one is in progress!\n");
1703 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1704 return 0;
1705 }
1706 if (banks[1] & MCI_STATUS_VAL)
1707 mce->status |= MCI_STATUS_OVER;
1708 banks[2] = mce->addr;
1709 banks[3] = mce->misc;
1710 vcpu->arch.mcg_status = mce->mcg_status;
1711 banks[1] = mce->status;
1712 kvm_queue_exception(vcpu, MC_VECTOR);
1713 } else if (!(banks[1] & MCI_STATUS_VAL)
1714 || !(banks[1] & MCI_STATUS_UC)) {
1715 if (banks[1] & MCI_STATUS_VAL)
1716 mce->status |= MCI_STATUS_OVER;
1717 banks[2] = mce->addr;
1718 banks[3] = mce->misc;
1719 banks[1] = mce->status;
1720 } else
1721 banks[1] |= MCI_STATUS_OVER;
1722 return 0;
1723}
1724
313a3dc7
CO		 1725long kvm_arch_vcpu_ioctl(struct file *filp,
1726 unsigned int ioctl, unsigned long arg)
1727{
1728 struct kvm_vcpu *vcpu = filp->private_data;
1729 void __user *argp = (void __user *)arg;
1730 int r;
b772ff36 1731 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1732
1733 switch (ioctl) {
1734 case KVM_GET_LAPIC: {
b772ff36 1735 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1736
b772ff36
DH		 1737 r = -ENOMEM;
1738 if (!lapic)
1739 goto out;
1740 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1741 if (r)
1742 goto out;
1743 r = -EFAULT;
b772ff36 1744 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1745 goto out;
1746 r = 0;
1747 break;
1748 }
1749 case KVM_SET_LAPIC: {
b772ff36
DH		 1750 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1751 r = -ENOMEM;
1752 if (!lapic)
1753 goto out;
313a3dc7 1754 r = -EFAULT;
b772ff36 1755 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1756 goto out;
b772ff36 1757 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1758 if (r)
1759 goto out;
1760 r = 0;
1761 break;
1762 }
f77bc6a4
ZX		 1763 case KVM_INTERRUPT: {
1764 struct kvm_interrupt irq;
1765
1766 r = -EFAULT;
1767 if (copy_from_user(&irq, argp, sizeof irq))
1768 goto out;
1769 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1770 if (r)
1771 goto out;
1772 r = 0;
1773 break;
1774 }
c4abb7c9
JK		 1775 case KVM_NMI: {
1776 r = kvm_vcpu_ioctl_nmi(vcpu);
1777 if (r)
1778 goto out;
1779 r = 0;
1780 break;
1781 }
313a3dc7
CO		 1782 case KVM_SET_CPUID: {
1783 struct kvm_cpuid __user *cpuid_arg = argp;
1784 struct kvm_cpuid cpuid;
1785
1786 r = -EFAULT;
1787 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1788 goto out;
1789 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1790 if (r)
1791 goto out;
1792 break;
1793 }
07716717
DK		 1794 case KVM_SET_CPUID2: {
1795 struct kvm_cpuid2 __user *cpuid_arg = argp;
1796 struct kvm_cpuid2 cpuid;
1797
1798 r = -EFAULT;
1799 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1800 goto out;
1801 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 1802 cpuid_arg->entries);
07716717
DK		 1803 if (r)
1804 goto out;
1805 break;
1806 }
1807 case KVM_GET_CPUID2: {
1808 struct kvm_cpuid2 __user *cpuid_arg = argp;
1809 struct kvm_cpuid2 cpuid;
1810
1811 r = -EFAULT;
1812 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1813 goto out;
1814 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 1815 cpuid_arg->entries);
07716717
DK		 1816 if (r)
1817 goto out;
1818 r = -EFAULT;
1819 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1820 goto out;
1821 r = 0;
1822 break;
1823 }
313a3dc7
CO		 1824 case KVM_GET_MSRS:
1825 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1826 break;
1827 case KVM_SET_MSRS:
1828 r = msr_io(vcpu, argp, do_set_msr, 0);
1829 break;
b209749f
AK		 1830 case KVM_TPR_ACCESS_REPORTING: {
1831 struct kvm_tpr_access_ctl tac;
1832
1833 r = -EFAULT;
1834 if (copy_from_user(&tac, argp, sizeof tac))
1835 goto out;
1836 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1837 if (r)
1838 goto out;
1839 r = -EFAULT;
1840 if (copy_to_user(argp, &tac, sizeof tac))
1841 goto out;
1842 r = 0;
1843 break;
1844 };
b93463aa
AK		 1845 case KVM_SET_VAPIC_ADDR: {
1846 struct kvm_vapic_addr va;
1847
1848 r = -EINVAL;
1849 if (!irqchip_in_kernel(vcpu->kvm))
1850 goto out;
1851 r = -EFAULT;
1852 if (copy_from_user(&va, argp, sizeof va))
1853 goto out;
1854 r = 0;
1855 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1856 break;
1857 }
890ca9ae
HY		 1858 case KVM_X86_SETUP_MCE: {
1859 u64 mcg_cap;
1860
1861 r = -EFAULT;
1862 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
1863 goto out;
1864 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
1865 break;
1866 }
1867 case KVM_X86_SET_MCE: {
1868 struct kvm_x86_mce mce;
1869
1870 r = -EFAULT;
1871 if (copy_from_user(&mce, argp, sizeof mce))
1872 goto out;
1873 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
1874 break;
1875 }
313a3dc7
CO		 1876 default:
1877 r = -EINVAL;
1878 }
1879out:
7a6ce84c 1880 kfree(lapic);
313a3dc7
CO		 1881 return r;
1882}
1883
1fe779f8
CO		 1884static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1885{
1886 int ret;
1887
1888 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1889 return -1;
1890 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1891 return ret;
1892}
1893
1894static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1895 u32 kvm_nr_mmu_pages)
1896{
1897 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1898 return -EINVAL;
1899
72dc67a6 1900 down_write(&kvm->slots_lock);
7c8a83b7 1901 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 1902
1903 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1904 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1905
7c8a83b7 1906 spin_unlock(&kvm->mmu_lock);
72dc67a6 1907 up_write(&kvm->slots_lock);
1fe779f8
CO		 1908 return 0;
1909}
1910
1911static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1912{
f05e70ac 1913 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1914}
1915
e9f85cde
ZX		 1916gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1917{
1918 int i;
1919 struct kvm_mem_alias *alias;
1920
d69fb81f
ZX		 1921 for (i = 0; i < kvm->arch.naliases; ++i) {
1922 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1923 if (gfn >= alias->base_gfn
1924 && gfn < alias->base_gfn + alias->npages)
1925 return alias->target_gfn + gfn - alias->base_gfn;
1926 }
1927 return gfn;
1928}
1929
1fe779f8
CO		 1930/*
1931 * Set a new alias region. Aliases map a portion of physical memory into
1932 * another portion. This is useful for memory windows, for example the PC
1933 * VGA region.
1934 */
1935static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1936 struct kvm_memory_alias *alias)
1937{
1938 int r, n;
1939 struct kvm_mem_alias *p;
1940
1941 r = -EINVAL;
1942 /* General sanity checks */
1943 if (alias->memory_size & (PAGE_SIZE - 1))
1944 goto out;
1945 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1946 goto out;
1947 if (alias->slot >= KVM_ALIAS_SLOTS)
1948 goto out;
1949 if (alias->guest_phys_addr + alias->memory_size
1950 < alias->guest_phys_addr)
1951 goto out;
1952 if (alias->target_phys_addr + alias->memory_size
1953 < alias->target_phys_addr)
1954 goto out;
1955
72dc67a6 1956 down_write(&kvm->slots_lock);
a1708ce8 1957 spin_lock(&kvm->mmu_lock);
1fe779f8 1958
d69fb81f 1959 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1960 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1961 p->npages = alias->memory_size >> PAGE_SHIFT;
1962 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1963
1964 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1965 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1966 break;
d69fb81f 1967 kvm->arch.naliases = n;
1fe779f8 1968
a1708ce8 1969 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1970 kvm_mmu_zap_all(kvm);
1971
72dc67a6 1972 up_write(&kvm->slots_lock);
1fe779f8
CO		 1973
1974 return 0;
1975
1976out:
1977 return r;
1978}
1979
1980static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1981{
1982 int r;
1983
1984 r = 0;
1985 switch (chip->chip_id) {
1986 case KVM_IRQCHIP_PIC_MASTER:
1987 memcpy(&chip->chip.pic,
1988 &pic_irqchip(kvm)->pics[0],
1989 sizeof(struct kvm_pic_state));
1990 break;
1991 case KVM_IRQCHIP_PIC_SLAVE:
1992 memcpy(&chip->chip.pic,
1993 &pic_irqchip(kvm)->pics[1],
1994 sizeof(struct kvm_pic_state));
1995 break;
1996 case KVM_IRQCHIP_IOAPIC:
1997 memcpy(&chip->chip.ioapic,
1998 ioapic_irqchip(kvm),
1999 sizeof(struct kvm_ioapic_state));
2000 break;
2001 default:
2002 r = -EINVAL;
2003 break;
2004 }
2005 return r;
2006}
2007
2008static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2009{
2010 int r;
2011
2012 r = 0;
2013 switch (chip->chip_id) {
2014 case KVM_IRQCHIP_PIC_MASTER:
894a9c55 2015 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2016 memcpy(&pic_irqchip(kvm)->pics[0],
2017 &chip->chip.pic,
2018 sizeof(struct kvm_pic_state));
894a9c55 2019 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2020 break;
2021 case KVM_IRQCHIP_PIC_SLAVE:
894a9c55 2022 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2023 memcpy(&pic_irqchip(kvm)->pics[1],
2024 &chip->chip.pic,
2025 sizeof(struct kvm_pic_state));
894a9c55 2026 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2027 break;
2028 case KVM_IRQCHIP_IOAPIC:
894a9c55 2029 mutex_lock(&kvm->irq_lock);
1fe779f8
CO		 2030 memcpy(ioapic_irqchip(kvm),
2031 &chip->chip.ioapic,
2032 sizeof(struct kvm_ioapic_state));
894a9c55 2033 mutex_unlock(&kvm->irq_lock);
1fe779f8
CO		 2034 break;
2035 default:
2036 r = -EINVAL;
2037 break;
2038 }
2039 kvm_pic_update_irq(pic_irqchip(kvm));
2040 return r;
2041}
2042
e0f63cb9
SY		 2043static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2044{
2045 int r = 0;
2046
894a9c55 2047 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2048 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2049 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2050 return r;
2051}
2052
2053static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2054{
2055 int r = 0;
2056
894a9c55 2057 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2058 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
2059 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
894a9c55 2060 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2061 return r;
2062}
2063
52d939a0
MT		 2064static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2065 struct kvm_reinject_control *control)
2066{
2067 if (!kvm->arch.vpit)
2068 return -ENXIO;
894a9c55 2069 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2070 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2071 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2072 return 0;
2073}
2074
5bb064dc
ZX		 2075/*
2076 * Get (and clear) the dirty memory log for a memory slot.
2077 */
2078int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2079 struct kvm_dirty_log *log)
2080{
2081 int r;
2082 int n;
2083 struct kvm_memory_slot *memslot;
2084 int is_dirty = 0;
2085
72dc67a6 2086 down_write(&kvm->slots_lock);
5bb064dc
ZX		 2087
2088 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2089 if (r)
2090 goto out;
2091
2092 /* If nothing is dirty, don't bother messing with page tables. */
2093 if (is_dirty) {
7c8a83b7 2094 spin_lock(&kvm->mmu_lock);
5bb064dc 2095 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2096 spin_unlock(&kvm->mmu_lock);
5bb064dc
ZX		 2097 kvm_flush_remote_tlbs(kvm);
2098 memslot = &kvm->memslots[log->slot];
2099 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2100 memset(memslot->dirty_bitmap, 0, n);
2101 }
2102 r = 0;
2103out:
72dc67a6 2104 up_write(&kvm->slots_lock);
5bb064dc
ZX		 2105 return r;
2106}
2107
1fe779f8
CO		 2108long kvm_arch_vm_ioctl(struct file *filp,
2109 unsigned int ioctl, unsigned long arg)
2110{
2111 struct kvm *kvm = filp->private_data;
2112 void __user *argp = (void __user *)arg;
2113 int r = -EINVAL;
f0d66275
DH		 2114 /*
2115 * This union makes it completely explicit to gcc-3.x
2116 * that these two variables' stack usage should be
2117 * combined, not added together.
2118 */
2119 union {
2120 struct kvm_pit_state ps;
2121 struct kvm_memory_alias alias;
c5ff41ce 2122 struct kvm_pit_config pit_config;
f0d66275 2123 } u;
1fe779f8
CO		 2124
2125 switch (ioctl) {
2126 case KVM_SET_TSS_ADDR:
2127 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2128 if (r < 0)
2129 goto out;
2130 break;
2131 case KVM_SET_MEMORY_REGION: {
2132 struct kvm_memory_region kvm_mem;
2133 struct kvm_userspace_memory_region kvm_userspace_mem;
2134
2135 r = -EFAULT;
2136 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2137 goto out;
2138 kvm_userspace_mem.slot = kvm_mem.slot;
2139 kvm_userspace_mem.flags = kvm_mem.flags;
2140 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2141 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2142 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2143 if (r)
2144 goto out;
2145 break;
2146 }
2147 case KVM_SET_NR_MMU_PAGES:
2148 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2149 if (r)
2150 goto out;
2151 break;
2152 case KVM_GET_NR_MMU_PAGES:
2153 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2154 break;
f0d66275 2155 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2156 r = -EFAULT;
f0d66275 2157 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2158 goto out;
f0d66275 2159 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2160 if (r)
2161 goto out;
2162 break;
1fe779f8
CO		 2163 case KVM_CREATE_IRQCHIP:
2164 r = -ENOMEM;
d7deeeb0
ZX		 2165 kvm->arch.vpic = kvm_create_pic(kvm);
2166 if (kvm->arch.vpic) {
1fe779f8
CO		 2167 r = kvm_ioapic_init(kvm);
2168 if (r) {
d7deeeb0
ZX		 2169 kfree(kvm->arch.vpic);
2170 kvm->arch.vpic = NULL;
1fe779f8
CO		 2171 goto out;
2172 }
2173 } else
2174 goto out;
399ec807
AK		 2175 r = kvm_setup_default_irq_routing(kvm);
2176 if (r) {
2177 kfree(kvm->arch.vpic);
2178 kfree(kvm->arch.vioapic);
2179 goto out;
2180 }
1fe779f8 2181 break;
7837699f 2182 case KVM_CREATE_PIT:
c5ff41ce
JK		 2183 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2184 goto create_pit;
2185 case KVM_CREATE_PIT2:
2186 r = -EFAULT;
2187 if (copy_from_user(&u.pit_config, argp,
2188 sizeof(struct kvm_pit_config)))
2189 goto out;
2190 create_pit:
108b5669 2191 down_write(&kvm->slots_lock);
269e05e4
AK		 2192 r = -EEXIST;
2193 if (kvm->arch.vpit)
2194 goto create_pit_unlock;
7837699f 2195 r = -ENOMEM;
c5ff41ce 2196 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2197 if (kvm->arch.vpit)
2198 r = 0;
269e05e4 2199 create_pit_unlock:
108b5669 2200 up_write(&kvm->slots_lock);
7837699f 2201 break;
4925663a 2202 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2203 case KVM_IRQ_LINE: {
2204 struct kvm_irq_level irq_event;
2205
2206 r = -EFAULT;
2207 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2208 goto out;
2209 if (irqchip_in_kernel(kvm)) {
4925663a 2210 __s32 status;
fa40a821 2211 mutex_lock(&kvm->irq_lock);
4925663a
GN		 2212 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2213 irq_event.irq, irq_event.level);
fa40a821 2214 mutex_unlock(&kvm->irq_lock);
4925663a
GN		 2215 if (ioctl == KVM_IRQ_LINE_STATUS) {
2216 irq_event.status = status;
2217 if (copy_to_user(argp, &irq_event,
2218 sizeof irq_event))
2219 goto out;
2220 }
1fe779f8
CO		 2221 r = 0;
2222 }
2223 break;
2224 }
2225 case KVM_GET_IRQCHIP: {
2226 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2227 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2228
f0d66275
DH		 2229 r = -ENOMEM;
2230 if (!chip)
1fe779f8 2231 goto out;
f0d66275
DH		 2232 r = -EFAULT;
2233 if (copy_from_user(chip, argp, sizeof *chip))
2234 goto get_irqchip_out;
1fe779f8
CO		 2235 r = -ENXIO;
2236 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2237 goto get_irqchip_out;
2238 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2239 if (r)
f0d66275 2240 goto get_irqchip_out;
1fe779f8 2241 r = -EFAULT;
f0d66275
DH		 2242 if (copy_to_user(argp, chip, sizeof *chip))
2243 goto get_irqchip_out;
1fe779f8 2244 r = 0;
f0d66275
DH		 2245 get_irqchip_out:
2246 kfree(chip);
2247 if (r)
2248 goto out;
1fe779f8
CO		 2249 break;
2250 }
2251 case KVM_SET_IRQCHIP: {
2252 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2253 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2254
f0d66275
DH		 2255 r = -ENOMEM;
2256 if (!chip)
1fe779f8 2257 goto out;
f0d66275
DH		 2258 r = -EFAULT;
2259 if (copy_from_user(chip, argp, sizeof *chip))
2260 goto set_irqchip_out;
1fe779f8
CO		 2261 r = -ENXIO;
2262 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2263 goto set_irqchip_out;
2264 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2265 if (r)
f0d66275 2266 goto set_irqchip_out;
1fe779f8 2267 r = 0;
f0d66275
DH		 2268 set_irqchip_out:
2269 kfree(chip);
2270 if (r)
2271 goto out;
1fe779f8
CO		 2272 break;
2273 }
e0f63cb9 2274 case KVM_GET_PIT: {
e0f63cb9 2275 r = -EFAULT;
f0d66275 2276 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2277 goto out;
2278 r = -ENXIO;
2279 if (!kvm->arch.vpit)
2280 goto out;
f0d66275 2281 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2282 if (r)
2283 goto out;
2284 r = -EFAULT;
f0d66275 2285 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2286 goto out;
2287 r = 0;
2288 break;
2289 }
2290 case KVM_SET_PIT: {
e0f63cb9 2291 r = -EFAULT;
f0d66275 2292 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2293 goto out;
2294 r = -ENXIO;
2295 if (!kvm->arch.vpit)
2296 goto out;
f0d66275 2297 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2298 if (r)
2299 goto out;
2300 r = 0;
2301 break;
2302 }
52d939a0
MT		 2303 case KVM_REINJECT_CONTROL: {
2304 struct kvm_reinject_control control;
2305 r = -EFAULT;
2306 if (copy_from_user(&control, argp, sizeof(control)))
2307 goto out;
2308 r = kvm_vm_ioctl_reinject(kvm, &control);
2309 if (r)
2310 goto out;
2311 r = 0;
2312 break;
2313 }
1fe779f8
CO		 2314 default:
2315 ;
2316 }
2317out:
2318 return r;
2319}
2320
a16b043c 2321static void kvm_init_msr_list(void)
043405e1
CO		 2322{
2323 u32 dummy[2];
2324 unsigned i, j;
2325
2326 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2327 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2328 continue;
2329 if (j < i)
2330 msrs_to_save[j] = msrs_to_save[i];
2331 j++;
2332 }
2333 num_msrs_to_save = j;
2334}
2335
bda9020e
MT		 2336static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2337 const void *v)
bbd9b64e 2338{
bda9020e
MT		 2339 if (vcpu->arch.apic &&
2340 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2341 return 0;
bbd9b64e 2342
bda9020e 2343 return kvm_io_bus_write(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2344}
2345
bda9020e 2346static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 2347{
bda9020e
MT		 2348 if (vcpu->arch.apic &&
2349 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2350 return 0;
bbd9b64e 2351
bda9020e 2352 return kvm_io_bus_read(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2353}
2354
cded19f3
HE		 2355static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2356 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2357{
2358 void *data = val;
10589a46 2359 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2360
2361 while (bytes) {
ad312c7c 2362 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2363 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2364 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2365 int ret;
2366
10589a46
MT		 2367 if (gpa == UNMAPPED_GVA) {
2368 r = X86EMUL_PROPAGATE_FAULT;
2369 goto out;
2370 }
77c2002e 2371 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2372 if (ret < 0) {
2373 r = X86EMUL_UNHANDLEABLE;
2374 goto out;
2375 }
bbd9b64e 2376
77c2002e
IE		 2377 bytes -= toread;
2378 data += toread;
2379 addr += toread;
bbd9b64e 2380 }
10589a46 2381out:
10589a46 2382 return r;
bbd9b64e 2383}
77c2002e 2384
cded19f3
HE		 2385static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2386 struct kvm_vcpu *vcpu)
77c2002e
IE		 2387{
2388 void *data = val;
2389 int r = X86EMUL_CONTINUE;
2390
2391 while (bytes) {
2392 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2393 unsigned offset = addr & (PAGE_SIZE-1);
2394 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2395 int ret;
2396
2397 if (gpa == UNMAPPED_GVA) {
2398 r = X86EMUL_PROPAGATE_FAULT;
2399 goto out;
2400 }
2401 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2402 if (ret < 0) {
2403 r = X86EMUL_UNHANDLEABLE;
2404 goto out;
2405 }
2406
2407 bytes -= towrite;
2408 data += towrite;
2409 addr += towrite;
2410 }
2411out:
2412 return r;
2413}
2414
bbd9b64e 2415
bbd9b64e
CO		 2416static int emulator_read_emulated(unsigned long addr,
2417 void *val,
2418 unsigned int bytes,
2419 struct kvm_vcpu *vcpu)
2420{
bbd9b64e
CO		 2421 gpa_t gpa;
2422
2423 if (vcpu->mmio_read_completed) {
2424 memcpy(val, vcpu->mmio_data, bytes);
2425 vcpu->mmio_read_completed = 0;
2426 return X86EMUL_CONTINUE;
2427 }
2428
ad312c7c 2429 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2430
2431 /* For APIC access vmexit */
2432 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2433 goto mmio;
2434
77c2002e
IE		 2435 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2436 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2437 return X86EMUL_CONTINUE;
2438 if (gpa == UNMAPPED_GVA)
2439 return X86EMUL_PROPAGATE_FAULT;
2440
2441mmio:
2442 /*
2443 * Is this MMIO handled locally?
2444 */
bda9020e 2445 if (!vcpu_mmio_read(vcpu, gpa, bytes, val))
bbd9b64e 2446 return X86EMUL_CONTINUE;
bbd9b64e
CO		 2447
2448 vcpu->mmio_needed = 1;
2449 vcpu->mmio_phys_addr = gpa;
2450 vcpu->mmio_size = bytes;
2451 vcpu->mmio_is_write = 0;
2452
2453 return X86EMUL_UNHANDLEABLE;
2454}
2455
3200f405 2456int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2457 const void *val, int bytes)
bbd9b64e
CO		 2458{
2459 int ret;
2460
2461 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2462 if (ret < 0)
bbd9b64e 2463 return 0;
ad218f85 2464 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2465 return 1;
2466}
2467
2468static int emulator_write_emulated_onepage(unsigned long addr,
2469 const void *val,
2470 unsigned int bytes,
2471 struct kvm_vcpu *vcpu)
2472{
10589a46
MT		 2473 gpa_t gpa;
2474
10589a46 2475 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2476
2477 if (gpa == UNMAPPED_GVA) {
c3c91fee 2478 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2479 return X86EMUL_PROPAGATE_FAULT;
2480 }
2481
2482 /* For APIC access vmexit */
2483 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2484 goto mmio;
2485
2486 if (emulator_write_phys(vcpu, gpa, val, bytes))
2487 return X86EMUL_CONTINUE;
2488
2489mmio:
2490 /*
2491 * Is this MMIO handled locally?
2492 */
bda9020e 2493 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 2494 return X86EMUL_CONTINUE;
bbd9b64e
CO		 2495
2496 vcpu->mmio_needed = 1;
2497 vcpu->mmio_phys_addr = gpa;
2498 vcpu->mmio_size = bytes;
2499 vcpu->mmio_is_write = 1;
2500 memcpy(vcpu->mmio_data, val, bytes);
2501
2502 return X86EMUL_CONTINUE;
2503}
2504
2505int emulator_write_emulated(unsigned long addr,
2506 const void *val,
2507 unsigned int bytes,
2508 struct kvm_vcpu *vcpu)
2509{
2510 /* Crossing a page boundary? */
2511 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2512 int rc, now;
2513
2514 now = -addr & ~PAGE_MASK;
2515 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2516 if (rc != X86EMUL_CONTINUE)
2517 return rc;
2518 addr += now;
2519 val += now;
2520 bytes -= now;
2521 }
2522 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2523}
2524EXPORT_SYMBOL_GPL(emulator_write_emulated);
2525
2526static int emulator_cmpxchg_emulated(unsigned long addr,
2527 const void *old,
2528 const void *new,
2529 unsigned int bytes,
2530 struct kvm_vcpu *vcpu)
2531{
2532 static int reported;
2533
2534 if (!reported) {
2535 reported = 1;
2536 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2537 }
2bacc55c
MT		 2538#ifndef CONFIG_X86_64
2539 /* guests cmpxchg8b have to be emulated atomically */
2540 if (bytes == 8) {
10589a46 2541 gpa_t gpa;
2bacc55c 2542 struct page *page;
c0b49b0d 2543 char *kaddr;
2bacc55c
MT		 2544 u64 val;
2545
10589a46
MT		 2546 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2547
2bacc55c
MT		 2548 if (gpa == UNMAPPED_GVA ||
2549 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2550 goto emul_write;
2551
2552 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2553 goto emul_write;
2554
2555 val = *(u64 *)new;
72dc67a6 2556
2bacc55c 2557 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2558
c0b49b0d
AM		 2559 kaddr = kmap_atomic(page, KM_USER0);
2560 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2561 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2562 kvm_release_page_dirty(page);
2563 }
3200f405 2564emul_write:
2bacc55c
MT		 2565#endif
2566
bbd9b64e
CO		 2567 return emulator_write_emulated(addr, new, bytes, vcpu);
2568}
2569
2570static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2571{
2572 return kvm_x86_ops->get_segment_base(vcpu, seg);
2573}
2574
2575int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2576{
a7052897 2577 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2578 return X86EMUL_CONTINUE;
2579}
2580
2581int emulate_clts(struct kvm_vcpu *vcpu)
2582{
ad312c7c 2583 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2584 return X86EMUL_CONTINUE;
2585}
2586
2587int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2588{
2589 struct kvm_vcpu *vcpu = ctxt->vcpu;
2590
2591 switch (dr) {
2592 case 0 ... 3:
2593 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2594 return X86EMUL_CONTINUE;
2595 default:
b8688d51 2596 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2597 return X86EMUL_UNHANDLEABLE;
2598 }
2599}
2600
2601int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2602{
2603 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2604 int exception;
2605
2606 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2607 if (exception) {
2608 /* FIXME: better handling */
2609 return X86EMUL_UNHANDLEABLE;
2610 }
2611 return X86EMUL_CONTINUE;
2612}
2613
2614void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2615{
bbd9b64e 2616 u8 opcodes[4];
5fdbf976 2617 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2618 unsigned long rip_linear;
2619
f76c710d 2620 if (!printk_ratelimit())
bbd9b64e
CO		 2621 return;
2622
25be4608
GC		 2623 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2624
77c2002e 2625 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2626
2627 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2628 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2629}
2630EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2631
14af3f3c 2632static struct x86_emulate_ops emulate_ops = {
77c2002e 2633 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2634 .read_emulated = emulator_read_emulated,
2635 .write_emulated = emulator_write_emulated,
2636 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2637};
2638
5fdbf976
MT		 2639static void cache_all_regs(struct kvm_vcpu *vcpu)
2640{
2641 kvm_register_read(vcpu, VCPU_REGS_RAX);
2642 kvm_register_read(vcpu, VCPU_REGS_RSP);
2643 kvm_register_read(vcpu, VCPU_REGS_RIP);
2644 vcpu->arch.regs_dirty = ~0;
2645}
2646
bbd9b64e
CO		 2647int emulate_instruction(struct kvm_vcpu *vcpu,
2648 struct kvm_run *run,
2649 unsigned long cr2,
2650 u16 error_code,
571008da 2651 int emulation_type)
bbd9b64e 2652{
310b5d30 2653 int r, shadow_mask;
571008da 2654 struct decode_cache *c;
bbd9b64e 2655
26eef70c 2656 kvm_clear_exception_queue(vcpu);
ad312c7c 2657 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2658 /*
2659 * TODO: fix x86_emulate.c to use guest_read/write_register
2660 * instead of direct ->regs accesses, can save hundred cycles
2661 * on Intel for instructions that don't read/change RSP, for
2662 * for example.
2663 */
2664 cache_all_regs(vcpu);
bbd9b64e
CO		 2665
2666 vcpu->mmio_is_write = 0;
ad312c7c 2667 vcpu->arch.pio.string = 0;
bbd9b64e 2668
571008da 2669 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2670 int cs_db, cs_l;
2671 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2672
ad312c7c
ZX		 2673 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2674 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2675 vcpu->arch.emulate_ctxt.mode =
2676 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2677 ? X86EMUL_MODE_REAL : cs_l
2678 ? X86EMUL_MODE_PROT64 : cs_db
2679 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2680
ad312c7c 2681 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 2682
0cb5762e
AP		 2683 /* Only allow emulation of specific instructions on #UD
2684 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 2685 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 2686 if (emulation_type & EMULTYPE_TRAP_UD) {
2687 if (!c->twobyte)
2688 return EMULATE_FAIL;
2689 switch (c->b) {
2690 case 0x01: /* VMMCALL */
2691 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2692 return EMULATE_FAIL;
2693 break;
2694 case 0x34: /* sysenter */
2695 case 0x35: /* sysexit */
2696 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2697 return EMULATE_FAIL;
2698 break;
2699 case 0x05: /* syscall */
2700 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2701 return EMULATE_FAIL;
2702 break;
2703 default:
2704 return EMULATE_FAIL;
2705 }
2706
2707 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
2708 return EMULATE_FAIL;
2709 }
571008da 2710
f2b5756b 2711 ++vcpu->stat.insn_emulation;
bbd9b64e 2712 if (r) {
f2b5756b 2713 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2714 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2715 return EMULATE_DONE;
2716 return EMULATE_FAIL;
2717 }
2718 }
2719
ba8afb6b
GN		 2720 if (emulation_type & EMULTYPE_SKIP) {
2721 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
2722 return EMULATE_DONE;
2723 }
2724
ad312c7c 2725 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 2726 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
2727
2728 if (r == 0)
2729 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 2730
ad312c7c 2731 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2732 return EMULATE_DO_MMIO;
2733
2734 if ((r || vcpu->mmio_is_write) && run) {
2735 run->exit_reason = KVM_EXIT_MMIO;
2736 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2737 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2738 run->mmio.len = vcpu->mmio_size;
2739 run->mmio.is_write = vcpu->mmio_is_write;
2740 }
2741
2742 if (r) {
2743 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2744 return EMULATE_DONE;
2745 if (!vcpu->mmio_needed) {
2746 kvm_report_emulation_failure(vcpu, "mmio");
2747 return EMULATE_FAIL;
2748 }
2749 return EMULATE_DO_MMIO;
2750 }
2751
ad312c7c 2752 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2753
2754 if (vcpu->mmio_is_write) {
2755 vcpu->mmio_needed = 0;
2756 return EMULATE_DO_MMIO;
2757 }
2758
2759 return EMULATE_DONE;
2760}
2761EXPORT_SYMBOL_GPL(emulate_instruction);
2762
de7d789a
CO		 2763static int pio_copy_data(struct kvm_vcpu *vcpu)
2764{
ad312c7c 2765 void *p = vcpu->arch.pio_data;
0f346074 2766 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2767 unsigned bytes;
0f346074 2768 int ret;
de7d789a 2769
ad312c7c
ZX		 2770 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2771 if (vcpu->arch.pio.in)
0f346074 2772 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2773 else
0f346074
IE		 2774 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2775 return ret;
de7d789a
CO		 2776}
2777
2778int complete_pio(struct kvm_vcpu *vcpu)
2779{
ad312c7c 2780 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2781 long delta;
2782 int r;
5fdbf976 2783 unsigned long val;
de7d789a
CO		 2784
2785 if (!io->string) {
5fdbf976
MT		 2786 if (io->in) {
2787 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2788 memcpy(&val, vcpu->arch.pio_data, io->size);
2789 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2790 }
de7d789a
CO		 2791 } else {
2792 if (io->in) {
2793 r = pio_copy_data(vcpu);
5fdbf976 2794 if (r)
de7d789a 2795 return r;
de7d789a
CO		 2796 }
2797
2798 delta = 1;
2799 if (io->rep) {
2800 delta *= io->cur_count;
2801 /*
2802 * The size of the register should really depend on
2803 * current address size.
2804 */
5fdbf976
MT		 2805 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2806 val -= delta;
2807 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2808 }
2809 if (io->down)
2810 delta = -delta;
2811 delta *= io->size;
5fdbf976
MT		 2812 if (io->in) {
2813 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2814 val += delta;
2815 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2816 } else {
2817 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2818 val += delta;
2819 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2820 }
de7d789a
CO		 2821 }
2822
de7d789a
CO		 2823 io->count -= io->cur_count;
2824 io->cur_count = 0;
2825
2826 return 0;
2827}
2828
bda9020e 2829static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 2830{
2831 /* TODO: String I/O for in kernel device */
bda9020e 2832 int r;
de7d789a 2833
ad312c7c 2834 if (vcpu->arch.pio.in)
bda9020e
MT		 2835 r = kvm_io_bus_read(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2836 vcpu->arch.pio.size, pd);
de7d789a 2837 else
bda9020e
MT		 2838 r = kvm_io_bus_write(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2839 vcpu->arch.pio.size, pd);
2840 return r;
de7d789a
CO		 2841}
2842
bda9020e 2843static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 2844{
ad312c7c
ZX		 2845 struct kvm_pio_request *io = &vcpu->arch.pio;
2846 void *pd = vcpu->arch.pio_data;
bda9020e 2847 int i, r = 0;
de7d789a 2848
de7d789a 2849 for (i = 0; i < io->cur_count; i++) {
bda9020e
MT		 2850 if (kvm_io_bus_write(&vcpu->kvm->pio_bus,
2851 io->port, io->size, pd)) {
2852 r = -EOPNOTSUPP;
2853 break;
2854 }
de7d789a
CO		 2855 pd += io->size;
2856 }
bda9020e 2857 return r;
de7d789a
CO		 2858}
2859
2860int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2861 int size, unsigned port)
2862{
5fdbf976 2863 unsigned long val;
de7d789a
CO		 2864
2865 vcpu->run->exit_reason = KVM_EXIT_IO;
2866 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2867 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2868 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2869 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2870 vcpu->run->io.port = vcpu->arch.pio.port = port;
2871 vcpu->arch.pio.in = in;
2872 vcpu->arch.pio.string = 0;
2873 vcpu->arch.pio.down = 0;
ad312c7c 2874 vcpu->arch.pio.rep = 0;
de7d789a 2875
229456fc
MT		 2876 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2877 size, 1);
2714d1d3 2878
5fdbf976
MT		 2879 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2880 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2881
bda9020e 2882 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 2883 complete_pio(vcpu);
2884 return 1;
2885 }
2886 return 0;
2887}
2888EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2889
2890int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2891 int size, unsigned long count, int down,
2892 gva_t address, int rep, unsigned port)
2893{
2894 unsigned now, in_page;
0f346074 2895 int ret = 0;
de7d789a
CO		 2896
2897 vcpu->run->exit_reason = KVM_EXIT_IO;
2898 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2899 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2900 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2901 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2902 vcpu->run->io.port = vcpu->arch.pio.port = port;
2903 vcpu->arch.pio.in = in;
2904 vcpu->arch.pio.string = 1;
2905 vcpu->arch.pio.down = down;
ad312c7c 2906 vcpu->arch.pio.rep = rep;
de7d789a 2907
229456fc
MT		 2908 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2909 size, count);
2714d1d3 2910
de7d789a
CO		 2911 if (!count) {
2912 kvm_x86_ops->skip_emulated_instruction(vcpu);
2913 return 1;
2914 }
2915
2916 if (!down)
2917 in_page = PAGE_SIZE - offset_in_page(address);
2918 else
2919 in_page = offset_in_page(address) + size;
2920 now = min(count, (unsigned long)in_page / size);
0f346074 2921 if (!now)
de7d789a 2922 now = 1;
de7d789a
CO		 2923 if (down) {
2924 /*
2925 * String I/O in reverse. Yuck. Kill the guest, fix later.
2926 */
2927 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2928 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2929 return 1;
2930 }
2931 vcpu->run->io.count = now;
ad312c7c 2932 vcpu->arch.pio.cur_count = now;
de7d789a 2933
ad312c7c 2934 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2935 kvm_x86_ops->skip_emulated_instruction(vcpu);
2936
0f346074 2937 vcpu->arch.pio.guest_gva = address;
de7d789a 2938
ad312c7c 2939 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2940 /* string PIO write */
2941 ret = pio_copy_data(vcpu);
0f346074
IE		 2942 if (ret == X86EMUL_PROPAGATE_FAULT) {
2943 kvm_inject_gp(vcpu, 0);
2944 return 1;
2945 }
bda9020e 2946 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 2947 complete_pio(vcpu);
ad312c7c 2948 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2949 ret = 1;
2950 }
bda9020e
MT		 2951 }
2952 /* no string PIO read support yet */
de7d789a
CO		 2953
2954 return ret;
2955}
2956EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2957
c8076604
GH		 2958static void bounce_off(void *info)
2959{
2960 /* nothing */
2961}
2962
2963static unsigned int ref_freq;
2964static unsigned long tsc_khz_ref;
2965
2966static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
2967 void *data)
2968{
2969 struct cpufreq_freqs *freq = data;
2970 struct kvm *kvm;
2971 struct kvm_vcpu *vcpu;
2972 int i, send_ipi = 0;
2973
2974 if (!ref_freq)
2975 ref_freq = freq->old;
2976
2977 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
2978 return 0;
2979 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
2980 return 0;
2981 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
2982
2983 spin_lock(&kvm_lock);
2984 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 2985 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 2986 if (vcpu->cpu != freq->cpu)
2987 continue;
2988 if (!kvm_request_guest_time_update(vcpu))
2989 continue;
2990 if (vcpu->cpu != smp_processor_id())
2991 send_ipi++;
2992 }
2993 }
2994 spin_unlock(&kvm_lock);
2995
2996 if (freq->old < freq->new && send_ipi) {
2997 /*
2998 * We upscale the frequency. Must make the guest
2999 * doesn't see old kvmclock values while running with
3000 * the new frequency, otherwise we risk the guest sees
3001 * time go backwards.
3002 *
3003 * In case we update the frequency for another cpu
3004 * (which might be in guest context) send an interrupt
3005 * to kick the cpu out of guest context. Next time
3006 * guest context is entered kvmclock will be updated,
3007 * so the guest will not see stale values.
3008 */
3009 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3010 }
3011 return 0;
3012}
3013
3014static struct notifier_block kvmclock_cpufreq_notifier_block = {
3015 .notifier_call = kvmclock_cpufreq_notifier
3016};
3017
f8c16bba 3018int kvm_arch_init(void *opaque)
043405e1 3019{
c8076604 3020 int r, cpu;
f8c16bba
ZX		 3021 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3022
f8c16bba
ZX		 3023 if (kvm_x86_ops) {
3024 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3025 r = -EEXIST;
3026 goto out;
f8c16bba
ZX		 3027 }
3028
3029 if (!ops->cpu_has_kvm_support()) {
3030 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3031 r = -EOPNOTSUPP;
3032 goto out;
f8c16bba
ZX		 3033 }
3034 if (ops->disabled_by_bios()) {
3035 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3036 r = -EOPNOTSUPP;
3037 goto out;
f8c16bba
ZX		 3038 }
3039
97db56ce
AK		 3040 r = kvm_mmu_module_init();
3041 if (r)
3042 goto out;
3043
3044 kvm_init_msr_list();
3045
f8c16bba 3046 kvm_x86_ops = ops;
56c6d28a 3047 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3048 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3049 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3050 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604
GH		 3051
3052 for_each_possible_cpu(cpu)
3053 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
3054 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
3055 tsc_khz_ref = tsc_khz;
3056 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3057 CPUFREQ_TRANSITION_NOTIFIER);
3058 }
3059
f8c16bba 3060 return 0;
56c6d28a
ZX		 3061
3062out:
56c6d28a 3063 return r;
043405e1 3064}
8776e519 3065
f8c16bba
ZX		 3066void kvm_arch_exit(void)
3067{
888d256e
JK		 3068 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3069 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3070 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3071 kvm_x86_ops = NULL;
56c6d28a
ZX		 3072 kvm_mmu_module_exit();
3073}
f8c16bba 3074
8776e519
HB		 3075int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3076{
3077 ++vcpu->stat.halt_exits;
3078 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3079 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3080 return 1;
3081 } else {
3082 vcpu->run->exit_reason = KVM_EXIT_HLT;
3083 return 0;
3084 }
3085}
3086EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3087
2f333bcb
MT		 3088static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3089 unsigned long a1)
3090{
3091 if (is_long_mode(vcpu))
3092 return a0;
3093 else
3094 return a0 | ((gpa_t)a1 << 32);
3095}
3096
8776e519
HB		 3097int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3098{
3099 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3100 int r = 1;
8776e519 3101
5fdbf976
MT		 3102 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3103 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3104 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3105 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3106 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3107
229456fc 3108 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3109
8776e519
HB		 3110 if (!is_long_mode(vcpu)) {
3111 nr &= 0xFFFFFFFF;
3112 a0 &= 0xFFFFFFFF;
3113 a1 &= 0xFFFFFFFF;
3114 a2 &= 0xFFFFFFFF;
3115 a3 &= 0xFFFFFFFF;
3116 }
3117
3118 switch (nr) {
b93463aa
AK		 3119 case KVM_HC_VAPIC_POLL_IRQ:
3120 ret = 0;
3121 break;
2f333bcb
MT		 3122 case KVM_HC_MMU_OP:
3123 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3124 break;
8776e519
HB		 3125 default:
3126 ret = -KVM_ENOSYS;
3127 break;
3128 }
5fdbf976 3129 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3130 ++vcpu->stat.hypercalls;
2f333bcb 3131 return r;
8776e519
HB		 3132}
3133EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3134
3135int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3136{
3137 char instruction[3];
3138 int ret = 0;
5fdbf976 3139 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3140
8776e519
HB		 3141
3142 /*
3143 * Blow out the MMU to ensure that no other VCPU has an active mapping
3144 * to ensure that the updated hypercall appears atomically across all
3145 * VCPUs.
3146 */
3147 kvm_mmu_zap_all(vcpu->kvm);
3148
8776e519 3149 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 3150 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 3151 != X86EMUL_CONTINUE)
3152 ret = -EFAULT;
3153
8776e519
HB		 3154 return ret;
3155}
3156
3157static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3158{
3159 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3160}
3161
3162void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3163{
3164 struct descriptor_table dt = { limit, base };
3165
3166 kvm_x86_ops->set_gdt(vcpu, &dt);
3167}
3168
3169void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3170{
3171 struct descriptor_table dt = { limit, base };
3172
3173 kvm_x86_ops->set_idt(vcpu, &dt);
3174}
3175
3176void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3177 unsigned long *rflags)
3178{
2d3ad1f4 3179 kvm_lmsw(vcpu, msw);
8776e519
HB		 3180 *rflags = kvm_x86_ops->get_rflags(vcpu);
3181}
3182
3183unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3184{
54e445ca
JR		 3185 unsigned long value;
3186
8776e519
HB		 3187 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3188 switch (cr) {
3189 case 0:
54e445ca
JR		 3190 value = vcpu->arch.cr0;
3191 break;
8776e519 3192 case 2:
54e445ca
JR		 3193 value = vcpu->arch.cr2;
3194 break;
8776e519 3195 case 3:
54e445ca
JR		 3196 value = vcpu->arch.cr3;
3197 break;
8776e519 3198 case 4:
54e445ca
JR		 3199 value = vcpu->arch.cr4;
3200 break;
152ff9be 3201 case 8:
54e445ca
JR		 3202 value = kvm_get_cr8(vcpu);
3203 break;
8776e519 3204 default:
b8688d51 3205 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3206 return 0;
3207 }
54e445ca
JR		 3208
3209 return value;
8776e519
HB		 3210}
3211
3212void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3213 unsigned long *rflags)
3214{
3215 switch (cr) {
3216 case 0:
2d3ad1f4 3217 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 3218 *rflags = kvm_x86_ops->get_rflags(vcpu);
3219 break;
3220 case 2:
ad312c7c 3221 vcpu->arch.cr2 = val;
8776e519
HB		 3222 break;
3223 case 3:
2d3ad1f4 3224 kvm_set_cr3(vcpu, val);
8776e519
HB		 3225 break;
3226 case 4:
2d3ad1f4 3227 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 3228 break;
152ff9be 3229 case 8:
2d3ad1f4 3230 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 3231 break;
8776e519 3232 default:
b8688d51 3233 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3234 }
3235}
3236
07716717
DK		 3237static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3238{
ad312c7c
ZX		 3239 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3240 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 3241
3242 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3243 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 3244 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 3245 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 3246 if (ej->function == e->function) {
3247 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3248 return j;
3249 }
3250 }
3251 return 0; /* silence gcc, even though control never reaches here */
3252}
3253
3254/* find an entry with matching function, matching index (if needed), and that
3255 * should be read next (if it's stateful) */
3256static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3257 u32 function, u32 index)
3258{
3259 if (e->function != function)
3260 return 0;
3261 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3262 return 0;
3263 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3264 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3265 return 0;
3266 return 1;
3267}
3268
d8017474
AG		 3269struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3270 u32 function, u32 index)
8776e519
HB		 3271{
3272 int i;
d8017474 3273 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3274
ad312c7c 3275 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3276 struct kvm_cpuid_entry2 *e;
3277
ad312c7c 3278 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3279 if (is_matching_cpuid_entry(e, function, index)) {
3280 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3281 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3282 best = e;
3283 break;
3284 }
3285 /*
3286 * Both basic or both extended?
3287 */
3288 if (((e->function ^ function) & 0x80000000) == 0)
3289 if (!best || e->function > best->function)
3290 best = e;
3291 }
d8017474
AG		 3292 return best;
3293}
3294
82725b20
DE		 3295int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3296{
3297 struct kvm_cpuid_entry2 *best;
3298
3299 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3300 if (best)
3301 return best->eax & 0xff;
3302 return 36;
3303}
3304
d8017474
AG		 3305void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3306{
3307 u32 function, index;
3308 struct kvm_cpuid_entry2 *best;
3309
3310 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3311 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3312 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3313 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3314 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3315 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3316 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3317 if (best) {
5fdbf976
MT		 3318 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3319 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3320 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3321 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3322 }
8776e519 3323 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 3324 trace_kvm_cpuid(function,
3325 kvm_register_read(vcpu, VCPU_REGS_RAX),
3326 kvm_register_read(vcpu, VCPU_REGS_RBX),
3327 kvm_register_read(vcpu, VCPU_REGS_RCX),
3328 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 3329}
3330EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3331
b6c7a5dc
HB		 3332/*
3333 * Check if userspace requested an interrupt window, and that the
3334 * interrupt window is open.
3335 *
3336 * No need to exit to userspace if we already have an interrupt queued.
3337 */
3338static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3339 struct kvm_run *kvm_run)
3340{
8061823a 3341 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
b6c7a5dc 3342 kvm_run->request_interrupt_window &&
5df56646 3343 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 3344}
3345
3346static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3347 struct kvm_run *kvm_run)
3348{
3349 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3350 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3351 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3352 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3353 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3354 else
b6c7a5dc 3355 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 3356 kvm_arch_interrupt_allowed(vcpu) &&
3357 !kvm_cpu_has_interrupt(vcpu) &&
3358 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 3359}
3360
b93463aa
AK		 3361static void vapic_enter(struct kvm_vcpu *vcpu)
3362{
3363 struct kvm_lapic *apic = vcpu->arch.apic;
3364 struct page *page;
3365
3366 if (!apic || !apic->vapic_addr)
3367 return;
3368
3369 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3370
3371 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3372}
3373
3374static void vapic_exit(struct kvm_vcpu *vcpu)
3375{
3376 struct kvm_lapic *apic = vcpu->arch.apic;
3377
3378 if (!apic || !apic->vapic_addr)
3379 return;
3380
f8b78fa3 3381 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3382 kvm_release_page_dirty(apic->vapic_page);
3383 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3384 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3385}
3386
95ba8273
GN		 3387static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3388{
3389 int max_irr, tpr;
3390
3391 if (!kvm_x86_ops->update_cr8_intercept)
3392 return;
3393
8db3baa2
GN		 3394 if (!vcpu->arch.apic->vapic_addr)
3395 max_irr = kvm_lapic_find_highest_irr(vcpu);
3396 else
3397 max_irr = -1;
95ba8273
GN		 3398
3399 if (max_irr != -1)
3400 max_irr >>= 4;
3401
3402 tpr = kvm_lapic_get_cr8(vcpu);
3403
3404 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3405}
3406
6a8b1d13 3407static void inject_pending_irq(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
95ba8273
GN		 3408{
3409 /* try to reinject previous events if any */
3410 if (vcpu->arch.nmi_injected) {
3411 kvm_x86_ops->set_nmi(vcpu);
3412 return;
3413 }
3414
3415 if (vcpu->arch.interrupt.pending) {
66fd3f7f 3416 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3417 return;
3418 }
3419
3420 /* try to inject new event if pending */
3421 if (vcpu->arch.nmi_pending) {
3422 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3423 vcpu->arch.nmi_pending = false;
3424 vcpu->arch.nmi_injected = true;
3425 kvm_x86_ops->set_nmi(vcpu);
3426 }
3427 } else if (kvm_cpu_has_interrupt(vcpu)) {
3428 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 3429 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3430 false);
3431 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3432 }
3433 }
3434}
3435
d7690175 3436static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 3437{
3438 int r;
6a8b1d13
GN		 3439 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
3440 kvm_run->request_interrupt_window;
b6c7a5dc 3441
2e53d63a
MT		 3442 if (vcpu->requests)
3443 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3444 kvm_mmu_unload(vcpu);
3445
b6c7a5dc
HB		 3446 r = kvm_mmu_reload(vcpu);
3447 if (unlikely(r))
3448 goto out;
3449
2f52d58c
AK		 3450 if (vcpu->requests) {
3451 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3452 __kvm_migrate_timers(vcpu);
c8076604
GH		 3453 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3454 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3455 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3456 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3457 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3458 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3459 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3460 &vcpu->requests)) {
3461 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3462 r = 0;
3463 goto out;
3464 }
71c4dfaf
JR		 3465 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3466 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3467 r = 0;
3468 goto out;
3469 }
2f52d58c 3470 }
b93463aa 3471
b6c7a5dc
HB		 3472 preempt_disable();
3473
3474 kvm_x86_ops->prepare_guest_switch(vcpu);
3475 kvm_load_guest_fpu(vcpu);
3476
3477 local_irq_disable();
3478
32f88400
MT		 3479 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3480 smp_mb__after_clear_bit();
3481
d7690175 3482 if (vcpu->requests || need_resched() || signal_pending(current)) {
6c142801
AK		 3483 local_irq_enable();
3484 preempt_enable();
3485 r = 1;
3486 goto out;
3487 }
3488
ad312c7c 3489 if (vcpu->arch.exception.pending)
298101da 3490 __queue_exception(vcpu);
eb9774f0 3491 else
95ba8273 3492 inject_pending_irq(vcpu, kvm_run);
b6c7a5dc 3493
6a8b1d13
GN		 3494 /* enable NMI/IRQ window open exits if needed */
3495 if (vcpu->arch.nmi_pending)
3496 kvm_x86_ops->enable_nmi_window(vcpu);
3497 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3498 kvm_x86_ops->enable_irq_window(vcpu);
3499
95ba8273 3500 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 3501 update_cr8_intercept(vcpu);
3502 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 3503 }
b93463aa 3504
3200f405
MT		 3505 up_read(&vcpu->kvm->slots_lock);
3506
b6c7a5dc
HB		 3507 kvm_guest_enter();
3508
42dbaa5a
JK		 3509 get_debugreg(vcpu->arch.host_dr6, 6);
3510 get_debugreg(vcpu->arch.host_dr7, 7);
3511 if (unlikely(vcpu->arch.switch_db_regs)) {
3512 get_debugreg(vcpu->arch.host_db[0], 0);
3513 get_debugreg(vcpu->arch.host_db[1], 1);
3514 get_debugreg(vcpu->arch.host_db[2], 2);
3515 get_debugreg(vcpu->arch.host_db[3], 3);
3516
3517 set_debugreg(0, 7);
3518 set_debugreg(vcpu->arch.eff_db[0], 0);
3519 set_debugreg(vcpu->arch.eff_db[1], 1);
3520 set_debugreg(vcpu->arch.eff_db[2], 2);
3521 set_debugreg(vcpu->arch.eff_db[3], 3);
3522 }
b6c7a5dc 3523
229456fc 3524 trace_kvm_entry(vcpu->vcpu_id);
b6c7a5dc
HB		 3525 kvm_x86_ops->run(vcpu, kvm_run);
3526
42dbaa5a
JK		 3527 if (unlikely(vcpu->arch.switch_db_regs)) {
3528 set_debugreg(0, 7);
3529 set_debugreg(vcpu->arch.host_db[0], 0);
3530 set_debugreg(vcpu->arch.host_db[1], 1);
3531 set_debugreg(vcpu->arch.host_db[2], 2);
3532 set_debugreg(vcpu->arch.host_db[3], 3);
3533 }
3534 set_debugreg(vcpu->arch.host_dr6, 6);
3535 set_debugreg(vcpu->arch.host_dr7, 7);
3536
32f88400 3537 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 3538 local_irq_enable();
3539
3540 ++vcpu->stat.exits;
3541
3542 /*
3543 * We must have an instruction between local_irq_enable() and
3544 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3545 * the interrupt shadow. The stat.exits increment will do nicely.
3546 * But we need to prevent reordering, hence this barrier():
3547 */
3548 barrier();
3549
3550 kvm_guest_exit();
3551
3552 preempt_enable();
3553
3200f405
MT		 3554 down_read(&vcpu->kvm->slots_lock);
3555
b6c7a5dc
HB		 3556 /*
3557 * Profile KVM exit RIPs:
3558 */
3559 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3560 unsigned long rip = kvm_rip_read(vcpu);
3561 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3562 }
3563
298101da 3564
b93463aa
AK		 3565 kvm_lapic_sync_from_vapic(vcpu);
3566
b6c7a5dc 3567 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3568out:
3569 return r;
3570}
b6c7a5dc 3571
09cec754 3572
d7690175
MT		 3573static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3574{
3575 int r;
3576
3577 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3578 pr_debug("vcpu %d received sipi with vector # %x\n",
3579 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3580 kvm_lapic_reset(vcpu);
5f179287 3581 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3582 if (r)
3583 return r;
3584 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3585 }
3586
d7690175
MT		 3587 down_read(&vcpu->kvm->slots_lock);
3588 vapic_enter(vcpu);
3589
3590 r = 1;
3591 while (r > 0) {
af2152f5 3592 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3593 r = vcpu_enter_guest(vcpu, kvm_run);
3594 else {
3595 up_read(&vcpu->kvm->slots_lock);
3596 kvm_vcpu_block(vcpu);
3597 down_read(&vcpu->kvm->slots_lock);
3598 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 3599 {
3600 switch(vcpu->arch.mp_state) {
3601 case KVM_MP_STATE_HALTED:
d7690175 3602 vcpu->arch.mp_state =
09cec754
GN		 3603 KVM_MP_STATE_RUNNABLE;
3604 case KVM_MP_STATE_RUNNABLE:
3605 break;
3606 case KVM_MP_STATE_SIPI_RECEIVED:
3607 default:
3608 r = -EINTR;
3609 break;
3610 }
3611 }
d7690175
MT		 3612 }
3613
09cec754
GN		 3614 if (r <= 0)
3615 break;
3616
3617 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3618 if (kvm_cpu_has_pending_timer(vcpu))
3619 kvm_inject_pending_timer_irqs(vcpu);
3620
3621 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3622 r = -EINTR;
3623 kvm_run->exit_reason = KVM_EXIT_INTR;
3624 ++vcpu->stat.request_irq_exits;
3625 }
3626 if (signal_pending(current)) {
3627 r = -EINTR;
3628 kvm_run->exit_reason = KVM_EXIT_INTR;
3629 ++vcpu->stat.signal_exits;
3630 }
3631 if (need_resched()) {
3632 up_read(&vcpu->kvm->slots_lock);
3633 kvm_resched(vcpu);
3634 down_read(&vcpu->kvm->slots_lock);
d7690175 3635 }
b6c7a5dc
HB		 3636 }
3637
d7690175 3638 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3639 post_kvm_run_save(vcpu, kvm_run);
3640
b93463aa
AK		 3641 vapic_exit(vcpu);
3642
b6c7a5dc
HB		 3643 return r;
3644}
3645
3646int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3647{
3648 int r;
3649 sigset_t sigsaved;
3650
3651 vcpu_load(vcpu);
3652
ac9f6dc0
AK		 3653 if (vcpu->sigset_active)
3654 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3655
a4535290 3656 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3657 kvm_vcpu_block(vcpu);
d7690175 3658 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3659 r = -EAGAIN;
3660 goto out;
b6c7a5dc
HB		 3661 }
3662
b6c7a5dc
HB		 3663 /* re-sync apic's tpr */
3664 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3665 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3666
ad312c7c 3667 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3668 r = complete_pio(vcpu);
3669 if (r)
3670 goto out;
3671 }
3672#if CONFIG_HAS_IOMEM
3673 if (vcpu->mmio_needed) {
3674 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3675 vcpu->mmio_read_completed = 1;
3676 vcpu->mmio_needed = 0;
3200f405
MT		 3677
3678 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3679 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3680 vcpu->arch.mmio_fault_cr2, 0,
3681 EMULTYPE_NO_DECODE);
3200f405 3682 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3683 if (r == EMULATE_DO_MMIO) {
3684 /*
3685 * Read-modify-write. Back to userspace.
3686 */
3687 r = 0;
3688 goto out;
3689 }
3690 }
3691#endif
5fdbf976
MT		 3692 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3693 kvm_register_write(vcpu, VCPU_REGS_RAX,
3694 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3695
3696 r = __vcpu_run(vcpu, kvm_run);
3697
3698out:
3699 if (vcpu->sigset_active)
3700 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3701
3702 vcpu_put(vcpu);
3703 return r;
3704}
3705
3706int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3707{
3708 vcpu_load(vcpu);
3709
5fdbf976
MT		 3710 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3711 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3712 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3713 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3714 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3715 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3716 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3717 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3718#ifdef CONFIG_X86_64
5fdbf976
MT		 3719 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3720 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3721 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3722 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3723 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3724 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3725 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3726 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3727#endif
3728
5fdbf976 3729 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3730 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3731
3732 /*
3733 * Don't leak debug flags in case they were set for guest debugging
3734 */
d0bfb940 3735 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3736 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3737
3738 vcpu_put(vcpu);
3739
3740 return 0;
3741}
3742
3743int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3744{
3745 vcpu_load(vcpu);
3746
5fdbf976
MT		 3747 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3748 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3749 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3750 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3751 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3752 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3753 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3754 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3755#ifdef CONFIG_X86_64
5fdbf976
MT		 3756 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3757 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3758 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3759 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3760 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3761 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3762 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3763 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3764
b6c7a5dc
HB		 3765#endif
3766
5fdbf976 3767 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3768 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3769
b6c7a5dc 3770
b4f14abd
JK		 3771 vcpu->arch.exception.pending = false;
3772
b6c7a5dc
HB		 3773 vcpu_put(vcpu);
3774
3775 return 0;
3776}
3777
3e6e0aab
GT		 3778void kvm_get_segment(struct kvm_vcpu *vcpu,
3779 struct kvm_segment *var, int seg)
b6c7a5dc 3780{
14af3f3c 3781 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3782}
3783
3784void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3785{
3786 struct kvm_segment cs;
3787
3e6e0aab 3788 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3789 *db = cs.db;
3790 *l = cs.l;
3791}
3792EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3793
3794int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3795 struct kvm_sregs *sregs)
3796{
3797 struct descriptor_table dt;
b6c7a5dc
HB		 3798
3799 vcpu_load(vcpu);
3800
3e6e0aab
GT		 3801 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3802 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3803 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3804 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3805 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3806 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3807
3e6e0aab
GT		 3808 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3809 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3810
3811 kvm_x86_ops->get_idt(vcpu, &dt);
3812 sregs->idt.limit = dt.limit;
3813 sregs->idt.base = dt.base;
3814 kvm_x86_ops->get_gdt(vcpu, &dt);
3815 sregs->gdt.limit = dt.limit;
3816 sregs->gdt.base = dt.base;
3817
3818 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3819 sregs->cr0 = vcpu->arch.cr0;
3820 sregs->cr2 = vcpu->arch.cr2;
3821 sregs->cr3 = vcpu->arch.cr3;
3822 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3823 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3824 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3825 sregs->apic_base = kvm_get_apic_base(vcpu);
3826
923c61bb 3827 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 3828
36752c9b 3829 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 3830 set_bit(vcpu->arch.interrupt.nr,
3831 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 3832
b6c7a5dc
HB		 3833 vcpu_put(vcpu);
3834
3835 return 0;
3836}
3837
62d9f0db
MT		 3838int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3839 struct kvm_mp_state *mp_state)
3840{
3841 vcpu_load(vcpu);
3842 mp_state->mp_state = vcpu->arch.mp_state;
3843 vcpu_put(vcpu);
3844 return 0;
3845}
3846
3847int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3848 struct kvm_mp_state *mp_state)
3849{
3850 vcpu_load(vcpu);
3851 vcpu->arch.mp_state = mp_state->mp_state;
3852 vcpu_put(vcpu);
3853 return 0;
3854}
3855
3e6e0aab 3856static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3857 struct kvm_segment *var, int seg)
3858{
14af3f3c 3859 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3860}
3861
37817f29
IE		 3862static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3863 struct kvm_segment *kvm_desct)
3864{
3865 kvm_desct->base = seg_desc->base0;
3866 kvm_desct->base |= seg_desc->base1 << 16;
3867 kvm_desct->base |= seg_desc->base2 << 24;
3868 kvm_desct->limit = seg_desc->limit0;
3869 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3870 if (seg_desc->g) {
3871 kvm_desct->limit <<= 12;
3872 kvm_desct->limit |= 0xfff;
3873 }
37817f29
IE		 3874 kvm_desct->selector = selector;
3875 kvm_desct->type = seg_desc->type;
3876 kvm_desct->present = seg_desc->p;
3877 kvm_desct->dpl = seg_desc->dpl;
3878 kvm_desct->db = seg_desc->d;
3879 kvm_desct->s = seg_desc->s;
3880 kvm_desct->l = seg_desc->l;
3881 kvm_desct->g = seg_desc->g;
3882 kvm_desct->avl = seg_desc->avl;
3883 if (!selector)
3884 kvm_desct->unusable = 1;
3885 else
3886 kvm_desct->unusable = 0;
3887 kvm_desct->padding = 0;
3888}
3889
b8222ad2
AS		 3890static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3891 u16 selector,
3892 struct descriptor_table *dtable)
37817f29
IE		 3893{
3894 if (selector & 1 << 2) {
3895 struct kvm_segment kvm_seg;
3896
3e6e0aab 3897 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3898
3899 if (kvm_seg.unusable)
3900 dtable->limit = 0;
3901 else
3902 dtable->limit = kvm_seg.limit;
3903 dtable->base = kvm_seg.base;
3904 }
3905 else
3906 kvm_x86_ops->get_gdt(vcpu, dtable);
3907}
3908
3909/* allowed just for 8 bytes segments */
3910static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3911 struct desc_struct *seg_desc)
3912{
98899aa0 3913 gpa_t gpa;
37817f29
IE		 3914 struct descriptor_table dtable;
3915 u16 index = selector >> 3;
3916
b8222ad2 3917 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3918
3919 if (dtable.limit < index * 8 + 7) {
3920 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3921 return 1;
3922 }
98899aa0
MT		 3923 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3924 gpa += index * 8;
3925 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3926}
3927
3928/* allowed just for 8 bytes segments */
3929static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3930 struct desc_struct *seg_desc)
3931{
98899aa0 3932 gpa_t gpa;
37817f29
IE		 3933 struct descriptor_table dtable;
3934 u16 index = selector >> 3;
3935
b8222ad2 3936 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3937
3938 if (dtable.limit < index * 8 + 7)
3939 return 1;
98899aa0
MT		 3940 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3941 gpa += index * 8;
3942 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3943}
3944
3945static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3946 struct desc_struct *seg_desc)
3947{
3948 u32 base_addr;
3949
3950 base_addr = seg_desc->base0;
3951 base_addr |= (seg_desc->base1 << 16);
3952 base_addr |= (seg_desc->base2 << 24);
3953
98899aa0 3954 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3955}
3956
37817f29
IE		 3957static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3958{
3959 struct kvm_segment kvm_seg;
3960
3e6e0aab 3961 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3962 return kvm_seg.selector;
3963}
3964
3965static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3966 u16 selector,
3967 struct kvm_segment *kvm_seg)
3968{
3969 struct desc_struct seg_desc;
3970
3971 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3972 return 1;
3973 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3974 return 0;
3975}
3976
2259e3a7 3977static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 3978{
3979 struct kvm_segment segvar = {
3980 .base = selector << 4,
3981 .limit = 0xffff,
3982 .selector = selector,
3983 .type = 3,
3984 .present = 1,
3985 .dpl = 3,
3986 .db = 0,
3987 .s = 1,
3988 .l = 0,
3989 .g = 0,
3990 .avl = 0,
3991 .unusable = 0,
3992 };
3993 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
3994 return 0;
3995}
3996
3e6e0aab
GT		 3997int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3998 int type_bits, int seg)
37817f29
IE		 3999{
4000 struct kvm_segment kvm_seg;
4001
f4bbd9aa
AK		 4002 if (!(vcpu->arch.cr0 & X86_CR0_PE))
4003 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 4004 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4005 return 1;
4006 kvm_seg.type |= type_bits;
4007
4008 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4009 seg != VCPU_SREG_LDTR)
4010 if (!kvm_seg.s)
4011 kvm_seg.unusable = 1;
4012
3e6e0aab 4013 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4014 return 0;
4015}
4016
4017static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4018 struct tss_segment_32 *tss)
4019{
4020 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4021 tss->eip = kvm_rip_read(vcpu);
37817f29 4022 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4023 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4024 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4025 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4026 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4027 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4028 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4029 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4030 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4031 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4032 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4033 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4034 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4035 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4036 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4037 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4038}
4039
4040static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4041 struct tss_segment_32 *tss)
4042{
4043 kvm_set_cr3(vcpu, tss->cr3);
4044
5fdbf976 4045 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 4046 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
4047
5fdbf976
MT		 4048 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4049 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4050 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4051 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4052 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4053 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4054 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4055 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4056
3e6e0aab 4057 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 4058 return 1;
4059
3e6e0aab 4060 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4061 return 1;
4062
3e6e0aab 4063 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4064 return 1;
4065
3e6e0aab 4066 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4067 return 1;
4068
3e6e0aab 4069 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4070 return 1;
4071
3e6e0aab 4072 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 4073 return 1;
4074
3e6e0aab 4075 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 4076 return 1;
4077 return 0;
4078}
4079
4080static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4081 struct tss_segment_16 *tss)
4082{
5fdbf976 4083 tss->ip = kvm_rip_read(vcpu);
37817f29 4084 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4085 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4086 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4087 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4088 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4089 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4090 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4091 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4092 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4093
4094 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4095 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4096 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4097 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4098 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4099 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
4100}
4101
4102static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4103 struct tss_segment_16 *tss)
4104{
5fdbf976 4105 kvm_rip_write(vcpu, tss->ip);
37817f29 4106 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4107 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4108 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4109 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4110 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4111 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4112 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4113 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4114 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 4115
3e6e0aab 4116 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 4117 return 1;
4118
3e6e0aab 4119 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4120 return 1;
4121
3e6e0aab 4122 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4123 return 1;
4124
3e6e0aab 4125 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4126 return 1;
4127
3e6e0aab 4128 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4129 return 1;
4130 return 0;
4131}
4132
8b2cf73c 4133static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 4134 u16 old_tss_sel, u32 old_tss_base,
4135 struct desc_struct *nseg_desc)
37817f29
IE		 4136{
4137 struct tss_segment_16 tss_segment_16;
4138 int ret = 0;
4139
34198bf8
MT		 4140 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4141 sizeof tss_segment_16))
37817f29
IE		 4142 goto out;
4143
4144 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 4145
34198bf8
MT		 4146 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4147 sizeof tss_segment_16))
37817f29 4148 goto out;
34198bf8
MT		 4149
4150 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4151 &tss_segment_16, sizeof tss_segment_16))
4152 goto out;
4153
b237ac37
GN		 4154 if (old_tss_sel != 0xffff) {
4155 tss_segment_16.prev_task_link = old_tss_sel;
4156
4157 if (kvm_write_guest(vcpu->kvm,
4158 get_tss_base_addr(vcpu, nseg_desc),
4159 &tss_segment_16.prev_task_link,
4160 sizeof tss_segment_16.prev_task_link))
4161 goto out;
4162 }
4163
37817f29
IE		 4164 if (load_state_from_tss16(vcpu, &tss_segment_16))
4165 goto out;
4166
4167 ret = 1;
4168out:
4169 return ret;
4170}
4171
8b2cf73c 4172static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 4173 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 4174 struct desc_struct *nseg_desc)
4175{
4176 struct tss_segment_32 tss_segment_32;
4177 int ret = 0;
4178
34198bf8
MT		 4179 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4180 sizeof tss_segment_32))
37817f29
IE		 4181 goto out;
4182
4183 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 4184
34198bf8
MT		 4185 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4186 sizeof tss_segment_32))
4187 goto out;
4188
4189 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4190 &tss_segment_32, sizeof tss_segment_32))
37817f29 4191 goto out;
34198bf8 4192
b237ac37
GN		 4193 if (old_tss_sel != 0xffff) {
4194 tss_segment_32.prev_task_link = old_tss_sel;
4195
4196 if (kvm_write_guest(vcpu->kvm,
4197 get_tss_base_addr(vcpu, nseg_desc),
4198 &tss_segment_32.prev_task_link,
4199 sizeof tss_segment_32.prev_task_link))
4200 goto out;
4201 }
4202
37817f29
IE		 4203 if (load_state_from_tss32(vcpu, &tss_segment_32))
4204 goto out;
4205
4206 ret = 1;
4207out:
4208 return ret;
4209}
4210
4211int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4212{
4213 struct kvm_segment tr_seg;
4214 struct desc_struct cseg_desc;
4215 struct desc_struct nseg_desc;
4216 int ret = 0;
34198bf8
MT		 4217 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4218 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 4219
34198bf8 4220 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 4221
34198bf8
MT		 4222 /* FIXME: Handle errors. Failure to read either TSS or their
4223 * descriptors should generate a pagefault.
4224 */
37817f29
IE		 4225 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4226 goto out;
4227
34198bf8 4228 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 4229 goto out;
4230
37817f29
IE		 4231 if (reason != TASK_SWITCH_IRET) {
4232 int cpl;
4233
4234 cpl = kvm_x86_ops->get_cpl(vcpu);
4235 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4236 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4237 return 1;
4238 }
4239 }
4240
4241 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
4242 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4243 return 1;
4244 }
4245
4246 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4247 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4248 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4249 }
4250
4251 if (reason == TASK_SWITCH_IRET) {
4252 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4253 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
4254 }
4255
64a7ec06
GN		 4256 /* set back link to prev task only if NT bit is set in eflags
4257 note that old_tss_sel is not used afetr this point */
4258 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4259 old_tss_sel = 0xffff;
37817f29 4260
b237ac37
GN		 4261 /* set back link to prev task only if NT bit is set in eflags
4262 note that old_tss_sel is not used afetr this point */
4263 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4264 old_tss_sel = 0xffff;
4265
37817f29 4266 if (nseg_desc.type & 8)
b237ac37
GN		 4267 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4268 old_tss_base, &nseg_desc);
37817f29 4269 else
b237ac37
GN		 4270 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4271 old_tss_base, &nseg_desc);
37817f29
IE		 4272
4273 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
4274 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4275 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
4276 }
4277
4278 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4279 nseg_desc.type |= (1 << 1);
37817f29
IE		 4280 save_guest_segment_descriptor(vcpu, tss_selector,
4281 &nseg_desc);
4282 }
4283
4284 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4285 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4286 tr_seg.type = 11;
3e6e0aab 4287 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 4288out:
37817f29
IE		 4289 return ret;
4290}
4291EXPORT_SYMBOL_GPL(kvm_task_switch);
4292
b6c7a5dc
HB		 4293int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4294 struct kvm_sregs *sregs)
4295{
4296 int mmu_reset_needed = 0;
923c61bb 4297 int pending_vec, max_bits;
b6c7a5dc
HB		 4298 struct descriptor_table dt;
4299
4300 vcpu_load(vcpu);
4301
4302 dt.limit = sregs->idt.limit;
4303 dt.base = sregs->idt.base;
4304 kvm_x86_ops->set_idt(vcpu, &dt);
4305 dt.limit = sregs->gdt.limit;
4306 dt.base = sregs->gdt.base;
4307 kvm_x86_ops->set_gdt(vcpu, &dt);
4308
ad312c7c
ZX		 4309 vcpu->arch.cr2 = sregs->cr2;
4310 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
59839dff
MT		 4311
4312 down_read(&vcpu->kvm->slots_lock);
4313 if (gfn_to_memslot(vcpu->kvm, sregs->cr3 >> PAGE_SHIFT))
4314 vcpu->arch.cr3 = sregs->cr3;
4315 else
4316 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
4317 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc 4318
2d3ad1f4 4319 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4320
ad312c7c 4321 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 4322 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4323 kvm_set_apic_base(vcpu, sregs->apic_base);
4324
4325 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4326
ad312c7c 4327 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 4328 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4329 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4330
ad312c7c 4331 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 4332 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4333 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 4334 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 4335
4336 if (mmu_reset_needed)
4337 kvm_mmu_reset_context(vcpu);
4338
923c61bb
GN		 4339 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4340 pending_vec = find_first_bit(
4341 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4342 if (pending_vec < max_bits) {
66fd3f7f 4343 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4344 pr_debug("Set back pending irq %d\n", pending_vec);
4345 if (irqchip_in_kernel(vcpu->kvm))
4346 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4347 }
4348
3e6e0aab
GT		 4349 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4350 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4351 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4352 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4353 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4354 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4355
3e6e0aab
GT		 4356 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4357 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4358
9c3e4aab 4359 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4360 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab
MT		 4361 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4362 !(vcpu->arch.cr0 & X86_CR0_PE))
4363 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4364
b6c7a5dc
HB		 4365 vcpu_put(vcpu);
4366
4367 return 0;
4368}
4369
d0bfb940
JK		 4370int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4371 struct kvm_guest_debug *dbg)
b6c7a5dc 4372{
ae675ef0 4373 int i, r;
b6c7a5dc
HB		 4374
4375 vcpu_load(vcpu);
4376
ae675ef0
JK		 4377 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4378 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4379 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4380 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4381 vcpu->arch.switch_db_regs =
4382 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4383 } else {
4384 for (i = 0; i < KVM_NR_DB_REGS; i++)
4385 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4386 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4387 }
4388
b6c7a5dc
HB		 4389 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4390
d0bfb940
JK		 4391 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4392 kvm_queue_exception(vcpu, DB_VECTOR);
4393 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4394 kvm_queue_exception(vcpu, BP_VECTOR);
4395
b6c7a5dc
HB		 4396 vcpu_put(vcpu);
4397
4398 return r;
4399}
4400
d0752060
HB		 4401/*
4402 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4403 * we have asm/x86/processor.h
4404 */
4405struct fxsave {
4406 u16 cwd;
4407 u16 swd;
4408 u16 twd;
4409 u16 fop;
4410 u64 rip;
4411 u64 rdp;
4412 u32 mxcsr;
4413 u32 mxcsr_mask;
4414 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4415#ifdef CONFIG_X86_64
4416 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4417#else
4418 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4419#endif
4420};
4421
8b006791
ZX		 4422/*
4423 * Translate a guest virtual address to a guest physical address.
4424 */
4425int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4426 struct kvm_translation *tr)
4427{
4428 unsigned long vaddr = tr->linear_address;
4429 gpa_t gpa;
4430
4431 vcpu_load(vcpu);
72dc67a6 4432 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4433 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4434 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4435 tr->physical_address = gpa;
4436 tr->valid = gpa != UNMAPPED_GVA;
4437 tr->writeable = 1;
4438 tr->usermode = 0;
8b006791
ZX		 4439 vcpu_put(vcpu);
4440
4441 return 0;
4442}
4443
d0752060
HB		 4444int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4445{
ad312c7c 4446 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4447
4448 vcpu_load(vcpu);
4449
4450 memcpy(fpu->fpr, fxsave->st_space, 128);
4451 fpu->fcw = fxsave->cwd;
4452 fpu->fsw = fxsave->swd;
4453 fpu->ftwx = fxsave->twd;
4454 fpu->last_opcode = fxsave->fop;
4455 fpu->last_ip = fxsave->rip;
4456 fpu->last_dp = fxsave->rdp;
4457 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4458
4459 vcpu_put(vcpu);
4460
4461 return 0;
4462}
4463
4464int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4465{
ad312c7c 4466 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4467
4468 vcpu_load(vcpu);
4469
4470 memcpy(fxsave->st_space, fpu->fpr, 128);
4471 fxsave->cwd = fpu->fcw;
4472 fxsave->swd = fpu->fsw;
4473 fxsave->twd = fpu->ftwx;
4474 fxsave->fop = fpu->last_opcode;
4475 fxsave->rip = fpu->last_ip;
4476 fxsave->rdp = fpu->last_dp;
4477 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4478
4479 vcpu_put(vcpu);
4480
4481 return 0;
4482}
4483
4484void fx_init(struct kvm_vcpu *vcpu)
4485{
4486 unsigned after_mxcsr_mask;
4487
bc1a34f1
AA		 4488 /*
4489 * Touch the fpu the first time in non atomic context as if
4490 * this is the first fpu instruction the exception handler
4491 * will fire before the instruction returns and it'll have to
4492 * allocate ram with GFP_KERNEL.
4493 */
4494 if (!used_math())
d6e88aec 4495 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4496
d0752060
HB		 4497 /* Initialize guest FPU by resetting ours and saving into guest's */
4498 preempt_disable();
d6e88aec
AK		 4499 kvm_fx_save(&vcpu->arch.host_fx_image);
4500 kvm_fx_finit();
4501 kvm_fx_save(&vcpu->arch.guest_fx_image);
4502 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4503 preempt_enable();
4504
ad312c7c 4505 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4506 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4507 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4508 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4509 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4510}
4511EXPORT_SYMBOL_GPL(fx_init);
4512
4513void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4514{
4515 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4516 return;
4517
4518 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4519 kvm_fx_save(&vcpu->arch.host_fx_image);
4520 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4521}
4522EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4523
4524void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4525{
4526 if (!vcpu->guest_fpu_loaded)
4527 return;
4528
4529 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4530 kvm_fx_save(&vcpu->arch.guest_fx_image);
4531 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4532 ++vcpu->stat.fpu_reload;
d0752060
HB		 4533}
4534EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4535
4536void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4537{
7f1ea208
JR		 4538 if (vcpu->arch.time_page) {
4539 kvm_release_page_dirty(vcpu->arch.time_page);
4540 vcpu->arch.time_page = NULL;
4541 }
4542
e9b11c17
ZX		 4543 kvm_x86_ops->vcpu_free(vcpu);
4544}
4545
4546struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4547 unsigned int id)
4548{
26e5215f
AK		 4549 return kvm_x86_ops->vcpu_create(kvm, id);
4550}
e9b11c17 4551
26e5215f
AK		 4552int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4553{
4554 int r;
e9b11c17
ZX		 4555
4556 /* We do fxsave: this must be aligned. */
ad312c7c 4557 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4558
0bed3b56 4559 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4560 vcpu_load(vcpu);
4561 r = kvm_arch_vcpu_reset(vcpu);
4562 if (r == 0)
4563 r = kvm_mmu_setup(vcpu);
4564 vcpu_put(vcpu);
4565 if (r < 0)
4566 goto free_vcpu;
4567
26e5215f 4568 return 0;
e9b11c17
ZX		 4569free_vcpu:
4570 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4571 return r;
e9b11c17
ZX		 4572}
4573
d40ccc62 4574void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4575{
4576 vcpu_load(vcpu);
4577 kvm_mmu_unload(vcpu);
4578 vcpu_put(vcpu);
4579
4580 kvm_x86_ops->vcpu_free(vcpu);
4581}
4582
4583int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4584{
448fa4a9
JK		 4585 vcpu->arch.nmi_pending = false;
4586 vcpu->arch.nmi_injected = false;
4587
42dbaa5a
JK		 4588 vcpu->arch.switch_db_regs = 0;
4589 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4590 vcpu->arch.dr6 = DR6_FIXED_1;
4591 vcpu->arch.dr7 = DR7_FIXED_1;
4592
e9b11c17
ZX		 4593 return kvm_x86_ops->vcpu_reset(vcpu);
4594}
4595
4596void kvm_arch_hardware_enable(void *garbage)
4597{
4598 kvm_x86_ops->hardware_enable(garbage);
4599}
4600
4601void kvm_arch_hardware_disable(void *garbage)
4602{
4603 kvm_x86_ops->hardware_disable(garbage);
4604}
4605
4606int kvm_arch_hardware_setup(void)
4607{
4608 return kvm_x86_ops->hardware_setup();
4609}
4610
4611void kvm_arch_hardware_unsetup(void)
4612{
4613 kvm_x86_ops->hardware_unsetup();
4614}
4615
4616void kvm_arch_check_processor_compat(void *rtn)
4617{
4618 kvm_x86_ops->check_processor_compatibility(rtn);
4619}
4620
4621int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4622{
4623 struct page *page;
4624 struct kvm *kvm;
4625 int r;
4626
4627 BUG_ON(vcpu->kvm == NULL);
4628 kvm = vcpu->kvm;
4629
ad312c7c 4630 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 4631 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 4632 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4633 else
a4535290 4634 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4635
4636 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4637 if (!page) {
4638 r = -ENOMEM;
4639 goto fail;
4640 }
ad312c7c 4641 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4642
4643 r = kvm_mmu_create(vcpu);
4644 if (r < 0)
4645 goto fail_free_pio_data;
4646
4647 if (irqchip_in_kernel(kvm)) {
4648 r = kvm_create_lapic(vcpu);
4649 if (r < 0)
4650 goto fail_mmu_destroy;
4651 }
4652
890ca9ae
HY		 4653 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
4654 GFP_KERNEL);
4655 if (!vcpu->arch.mce_banks) {
4656 r = -ENOMEM;
4657 goto fail_mmu_destroy;
4658 }
4659 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
4660
e9b11c17
ZX		 4661 return 0;
4662
4663fail_mmu_destroy:
4664 kvm_mmu_destroy(vcpu);
4665fail_free_pio_data:
ad312c7c 4666 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4667fail:
4668 return r;
4669}
4670
4671void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4672{
4673 kvm_free_lapic(vcpu);
3200f405 4674 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4675 kvm_mmu_destroy(vcpu);
3200f405 4676 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4677 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4678}
d19a9cd2
ZX		 4679
4680struct kvm *kvm_arch_create_vm(void)
4681{
4682 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4683
4684 if (!kvm)
4685 return ERR_PTR(-ENOMEM);
4686
f05e70ac 4687 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 4688 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4689
5550af4d
SY		 4690 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4691 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4692
53f658b3
MT		 4693 rdtscll(kvm->arch.vm_init_tsc);
4694
d19a9cd2
ZX		 4695 return kvm;
4696}
4697
4698static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4699{
4700 vcpu_load(vcpu);
4701 kvm_mmu_unload(vcpu);
4702 vcpu_put(vcpu);
4703}
4704
4705static void kvm_free_vcpus(struct kvm *kvm)
4706{
4707 unsigned int i;
988a2cae 4708 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 4709
4710 /*
4711 * Unpin any mmu pages first.
4712 */
988a2cae
GN		 4713 kvm_for_each_vcpu(i, vcpu, kvm)
4714 kvm_unload_vcpu_mmu(vcpu);
4715 kvm_for_each_vcpu(i, vcpu, kvm)
4716 kvm_arch_vcpu_free(vcpu);
4717
4718 mutex_lock(&kvm->lock);
4719 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
4720 kvm->vcpus[i] = NULL;
d19a9cd2 4721
988a2cae
GN		 4722 atomic_set(&kvm->online_vcpus, 0);
4723 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 4724}
4725
ad8ba2cd
SY		 4726void kvm_arch_sync_events(struct kvm *kvm)
4727{
ba4cef31 4728 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4729}
4730
d19a9cd2
ZX		 4731void kvm_arch_destroy_vm(struct kvm *kvm)
4732{
6eb55818 4733 kvm_iommu_unmap_guest(kvm);
7837699f 4734 kvm_free_pit(kvm);
d7deeeb0
ZX		 4735 kfree(kvm->arch.vpic);
4736 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4737 kvm_free_vcpus(kvm);
4738 kvm_free_physmem(kvm);
3d45830c
AK		 4739 if (kvm->arch.apic_access_page)
4740 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4741 if (kvm->arch.ept_identity_pagetable)
4742 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4743 kfree(kvm);
4744}
0de10343
ZX		 4745
4746int kvm_arch_set_memory_region(struct kvm *kvm,
4747 struct kvm_userspace_memory_region *mem,
4748 struct kvm_memory_slot old,
4749 int user_alloc)
4750{
4751 int npages = mem->memory_size >> PAGE_SHIFT;
4752 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4753
4754 /*To keep backward compatibility with older userspace,
4755 *x86 needs to hanlde !user_alloc case.
4756 */
4757 if (!user_alloc) {
4758 if (npages && !old.rmap) {
604b38ac
AA		 4759 unsigned long userspace_addr;
4760
72dc67a6 4761 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4762 userspace_addr = do_mmap(NULL, 0,
4763 npages * PAGE_SIZE,
4764 PROT_READ | PROT_WRITE,
acee3c04 4765 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4766 0);
72dc67a6 4767 up_write(&current->mm->mmap_sem);
0de10343 4768
604b38ac
AA		 4769 if (IS_ERR((void *)userspace_addr))
4770 return PTR_ERR((void *)userspace_addr);
4771
4772 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4773 spin_lock(&kvm->mmu_lock);
4774 memslot->userspace_addr = userspace_addr;
4775 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4776 } else {
4777 if (!old.user_alloc && old.rmap) {
4778 int ret;
4779
72dc67a6 4780 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4781 ret = do_munmap(current->mm, old.userspace_addr,
4782 old.npages * PAGE_SIZE);
72dc67a6 4783 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4784 if (ret < 0)
4785 printk(KERN_WARNING
4786 "kvm_vm_ioctl_set_memory_region: "
4787 "failed to munmap memory\n");
4788 }
4789 }
4790 }
4791
7c8a83b7 4792 spin_lock(&kvm->mmu_lock);
f05e70ac 4793 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4794 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4795 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4796 }
4797
4798 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 4799 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4800 kvm_flush_remote_tlbs(kvm);
4801
4802 return 0;
4803}
1d737c8a 4804
34d4cb8f
MT		 4805void kvm_arch_flush_shadow(struct kvm *kvm)
4806{
4807 kvm_mmu_zap_all(kvm);
8986ecc0 4808 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 4809}
4810
1d737c8a
ZX		 4811int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4812{
a4535290 4813 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
0496fbb9
JK		 4814 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4815 || vcpu->arch.nmi_pending;
1d737c8a 4816}
5736199a 4817
5736199a
ZX		 4818void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4819{
32f88400
MT		 4820 int me;
4821 int cpu = vcpu->cpu;
5736199a
ZX		 4822
4823 if (waitqueue_active(&vcpu->wq)) {
4824 wake_up_interruptible(&vcpu->wq);
4825 ++vcpu->stat.halt_wakeup;
4826 }
32f88400
MT		 4827
4828 me = get_cpu();
4829 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
4830 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
4831 smp_send_reschedule(cpu);
e9571ed5 4832 put_cpu();
5736199a 4833}
78646121
GN		 4834
4835int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
4836{
4837 return kvm_x86_ops->interrupt_allowed(vcpu);
4838}
229456fc
MT		 4839
4840EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
4841EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
4842EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
4843EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
4844EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
kernel source for telekom puls (alcatel/mediatek)