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KVM: Add coalesced MMIO support (common part)
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Avi Kivity <avi@qumranet.com>
10 * Yaniv Kamay <yaniv@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16
edf88417 17#include <linux/kvm_host.h>
313a3dc7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
7837699f 20#include "i8254.h"
37817f29 21#include "tss.h"
313a3dc7 22
18068523 23#include <linux/clocksource.h>
313a3dc7
CO		 24#include <linux/kvm.h>
25#include <linux/fs.h>
26#include <linux/vmalloc.h>
5fb76f9b 27#include <linux/module.h>
0de10343 28#include <linux/mman.h>
2bacc55c 29#include <linux/highmem.h>
043405e1
CO		 30
31#include <asm/uaccess.h>
d825ed0a 32#include <asm/msr.h>
a5f61300 33#include <asm/desc.h>
043405e1 34
313a3dc7 35#define MAX_IO_MSRS 256
a03490ed
CO		 36#define CR0_RESERVED_BITS \
37 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
38 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
39 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
40#define CR4_RESERVED_BITS \
41 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
42 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
43 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
44 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
45
46#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
50a37eb4
JR		 47/* EFER defaults:
48 * - enable syscall per default because its emulated by KVM
49 * - enable LME and LMA per default on 64 bit KVM
50 */
51#ifdef CONFIG_X86_64
52static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
53#else
54static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
55#endif
313a3dc7 56
ba1389b7
AK		 57#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
58#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 59
674eea0f
AK		 60static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
61 struct kvm_cpuid_entry2 __user *entries);
62
97896d04
ZX		 63struct kvm_x86_ops *kvm_x86_ops;
64
417bc304 65struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 66 { "pf_fixed", VCPU_STAT(pf_fixed) },
67 { "pf_guest", VCPU_STAT(pf_guest) },
68 { "tlb_flush", VCPU_STAT(tlb_flush) },
69 { "invlpg", VCPU_STAT(invlpg) },
70 { "exits", VCPU_STAT(exits) },
71 { "io_exits", VCPU_STAT(io_exits) },
72 { "mmio_exits", VCPU_STAT(mmio_exits) },
73 { "signal_exits", VCPU_STAT(signal_exits) },
74 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 75 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 76 { "halt_exits", VCPU_STAT(halt_exits) },
77 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 78 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 79 { "request_irq", VCPU_STAT(request_irq_exits) },
80 { "irq_exits", VCPU_STAT(irq_exits) },
81 { "host_state_reload", VCPU_STAT(host_state_reload) },
82 { "efer_reload", VCPU_STAT(efer_reload) },
83 { "fpu_reload", VCPU_STAT(fpu_reload) },
84 { "insn_emulation", VCPU_STAT(insn_emulation) },
85 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
4cee5764
AK		 86 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
87 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
88 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
89 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
90 { "mmu_flooded", VM_STAT(mmu_flooded) },
91 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 92 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
0f74a24c 93 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 94 { "largepages", VM_STAT(lpages) },
417bc304
HB		 95 { NULL }
96};
97
98
5fb76f9b
CO		 99unsigned long segment_base(u16 selector)
100{
101 struct descriptor_table gdt;
a5f61300 102 struct desc_struct *d;
5fb76f9b
CO		 103 unsigned long table_base;
104 unsigned long v;
105
106 if (selector == 0)
107 return 0;
108
109 asm("sgdt %0" : "=m"(gdt));
110 table_base = gdt.base;
111
112 if (selector & 4) { /* from ldt */
113 u16 ldt_selector;
114
115 asm("sldt %0" : "=g"(ldt_selector));
116 table_base = segment_base(ldt_selector);
117 }
a5f61300
AK		 118 d = (struct desc_struct *)(table_base + (selector & ~7));
119 v = d->base0 | ((unsigned long)d->base1 << 16) |
120 ((unsigned long)d->base2 << 24);
5fb76f9b 121#ifdef CONFIG_X86_64
a5f61300
AK		 122 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
123 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 124#endif
125 return v;
126}
127EXPORT_SYMBOL_GPL(segment_base);
128
6866b83e
CO		 129u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
130{
131 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 132 return vcpu->arch.apic_base;
6866b83e 133 else
ad312c7c 134 return vcpu->arch.apic_base;
6866b83e
CO		 135}
136EXPORT_SYMBOL_GPL(kvm_get_apic_base);
137
138void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
139{
140 /* TODO: reserve bits check */
141 if (irqchip_in_kernel(vcpu->kvm))
142 kvm_lapic_set_base(vcpu, data);
143 else
ad312c7c 144 vcpu->arch.apic_base = data;
6866b83e
CO		 145}
146EXPORT_SYMBOL_GPL(kvm_set_apic_base);
147
298101da
AK		 148void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
149{
ad312c7c
ZX		 150 WARN_ON(vcpu->arch.exception.pending);
151 vcpu->arch.exception.pending = true;
152 vcpu->arch.exception.has_error_code = false;
153 vcpu->arch.exception.nr = nr;
298101da
AK		 154}
155EXPORT_SYMBOL_GPL(kvm_queue_exception);
156
c3c91fee
AK		 157void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
158 u32 error_code)
159{
160 ++vcpu->stat.pf_guest;
71c4dfaf
JR		 161 if (vcpu->arch.exception.pending) {
162 if (vcpu->arch.exception.nr == PF_VECTOR) {
163 printk(KERN_DEBUG "kvm: inject_page_fault:"
164 " double fault 0x%lx\n", addr);
165 vcpu->arch.exception.nr = DF_VECTOR;
166 vcpu->arch.exception.error_code = 0;
167 } else if (vcpu->arch.exception.nr == DF_VECTOR) {
168 /* triple fault -> shutdown */
169 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
170 }
c3c91fee
AK		 171 return;
172 }
ad312c7c 173 vcpu->arch.cr2 = addr;
c3c91fee
AK		 174 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
175}
176
3419ffc8
SY		 177void kvm_inject_nmi(struct kvm_vcpu *vcpu)
178{
179 vcpu->arch.nmi_pending = 1;
180}
181EXPORT_SYMBOL_GPL(kvm_inject_nmi);
182
298101da
AK		 183void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
184{
ad312c7c
ZX		 185 WARN_ON(vcpu->arch.exception.pending);
186 vcpu->arch.exception.pending = true;
187 vcpu->arch.exception.has_error_code = true;
188 vcpu->arch.exception.nr = nr;
189 vcpu->arch.exception.error_code = error_code;
298101da
AK		 190}
191EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
192
193static void __queue_exception(struct kvm_vcpu *vcpu)
194{
ad312c7c
ZX		 195 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
196 vcpu->arch.exception.has_error_code,
197 vcpu->arch.exception.error_code);
298101da
AK		 198}
199
a03490ed
CO		 200/*
201 * Load the pae pdptrs. Return true is they are all valid.
202 */
203int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
204{
205 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
206 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
207 int i;
208 int ret;
ad312c7c 209 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 210
a03490ed
CO		 211 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
212 offset * sizeof(u64), sizeof(pdpte));
213 if (ret < 0) {
214 ret = 0;
215 goto out;
216 }
217 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
218 if ((pdpte[i] & 1) && (pdpte[i] & 0xfffffff0000001e6ull)) {
219 ret = 0;
220 goto out;
221 }
222 }
223 ret = 1;
224
ad312c7c 225 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
a03490ed 226out:
a03490ed
CO		 227
228 return ret;
229}
cc4b6871 230EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 231
d835dfec
AK		 232static bool pdptrs_changed(struct kvm_vcpu *vcpu)
233{
ad312c7c 234 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 235 bool changed = true;
236 int r;
237
238 if (is_long_mode(vcpu) || !is_pae(vcpu))
239 return false;
240
ad312c7c 241 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 242 if (r < 0)
243 goto out;
ad312c7c 244 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 245out:
d835dfec
AK		 246
247 return changed;
248}
249
2d3ad1f4 250void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 251{
252 if (cr0 & CR0_RESERVED_BITS) {
253 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 254 cr0, vcpu->arch.cr0);
c1a5d4f9 255 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 256 return;
257 }
258
259 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
260 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 261 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 262 return;
263 }
264
265 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
266 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
267 "and a clear PE flag\n");
c1a5d4f9 268 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 269 return;
270 }
271
272 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
273#ifdef CONFIG_X86_64
ad312c7c 274 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 275 int cs_db, cs_l;
276
277 if (!is_pae(vcpu)) {
278 printk(KERN_DEBUG "set_cr0: #GP, start paging "
279 "in long mode while PAE is disabled\n");
c1a5d4f9 280 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 281 return;
282 }
283 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
284 if (cs_l) {
285 printk(KERN_DEBUG "set_cr0: #GP, start paging "
286 "in long mode while CS.L == 1\n");
c1a5d4f9 287 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 288 return;
289
290 }
291 } else
292#endif
ad312c7c 293 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 294 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
295 "reserved bits\n");
c1a5d4f9 296 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 297 return;
298 }
299
300 }
301
302 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 303 vcpu->arch.cr0 = cr0;
a03490ed 304
a03490ed 305 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 306 return;
307}
2d3ad1f4 308EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 309
2d3ad1f4 310void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 311{
2d3ad1f4 312 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
2714d1d3
FEL		 313 KVMTRACE_1D(LMSW, vcpu,
314 (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
315 handler);
a03490ed 316}
2d3ad1f4 317EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 318
2d3ad1f4 319void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed
CO		 320{
321 if (cr4 & CR4_RESERVED_BITS) {
322 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 323 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 324 return;
325 }
326
327 if (is_long_mode(vcpu)) {
328 if (!(cr4 & X86_CR4_PAE)) {
329 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
330 "in long mode\n");
c1a5d4f9 331 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 332 return;
333 }
334 } else if (is_paging(vcpu) && !is_pae(vcpu) && (cr4 & X86_CR4_PAE)
ad312c7c 335 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 336 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 337 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 338 return;
339 }
340
341 if (cr4 & X86_CR4_VMXE) {
342 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 343 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 344 return;
345 }
346 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 347 vcpu->arch.cr4 = cr4;
a03490ed 348 kvm_mmu_reset_context(vcpu);
a03490ed 349}
2d3ad1f4 350EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 351
2d3ad1f4 352void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 353{
ad312c7c 354 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
d835dfec
AK		 355 kvm_mmu_flush_tlb(vcpu);
356 return;
357 }
358
a03490ed
CO		 359 if (is_long_mode(vcpu)) {
360 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
361 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 362 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 363 return;
364 }
365 } else {
366 if (is_pae(vcpu)) {
367 if (cr3 & CR3_PAE_RESERVED_BITS) {
368 printk(KERN_DEBUG
369 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 370 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 371 return;
372 }
373 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
374 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
375 "reserved bits\n");
c1a5d4f9 376 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 377 return;
378 }
379 }
380 /*
381 * We don't check reserved bits in nonpae mode, because
382 * this isn't enforced, and VMware depends on this.
383 */
384 }
385
a03490ed
CO		 386 /*
387 * Does the new cr3 value map to physical memory? (Note, we
388 * catch an invalid cr3 even in real-mode, because it would
389 * cause trouble later on when we turn on paging anyway.)
390 *
391 * A real CPU would silently accept an invalid cr3 and would
392 * attempt to use it - with largely undefined (and often hard
393 * to debug) behavior on the guest side.
394 */
395 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 396 kvm_inject_gp(vcpu, 0);
a03490ed 397 else {
ad312c7c
ZX		 398 vcpu->arch.cr3 = cr3;
399 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 400 }
a03490ed 401}
2d3ad1f4 402EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 403
2d3ad1f4 404void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 405{
406 if (cr8 & CR8_RESERVED_BITS) {
407 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 408 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 409 return;
410 }
411 if (irqchip_in_kernel(vcpu->kvm))
412 kvm_lapic_set_tpr(vcpu, cr8);
413 else
ad312c7c 414 vcpu->arch.cr8 = cr8;
a03490ed 415}
2d3ad1f4 416EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 417
2d3ad1f4 418unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 419{
420 if (irqchip_in_kernel(vcpu->kvm))
421 return kvm_lapic_get_cr8(vcpu);
422 else
ad312c7c 423 return vcpu->arch.cr8;
a03490ed 424}
2d3ad1f4 425EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 426
043405e1
CO		 427/*
428 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
429 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
430 *
431 * This list is modified at module load time to reflect the
432 * capabilities of the host cpu.
433 */
434static u32 msrs_to_save[] = {
435 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
436 MSR_K6_STAR,
437#ifdef CONFIG_X86_64
438 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
439#endif
18068523 440 MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
847f0ad8 441 MSR_IA32_PERF_STATUS,
043405e1
CO		 442};
443
444static unsigned num_msrs_to_save;
445
446static u32 emulated_msrs[] = {
447 MSR_IA32_MISC_ENABLE,
448};
449
15c4a640
CO		 450static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
451{
f2b4b7dd 452 if (efer & efer_reserved_bits) {
15c4a640
CO		 453 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
454 efer);
c1a5d4f9 455 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 456 return;
457 }
458
459 if (is_paging(vcpu)
ad312c7c 460 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 461 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 462 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 463 return;
464 }
465
466 kvm_x86_ops->set_efer(vcpu, efer);
467
468 efer &= ~EFER_LMA;
ad312c7c 469 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 470
ad312c7c 471 vcpu->arch.shadow_efer = efer;
15c4a640
CO		 472}
473
f2b4b7dd
JR		 474void kvm_enable_efer_bits(u64 mask)
475{
476 efer_reserved_bits &= ~mask;
477}
478EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
479
480
15c4a640
CO		 481/*
482 * Writes msr value into into the appropriate "register".
483 * Returns 0 on success, non-0 otherwise.
484 * Assumes vcpu_load() was already called.
485 */
486int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
487{
488 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
489}
490
313a3dc7
CO		 491/*
492 * Adapt set_msr() to msr_io()'s calling convention
493 */
494static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
495{
496 return kvm_set_msr(vcpu, index, *data);
497}
498
18068523
GOC		 499static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
500{
501 static int version;
50d0a0f9
GH		 502 struct pvclock_wall_clock wc;
503 struct timespec now, sys, boot;
18068523
GOC		 504
505 if (!wall_clock)
506 return;
507
508 version++;
509
18068523
GOC		 510 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
511
50d0a0f9
GH		 512 /*
513 * The guest calculates current wall clock time by adding
514 * system time (updated by kvm_write_guest_time below) to the
515 * wall clock specified here. guest system time equals host
516 * system time for us, thus we must fill in host boot time here.
517 */
518 now = current_kernel_time();
519 ktime_get_ts(&sys);
520 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
521
522 wc.sec = boot.tv_sec;
523 wc.nsec = boot.tv_nsec;
524 wc.version = version;
18068523
GOC		 525
526 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
527
528 version++;
529 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 530}
531
50d0a0f9
GH		 532static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
533{
534 uint32_t quotient, remainder;
535
536 /* Don't try to replace with do_div(), this one calculates
537 * "(dividend << 32) / divisor" */
538 __asm__ ( "divl %4"
539 : "=a" (quotient), "=d" (remainder)
540 : "0" (0), "1" (dividend), "r" (divisor) );
541 return quotient;
542}
543
544static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
545{
546 uint64_t nsecs = 1000000000LL;
547 int32_t shift = 0;
548 uint64_t tps64;
549 uint32_t tps32;
550
551 tps64 = tsc_khz * 1000LL;
552 while (tps64 > nsecs*2) {
553 tps64 >>= 1;
554 shift--;
555 }
556
557 tps32 = (uint32_t)tps64;
558 while (tps32 <= (uint32_t)nsecs) {
559 tps32 <<= 1;
560 shift++;
561 }
562
563 hv_clock->tsc_shift = shift;
564 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
565
566 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
567 __FUNCTION__, tsc_khz, hv_clock->tsc_shift,
568 hv_clock->tsc_to_system_mul);
569}
570
18068523
GOC		 571static void kvm_write_guest_time(struct kvm_vcpu *v)
572{
573 struct timespec ts;
574 unsigned long flags;
575 struct kvm_vcpu_arch *vcpu = &v->arch;
576 void *shared_kaddr;
577
578 if ((!vcpu->time_page))
579 return;
580
50d0a0f9
GH		 581 if (unlikely(vcpu->hv_clock_tsc_khz != tsc_khz)) {
582 kvm_set_time_scale(tsc_khz, &vcpu->hv_clock);
583 vcpu->hv_clock_tsc_khz = tsc_khz;
584 }
585
18068523
GOC		 586 /* Keep irq disabled to prevent changes to the clock */
587 local_irq_save(flags);
588 kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
589 &vcpu->hv_clock.tsc_timestamp);
590 ktime_get_ts(&ts);
591 local_irq_restore(flags);
592
593 /* With all the info we got, fill in the values */
594
595 vcpu->hv_clock.system_time = ts.tv_nsec +
596 (NSEC_PER_SEC * (u64)ts.tv_sec);
597 /*
598 * The interface expects us to write an even number signaling that the
599 * update is finished. Since the guest won't see the intermediate
50d0a0f9 600 * state, we just increase by 2 at the end.
18068523 601 */
50d0a0f9 602 vcpu->hv_clock.version += 2;
18068523
GOC		 603
604 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
605
606 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 607 sizeof(vcpu->hv_clock));
18068523
GOC		 608
609 kunmap_atomic(shared_kaddr, KM_USER0);
610
611 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
612}
613
9ba075a6
AK		 614static bool msr_mtrr_valid(unsigned msr)
615{
616 switch (msr) {
617 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
618 case MSR_MTRRfix64K_00000:
619 case MSR_MTRRfix16K_80000:
620 case MSR_MTRRfix16K_A0000:
621 case MSR_MTRRfix4K_C0000:
622 case MSR_MTRRfix4K_C8000:
623 case MSR_MTRRfix4K_D0000:
624 case MSR_MTRRfix4K_D8000:
625 case MSR_MTRRfix4K_E0000:
626 case MSR_MTRRfix4K_E8000:
627 case MSR_MTRRfix4K_F0000:
628 case MSR_MTRRfix4K_F8000:
629 case MSR_MTRRdefType:
630 case MSR_IA32_CR_PAT:
631 return true;
632 case 0x2f8:
633 return true;
634 }
635 return false;
636}
637
638static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
639{
640 if (!msr_mtrr_valid(msr))
641 return 1;
642
643 vcpu->arch.mtrr[msr - 0x200] = data;
644 return 0;
645}
15c4a640
CO		 646
647int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
648{
649 switch (msr) {
15c4a640
CO		 650 case MSR_EFER:
651 set_efer(vcpu, data);
652 break;
15c4a640
CO		 653 case MSR_IA32_MC0_STATUS:
654 pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
b8688d51 655 __func__, data);
15c4a640
CO		 656 break;
657 case MSR_IA32_MCG_STATUS:
658 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
b8688d51 659 __func__, data);
15c4a640 660 break;
c7ac679c
JR		 661 case MSR_IA32_MCG_CTL:
662 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
b8688d51 663 __func__, data);
c7ac679c 664 break;
15c4a640
CO		 665 case MSR_IA32_UCODE_REV:
666 case MSR_IA32_UCODE_WRITE:
15c4a640 667 break;
9ba075a6
AK		 668 case 0x200 ... 0x2ff:
669 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 670 case MSR_IA32_APICBASE:
671 kvm_set_apic_base(vcpu, data);
672 break;
673 case MSR_IA32_MISC_ENABLE:
ad312c7c 674 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 675 break;
18068523
GOC		 676 case MSR_KVM_WALL_CLOCK:
677 vcpu->kvm->arch.wall_clock = data;
678 kvm_write_wall_clock(vcpu->kvm, data);
679 break;
680 case MSR_KVM_SYSTEM_TIME: {
681 if (vcpu->arch.time_page) {
682 kvm_release_page_dirty(vcpu->arch.time_page);
683 vcpu->arch.time_page = NULL;
684 }
685
686 vcpu->arch.time = data;
687
688 /* we verify if the enable bit is set... */
689 if (!(data & 1))
690 break;
691
692 /* ...but clean it before doing the actual write */
693 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
694
18068523 695 down_read(&current->mm->mmap_sem);
18068523
GOC		 696 vcpu->arch.time_page =
697 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 698 up_read(&current->mm->mmap_sem);
699
700 if (is_error_page(vcpu->arch.time_page)) {
701 kvm_release_page_clean(vcpu->arch.time_page);
702 vcpu->arch.time_page = NULL;
703 }
704
705 kvm_write_guest_time(vcpu);
706 break;
707 }
15c4a640 708 default:
565f1fbd 709 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 710 return 1;
711 }
712 return 0;
713}
714EXPORT_SYMBOL_GPL(kvm_set_msr_common);
715
716
717/*
718 * Reads an msr value (of 'msr_index') into 'pdata'.
719 * Returns 0 on success, non-0 otherwise.
720 * Assumes vcpu_load() was already called.
721 */
722int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
723{
724 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
725}
726
9ba075a6
AK		 727static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
728{
729 if (!msr_mtrr_valid(msr))
730 return 1;
731
732 *pdata = vcpu->arch.mtrr[msr - 0x200];
733 return 0;
734}
735
15c4a640
CO		 736int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
737{
738 u64 data;
739
740 switch (msr) {
741 case 0xc0010010: /* SYSCFG */
742 case 0xc0010015: /* HWCR */
743 case MSR_IA32_PLATFORM_ID:
744 case MSR_IA32_P5_MC_ADDR:
745 case MSR_IA32_P5_MC_TYPE:
746 case MSR_IA32_MC0_CTL:
747 case MSR_IA32_MCG_STATUS:
748 case MSR_IA32_MCG_CAP:
c7ac679c 749 case MSR_IA32_MCG_CTL:
15c4a640
CO		 750 case MSR_IA32_MC0_MISC:
751 case MSR_IA32_MC0_MISC+4:
752 case MSR_IA32_MC0_MISC+8:
753 case MSR_IA32_MC0_MISC+12:
754 case MSR_IA32_MC0_MISC+16:
755 case MSR_IA32_UCODE_REV:
15c4a640 756 case MSR_IA32_EBL_CR_POWERON:
15c4a640
CO		 757 data = 0;
758 break;
9ba075a6
AK		 759 case MSR_MTRRcap:
760 data = 0x500 | KVM_NR_VAR_MTRR;
761 break;
762 case 0x200 ... 0x2ff:
763 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 764 case 0xcd: /* fsb frequency */
765 data = 3;
766 break;
767 case MSR_IA32_APICBASE:
768 data = kvm_get_apic_base(vcpu);
769 break;
770 case MSR_IA32_MISC_ENABLE:
ad312c7c 771 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 772 break;
847f0ad8
AG		 773 case MSR_IA32_PERF_STATUS:
774 /* TSC increment by tick */
775 data = 1000ULL;
776 /* CPU multiplier */
777 data |= (((uint64_t)4ULL) << 40);
778 break;
15c4a640 779 case MSR_EFER:
ad312c7c 780 data = vcpu->arch.shadow_efer;
15c4a640 781 break;
18068523
GOC		 782 case MSR_KVM_WALL_CLOCK:
783 data = vcpu->kvm->arch.wall_clock;
784 break;
785 case MSR_KVM_SYSTEM_TIME:
786 data = vcpu->arch.time;
787 break;
15c4a640
CO		 788 default:
789 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
790 return 1;
791 }
792 *pdata = data;
793 return 0;
794}
795EXPORT_SYMBOL_GPL(kvm_get_msr_common);
796
313a3dc7
CO		 797/*
798 * Read or write a bunch of msrs. All parameters are kernel addresses.
799 *
800 * @return number of msrs set successfully.
801 */
802static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
803 struct kvm_msr_entry *entries,
804 int (*do_msr)(struct kvm_vcpu *vcpu,
805 unsigned index, u64 *data))
806{
807 int i;
808
809 vcpu_load(vcpu);
810
3200f405 811 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 812 for (i = 0; i < msrs->nmsrs; ++i)
813 if (do_msr(vcpu, entries[i].index, &entries[i].data))
814 break;
3200f405 815 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 816
817 vcpu_put(vcpu);
818
819 return i;
820}
821
822/*
823 * Read or write a bunch of msrs. Parameters are user addresses.
824 *
825 * @return number of msrs set successfully.
826 */
827static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
828 int (*do_msr)(struct kvm_vcpu *vcpu,
829 unsigned index, u64 *data),
830 int writeback)
831{
832 struct kvm_msrs msrs;
833 struct kvm_msr_entry *entries;
834 int r, n;
835 unsigned size;
836
837 r = -EFAULT;
838 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
839 goto out;
840
841 r = -E2BIG;
842 if (msrs.nmsrs >= MAX_IO_MSRS)
843 goto out;
844
845 r = -ENOMEM;
846 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
847 entries = vmalloc(size);
848 if (!entries)
849 goto out;
850
851 r = -EFAULT;
852 if (copy_from_user(entries, user_msrs->entries, size))
853 goto out_free;
854
855 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
856 if (r < 0)
857 goto out_free;
858
859 r = -EFAULT;
860 if (writeback && copy_to_user(user_msrs->entries, entries, size))
861 goto out_free;
862
863 r = n;
864
865out_free:
866 vfree(entries);
867out:
868 return r;
869}
870
018d00d2
ZX		 871int kvm_dev_ioctl_check_extension(long ext)
872{
873 int r;
874
875 switch (ext) {
876 case KVM_CAP_IRQCHIP:
877 case KVM_CAP_HLT:
878 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
879 case KVM_CAP_USER_MEMORY:
880 case KVM_CAP_SET_TSS_ADDR:
07716717 881 case KVM_CAP_EXT_CPUID:
18068523 882 case KVM_CAP_CLOCKSOURCE:
7837699f 883 case KVM_CAP_PIT:
a28e4f5a 884 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 885 case KVM_CAP_MP_STATE:
018d00d2
ZX		 886 r = 1;
887 break;
774ead3a
AK		 888 case KVM_CAP_VAPIC:
889 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
890 break;
f725230a
AK		 891 case KVM_CAP_NR_VCPUS:
892 r = KVM_MAX_VCPUS;
893 break;
a988b910
AK		 894 case KVM_CAP_NR_MEMSLOTS:
895 r = KVM_MEMORY_SLOTS;
896 break;
2f333bcb
MT		 897 case KVM_CAP_PV_MMU:
898 r = !tdp_enabled;
899 break;
018d00d2
ZX		 900 default:
901 r = 0;
902 break;
903 }
904 return r;
905
906}
907
043405e1
CO		 908long kvm_arch_dev_ioctl(struct file *filp,
909 unsigned int ioctl, unsigned long arg)
910{
911 void __user *argp = (void __user *)arg;
912 long r;
913
914 switch (ioctl) {
915 case KVM_GET_MSR_INDEX_LIST: {
916 struct kvm_msr_list __user *user_msr_list = argp;
917 struct kvm_msr_list msr_list;
918 unsigned n;
919
920 r = -EFAULT;
921 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
922 goto out;
923 n = msr_list.nmsrs;
924 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
925 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
926 goto out;
927 r = -E2BIG;
928 if (n < num_msrs_to_save)
929 goto out;
930 r = -EFAULT;
931 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
932 num_msrs_to_save * sizeof(u32)))
933 goto out;
934 if (copy_to_user(user_msr_list->indices
935 + num_msrs_to_save * sizeof(u32),
936 &emulated_msrs,
937 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
938 goto out;
939 r = 0;
940 break;
941 }
674eea0f
AK		 942 case KVM_GET_SUPPORTED_CPUID: {
943 struct kvm_cpuid2 __user *cpuid_arg = argp;
944 struct kvm_cpuid2 cpuid;
945
946 r = -EFAULT;
947 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
948 goto out;
949 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
950 cpuid_arg->entries);
951 if (r)
952 goto out;
953
954 r = -EFAULT;
955 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
956 goto out;
957 r = 0;
958 break;
959 }
043405e1
CO		 960 default:
961 r = -EINVAL;
962 }
963out:
964 return r;
965}
966
313a3dc7
CO		 967void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
968{
969 kvm_x86_ops->vcpu_load(vcpu, cpu);
18068523 970 kvm_write_guest_time(vcpu);
313a3dc7
CO		 971}
972
973void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
974{
975 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 976 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 977}
978
07716717 979static int is_efer_nx(void)
313a3dc7
CO		 980{
981 u64 efer;
313a3dc7
CO		 982
983 rdmsrl(MSR_EFER, efer);
07716717
DK		 984 return efer & EFER_NX;
985}
986
987static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
988{
989 int i;
990 struct kvm_cpuid_entry2 *e, *entry;
991
313a3dc7 992 entry = NULL;
ad312c7c
ZX		 993 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
994 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 995 if (e->function == 0x80000001) {
996 entry = e;
997 break;
998 }
999 }
07716717 1000 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1001 entry->edx &= ~(1 << 20);
1002 printk(KERN_INFO "kvm: guest NX capability removed\n");
1003 }
1004}
1005
07716717 1006/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1007static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1008 struct kvm_cpuid *cpuid,
1009 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1010{
1011 int r, i;
1012 struct kvm_cpuid_entry *cpuid_entries;
1013
1014 r = -E2BIG;
1015 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1016 goto out;
1017 r = -ENOMEM;
1018 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1019 if (!cpuid_entries)
1020 goto out;
1021 r = -EFAULT;
1022 if (copy_from_user(cpuid_entries, entries,
1023 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1024 goto out_free;
1025 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1026 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1027 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1028 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1029 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1030 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1031 vcpu->arch.cpuid_entries[i].index = 0;
1032 vcpu->arch.cpuid_entries[i].flags = 0;
1033 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1034 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1035 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1036 }
1037 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1038 cpuid_fix_nx_cap(vcpu);
1039 r = 0;
1040
1041out_free:
1042 vfree(cpuid_entries);
1043out:
1044 return r;
1045}
1046
1047static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
1048 struct kvm_cpuid2 *cpuid,
1049 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1050{
1051 int r;
1052
1053 r = -E2BIG;
1054 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1055 goto out;
1056 r = -EFAULT;
ad312c7c 1057 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1058 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1059 goto out;
ad312c7c 1060 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1061 return 0;
1062
1063out:
1064 return r;
1065}
1066
07716717
DK		 1067static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
1068 struct kvm_cpuid2 *cpuid,
1069 struct kvm_cpuid_entry2 __user *entries)
1070{
1071 int r;
1072
1073 r = -E2BIG;
ad312c7c 1074 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1075 goto out;
1076 r = -EFAULT;
ad312c7c
ZX		 1077 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
1078 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1079 goto out;
1080 return 0;
1081
1082out:
ad312c7c 1083 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1084 return r;
1085}
1086
1087static inline u32 bit(int bitno)
1088{
1089 return 1 << (bitno & 31);
1090}
1091
1092static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1093 u32 index)
1094{
1095 entry->function = function;
1096 entry->index = index;
1097 cpuid_count(entry->function, entry->index,
1098 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
1099 entry->flags = 0;
1100}
1101
1102static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1103 u32 index, int *nent, int maxnent)
1104{
1105 const u32 kvm_supported_word0_x86_features = bit(X86_FEATURE_FPU) |
1106 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1107 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1108 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1109 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1110 bit(X86_FEATURE_SEP) | bit(X86_FEATURE_PGE) |
1111 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1112 bit(X86_FEATURE_CLFLSH) | bit(X86_FEATURE_MMX) |
1113 bit(X86_FEATURE_FXSR) | bit(X86_FEATURE_XMM) |
1114 bit(X86_FEATURE_XMM2) | bit(X86_FEATURE_SELFSNOOP);
1115 const u32 kvm_supported_word1_x86_features = bit(X86_FEATURE_FPU) |
1116 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1117 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1118 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1119 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1120 bit(X86_FEATURE_PGE) |
1121 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1122 bit(X86_FEATURE_MMX) | bit(X86_FEATURE_FXSR) |
1123 bit(X86_FEATURE_SYSCALL) |
1124 (bit(X86_FEATURE_NX) && is_efer_nx()) |
1125#ifdef CONFIG_X86_64
1126 bit(X86_FEATURE_LM) |
1127#endif
1128 bit(X86_FEATURE_MMXEXT) |
1129 bit(X86_FEATURE_3DNOWEXT) |
1130 bit(X86_FEATURE_3DNOW);
1131 const u32 kvm_supported_word3_x86_features =
1132 bit(X86_FEATURE_XMM3) | bit(X86_FEATURE_CX16);
1133 const u32 kvm_supported_word6_x86_features =
1134 bit(X86_FEATURE_LAHF_LM) | bit(X86_FEATURE_CMP_LEGACY);
1135
1136 /* all func 2 cpuid_count() should be called on the same cpu */
1137 get_cpu();
1138 do_cpuid_1_ent(entry, function, index);
1139 ++*nent;
1140
1141 switch (function) {
1142 case 0:
1143 entry->eax = min(entry->eax, (u32)0xb);
1144 break;
1145 case 1:
1146 entry->edx &= kvm_supported_word0_x86_features;
1147 entry->ecx &= kvm_supported_word3_x86_features;
1148 break;
1149 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1150 * may return different values. This forces us to get_cpu() before
1151 * issuing the first command, and also to emulate this annoying behavior
1152 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1153 case 2: {
1154 int t, times = entry->eax & 0xff;
1155
1156 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1157 for (t = 1; t < times && *nent < maxnent; ++t) {
1158 do_cpuid_1_ent(&entry[t], function, 0);
1159 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1160 ++*nent;
1161 }
1162 break;
1163 }
1164 /* function 4 and 0xb have additional index. */
1165 case 4: {
14af3f3c 1166 int i, cache_type;
07716717
DK		 1167
1168 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1169 /* read more entries until cache_type is zero */
14af3f3c
HH		 1170 for (i = 1; *nent < maxnent; ++i) {
1171 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1172 if (!cache_type)
1173 break;
14af3f3c
HH		 1174 do_cpuid_1_ent(&entry[i], function, i);
1175 entry[i].flags |=
07716717
DK		 1176 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1177 ++*nent;
1178 }
1179 break;
1180 }
1181 case 0xb: {
14af3f3c 1182 int i, level_type;
07716717
DK		 1183
1184 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1185 /* read more entries until level_type is zero */
14af3f3c
HH		 1186 for (i = 1; *nent < maxnent; ++i) {
1187 level_type = entry[i - 1].ecx & 0xff;
07716717
DK		 1188 if (!level_type)
1189 break;
14af3f3c
HH		 1190 do_cpuid_1_ent(&entry[i], function, i);
1191 entry[i].flags |=
07716717
DK		 1192 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1193 ++*nent;
1194 }
1195 break;
1196 }
1197 case 0x80000000:
1198 entry->eax = min(entry->eax, 0x8000001a);
1199 break;
1200 case 0x80000001:
1201 entry->edx &= kvm_supported_word1_x86_features;
1202 entry->ecx &= kvm_supported_word6_x86_features;
1203 break;
1204 }
1205 put_cpu();
1206}
1207
674eea0f 1208static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
07716717
DK		 1209 struct kvm_cpuid_entry2 __user *entries)
1210{
1211 struct kvm_cpuid_entry2 *cpuid_entries;
1212 int limit, nent = 0, r = -E2BIG;
1213 u32 func;
1214
1215 if (cpuid->nent < 1)
1216 goto out;
1217 r = -ENOMEM;
1218 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1219 if (!cpuid_entries)
1220 goto out;
1221
1222 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1223 limit = cpuid_entries[0].eax;
1224 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1225 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1226 &nent, cpuid->nent);
1227 r = -E2BIG;
1228 if (nent >= cpuid->nent)
1229 goto out_free;
1230
1231 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1232 limit = cpuid_entries[nent - 1].eax;
1233 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1234 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1235 &nent, cpuid->nent);
1236 r = -EFAULT;
1237 if (copy_to_user(entries, cpuid_entries,
1238 nent * sizeof(struct kvm_cpuid_entry2)))
1239 goto out_free;
1240 cpuid->nent = nent;
1241 r = 0;
1242
1243out_free:
1244 vfree(cpuid_entries);
1245out:
1246 return r;
1247}
1248
313a3dc7
CO		 1249static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1250 struct kvm_lapic_state *s)
1251{
1252 vcpu_load(vcpu);
ad312c7c 1253 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1254 vcpu_put(vcpu);
1255
1256 return 0;
1257}
1258
1259static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1260 struct kvm_lapic_state *s)
1261{
1262 vcpu_load(vcpu);
ad312c7c 1263 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1264 kvm_apic_post_state_restore(vcpu);
1265 vcpu_put(vcpu);
1266
1267 return 0;
1268}
1269
f77bc6a4
ZX		 1270static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1271 struct kvm_interrupt *irq)
1272{
1273 if (irq->irq < 0 || irq->irq >= 256)
1274 return -EINVAL;
1275 if (irqchip_in_kernel(vcpu->kvm))
1276 return -ENXIO;
1277 vcpu_load(vcpu);
1278
ad312c7c
ZX		 1279 set_bit(irq->irq, vcpu->arch.irq_pending);
1280 set_bit(irq->irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
f77bc6a4
ZX		 1281
1282 vcpu_put(vcpu);
1283
1284 return 0;
1285}
1286
b209749f
AK		 1287static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1288 struct kvm_tpr_access_ctl *tac)
1289{
1290 if (tac->flags)
1291 return -EINVAL;
1292 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1293 return 0;
1294}
1295
313a3dc7
CO		 1296long kvm_arch_vcpu_ioctl(struct file *filp,
1297 unsigned int ioctl, unsigned long arg)
1298{
1299 struct kvm_vcpu *vcpu = filp->private_data;
1300 void __user *argp = (void __user *)arg;
1301 int r;
1302
1303 switch (ioctl) {
1304 case KVM_GET_LAPIC: {
1305 struct kvm_lapic_state lapic;
1306
1307 memset(&lapic, 0, sizeof lapic);
1308 r = kvm_vcpu_ioctl_get_lapic(vcpu, &lapic);
1309 if (r)
1310 goto out;
1311 r = -EFAULT;
1312 if (copy_to_user(argp, &lapic, sizeof lapic))
1313 goto out;
1314 r = 0;
1315 break;
1316 }
1317 case KVM_SET_LAPIC: {
1318 struct kvm_lapic_state lapic;
1319
1320 r = -EFAULT;
1321 if (copy_from_user(&lapic, argp, sizeof lapic))
1322 goto out;
1323 r = kvm_vcpu_ioctl_set_lapic(vcpu, &lapic);;
1324 if (r)
1325 goto out;
1326 r = 0;
1327 break;
1328 }
f77bc6a4
ZX		 1329 case KVM_INTERRUPT: {
1330 struct kvm_interrupt irq;
1331
1332 r = -EFAULT;
1333 if (copy_from_user(&irq, argp, sizeof irq))
1334 goto out;
1335 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1336 if (r)
1337 goto out;
1338 r = 0;
1339 break;
1340 }
313a3dc7
CO		 1341 case KVM_SET_CPUID: {
1342 struct kvm_cpuid __user *cpuid_arg = argp;
1343 struct kvm_cpuid cpuid;
1344
1345 r = -EFAULT;
1346 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1347 goto out;
1348 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1349 if (r)
1350 goto out;
1351 break;
1352 }
07716717
DK		 1353 case KVM_SET_CPUID2: {
1354 struct kvm_cpuid2 __user *cpuid_arg = argp;
1355 struct kvm_cpuid2 cpuid;
1356
1357 r = -EFAULT;
1358 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1359 goto out;
1360 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
1361 cpuid_arg->entries);
1362 if (r)
1363 goto out;
1364 break;
1365 }
1366 case KVM_GET_CPUID2: {
1367 struct kvm_cpuid2 __user *cpuid_arg = argp;
1368 struct kvm_cpuid2 cpuid;
1369
1370 r = -EFAULT;
1371 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1372 goto out;
1373 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
1374 cpuid_arg->entries);
1375 if (r)
1376 goto out;
1377 r = -EFAULT;
1378 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1379 goto out;
1380 r = 0;
1381 break;
1382 }
313a3dc7
CO		 1383 case KVM_GET_MSRS:
1384 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1385 break;
1386 case KVM_SET_MSRS:
1387 r = msr_io(vcpu, argp, do_set_msr, 0);
1388 break;
b209749f
AK		 1389 case KVM_TPR_ACCESS_REPORTING: {
1390 struct kvm_tpr_access_ctl tac;
1391
1392 r = -EFAULT;
1393 if (copy_from_user(&tac, argp, sizeof tac))
1394 goto out;
1395 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1396 if (r)
1397 goto out;
1398 r = -EFAULT;
1399 if (copy_to_user(argp, &tac, sizeof tac))
1400 goto out;
1401 r = 0;
1402 break;
1403 };
b93463aa
AK		 1404 case KVM_SET_VAPIC_ADDR: {
1405 struct kvm_vapic_addr va;
1406
1407 r = -EINVAL;
1408 if (!irqchip_in_kernel(vcpu->kvm))
1409 goto out;
1410 r = -EFAULT;
1411 if (copy_from_user(&va, argp, sizeof va))
1412 goto out;
1413 r = 0;
1414 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1415 break;
1416 }
313a3dc7
CO		 1417 default:
1418 r = -EINVAL;
1419 }
1420out:
1421 return r;
1422}
1423
1fe779f8
CO		 1424static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1425{
1426 int ret;
1427
1428 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1429 return -1;
1430 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1431 return ret;
1432}
1433
1434static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1435 u32 kvm_nr_mmu_pages)
1436{
1437 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1438 return -EINVAL;
1439
72dc67a6 1440 down_write(&kvm->slots_lock);
1fe779f8
CO		 1441
1442 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1443 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1444
72dc67a6 1445 up_write(&kvm->slots_lock);
1fe779f8
CO		 1446 return 0;
1447}
1448
1449static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1450{
f05e70ac 1451 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1452}
1453
e9f85cde
ZX		 1454gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1455{
1456 int i;
1457 struct kvm_mem_alias *alias;
1458
d69fb81f
ZX		 1459 for (i = 0; i < kvm->arch.naliases; ++i) {
1460 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1461 if (gfn >= alias->base_gfn
1462 && gfn < alias->base_gfn + alias->npages)
1463 return alias->target_gfn + gfn - alias->base_gfn;
1464 }
1465 return gfn;
1466}
1467
1fe779f8
CO		 1468/*
1469 * Set a new alias region. Aliases map a portion of physical memory into
1470 * another portion. This is useful for memory windows, for example the PC
1471 * VGA region.
1472 */
1473static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1474 struct kvm_memory_alias *alias)
1475{
1476 int r, n;
1477 struct kvm_mem_alias *p;
1478
1479 r = -EINVAL;
1480 /* General sanity checks */
1481 if (alias->memory_size & (PAGE_SIZE - 1))
1482 goto out;
1483 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1484 goto out;
1485 if (alias->slot >= KVM_ALIAS_SLOTS)
1486 goto out;
1487 if (alias->guest_phys_addr + alias->memory_size
1488 < alias->guest_phys_addr)
1489 goto out;
1490 if (alias->target_phys_addr + alias->memory_size
1491 < alias->target_phys_addr)
1492 goto out;
1493
72dc67a6 1494 down_write(&kvm->slots_lock);
1fe779f8 1495
d69fb81f 1496 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1497 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1498 p->npages = alias->memory_size >> PAGE_SHIFT;
1499 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1500
1501 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1502 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1503 break;
d69fb81f 1504 kvm->arch.naliases = n;
1fe779f8
CO		 1505
1506 kvm_mmu_zap_all(kvm);
1507
72dc67a6 1508 up_write(&kvm->slots_lock);
1fe779f8
CO		 1509
1510 return 0;
1511
1512out:
1513 return r;
1514}
1515
1516static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1517{
1518 int r;
1519
1520 r = 0;
1521 switch (chip->chip_id) {
1522 case KVM_IRQCHIP_PIC_MASTER:
1523 memcpy(&chip->chip.pic,
1524 &pic_irqchip(kvm)->pics[0],
1525 sizeof(struct kvm_pic_state));
1526 break;
1527 case KVM_IRQCHIP_PIC_SLAVE:
1528 memcpy(&chip->chip.pic,
1529 &pic_irqchip(kvm)->pics[1],
1530 sizeof(struct kvm_pic_state));
1531 break;
1532 case KVM_IRQCHIP_IOAPIC:
1533 memcpy(&chip->chip.ioapic,
1534 ioapic_irqchip(kvm),
1535 sizeof(struct kvm_ioapic_state));
1536 break;
1537 default:
1538 r = -EINVAL;
1539 break;
1540 }
1541 return r;
1542}
1543
1544static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1545{
1546 int r;
1547
1548 r = 0;
1549 switch (chip->chip_id) {
1550 case KVM_IRQCHIP_PIC_MASTER:
1551 memcpy(&pic_irqchip(kvm)->pics[0],
1552 &chip->chip.pic,
1553 sizeof(struct kvm_pic_state));
1554 break;
1555 case KVM_IRQCHIP_PIC_SLAVE:
1556 memcpy(&pic_irqchip(kvm)->pics[1],
1557 &chip->chip.pic,
1558 sizeof(struct kvm_pic_state));
1559 break;
1560 case KVM_IRQCHIP_IOAPIC:
1561 memcpy(ioapic_irqchip(kvm),
1562 &chip->chip.ioapic,
1563 sizeof(struct kvm_ioapic_state));
1564 break;
1565 default:
1566 r = -EINVAL;
1567 break;
1568 }
1569 kvm_pic_update_irq(pic_irqchip(kvm));
1570 return r;
1571}
1572
e0f63cb9
SY		 1573static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1574{
1575 int r = 0;
1576
1577 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
1578 return r;
1579}
1580
1581static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1582{
1583 int r = 0;
1584
1585 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
1586 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
1587 return r;
1588}
1589
5bb064dc
ZX		 1590/*
1591 * Get (and clear) the dirty memory log for a memory slot.
1592 */
1593int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
1594 struct kvm_dirty_log *log)
1595{
1596 int r;
1597 int n;
1598 struct kvm_memory_slot *memslot;
1599 int is_dirty = 0;
1600
72dc67a6 1601 down_write(&kvm->slots_lock);
5bb064dc
ZX		 1602
1603 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1604 if (r)
1605 goto out;
1606
1607 /* If nothing is dirty, don't bother messing with page tables. */
1608 if (is_dirty) {
1609 kvm_mmu_slot_remove_write_access(kvm, log->slot);
1610 kvm_flush_remote_tlbs(kvm);
1611 memslot = &kvm->memslots[log->slot];
1612 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
1613 memset(memslot->dirty_bitmap, 0, n);
1614 }
1615 r = 0;
1616out:
72dc67a6 1617 up_write(&kvm->slots_lock);
5bb064dc
ZX		 1618 return r;
1619}
1620
1fe779f8
CO		 1621long kvm_arch_vm_ioctl(struct file *filp,
1622 unsigned int ioctl, unsigned long arg)
1623{
1624 struct kvm *kvm = filp->private_data;
1625 void __user *argp = (void __user *)arg;
1626 int r = -EINVAL;
1627
1628 switch (ioctl) {
1629 case KVM_SET_TSS_ADDR:
1630 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1631 if (r < 0)
1632 goto out;
1633 break;
1634 case KVM_SET_MEMORY_REGION: {
1635 struct kvm_memory_region kvm_mem;
1636 struct kvm_userspace_memory_region kvm_userspace_mem;
1637
1638 r = -EFAULT;
1639 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
1640 goto out;
1641 kvm_userspace_mem.slot = kvm_mem.slot;
1642 kvm_userspace_mem.flags = kvm_mem.flags;
1643 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
1644 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
1645 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
1646 if (r)
1647 goto out;
1648 break;
1649 }
1650 case KVM_SET_NR_MMU_PAGES:
1651 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1652 if (r)
1653 goto out;
1654 break;
1655 case KVM_GET_NR_MMU_PAGES:
1656 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
1657 break;
1658 case KVM_SET_MEMORY_ALIAS: {
1659 struct kvm_memory_alias alias;
1660
1661 r = -EFAULT;
1662 if (copy_from_user(&alias, argp, sizeof alias))
1663 goto out;
1664 r = kvm_vm_ioctl_set_memory_alias(kvm, &alias);
1665 if (r)
1666 goto out;
1667 break;
1668 }
1669 case KVM_CREATE_IRQCHIP:
1670 r = -ENOMEM;
d7deeeb0
ZX		 1671 kvm->arch.vpic = kvm_create_pic(kvm);
1672 if (kvm->arch.vpic) {
1fe779f8
CO		 1673 r = kvm_ioapic_init(kvm);
1674 if (r) {
d7deeeb0
ZX		 1675 kfree(kvm->arch.vpic);
1676 kvm->arch.vpic = NULL;
1fe779f8
CO		 1677 goto out;
1678 }
1679 } else
1680 goto out;
1681 break;
7837699f
SY		 1682 case KVM_CREATE_PIT:
1683 r = -ENOMEM;
1684 kvm->arch.vpit = kvm_create_pit(kvm);
1685 if (kvm->arch.vpit)
1686 r = 0;
1687 break;
1fe779f8
CO		 1688 case KVM_IRQ_LINE: {
1689 struct kvm_irq_level irq_event;
1690
1691 r = -EFAULT;
1692 if (copy_from_user(&irq_event, argp, sizeof irq_event))
1693 goto out;
1694 if (irqchip_in_kernel(kvm)) {
1695 mutex_lock(&kvm->lock);
1696 if (irq_event.irq < 16)
1697 kvm_pic_set_irq(pic_irqchip(kvm),
1698 irq_event.irq,
1699 irq_event.level);
d7deeeb0 1700 kvm_ioapic_set_irq(kvm->arch.vioapic,
1fe779f8
CO		 1701 irq_event.irq,
1702 irq_event.level);
1703 mutex_unlock(&kvm->lock);
1704 r = 0;
1705 }
1706 break;
1707 }
1708 case KVM_GET_IRQCHIP: {
1709 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
1710 struct kvm_irqchip chip;
1711
1712 r = -EFAULT;
1713 if (copy_from_user(&chip, argp, sizeof chip))
1714 goto out;
1715 r = -ENXIO;
1716 if (!irqchip_in_kernel(kvm))
1717 goto out;
1718 r = kvm_vm_ioctl_get_irqchip(kvm, &chip);
1719 if (r)
1720 goto out;
1721 r = -EFAULT;
1722 if (copy_to_user(argp, &chip, sizeof chip))
1723 goto out;
1724 r = 0;
1725 break;
1726 }
1727 case KVM_SET_IRQCHIP: {
1728 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
1729 struct kvm_irqchip chip;
1730
1731 r = -EFAULT;
1732 if (copy_from_user(&chip, argp, sizeof chip))
1733 goto out;
1734 r = -ENXIO;
1735 if (!irqchip_in_kernel(kvm))
1736 goto out;
1737 r = kvm_vm_ioctl_set_irqchip(kvm, &chip);
1738 if (r)
1739 goto out;
1740 r = 0;
1741 break;
1742 }
e0f63cb9
SY		 1743 case KVM_GET_PIT: {
1744 struct kvm_pit_state ps;
1745 r = -EFAULT;
1746 if (copy_from_user(&ps, argp, sizeof ps))
1747 goto out;
1748 r = -ENXIO;
1749 if (!kvm->arch.vpit)
1750 goto out;
1751 r = kvm_vm_ioctl_get_pit(kvm, &ps);
1752 if (r)
1753 goto out;
1754 r = -EFAULT;
1755 if (copy_to_user(argp, &ps, sizeof ps))
1756 goto out;
1757 r = 0;
1758 break;
1759 }
1760 case KVM_SET_PIT: {
1761 struct kvm_pit_state ps;
1762 r = -EFAULT;
1763 if (copy_from_user(&ps, argp, sizeof ps))
1764 goto out;
1765 r = -ENXIO;
1766 if (!kvm->arch.vpit)
1767 goto out;
1768 r = kvm_vm_ioctl_set_pit(kvm, &ps);
1769 if (r)
1770 goto out;
1771 r = 0;
1772 break;
1773 }
1fe779f8
CO		 1774 default:
1775 ;
1776 }
1777out:
1778 return r;
1779}
1780
a16b043c 1781static void kvm_init_msr_list(void)
043405e1
CO		 1782{
1783 u32 dummy[2];
1784 unsigned i, j;
1785
1786 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
1787 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
1788 continue;
1789 if (j < i)
1790 msrs_to_save[j] = msrs_to_save[i];
1791 j++;
1792 }
1793 num_msrs_to_save = j;
1794}
1795
bbd9b64e
CO		 1796/*
1797 * Only apic need an MMIO device hook, so shortcut now..
1798 */
1799static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
92760499
LV		 1800 gpa_t addr, int len,
1801 int is_write)
bbd9b64e
CO		 1802{
1803 struct kvm_io_device *dev;
1804
ad312c7c
ZX		 1805 if (vcpu->arch.apic) {
1806 dev = &vcpu->arch.apic->dev;
92760499 1807 if (dev->in_range(dev, addr, len, is_write))
bbd9b64e
CO		 1808 return dev;
1809 }
1810 return NULL;
1811}
1812
1813
1814static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 1815 gpa_t addr, int len,
1816 int is_write)
bbd9b64e
CO		 1817{
1818 struct kvm_io_device *dev;
1819
92760499 1820 dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
bbd9b64e 1821 if (dev == NULL)
92760499
LV		 1822 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
1823 is_write);
bbd9b64e
CO		 1824 return dev;
1825}
1826
1827int emulator_read_std(unsigned long addr,
1828 void *val,
1829 unsigned int bytes,
1830 struct kvm_vcpu *vcpu)
1831{
1832 void *data = val;
10589a46 1833 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 1834
1835 while (bytes) {
ad312c7c 1836 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1837 unsigned offset = addr & (PAGE_SIZE-1);
1838 unsigned tocopy = min(bytes, (unsigned)PAGE_SIZE - offset);
1839 int ret;
1840
10589a46
MT		 1841 if (gpa == UNMAPPED_GVA) {
1842 r = X86EMUL_PROPAGATE_FAULT;
1843 goto out;
1844 }
bbd9b64e 1845 ret = kvm_read_guest(vcpu->kvm, gpa, data, tocopy);
10589a46
MT		 1846 if (ret < 0) {
1847 r = X86EMUL_UNHANDLEABLE;
1848 goto out;
1849 }
bbd9b64e
CO		 1850
1851 bytes -= tocopy;
1852 data += tocopy;
1853 addr += tocopy;
1854 }
10589a46 1855out:
10589a46 1856 return r;
bbd9b64e
CO		 1857}
1858EXPORT_SYMBOL_GPL(emulator_read_std);
1859
bbd9b64e
CO		 1860static int emulator_read_emulated(unsigned long addr,
1861 void *val,
1862 unsigned int bytes,
1863 struct kvm_vcpu *vcpu)
1864{
1865 struct kvm_io_device *mmio_dev;
1866 gpa_t gpa;
1867
1868 if (vcpu->mmio_read_completed) {
1869 memcpy(val, vcpu->mmio_data, bytes);
1870 vcpu->mmio_read_completed = 0;
1871 return X86EMUL_CONTINUE;
1872 }
1873
ad312c7c 1874 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1875
1876 /* For APIC access vmexit */
1877 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
1878 goto mmio;
1879
1880 if (emulator_read_std(addr, val, bytes, vcpu)
1881 == X86EMUL_CONTINUE)
1882 return X86EMUL_CONTINUE;
1883 if (gpa == UNMAPPED_GVA)
1884 return X86EMUL_PROPAGATE_FAULT;
1885
1886mmio:
1887 /*
1888 * Is this MMIO handled locally?
1889 */
10589a46 1890 mutex_lock(&vcpu->kvm->lock);
92760499 1891 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
bbd9b64e
CO		 1892 if (mmio_dev) {
1893 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
10589a46 1894 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1895 return X86EMUL_CONTINUE;
1896 }
10589a46 1897 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1898
1899 vcpu->mmio_needed = 1;
1900 vcpu->mmio_phys_addr = gpa;
1901 vcpu->mmio_size = bytes;
1902 vcpu->mmio_is_write = 0;
1903
1904 return X86EMUL_UNHANDLEABLE;
1905}
1906
3200f405 1907int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 1908 const void *val, int bytes)
bbd9b64e
CO		 1909{
1910 int ret;
1911
1912 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 1913 if (ret < 0)
bbd9b64e
CO		 1914 return 0;
1915 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
1916 return 1;
1917}
1918
1919static int emulator_write_emulated_onepage(unsigned long addr,
1920 const void *val,
1921 unsigned int bytes,
1922 struct kvm_vcpu *vcpu)
1923{
1924 struct kvm_io_device *mmio_dev;
10589a46
MT		 1925 gpa_t gpa;
1926
10589a46 1927 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 1928
1929 if (gpa == UNMAPPED_GVA) {
c3c91fee 1930 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 1931 return X86EMUL_PROPAGATE_FAULT;
1932 }
1933
1934 /* For APIC access vmexit */
1935 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
1936 goto mmio;
1937
1938 if (emulator_write_phys(vcpu, gpa, val, bytes))
1939 return X86EMUL_CONTINUE;
1940
1941mmio:
1942 /*
1943 * Is this MMIO handled locally?
1944 */
10589a46 1945 mutex_lock(&vcpu->kvm->lock);
92760499 1946 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
bbd9b64e
CO		 1947 if (mmio_dev) {
1948 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
10589a46 1949 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1950 return X86EMUL_CONTINUE;
1951 }
10589a46 1952 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 1953
1954 vcpu->mmio_needed = 1;
1955 vcpu->mmio_phys_addr = gpa;
1956 vcpu->mmio_size = bytes;
1957 vcpu->mmio_is_write = 1;
1958 memcpy(vcpu->mmio_data, val, bytes);
1959
1960 return X86EMUL_CONTINUE;
1961}
1962
1963int emulator_write_emulated(unsigned long addr,
1964 const void *val,
1965 unsigned int bytes,
1966 struct kvm_vcpu *vcpu)
1967{
1968 /* Crossing a page boundary? */
1969 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
1970 int rc, now;
1971
1972 now = -addr & ~PAGE_MASK;
1973 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
1974 if (rc != X86EMUL_CONTINUE)
1975 return rc;
1976 addr += now;
1977 val += now;
1978 bytes -= now;
1979 }
1980 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
1981}
1982EXPORT_SYMBOL_GPL(emulator_write_emulated);
1983
1984static int emulator_cmpxchg_emulated(unsigned long addr,
1985 const void *old,
1986 const void *new,
1987 unsigned int bytes,
1988 struct kvm_vcpu *vcpu)
1989{
1990 static int reported;
1991
1992 if (!reported) {
1993 reported = 1;
1994 printk(KERN_WARNING "kvm: emulating exchange as write\n");
1995 }
2bacc55c
MT		 1996#ifndef CONFIG_X86_64
1997 /* guests cmpxchg8b have to be emulated atomically */
1998 if (bytes == 8) {
10589a46 1999 gpa_t gpa;
2bacc55c 2000 struct page *page;
c0b49b0d 2001 char *kaddr;
2bacc55c
MT		 2002 u64 val;
2003
10589a46
MT		 2004 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2005
2bacc55c
MT		 2006 if (gpa == UNMAPPED_GVA ||
2007 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2008 goto emul_write;
2009
2010 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2011 goto emul_write;
2012
2013 val = *(u64 *)new;
72dc67a6
IE		 2014
2015 down_read(&current->mm->mmap_sem);
2bacc55c 2016 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6
IE		 2017 up_read(&current->mm->mmap_sem);
2018
c0b49b0d
AM		 2019 kaddr = kmap_atomic(page, KM_USER0);
2020 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2021 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2022 kvm_release_page_dirty(page);
2023 }
3200f405 2024emul_write:
2bacc55c
MT		 2025#endif
2026
bbd9b64e
CO		 2027 return emulator_write_emulated(addr, new, bytes, vcpu);
2028}
2029
2030static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2031{
2032 return kvm_x86_ops->get_segment_base(vcpu, seg);
2033}
2034
2035int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2036{
2037 return X86EMUL_CONTINUE;
2038}
2039
2040int emulate_clts(struct kvm_vcpu *vcpu)
2041{
54e445ca 2042 KVMTRACE_0D(CLTS, vcpu, handler);
ad312c7c 2043 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2044 return X86EMUL_CONTINUE;
2045}
2046
2047int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2048{
2049 struct kvm_vcpu *vcpu = ctxt->vcpu;
2050
2051 switch (dr) {
2052 case 0 ... 3:
2053 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2054 return X86EMUL_CONTINUE;
2055 default:
b8688d51 2056 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2057 return X86EMUL_UNHANDLEABLE;
2058 }
2059}
2060
2061int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2062{
2063 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2064 int exception;
2065
2066 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2067 if (exception) {
2068 /* FIXME: better handling */
2069 return X86EMUL_UNHANDLEABLE;
2070 }
2071 return X86EMUL_CONTINUE;
2072}
2073
2074void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2075{
2076 static int reported;
2077 u8 opcodes[4];
ad312c7c 2078 unsigned long rip = vcpu->arch.rip;
bbd9b64e
CO		 2079 unsigned long rip_linear;
2080
2081 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2082
2083 if (reported)
2084 return;
2085
2086 emulator_read_std(rip_linear, (void *)opcodes, 4, vcpu);
2087
2088 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2089 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
2090 reported = 1;
2091}
2092EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2093
14af3f3c 2094static struct x86_emulate_ops emulate_ops = {
bbd9b64e 2095 .read_std = emulator_read_std,
bbd9b64e
CO		 2096 .read_emulated = emulator_read_emulated,
2097 .write_emulated = emulator_write_emulated,
2098 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2099};
2100
2101int emulate_instruction(struct kvm_vcpu *vcpu,
2102 struct kvm_run *run,
2103 unsigned long cr2,
2104 u16 error_code,
571008da 2105 int emulation_type)
bbd9b64e
CO		 2106{
2107 int r;
571008da 2108 struct decode_cache *c;
bbd9b64e 2109
ad312c7c 2110 vcpu->arch.mmio_fault_cr2 = cr2;
bbd9b64e
CO		 2111 kvm_x86_ops->cache_regs(vcpu);
2112
2113 vcpu->mmio_is_write = 0;
ad312c7c 2114 vcpu->arch.pio.string = 0;
bbd9b64e 2115
571008da 2116 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2117 int cs_db, cs_l;
2118 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2119
ad312c7c
ZX		 2120 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2121 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2122 vcpu->arch.emulate_ctxt.mode =
2123 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2124 ? X86EMUL_MODE_REAL : cs_l
2125 ? X86EMUL_MODE_PROT64 : cs_db
2126 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2127
ad312c7c
ZX		 2128 if (vcpu->arch.emulate_ctxt.mode == X86EMUL_MODE_PROT64) {
2129 vcpu->arch.emulate_ctxt.cs_base = 0;
2130 vcpu->arch.emulate_ctxt.ds_base = 0;
2131 vcpu->arch.emulate_ctxt.es_base = 0;
2132 vcpu->arch.emulate_ctxt.ss_base = 0;
bbd9b64e 2133 } else {
ad312c7c 2134 vcpu->arch.emulate_ctxt.cs_base =
bbd9b64e 2135 get_segment_base(vcpu, VCPU_SREG_CS);
ad312c7c 2136 vcpu->arch.emulate_ctxt.ds_base =
bbd9b64e 2137 get_segment_base(vcpu, VCPU_SREG_DS);
ad312c7c 2138 vcpu->arch.emulate_ctxt.es_base =
bbd9b64e 2139 get_segment_base(vcpu, VCPU_SREG_ES);
ad312c7c 2140 vcpu->arch.emulate_ctxt.ss_base =
bbd9b64e
CO		 2141 get_segment_base(vcpu, VCPU_SREG_SS);
2142 }
2143
ad312c7c 2144 vcpu->arch.emulate_ctxt.gs_base =
bbd9b64e 2145 get_segment_base(vcpu, VCPU_SREG_GS);
ad312c7c 2146 vcpu->arch.emulate_ctxt.fs_base =
bbd9b64e
CO		 2147 get_segment_base(vcpu, VCPU_SREG_FS);
2148
ad312c7c 2149 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2150
2151 /* Reject the instructions other than VMCALL/VMMCALL when
2152 * try to emulate invalid opcode */
2153 c = &vcpu->arch.emulate_ctxt.decode;
2154 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2155 (!(c->twobyte && c->b == 0x01 &&
2156 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2157 c->modrm_mod == 3 && c->modrm_rm == 1)))
2158 return EMULATE_FAIL;
2159
f2b5756b 2160 ++vcpu->stat.insn_emulation;
bbd9b64e 2161 if (r) {
f2b5756b 2162 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2163 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2164 return EMULATE_DONE;
2165 return EMULATE_FAIL;
2166 }
2167 }
2168
ad312c7c 2169 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 2170
ad312c7c 2171 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2172 return EMULATE_DO_MMIO;
2173
2174 if ((r || vcpu->mmio_is_write) && run) {
2175 run->exit_reason = KVM_EXIT_MMIO;
2176 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2177 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2178 run->mmio.len = vcpu->mmio_size;
2179 run->mmio.is_write = vcpu->mmio_is_write;
2180 }
2181
2182 if (r) {
2183 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2184 return EMULATE_DONE;
2185 if (!vcpu->mmio_needed) {
2186 kvm_report_emulation_failure(vcpu, "mmio");
2187 return EMULATE_FAIL;
2188 }
2189 return EMULATE_DO_MMIO;
2190 }
2191
2192 kvm_x86_ops->decache_regs(vcpu);
ad312c7c 2193 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2194
2195 if (vcpu->mmio_is_write) {
2196 vcpu->mmio_needed = 0;
2197 return EMULATE_DO_MMIO;
2198 }
2199
2200 return EMULATE_DONE;
2201}
2202EXPORT_SYMBOL_GPL(emulate_instruction);
2203
de7d789a
CO		 2204static void free_pio_guest_pages(struct kvm_vcpu *vcpu)
2205{
2206 int i;
2207
ad312c7c
ZX		 2208 for (i = 0; i < ARRAY_SIZE(vcpu->arch.pio.guest_pages); ++i)
2209 if (vcpu->arch.pio.guest_pages[i]) {
2210 kvm_release_page_dirty(vcpu->arch.pio.guest_pages[i]);
2211 vcpu->arch.pio.guest_pages[i] = NULL;
de7d789a
CO		 2212 }
2213}
2214
2215static int pio_copy_data(struct kvm_vcpu *vcpu)
2216{
ad312c7c 2217 void *p = vcpu->arch.pio_data;
de7d789a
CO		 2218 void *q;
2219 unsigned bytes;
ad312c7c 2220 int nr_pages = vcpu->arch.pio.guest_pages[1] ? 2 : 1;
de7d789a 2221
ad312c7c 2222 q = vmap(vcpu->arch.pio.guest_pages, nr_pages, VM_READ|VM_WRITE,
de7d789a
CO		 2223 PAGE_KERNEL);
2224 if (!q) {
2225 free_pio_guest_pages(vcpu);
2226 return -ENOMEM;
2227 }
ad312c7c
ZX		 2228 q += vcpu->arch.pio.guest_page_offset;
2229 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2230 if (vcpu->arch.pio.in)
de7d789a
CO		 2231 memcpy(q, p, bytes);
2232 else
2233 memcpy(p, q, bytes);
ad312c7c 2234 q -= vcpu->arch.pio.guest_page_offset;
de7d789a
CO		 2235 vunmap(q);
2236 free_pio_guest_pages(vcpu);
2237 return 0;
2238}
2239
2240int complete_pio(struct kvm_vcpu *vcpu)
2241{
ad312c7c 2242 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2243 long delta;
2244 int r;
2245
2246 kvm_x86_ops->cache_regs(vcpu);
2247
2248 if (!io->string) {
2249 if (io->in)
ad312c7c 2250 memcpy(&vcpu->arch.regs[VCPU_REGS_RAX], vcpu->arch.pio_data,
de7d789a
CO		 2251 io->size);
2252 } else {
2253 if (io->in) {
2254 r = pio_copy_data(vcpu);
2255 if (r) {
2256 kvm_x86_ops->cache_regs(vcpu);
2257 return r;
2258 }
2259 }
2260
2261 delta = 1;
2262 if (io->rep) {
2263 delta *= io->cur_count;
2264 /*
2265 * The size of the register should really depend on
2266 * current address size.
2267 */
ad312c7c 2268 vcpu->arch.regs[VCPU_REGS_RCX] -= delta;
de7d789a
CO		 2269 }
2270 if (io->down)
2271 delta = -delta;
2272 delta *= io->size;
2273 if (io->in)
ad312c7c 2274 vcpu->arch.regs[VCPU_REGS_RDI] += delta;
de7d789a 2275 else
ad312c7c 2276 vcpu->arch.regs[VCPU_REGS_RSI] += delta;
de7d789a
CO		 2277 }
2278
2279 kvm_x86_ops->decache_regs(vcpu);
2280
2281 io->count -= io->cur_count;
2282 io->cur_count = 0;
2283
2284 return 0;
2285}
2286
2287static void kernel_pio(struct kvm_io_device *pio_dev,
2288 struct kvm_vcpu *vcpu,
2289 void *pd)
2290{
2291 /* TODO: String I/O for in kernel device */
2292
2293 mutex_lock(&vcpu->kvm->lock);
ad312c7c
ZX		 2294 if (vcpu->arch.pio.in)
2295 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2296 vcpu->arch.pio.size,
de7d789a
CO		 2297 pd);
2298 else
ad312c7c
ZX		 2299 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2300 vcpu->arch.pio.size,
de7d789a
CO		 2301 pd);
2302 mutex_unlock(&vcpu->kvm->lock);
2303}
2304
2305static void pio_string_write(struct kvm_io_device *pio_dev,
2306 struct kvm_vcpu *vcpu)
2307{
ad312c7c
ZX		 2308 struct kvm_pio_request *io = &vcpu->arch.pio;
2309 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2310 int i;
2311
2312 mutex_lock(&vcpu->kvm->lock);
2313 for (i = 0; i < io->cur_count; i++) {
2314 kvm_iodevice_write(pio_dev, io->port,
2315 io->size,
2316 pd);
2317 pd += io->size;
2318 }
2319 mutex_unlock(&vcpu->kvm->lock);
2320}
2321
2322static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2323 gpa_t addr, int len,
2324 int is_write)
de7d789a 2325{
92760499 2326 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
de7d789a
CO		 2327}
2328
2329int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2330 int size, unsigned port)
2331{
2332 struct kvm_io_device *pio_dev;
2333
2334 vcpu->run->exit_reason = KVM_EXIT_IO;
2335 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2336 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2337 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2338 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2339 vcpu->run->io.port = vcpu->arch.pio.port = port;
2340 vcpu->arch.pio.in = in;
2341 vcpu->arch.pio.string = 0;
2342 vcpu->arch.pio.down = 0;
2343 vcpu->arch.pio.guest_page_offset = 0;
2344 vcpu->arch.pio.rep = 0;
de7d789a 2345
2714d1d3
FEL		 2346 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2347 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2348 handler);
2349 else
2350 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2351 handler);
2352
de7d789a 2353 kvm_x86_ops->cache_regs(vcpu);
ad312c7c 2354 memcpy(vcpu->arch.pio_data, &vcpu->arch.regs[VCPU_REGS_RAX], 4);
de7d789a
CO		 2355
2356 kvm_x86_ops->skip_emulated_instruction(vcpu);
2357
92760499 2358 pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
de7d789a 2359 if (pio_dev) {
ad312c7c 2360 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2361 complete_pio(vcpu);
2362 return 1;
2363 }
2364 return 0;
2365}
2366EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2367
2368int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2369 int size, unsigned long count, int down,
2370 gva_t address, int rep, unsigned port)
2371{
2372 unsigned now, in_page;
2373 int i, ret = 0;
2374 int nr_pages = 1;
2375 struct page *page;
2376 struct kvm_io_device *pio_dev;
2377
2378 vcpu->run->exit_reason = KVM_EXIT_IO;
2379 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2380 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2381 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2382 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2383 vcpu->run->io.port = vcpu->arch.pio.port = port;
2384 vcpu->arch.pio.in = in;
2385 vcpu->arch.pio.string = 1;
2386 vcpu->arch.pio.down = down;
2387 vcpu->arch.pio.guest_page_offset = offset_in_page(address);
2388 vcpu->arch.pio.rep = rep;
de7d789a 2389
2714d1d3
FEL		 2390 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2391 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2392 handler);
2393 else
2394 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2395 handler);
2396
de7d789a
CO		 2397 if (!count) {
2398 kvm_x86_ops->skip_emulated_instruction(vcpu);
2399 return 1;
2400 }
2401
2402 if (!down)
2403 in_page = PAGE_SIZE - offset_in_page(address);
2404 else
2405 in_page = offset_in_page(address) + size;
2406 now = min(count, (unsigned long)in_page / size);
2407 if (!now) {
2408 /*
2409 * String I/O straddles page boundary. Pin two guest pages
2410 * so that we satisfy atomicity constraints. Do just one
2411 * transaction to avoid complexity.
2412 */
2413 nr_pages = 2;
2414 now = 1;
2415 }
2416 if (down) {
2417 /*
2418 * String I/O in reverse. Yuck. Kill the guest, fix later.
2419 */
2420 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2421 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2422 return 1;
2423 }
2424 vcpu->run->io.count = now;
ad312c7c 2425 vcpu->arch.pio.cur_count = now;
de7d789a 2426
ad312c7c 2427 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2428 kvm_x86_ops->skip_emulated_instruction(vcpu);
2429
2430 for (i = 0; i < nr_pages; ++i) {
de7d789a 2431 page = gva_to_page(vcpu, address + i * PAGE_SIZE);
ad312c7c 2432 vcpu->arch.pio.guest_pages[i] = page;
de7d789a 2433 if (!page) {
c1a5d4f9 2434 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2435 free_pio_guest_pages(vcpu);
2436 return 1;
2437 }
2438 }
2439
92760499
LV		 2440 pio_dev = vcpu_find_pio_dev(vcpu, port,
2441 vcpu->arch.pio.cur_count,
2442 !vcpu->arch.pio.in);
ad312c7c 2443 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2444 /* string PIO write */
2445 ret = pio_copy_data(vcpu);
2446 if (ret >= 0 && pio_dev) {
2447 pio_string_write(pio_dev, vcpu);
2448 complete_pio(vcpu);
ad312c7c 2449 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2450 ret = 1;
2451 }
2452 } else if (pio_dev)
2453 pr_unimpl(vcpu, "no string pio read support yet, "
2454 "port %x size %d count %ld\n",
2455 port, size, count);
2456
2457 return ret;
2458}
2459EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2460
f8c16bba 2461int kvm_arch_init(void *opaque)
043405e1 2462{
56c6d28a 2463 int r;
f8c16bba
ZX		 2464 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
2465
f8c16bba
ZX		 2466 if (kvm_x86_ops) {
2467 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 2468 r = -EEXIST;
2469 goto out;
f8c16bba
ZX		 2470 }
2471
2472 if (!ops->cpu_has_kvm_support()) {
2473 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 2474 r = -EOPNOTSUPP;
2475 goto out;
f8c16bba
ZX		 2476 }
2477 if (ops->disabled_by_bios()) {
2478 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 2479 r = -EOPNOTSUPP;
2480 goto out;
f8c16bba
ZX		 2481 }
2482
97db56ce
AK		 2483 r = kvm_mmu_module_init();
2484 if (r)
2485 goto out;
2486
2487 kvm_init_msr_list();
2488
f8c16bba 2489 kvm_x86_ops = ops;
56c6d28a 2490 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 2491 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
2492 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
2493 PT_DIRTY_MASK, PT64_NX_MASK, 0);
f8c16bba 2494 return 0;
56c6d28a
ZX		 2495
2496out:
56c6d28a 2497 return r;
043405e1 2498}
8776e519 2499
f8c16bba
ZX		 2500void kvm_arch_exit(void)
2501{
2502 kvm_x86_ops = NULL;
56c6d28a
ZX		 2503 kvm_mmu_module_exit();
2504}
f8c16bba 2505
8776e519
HB		 2506int kvm_emulate_halt(struct kvm_vcpu *vcpu)
2507{
2508 ++vcpu->stat.halt_exits;
2714d1d3 2509 KVMTRACE_0D(HLT, vcpu, handler);
8776e519 2510 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 2511 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
3200f405 2512 up_read(&vcpu->kvm->slots_lock);
8776e519 2513 kvm_vcpu_block(vcpu);
3200f405 2514 down_read(&vcpu->kvm->slots_lock);
a4535290 2515 if (vcpu->arch.mp_state != KVM_MP_STATE_RUNNABLE)
8776e519
HB		 2516 return -EINTR;
2517 return 1;
2518 } else {
2519 vcpu->run->exit_reason = KVM_EXIT_HLT;
2520 return 0;
2521 }
2522}
2523EXPORT_SYMBOL_GPL(kvm_emulate_halt);
2524
2f333bcb
MT		 2525static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
2526 unsigned long a1)
2527{
2528 if (is_long_mode(vcpu))
2529 return a0;
2530 else
2531 return a0 | ((gpa_t)a1 << 32);
2532}
2533
8776e519
HB		 2534int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
2535{
2536 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 2537 int r = 1;
8776e519
HB		 2538
2539 kvm_x86_ops->cache_regs(vcpu);
2540
ad312c7c
ZX		 2541 nr = vcpu->arch.regs[VCPU_REGS_RAX];
2542 a0 = vcpu->arch.regs[VCPU_REGS_RBX];
2543 a1 = vcpu->arch.regs[VCPU_REGS_RCX];
2544 a2 = vcpu->arch.regs[VCPU_REGS_RDX];
2545 a3 = vcpu->arch.regs[VCPU_REGS_RSI];
8776e519 2546
2714d1d3
FEL		 2547 KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
2548
8776e519
HB		 2549 if (!is_long_mode(vcpu)) {
2550 nr &= 0xFFFFFFFF;
2551 a0 &= 0xFFFFFFFF;
2552 a1 &= 0xFFFFFFFF;
2553 a2 &= 0xFFFFFFFF;
2554 a3 &= 0xFFFFFFFF;
2555 }
2556
2557 switch (nr) {
b93463aa
AK		 2558 case KVM_HC_VAPIC_POLL_IRQ:
2559 ret = 0;
2560 break;
2f333bcb
MT		 2561 case KVM_HC_MMU_OP:
2562 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
2563 break;
8776e519
HB		 2564 default:
2565 ret = -KVM_ENOSYS;
2566 break;
2567 }
ad312c7c 2568 vcpu->arch.regs[VCPU_REGS_RAX] = ret;
8776e519 2569 kvm_x86_ops->decache_regs(vcpu);
f11c3a8d 2570 ++vcpu->stat.hypercalls;
2f333bcb 2571 return r;
8776e519
HB		 2572}
2573EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
2574
2575int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
2576{
2577 char instruction[3];
2578 int ret = 0;
2579
8776e519
HB		 2580
2581 /*
2582 * Blow out the MMU to ensure that no other VCPU has an active mapping
2583 * to ensure that the updated hypercall appears atomically across all
2584 * VCPUs.
2585 */
2586 kvm_mmu_zap_all(vcpu->kvm);
2587
2588 kvm_x86_ops->cache_regs(vcpu);
2589 kvm_x86_ops->patch_hypercall(vcpu, instruction);
ad312c7c 2590 if (emulator_write_emulated(vcpu->arch.rip, instruction, 3, vcpu)
8776e519
HB		 2591 != X86EMUL_CONTINUE)
2592 ret = -EFAULT;
2593
8776e519
HB		 2594 return ret;
2595}
2596
2597static u64 mk_cr_64(u64 curr_cr, u32 new_val)
2598{
2599 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
2600}
2601
2602void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2603{
2604 struct descriptor_table dt = { limit, base };
2605
2606 kvm_x86_ops->set_gdt(vcpu, &dt);
2607}
2608
2609void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2610{
2611 struct descriptor_table dt = { limit, base };
2612
2613 kvm_x86_ops->set_idt(vcpu, &dt);
2614}
2615
2616void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
2617 unsigned long *rflags)
2618{
2d3ad1f4 2619 kvm_lmsw(vcpu, msw);
8776e519
HB		 2620 *rflags = kvm_x86_ops->get_rflags(vcpu);
2621}
2622
2623unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
2624{
54e445ca
JR		 2625 unsigned long value;
2626
8776e519
HB		 2627 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
2628 switch (cr) {
2629 case 0:
54e445ca
JR		 2630 value = vcpu->arch.cr0;
2631 break;
8776e519 2632 case 2:
54e445ca
JR		 2633 value = vcpu->arch.cr2;
2634 break;
8776e519 2635 case 3:
54e445ca
JR		 2636 value = vcpu->arch.cr3;
2637 break;
8776e519 2638 case 4:
54e445ca
JR		 2639 value = vcpu->arch.cr4;
2640 break;
152ff9be 2641 case 8:
54e445ca
JR		 2642 value = kvm_get_cr8(vcpu);
2643 break;
8776e519 2644 default:
b8688d51 2645 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2646 return 0;
2647 }
54e445ca
JR		 2648 KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value,
2649 (u32)((u64)value >> 32), handler);
2650
2651 return value;
8776e519
HB		 2652}
2653
2654void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
2655 unsigned long *rflags)
2656{
54e445ca
JR		 2657 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val,
2658 (u32)((u64)val >> 32), handler);
2659
8776e519
HB		 2660 switch (cr) {
2661 case 0:
2d3ad1f4 2662 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 2663 *rflags = kvm_x86_ops->get_rflags(vcpu);
2664 break;
2665 case 2:
ad312c7c 2666 vcpu->arch.cr2 = val;
8776e519
HB		 2667 break;
2668 case 3:
2d3ad1f4 2669 kvm_set_cr3(vcpu, val);
8776e519
HB		 2670 break;
2671 case 4:
2d3ad1f4 2672 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 2673 break;
152ff9be 2674 case 8:
2d3ad1f4 2675 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 2676 break;
8776e519 2677 default:
b8688d51 2678 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2679 }
2680}
2681
07716717
DK		 2682static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
2683{
ad312c7c
ZX		 2684 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
2685 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 2686
2687 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
2688 /* when no next entry is found, the current entry[i] is reselected */
2689 for (j = i + 1; j == i; j = (j + 1) % nent) {
ad312c7c 2690 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 2691 if (ej->function == e->function) {
2692 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2693 return j;
2694 }
2695 }
2696 return 0; /* silence gcc, even though control never reaches here */
2697}
2698
2699/* find an entry with matching function, matching index (if needed), and that
2700 * should be read next (if it's stateful) */
2701static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
2702 u32 function, u32 index)
2703{
2704 if (e->function != function)
2705 return 0;
2706 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
2707 return 0;
2708 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
2709 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
2710 return 0;
2711 return 1;
2712}
2713
8776e519
HB		 2714void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
2715{
2716 int i;
07716717
DK		 2717 u32 function, index;
2718 struct kvm_cpuid_entry2 *e, *best;
8776e519
HB		 2719
2720 kvm_x86_ops->cache_regs(vcpu);
ad312c7c
ZX		 2721 function = vcpu->arch.regs[VCPU_REGS_RAX];
2722 index = vcpu->arch.regs[VCPU_REGS_RCX];
2723 vcpu->arch.regs[VCPU_REGS_RAX] = 0;
2724 vcpu->arch.regs[VCPU_REGS_RBX] = 0;
2725 vcpu->arch.regs[VCPU_REGS_RCX] = 0;
2726 vcpu->arch.regs[VCPU_REGS_RDX] = 0;
8776e519 2727 best = NULL;
ad312c7c
ZX		 2728 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2729 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 2730 if (is_matching_cpuid_entry(e, function, index)) {
2731 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
2732 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 2733 best = e;
2734 break;
2735 }
2736 /*
2737 * Both basic or both extended?
2738 */
2739 if (((e->function ^ function) & 0x80000000) == 0)
2740 if (!best || e->function > best->function)
2741 best = e;
2742 }
2743 if (best) {
ad312c7c
ZX		 2744 vcpu->arch.regs[VCPU_REGS_RAX] = best->eax;
2745 vcpu->arch.regs[VCPU_REGS_RBX] = best->ebx;
2746 vcpu->arch.regs[VCPU_REGS_RCX] = best->ecx;
2747 vcpu->arch.regs[VCPU_REGS_RDX] = best->edx;
8776e519
HB		 2748 }
2749 kvm_x86_ops->decache_regs(vcpu);
2750 kvm_x86_ops->skip_emulated_instruction(vcpu);
2714d1d3
FEL		 2751 KVMTRACE_5D(CPUID, vcpu, function,
2752 (u32)vcpu->arch.regs[VCPU_REGS_RAX],
2753 (u32)vcpu->arch.regs[VCPU_REGS_RBX],
2754 (u32)vcpu->arch.regs[VCPU_REGS_RCX],
2755 (u32)vcpu->arch.regs[VCPU_REGS_RDX], handler);
8776e519
HB		 2756}
2757EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 2758
b6c7a5dc
HB		 2759/*
2760 * Check if userspace requested an interrupt window, and that the
2761 * interrupt window is open.
2762 *
2763 * No need to exit to userspace if we already have an interrupt queued.
2764 */
2765static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
2766 struct kvm_run *kvm_run)
2767{
ad312c7c 2768 return (!vcpu->arch.irq_summary &&
b6c7a5dc 2769 kvm_run->request_interrupt_window &&
ad312c7c 2770 vcpu->arch.interrupt_window_open &&
b6c7a5dc
HB		 2771 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF));
2772}
2773
2774static void post_kvm_run_save(struct kvm_vcpu *vcpu,
2775 struct kvm_run *kvm_run)
2776{
2777 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 2778 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc
HB		 2779 kvm_run->apic_base = kvm_get_apic_base(vcpu);
2780 if (irqchip_in_kernel(vcpu->kvm))
2781 kvm_run->ready_for_interrupt_injection = 1;
2782 else
2783 kvm_run->ready_for_interrupt_injection =
ad312c7c
ZX		 2784 (vcpu->arch.interrupt_window_open &&
2785 vcpu->arch.irq_summary == 0);
b6c7a5dc
HB		 2786}
2787
b93463aa
AK		 2788static void vapic_enter(struct kvm_vcpu *vcpu)
2789{
2790 struct kvm_lapic *apic = vcpu->arch.apic;
2791 struct page *page;
2792
2793 if (!apic || !apic->vapic_addr)
2794 return;
2795
10589a46 2796 down_read(&current->mm->mmap_sem);
b93463aa 2797 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
10589a46 2798 up_read(&current->mm->mmap_sem);
72dc67a6
IE		 2799
2800 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 2801}
2802
2803static void vapic_exit(struct kvm_vcpu *vcpu)
2804{
2805 struct kvm_lapic *apic = vcpu->arch.apic;
2806
2807 if (!apic || !apic->vapic_addr)
2808 return;
2809
2810 kvm_release_page_dirty(apic->vapic_page);
2811 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
2812}
2813
b6c7a5dc
HB		 2814static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2815{
2816 int r;
2817
a4535290 2818 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
b6c7a5dc 2819 pr_debug("vcpu %d received sipi with vector # %x\n",
ad312c7c 2820 vcpu->vcpu_id, vcpu->arch.sipi_vector);
b6c7a5dc
HB		 2821 kvm_lapic_reset(vcpu);
2822 r = kvm_x86_ops->vcpu_reset(vcpu);
2823 if (r)
2824 return r;
a4535290 2825 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 2826 }
2827
3200f405 2828 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2829 vapic_enter(vcpu);
2830
b6c7a5dc
HB		 2831preempted:
2832 if (vcpu->guest_debug.enabled)
2833 kvm_x86_ops->guest_debug_pre(vcpu);
2834
2835again:
2e53d63a
MT		 2836 if (vcpu->requests)
2837 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
2838 kvm_mmu_unload(vcpu);
2839
b6c7a5dc
HB		 2840 r = kvm_mmu_reload(vcpu);
2841 if (unlikely(r))
2842 goto out;
2843
2f52d58c
AK		 2844 if (vcpu->requests) {
2845 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 2846 __kvm_migrate_timers(vcpu);
d4acf7e7
MT		 2847 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
2848 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 2849 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
2850 &vcpu->requests)) {
2851 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
2852 r = 0;
2853 goto out;
2854 }
71c4dfaf
JR		 2855 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
2856 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2857 r = 0;
2858 goto out;
2859 }
2f52d58c 2860 }
b93463aa 2861
06e05645 2862 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
b6c7a5dc
HB		 2863 kvm_inject_pending_timer_irqs(vcpu);
2864
2865 preempt_disable();
2866
2867 kvm_x86_ops->prepare_guest_switch(vcpu);
2868 kvm_load_guest_fpu(vcpu);
2869
2870 local_irq_disable();
2871
d4acf7e7 2872 if (vcpu->requests || need_resched()) {
6c142801
AK		 2873 local_irq_enable();
2874 preempt_enable();
2875 r = 1;
2876 goto out;
2877 }
2878
b6c7a5dc
HB		 2879 if (signal_pending(current)) {
2880 local_irq_enable();
2881 preempt_enable();
2882 r = -EINTR;
2883 kvm_run->exit_reason = KVM_EXIT_INTR;
2884 ++vcpu->stat.signal_exits;
2885 goto out;
2886 }
2887
e9571ed5
MT		 2888 vcpu->guest_mode = 1;
2889 /*
2890 * Make sure that guest_mode assignment won't happen after
2891 * testing the pending IRQ vector bitmap.
2892 */
2893 smp_wmb();
2894
ad312c7c 2895 if (vcpu->arch.exception.pending)
298101da
AK		 2896 __queue_exception(vcpu);
2897 else if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 2898 kvm_x86_ops->inject_pending_irq(vcpu);
eb9774f0 2899 else
b6c7a5dc
HB		 2900 kvm_x86_ops->inject_pending_vectors(vcpu, kvm_run);
2901
b93463aa
AK		 2902 kvm_lapic_sync_to_vapic(vcpu);
2903
3200f405
MT		 2904 up_read(&vcpu->kvm->slots_lock);
2905
b6c7a5dc
HB		 2906 kvm_guest_enter();
2907
b6c7a5dc 2908
2714d1d3 2909 KVMTRACE_0D(VMENTRY, vcpu, entryexit);
b6c7a5dc
HB		 2910 kvm_x86_ops->run(vcpu, kvm_run);
2911
2912 vcpu->guest_mode = 0;
2913 local_irq_enable();
2914
2915 ++vcpu->stat.exits;
2916
2917 /*
2918 * We must have an instruction between local_irq_enable() and
2919 * kvm_guest_exit(), so the timer interrupt isn't delayed by
2920 * the interrupt shadow. The stat.exits increment will do nicely.
2921 * But we need to prevent reordering, hence this barrier():
2922 */
2923 barrier();
2924
2925 kvm_guest_exit();
2926
2927 preempt_enable();
2928
3200f405
MT		 2929 down_read(&vcpu->kvm->slots_lock);
2930
b6c7a5dc
HB		 2931 /*
2932 * Profile KVM exit RIPs:
2933 */
2934 if (unlikely(prof_on == KVM_PROFILING)) {
2935 kvm_x86_ops->cache_regs(vcpu);
ad312c7c 2936 profile_hit(KVM_PROFILING, (void *)vcpu->arch.rip);
b6c7a5dc
HB		 2937 }
2938
ad312c7c
ZX		 2939 if (vcpu->arch.exception.pending && kvm_x86_ops->exception_injected(vcpu))
2940 vcpu->arch.exception.pending = false;
298101da 2941
b93463aa
AK		 2942 kvm_lapic_sync_from_vapic(vcpu);
2943
b6c7a5dc
HB		 2944 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
2945
2946 if (r > 0) {
2947 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
2948 r = -EINTR;
2949 kvm_run->exit_reason = KVM_EXIT_INTR;
2950 ++vcpu->stat.request_irq_exits;
2951 goto out;
2952 }
e1beb1d3 2953 if (!need_resched())
b6c7a5dc 2954 goto again;
b6c7a5dc
HB		 2955 }
2956
2957out:
3200f405 2958 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 2959 if (r > 0) {
2960 kvm_resched(vcpu);
3200f405 2961 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 2962 goto preempted;
2963 }
2964
2965 post_kvm_run_save(vcpu, kvm_run);
2966
3200f405 2967 down_read(&vcpu->kvm->slots_lock);
b93463aa 2968 vapic_exit(vcpu);
3200f405 2969 up_read(&vcpu->kvm->slots_lock);
b93463aa 2970
b6c7a5dc
HB		 2971 return r;
2972}
2973
2974int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2975{
2976 int r;
2977 sigset_t sigsaved;
2978
2979 vcpu_load(vcpu);
2980
a4535290 2981 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc
HB		 2982 kvm_vcpu_block(vcpu);
2983 vcpu_put(vcpu);
2984 return -EAGAIN;
2985 }
2986
2987 if (vcpu->sigset_active)
2988 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
2989
2990 /* re-sync apic's tpr */
2991 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 2992 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 2993
ad312c7c 2994 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 2995 r = complete_pio(vcpu);
2996 if (r)
2997 goto out;
2998 }
2999#if CONFIG_HAS_IOMEM
3000 if (vcpu->mmio_needed) {
3001 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3002 vcpu->mmio_read_completed = 1;
3003 vcpu->mmio_needed = 0;
3200f405
MT		 3004
3005 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3006 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3007 vcpu->arch.mmio_fault_cr2, 0,
3008 EMULTYPE_NO_DECODE);
3200f405 3009 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3010 if (r == EMULATE_DO_MMIO) {
3011 /*
3012 * Read-modify-write. Back to userspace.
3013 */
3014 r = 0;
3015 goto out;
3016 }
3017 }
3018#endif
3019 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL) {
3020 kvm_x86_ops->cache_regs(vcpu);
ad312c7c 3021 vcpu->arch.regs[VCPU_REGS_RAX] = kvm_run->hypercall.ret;
b6c7a5dc
HB		 3022 kvm_x86_ops->decache_regs(vcpu);
3023 }
3024
3025 r = __vcpu_run(vcpu, kvm_run);
3026
3027out:
3028 if (vcpu->sigset_active)
3029 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3030
3031 vcpu_put(vcpu);
3032 return r;
3033}
3034
3035int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3036{
3037 vcpu_load(vcpu);
3038
3039 kvm_x86_ops->cache_regs(vcpu);
3040
ad312c7c
ZX		 3041 regs->rax = vcpu->arch.regs[VCPU_REGS_RAX];
3042 regs->rbx = vcpu->arch.regs[VCPU_REGS_RBX];
3043 regs->rcx = vcpu->arch.regs[VCPU_REGS_RCX];
3044 regs->rdx = vcpu->arch.regs[VCPU_REGS_RDX];
3045 regs->rsi = vcpu->arch.regs[VCPU_REGS_RSI];
3046 regs->rdi = vcpu->arch.regs[VCPU_REGS_RDI];
3047 regs->rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3048 regs->rbp = vcpu->arch.regs[VCPU_REGS_RBP];
b6c7a5dc 3049#ifdef CONFIG_X86_64
ad312c7c
ZX		 3050 regs->r8 = vcpu->arch.regs[VCPU_REGS_R8];
3051 regs->r9 = vcpu->arch.regs[VCPU_REGS_R9];
3052 regs->r10 = vcpu->arch.regs[VCPU_REGS_R10];
3053 regs->r11 = vcpu->arch.regs[VCPU_REGS_R11];
3054 regs->r12 = vcpu->arch.regs[VCPU_REGS_R12];
3055 regs->r13 = vcpu->arch.regs[VCPU_REGS_R13];
3056 regs->r14 = vcpu->arch.regs[VCPU_REGS_R14];
3057 regs->r15 = vcpu->arch.regs[VCPU_REGS_R15];
b6c7a5dc
HB		 3058#endif
3059
ad312c7c 3060 regs->rip = vcpu->arch.rip;
b6c7a5dc
HB		 3061 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3062
3063 /*
3064 * Don't leak debug flags in case they were set for guest debugging
3065 */
3066 if (vcpu->guest_debug.enabled && vcpu->guest_debug.singlestep)
3067 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3068
3069 vcpu_put(vcpu);
3070
3071 return 0;
3072}
3073
3074int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3075{
3076 vcpu_load(vcpu);
3077
ad312c7c
ZX		 3078 vcpu->arch.regs[VCPU_REGS_RAX] = regs->rax;
3079 vcpu->arch.regs[VCPU_REGS_RBX] = regs->rbx;
3080 vcpu->arch.regs[VCPU_REGS_RCX] = regs->rcx;
3081 vcpu->arch.regs[VCPU_REGS_RDX] = regs->rdx;
3082 vcpu->arch.regs[VCPU_REGS_RSI] = regs->rsi;
3083 vcpu->arch.regs[VCPU_REGS_RDI] = regs->rdi;
3084 vcpu->arch.regs[VCPU_REGS_RSP] = regs->rsp;
3085 vcpu->arch.regs[VCPU_REGS_RBP] = regs->rbp;
b6c7a5dc 3086#ifdef CONFIG_X86_64
ad312c7c
ZX		 3087 vcpu->arch.regs[VCPU_REGS_R8] = regs->r8;
3088 vcpu->arch.regs[VCPU_REGS_R9] = regs->r9;
3089 vcpu->arch.regs[VCPU_REGS_R10] = regs->r10;
3090 vcpu->arch.regs[VCPU_REGS_R11] = regs->r11;
3091 vcpu->arch.regs[VCPU_REGS_R12] = regs->r12;
3092 vcpu->arch.regs[VCPU_REGS_R13] = regs->r13;
3093 vcpu->arch.regs[VCPU_REGS_R14] = regs->r14;
3094 vcpu->arch.regs[VCPU_REGS_R15] = regs->r15;
b6c7a5dc
HB		 3095#endif
3096
ad312c7c 3097 vcpu->arch.rip = regs->rip;
b6c7a5dc
HB		 3098 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3099
3100 kvm_x86_ops->decache_regs(vcpu);
3101
b4f14abd
JK		 3102 vcpu->arch.exception.pending = false;
3103
b6c7a5dc
HB		 3104 vcpu_put(vcpu);
3105
3106 return 0;
3107}
3108
3e6e0aab
GT		 3109void kvm_get_segment(struct kvm_vcpu *vcpu,
3110 struct kvm_segment *var, int seg)
b6c7a5dc 3111{
14af3f3c 3112 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3113}
3114
3115void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3116{
3117 struct kvm_segment cs;
3118
3e6e0aab 3119 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3120 *db = cs.db;
3121 *l = cs.l;
3122}
3123EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3124
3125int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3126 struct kvm_sregs *sregs)
3127{
3128 struct descriptor_table dt;
3129 int pending_vec;
3130
3131 vcpu_load(vcpu);
3132
3e6e0aab
GT		 3133 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3134 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3135 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3136 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3137 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3138 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3139
3e6e0aab
GT		 3140 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3141 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3142
3143 kvm_x86_ops->get_idt(vcpu, &dt);
3144 sregs->idt.limit = dt.limit;
3145 sregs->idt.base = dt.base;
3146 kvm_x86_ops->get_gdt(vcpu, &dt);
3147 sregs->gdt.limit = dt.limit;
3148 sregs->gdt.base = dt.base;
3149
3150 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3151 sregs->cr0 = vcpu->arch.cr0;
3152 sregs->cr2 = vcpu->arch.cr2;
3153 sregs->cr3 = vcpu->arch.cr3;
3154 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3155 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3156 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3157 sregs->apic_base = kvm_get_apic_base(vcpu);
3158
3159 if (irqchip_in_kernel(vcpu->kvm)) {
3160 memset(sregs->interrupt_bitmap, 0,
3161 sizeof sregs->interrupt_bitmap);
3162 pending_vec = kvm_x86_ops->get_irq(vcpu);
3163 if (pending_vec >= 0)
3164 set_bit(pending_vec,
3165 (unsigned long *)sregs->interrupt_bitmap);
3166 } else
ad312c7c 3167 memcpy(sregs->interrupt_bitmap, vcpu->arch.irq_pending,
b6c7a5dc
HB		 3168 sizeof sregs->interrupt_bitmap);
3169
3170 vcpu_put(vcpu);
3171
3172 return 0;
3173}
3174
62d9f0db
MT		 3175int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3176 struct kvm_mp_state *mp_state)
3177{
3178 vcpu_load(vcpu);
3179 mp_state->mp_state = vcpu->arch.mp_state;
3180 vcpu_put(vcpu);
3181 return 0;
3182}
3183
3184int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3185 struct kvm_mp_state *mp_state)
3186{
3187 vcpu_load(vcpu);
3188 vcpu->arch.mp_state = mp_state->mp_state;
3189 vcpu_put(vcpu);
3190 return 0;
3191}
3192
3e6e0aab 3193static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3194 struct kvm_segment *var, int seg)
3195{
14af3f3c 3196 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3197}
3198
37817f29
IE		 3199static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3200 struct kvm_segment *kvm_desct)
3201{
3202 kvm_desct->base = seg_desc->base0;
3203 kvm_desct->base |= seg_desc->base1 << 16;
3204 kvm_desct->base |= seg_desc->base2 << 24;
3205 kvm_desct->limit = seg_desc->limit0;
3206 kvm_desct->limit |= seg_desc->limit << 16;
3207 kvm_desct->selector = selector;
3208 kvm_desct->type = seg_desc->type;
3209 kvm_desct->present = seg_desc->p;
3210 kvm_desct->dpl = seg_desc->dpl;
3211 kvm_desct->db = seg_desc->d;
3212 kvm_desct->s = seg_desc->s;
3213 kvm_desct->l = seg_desc->l;
3214 kvm_desct->g = seg_desc->g;
3215 kvm_desct->avl = seg_desc->avl;
3216 if (!selector)
3217 kvm_desct->unusable = 1;
3218 else
3219 kvm_desct->unusable = 0;
3220 kvm_desct->padding = 0;
3221}
3222
3223static void get_segment_descritptor_dtable(struct kvm_vcpu *vcpu,
3224 u16 selector,
3225 struct descriptor_table *dtable)
3226{
3227 if (selector & 1 << 2) {
3228 struct kvm_segment kvm_seg;
3229
3e6e0aab 3230 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3231
3232 if (kvm_seg.unusable)
3233 dtable->limit = 0;
3234 else
3235 dtable->limit = kvm_seg.limit;
3236 dtable->base = kvm_seg.base;
3237 }
3238 else
3239 kvm_x86_ops->get_gdt(vcpu, dtable);
3240}
3241
3242/* allowed just for 8 bytes segments */
3243static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3244 struct desc_struct *seg_desc)
3245{
3246 struct descriptor_table dtable;
3247 u16 index = selector >> 3;
3248
3249 get_segment_descritptor_dtable(vcpu, selector, &dtable);
3250
3251 if (dtable.limit < index * 8 + 7) {
3252 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3253 return 1;
3254 }
3255 return kvm_read_guest(vcpu->kvm, dtable.base + index * 8, seg_desc, 8);
3256}
3257
3258/* allowed just for 8 bytes segments */
3259static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3260 struct desc_struct *seg_desc)
3261{
3262 struct descriptor_table dtable;
3263 u16 index = selector >> 3;
3264
3265 get_segment_descritptor_dtable(vcpu, selector, &dtable);
3266
3267 if (dtable.limit < index * 8 + 7)
3268 return 1;
3269 return kvm_write_guest(vcpu->kvm, dtable.base + index * 8, seg_desc, 8);
3270}
3271
3272static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3273 struct desc_struct *seg_desc)
3274{
3275 u32 base_addr;
3276
3277 base_addr = seg_desc->base0;
3278 base_addr |= (seg_desc->base1 << 16);
3279 base_addr |= (seg_desc->base2 << 24);
3280
3281 return base_addr;
3282}
3283
3284static int load_tss_segment32(struct kvm_vcpu *vcpu,
3285 struct desc_struct *seg_desc,
3286 struct tss_segment_32 *tss)
3287{
3288 u32 base_addr;
3289
3290 base_addr = get_tss_base_addr(vcpu, seg_desc);
3291
3292 return kvm_read_guest(vcpu->kvm, base_addr, tss,
3293 sizeof(struct tss_segment_32));
3294}
3295
3296static int save_tss_segment32(struct kvm_vcpu *vcpu,
3297 struct desc_struct *seg_desc,
3298 struct tss_segment_32 *tss)
3299{
3300 u32 base_addr;
3301
3302 base_addr = get_tss_base_addr(vcpu, seg_desc);
3303
3304 return kvm_write_guest(vcpu->kvm, base_addr, tss,
3305 sizeof(struct tss_segment_32));
3306}
3307
3308static int load_tss_segment16(struct kvm_vcpu *vcpu,
3309 struct desc_struct *seg_desc,
3310 struct tss_segment_16 *tss)
3311{
3312 u32 base_addr;
3313
3314 base_addr = get_tss_base_addr(vcpu, seg_desc);
3315
3316 return kvm_read_guest(vcpu->kvm, base_addr, tss,
3317 sizeof(struct tss_segment_16));
3318}
3319
3320static int save_tss_segment16(struct kvm_vcpu *vcpu,
3321 struct desc_struct *seg_desc,
3322 struct tss_segment_16 *tss)
3323{
3324 u32 base_addr;
3325
3326 base_addr = get_tss_base_addr(vcpu, seg_desc);
3327
3328 return kvm_write_guest(vcpu->kvm, base_addr, tss,
3329 sizeof(struct tss_segment_16));
3330}
3331
3332static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3333{
3334 struct kvm_segment kvm_seg;
3335
3e6e0aab 3336 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3337 return kvm_seg.selector;
3338}
3339
3340static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3341 u16 selector,
3342 struct kvm_segment *kvm_seg)
3343{
3344 struct desc_struct seg_desc;
3345
3346 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3347 return 1;
3348 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3349 return 0;
3350}
3351
3e6e0aab
GT		 3352int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3353 int type_bits, int seg)
37817f29
IE		 3354{
3355 struct kvm_segment kvm_seg;
3356
3357 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
3358 return 1;
3359 kvm_seg.type |= type_bits;
3360
3361 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
3362 seg != VCPU_SREG_LDTR)
3363 if (!kvm_seg.s)
3364 kvm_seg.unusable = 1;
3365
3e6e0aab 3366 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3367 return 0;
3368}
3369
3370static void save_state_to_tss32(struct kvm_vcpu *vcpu,
3371 struct tss_segment_32 *tss)
3372{
3373 tss->cr3 = vcpu->arch.cr3;
3374 tss->eip = vcpu->arch.rip;
3375 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
3376 tss->eax = vcpu->arch.regs[VCPU_REGS_RAX];
3377 tss->ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3378 tss->edx = vcpu->arch.regs[VCPU_REGS_RDX];
3379 tss->ebx = vcpu->arch.regs[VCPU_REGS_RBX];
3380 tss->esp = vcpu->arch.regs[VCPU_REGS_RSP];
3381 tss->ebp = vcpu->arch.regs[VCPU_REGS_RBP];
3382 tss->esi = vcpu->arch.regs[VCPU_REGS_RSI];
3383 tss->edi = vcpu->arch.regs[VCPU_REGS_RDI];
3384
3385 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3386 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3387 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3388 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3389 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
3390 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
3391 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3392 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3393}
3394
3395static int load_state_from_tss32(struct kvm_vcpu *vcpu,
3396 struct tss_segment_32 *tss)
3397{
3398 kvm_set_cr3(vcpu, tss->cr3);
3399
3400 vcpu->arch.rip = tss->eip;
3401 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
3402
3403 vcpu->arch.regs[VCPU_REGS_RAX] = tss->eax;
3404 vcpu->arch.regs[VCPU_REGS_RCX] = tss->ecx;
3405 vcpu->arch.regs[VCPU_REGS_RDX] = tss->edx;
3406 vcpu->arch.regs[VCPU_REGS_RBX] = tss->ebx;
3407 vcpu->arch.regs[VCPU_REGS_RSP] = tss->esp;
3408 vcpu->arch.regs[VCPU_REGS_RBP] = tss->ebp;
3409 vcpu->arch.regs[VCPU_REGS_RSI] = tss->esi;
3410 vcpu->arch.regs[VCPU_REGS_RDI] = tss->edi;
3411
3e6e0aab 3412 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 3413 return 1;
3414
3e6e0aab 3415 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3416 return 1;
3417
3e6e0aab 3418 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3419 return 1;
3420
3e6e0aab 3421 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3422 return 1;
3423
3e6e0aab 3424 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3425 return 1;
3426
3e6e0aab 3427 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 3428 return 1;
3429
3e6e0aab 3430 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 3431 return 1;
3432 return 0;
3433}
3434
3435static void save_state_to_tss16(struct kvm_vcpu *vcpu,
3436 struct tss_segment_16 *tss)
3437{
3438 tss->ip = vcpu->arch.rip;
3439 tss->flag = kvm_x86_ops->get_rflags(vcpu);
3440 tss->ax = vcpu->arch.regs[VCPU_REGS_RAX];
3441 tss->cx = vcpu->arch.regs[VCPU_REGS_RCX];
3442 tss->dx = vcpu->arch.regs[VCPU_REGS_RDX];
3443 tss->bx = vcpu->arch.regs[VCPU_REGS_RBX];
3444 tss->sp = vcpu->arch.regs[VCPU_REGS_RSP];
3445 tss->bp = vcpu->arch.regs[VCPU_REGS_RBP];
3446 tss->si = vcpu->arch.regs[VCPU_REGS_RSI];
3447 tss->di = vcpu->arch.regs[VCPU_REGS_RDI];
3448
3449 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3450 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3451 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3452 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3453 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3454 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3455}
3456
3457static int load_state_from_tss16(struct kvm_vcpu *vcpu,
3458 struct tss_segment_16 *tss)
3459{
3460 vcpu->arch.rip = tss->ip;
3461 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
3462 vcpu->arch.regs[VCPU_REGS_RAX] = tss->ax;
3463 vcpu->arch.regs[VCPU_REGS_RCX] = tss->cx;
3464 vcpu->arch.regs[VCPU_REGS_RDX] = tss->dx;
3465 vcpu->arch.regs[VCPU_REGS_RBX] = tss->bx;
3466 vcpu->arch.regs[VCPU_REGS_RSP] = tss->sp;
3467 vcpu->arch.regs[VCPU_REGS_RBP] = tss->bp;
3468 vcpu->arch.regs[VCPU_REGS_RSI] = tss->si;
3469 vcpu->arch.regs[VCPU_REGS_RDI] = tss->di;
3470
3e6e0aab 3471 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 3472 return 1;
3473
3e6e0aab 3474 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3475 return 1;
3476
3e6e0aab 3477 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3478 return 1;
3479
3e6e0aab 3480 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3481 return 1;
3482
3e6e0aab 3483 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3484 return 1;
3485 return 0;
3486}
3487
8b2cf73c 3488static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
37817f29
IE		 3489 struct desc_struct *cseg_desc,
3490 struct desc_struct *nseg_desc)
3491{
3492 struct tss_segment_16 tss_segment_16;
3493 int ret = 0;
3494
3495 if (load_tss_segment16(vcpu, cseg_desc, &tss_segment_16))
3496 goto out;
3497
3498 save_state_to_tss16(vcpu, &tss_segment_16);
3499 save_tss_segment16(vcpu, cseg_desc, &tss_segment_16);
3500
3501 if (load_tss_segment16(vcpu, nseg_desc, &tss_segment_16))
3502 goto out;
3503 if (load_state_from_tss16(vcpu, &tss_segment_16))
3504 goto out;
3505
3506 ret = 1;
3507out:
3508 return ret;
3509}
3510
8b2cf73c 3511static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
37817f29
IE		 3512 struct desc_struct *cseg_desc,
3513 struct desc_struct *nseg_desc)
3514{
3515 struct tss_segment_32 tss_segment_32;
3516 int ret = 0;
3517
3518 if (load_tss_segment32(vcpu, cseg_desc, &tss_segment_32))
3519 goto out;
3520
3521 save_state_to_tss32(vcpu, &tss_segment_32);
3522 save_tss_segment32(vcpu, cseg_desc, &tss_segment_32);
3523
3524 if (load_tss_segment32(vcpu, nseg_desc, &tss_segment_32))
3525 goto out;
3526 if (load_state_from_tss32(vcpu, &tss_segment_32))
3527 goto out;
3528
3529 ret = 1;
3530out:
3531 return ret;
3532}
3533
3534int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
3535{
3536 struct kvm_segment tr_seg;
3537 struct desc_struct cseg_desc;
3538 struct desc_struct nseg_desc;
3539 int ret = 0;
3540
3e6e0aab 3541 kvm_get_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29
IE		 3542
3543 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
3544 goto out;
3545
3546 if (load_guest_segment_descriptor(vcpu, tr_seg.selector, &cseg_desc))
3547 goto out;
3548
3549
3550 if (reason != TASK_SWITCH_IRET) {
3551 int cpl;
3552
3553 cpl = kvm_x86_ops->get_cpl(vcpu);
3554 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
3555 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
3556 return 1;
3557 }
3558 }
3559
3560 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
3561 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
3562 return 1;
3563 }
3564
3565 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 3566 cseg_desc.type &= ~(1 << 1); //clear the B flag
37817f29
IE		 3567 save_guest_segment_descriptor(vcpu, tr_seg.selector,
3568 &cseg_desc);
3569 }
3570
3571 if (reason == TASK_SWITCH_IRET) {
3572 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3573 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
3574 }
3575
3576 kvm_x86_ops->skip_emulated_instruction(vcpu);
3577 kvm_x86_ops->cache_regs(vcpu);
3578
3579 if (nseg_desc.type & 8)
3580 ret = kvm_task_switch_32(vcpu, tss_selector, &cseg_desc,
3581 &nseg_desc);
3582 else
3583 ret = kvm_task_switch_16(vcpu, tss_selector, &cseg_desc,
3584 &nseg_desc);
3585
3586 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
3587 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3588 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
3589 }
3590
3591 if (reason != TASK_SWITCH_IRET) {
3fe913e7 3592 nseg_desc.type |= (1 << 1);
37817f29
IE		 3593 save_guest_segment_descriptor(vcpu, tss_selector,
3594 &nseg_desc);
3595 }
3596
3597 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
3598 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
3599 tr_seg.type = 11;
3e6e0aab 3600 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29
IE		 3601out:
3602 kvm_x86_ops->decache_regs(vcpu);
3603 return ret;
3604}
3605EXPORT_SYMBOL_GPL(kvm_task_switch);
3606
b6c7a5dc
HB		 3607int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
3608 struct kvm_sregs *sregs)
3609{
3610 int mmu_reset_needed = 0;
3611 int i, pending_vec, max_bits;
3612 struct descriptor_table dt;
3613
3614 vcpu_load(vcpu);
3615
3616 dt.limit = sregs->idt.limit;
3617 dt.base = sregs->idt.base;
3618 kvm_x86_ops->set_idt(vcpu, &dt);
3619 dt.limit = sregs->gdt.limit;
3620 dt.base = sregs->gdt.base;
3621 kvm_x86_ops->set_gdt(vcpu, &dt);
3622
ad312c7c
ZX		 3623 vcpu->arch.cr2 = sregs->cr2;
3624 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
3625 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 3626
2d3ad1f4 3627 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 3628
ad312c7c 3629 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 3630 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 3631 kvm_set_apic_base(vcpu, sregs->apic_base);
3632
3633 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3634
ad312c7c 3635 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 3636 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 3637 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 3638
ad312c7c 3639 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 3640 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3641 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 3642 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 3643
3644 if (mmu_reset_needed)
3645 kvm_mmu_reset_context(vcpu);
3646
3647 if (!irqchip_in_kernel(vcpu->kvm)) {
ad312c7c
ZX		 3648 memcpy(vcpu->arch.irq_pending, sregs->interrupt_bitmap,
3649 sizeof vcpu->arch.irq_pending);
3650 vcpu->arch.irq_summary = 0;
3651 for (i = 0; i < ARRAY_SIZE(vcpu->arch.irq_pending); ++i)
3652 if (vcpu->arch.irq_pending[i])
3653 __set_bit(i, &vcpu->arch.irq_summary);
b6c7a5dc
HB		 3654 } else {
3655 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
3656 pending_vec = find_first_bit(
3657 (const unsigned long *)sregs->interrupt_bitmap,
3658 max_bits);
3659 /* Only pending external irq is handled here */
3660 if (pending_vec < max_bits) {
3661 kvm_x86_ops->set_irq(vcpu, pending_vec);
3662 pr_debug("Set back pending irq %d\n",
3663 pending_vec);
3664 }
3665 }
3666
3e6e0aab
GT		 3667 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3668 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3669 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3670 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3671 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3672 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3673
3e6e0aab
GT		 3674 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3675 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3676
3677 vcpu_put(vcpu);
3678
3679 return 0;
3680}
3681
3682int kvm_arch_vcpu_ioctl_debug_guest(struct kvm_vcpu *vcpu,
3683 struct kvm_debug_guest *dbg)
3684{
3685 int r;
3686
3687 vcpu_load(vcpu);
3688
3689 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
3690
3691 vcpu_put(vcpu);
3692
3693 return r;
3694}
3695
d0752060
HB		 3696/*
3697 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
3698 * we have asm/x86/processor.h
3699 */
3700struct fxsave {
3701 u16 cwd;
3702 u16 swd;
3703 u16 twd;
3704 u16 fop;
3705 u64 rip;
3706 u64 rdp;
3707 u32 mxcsr;
3708 u32 mxcsr_mask;
3709 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
3710#ifdef CONFIG_X86_64
3711 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
3712#else
3713 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
3714#endif
3715};
3716
8b006791
ZX		 3717/*
3718 * Translate a guest virtual address to a guest physical address.
3719 */
3720int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
3721 struct kvm_translation *tr)
3722{
3723 unsigned long vaddr = tr->linear_address;
3724 gpa_t gpa;
3725
3726 vcpu_load(vcpu);
72dc67a6 3727 down_read(&vcpu->kvm->slots_lock);
ad312c7c 3728 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 3729 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 3730 tr->physical_address = gpa;
3731 tr->valid = gpa != UNMAPPED_GVA;
3732 tr->writeable = 1;
3733 tr->usermode = 0;
8b006791
ZX		 3734 vcpu_put(vcpu);
3735
3736 return 0;
3737}
3738
d0752060
HB		 3739int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3740{
ad312c7c 3741 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3742
3743 vcpu_load(vcpu);
3744
3745 memcpy(fpu->fpr, fxsave->st_space, 128);
3746 fpu->fcw = fxsave->cwd;
3747 fpu->fsw = fxsave->swd;
3748 fpu->ftwx = fxsave->twd;
3749 fpu->last_opcode = fxsave->fop;
3750 fpu->last_ip = fxsave->rip;
3751 fpu->last_dp = fxsave->rdp;
3752 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
3753
3754 vcpu_put(vcpu);
3755
3756 return 0;
3757}
3758
3759int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3760{
ad312c7c 3761 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3762
3763 vcpu_load(vcpu);
3764
3765 memcpy(fxsave->st_space, fpu->fpr, 128);
3766 fxsave->cwd = fpu->fcw;
3767 fxsave->swd = fpu->fsw;
3768 fxsave->twd = fpu->ftwx;
3769 fxsave->fop = fpu->last_opcode;
3770 fxsave->rip = fpu->last_ip;
3771 fxsave->rdp = fpu->last_dp;
3772 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
3773
3774 vcpu_put(vcpu);
3775
3776 return 0;
3777}
3778
3779void fx_init(struct kvm_vcpu *vcpu)
3780{
3781 unsigned after_mxcsr_mask;
3782
bc1a34f1
AA		 3783 /*
3784 * Touch the fpu the first time in non atomic context as if
3785 * this is the first fpu instruction the exception handler
3786 * will fire before the instruction returns and it'll have to
3787 * allocate ram with GFP_KERNEL.
3788 */
3789 if (!used_math())
3790 fx_save(&vcpu->arch.host_fx_image);
3791
d0752060
HB		 3792 /* Initialize guest FPU by resetting ours and saving into guest's */
3793 preempt_disable();
ad312c7c 3794 fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 3795 fx_finit();
ad312c7c
ZX		 3796 fx_save(&vcpu->arch.guest_fx_image);
3797 fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 3798 preempt_enable();
3799
ad312c7c 3800 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 3801 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 3802 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
3803 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 3804 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
3805}
3806EXPORT_SYMBOL_GPL(fx_init);
3807
3808void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
3809{
3810 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
3811 return;
3812
3813 vcpu->guest_fpu_loaded = 1;
ad312c7c
ZX		 3814 fx_save(&vcpu->arch.host_fx_image);
3815 fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 3816}
3817EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
3818
3819void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
3820{
3821 if (!vcpu->guest_fpu_loaded)
3822 return;
3823
3824 vcpu->guest_fpu_loaded = 0;
ad312c7c
ZX		 3825 fx_save(&vcpu->arch.guest_fx_image);
3826 fx_restore(&vcpu->arch.host_fx_image);
f096ed85 3827 ++vcpu->stat.fpu_reload;
d0752060
HB		 3828}
3829EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 3830
3831void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
3832{
3833 kvm_x86_ops->vcpu_free(vcpu);
3834}
3835
3836struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
3837 unsigned int id)
3838{
26e5215f
AK		 3839 return kvm_x86_ops->vcpu_create(kvm, id);
3840}
e9b11c17 3841
26e5215f
AK		 3842int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
3843{
3844 int r;
e9b11c17
ZX		 3845
3846 /* We do fxsave: this must be aligned. */
ad312c7c 3847 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17
ZX		 3848
3849 vcpu_load(vcpu);
3850 r = kvm_arch_vcpu_reset(vcpu);
3851 if (r == 0)
3852 r = kvm_mmu_setup(vcpu);
3853 vcpu_put(vcpu);
3854 if (r < 0)
3855 goto free_vcpu;
3856
26e5215f 3857 return 0;
e9b11c17
ZX		 3858free_vcpu:
3859 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 3860 return r;
e9b11c17
ZX		 3861}
3862
d40ccc62 3863void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 3864{
3865 vcpu_load(vcpu);
3866 kvm_mmu_unload(vcpu);
3867 vcpu_put(vcpu);
3868
3869 kvm_x86_ops->vcpu_free(vcpu);
3870}
3871
3872int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
3873{
3874 return kvm_x86_ops->vcpu_reset(vcpu);
3875}
3876
3877void kvm_arch_hardware_enable(void *garbage)
3878{
3879 kvm_x86_ops->hardware_enable(garbage);
3880}
3881
3882void kvm_arch_hardware_disable(void *garbage)
3883{
3884 kvm_x86_ops->hardware_disable(garbage);
3885}
3886
3887int kvm_arch_hardware_setup(void)
3888{
3889 return kvm_x86_ops->hardware_setup();
3890}
3891
3892void kvm_arch_hardware_unsetup(void)
3893{
3894 kvm_x86_ops->hardware_unsetup();
3895}
3896
3897void kvm_arch_check_processor_compat(void *rtn)
3898{
3899 kvm_x86_ops->check_processor_compatibility(rtn);
3900}
3901
3902int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
3903{
3904 struct page *page;
3905 struct kvm *kvm;
3906 int r;
3907
3908 BUG_ON(vcpu->kvm == NULL);
3909 kvm = vcpu->kvm;
3910
ad312c7c 3911 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
e9b11c17 3912 if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
a4535290 3913 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 3914 else
a4535290 3915 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 3916
3917 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
3918 if (!page) {
3919 r = -ENOMEM;
3920 goto fail;
3921 }
ad312c7c 3922 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 3923
3924 r = kvm_mmu_create(vcpu);
3925 if (r < 0)
3926 goto fail_free_pio_data;
3927
3928 if (irqchip_in_kernel(kvm)) {
3929 r = kvm_create_lapic(vcpu);
3930 if (r < 0)
3931 goto fail_mmu_destroy;
3932 }
3933
3934 return 0;
3935
3936fail_mmu_destroy:
3937 kvm_mmu_destroy(vcpu);
3938fail_free_pio_data:
ad312c7c 3939 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 3940fail:
3941 return r;
3942}
3943
3944void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
3945{
3946 kvm_free_lapic(vcpu);
3200f405 3947 down_read(&vcpu->kvm->slots_lock);
e9b11c17 3948 kvm_mmu_destroy(vcpu);
3200f405 3949 up_read(&vcpu->kvm->slots_lock);
ad312c7c 3950 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 3951}
d19a9cd2
ZX		 3952
3953struct kvm *kvm_arch_create_vm(void)
3954{
3955 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
3956
3957 if (!kvm)
3958 return ERR_PTR(-ENOMEM);
3959
f05e70ac 3960 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
d19a9cd2
ZX		 3961
3962 return kvm;
3963}
3964
3965static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
3966{
3967 vcpu_load(vcpu);
3968 kvm_mmu_unload(vcpu);
3969 vcpu_put(vcpu);
3970}
3971
3972static void kvm_free_vcpus(struct kvm *kvm)
3973{
3974 unsigned int i;
3975
3976 /*
3977 * Unpin any mmu pages first.
3978 */
3979 for (i = 0; i < KVM_MAX_VCPUS; ++i)
3980 if (kvm->vcpus[i])
3981 kvm_unload_vcpu_mmu(kvm->vcpus[i]);
3982 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
3983 if (kvm->vcpus[i]) {
3984 kvm_arch_vcpu_free(kvm->vcpus[i]);
3985 kvm->vcpus[i] = NULL;
3986 }
3987 }
3988
3989}
3990
3991void kvm_arch_destroy_vm(struct kvm *kvm)
3992{
7837699f 3993 kvm_free_pit(kvm);
d7deeeb0
ZX		 3994 kfree(kvm->arch.vpic);
3995 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 3996 kvm_free_vcpus(kvm);
3997 kvm_free_physmem(kvm);
3d45830c
AK		 3998 if (kvm->arch.apic_access_page)
3999 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4000 if (kvm->arch.ept_identity_pagetable)
4001 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4002 kfree(kvm);
4003}
0de10343
ZX		 4004
4005int kvm_arch_set_memory_region(struct kvm *kvm,
4006 struct kvm_userspace_memory_region *mem,
4007 struct kvm_memory_slot old,
4008 int user_alloc)
4009{
4010 int npages = mem->memory_size >> PAGE_SHIFT;
4011 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4012
4013 /*To keep backward compatibility with older userspace,
4014 *x86 needs to hanlde !user_alloc case.
4015 */
4016 if (!user_alloc) {
4017 if (npages && !old.rmap) {
72dc67a6 4018 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4019 memslot->userspace_addr = do_mmap(NULL, 0,
4020 npages * PAGE_SIZE,
4021 PROT_READ | PROT_WRITE,
4022 MAP_SHARED | MAP_ANONYMOUS,
4023 0);
72dc67a6 4024 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4025
4026 if (IS_ERR((void *)memslot->userspace_addr))
4027 return PTR_ERR((void *)memslot->userspace_addr);
4028 } else {
4029 if (!old.user_alloc && old.rmap) {
4030 int ret;
4031
72dc67a6 4032 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4033 ret = do_munmap(current->mm, old.userspace_addr,
4034 old.npages * PAGE_SIZE);
72dc67a6 4035 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4036 if (ret < 0)
4037 printk(KERN_WARNING
4038 "kvm_vm_ioctl_set_memory_region: "
4039 "failed to munmap memory\n");
4040 }
4041 }
4042 }
4043
f05e70ac 4044 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4045 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4046 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4047 }
4048
4049 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
4050 kvm_flush_remote_tlbs(kvm);
4051
4052 return 0;
4053}
1d737c8a
ZX		 4054
4055int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4056{
a4535290
AK		 4057 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
4058 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED;
1d737c8a 4059}
5736199a
ZX		 4060
4061static void vcpu_kick_intr(void *info)
4062{
4063#ifdef DEBUG
4064 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)info;
4065 printk(KERN_DEBUG "vcpu_kick_intr %p \n", vcpu);
4066#endif
4067}
4068
4069void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4070{
4071 int ipi_pcpu = vcpu->cpu;
e9571ed5 4072 int cpu = get_cpu();
5736199a
ZX		 4073
4074 if (waitqueue_active(&vcpu->wq)) {
4075 wake_up_interruptible(&vcpu->wq);
4076 ++vcpu->stat.halt_wakeup;
4077 }
e9571ed5
MT		 4078 /*
4079 * We may be called synchronously with irqs disabled in guest mode,
4080 * So need not to call smp_call_function_single() in that case.
4081 */
4082 if (vcpu->guest_mode && vcpu->cpu != cpu)
8691e5a8 4083 smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0);
e9571ed5 4084 put_cpu();
5736199a 4085}
kernel source for telekom puls (alcatel/mediatek)