Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 7 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
8 | * |
9 | * Authors: | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
edf88417 AK |
17 | #include <linux/kvm_host.h> |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
5fdbf976 | 21 | #include "kvm_cache_regs.h" |
fe4c7b19 | 22 | #include "x86.h" |
66f7b72e | 23 | #include "cpuid.h" |
e495606d | 24 | |
6aa8b732 | 25 | #include <linux/module.h> |
ae759544 | 26 | #include <linux/mod_devicetable.h> |
9d8f549d | 27 | #include <linux/kernel.h> |
6aa8b732 AK |
28 | #include <linux/vmalloc.h> |
29 | #include <linux/highmem.h> | |
e8edc6e0 | 30 | #include <linux/sched.h> |
229456fc | 31 | #include <linux/ftrace_event.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
6aa8b732 | 33 | |
1018faa6 | 34 | #include <asm/perf_event.h> |
67ec6607 | 35 | #include <asm/tlbflush.h> |
e495606d | 36 | #include <asm/desc.h> |
631bc487 | 37 | #include <asm/kvm_para.h> |
6aa8b732 | 38 | |
63d1142f | 39 | #include <asm/virtext.h> |
229456fc | 40 | #include "trace.h" |
63d1142f | 41 | |
4ecac3fd AK |
42 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
43 | ||
6aa8b732 AK |
44 | MODULE_AUTHOR("Qumranet"); |
45 | MODULE_LICENSE("GPL"); | |
46 | ||
ae759544 JT |
47 | static const struct x86_cpu_id svm_cpu_id[] = { |
48 | X86_FEATURE_MATCH(X86_FEATURE_SVM), | |
49 | {} | |
50 | }; | |
51 | MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id); | |
52 | ||
6aa8b732 AK |
53 | #define IOPM_ALLOC_ORDER 2 |
54 | #define MSRPM_ALLOC_ORDER 1 | |
55 | ||
6aa8b732 AK |
56 | #define SEG_TYPE_LDT 2 |
57 | #define SEG_TYPE_BUSY_TSS16 3 | |
58 | ||
6bc31bdc AP |
59 | #define SVM_FEATURE_NPT (1 << 0) |
60 | #define SVM_FEATURE_LBRV (1 << 1) | |
61 | #define SVM_FEATURE_SVML (1 << 2) | |
62 | #define SVM_FEATURE_NRIP (1 << 3) | |
ddce97aa AP |
63 | #define SVM_FEATURE_TSC_RATE (1 << 4) |
64 | #define SVM_FEATURE_VMCB_CLEAN (1 << 5) | |
65 | #define SVM_FEATURE_FLUSH_ASID (1 << 6) | |
66 | #define SVM_FEATURE_DECODE_ASSIST (1 << 7) | |
6bc31bdc | 67 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) |
80b7706e | 68 | |
410e4d57 JR |
69 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
70 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
71 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
72 | ||
24e09cbf JR |
73 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
74 | ||
fbc0db76 | 75 | #define TSC_RATIO_RSVD 0xffffff0000000000ULL |
92a1f12d JR |
76 | #define TSC_RATIO_MIN 0x0000000000000001ULL |
77 | #define TSC_RATIO_MAX 0x000000ffffffffffULL | |
fbc0db76 | 78 | |
67ec6607 JR |
79 | static bool erratum_383_found __read_mostly; |
80 | ||
6c8166a7 AK |
81 | static const u32 host_save_user_msrs[] = { |
82 | #ifdef CONFIG_X86_64 | |
83 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
84 | MSR_FS_BASE, | |
85 | #endif | |
86 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
87 | }; | |
88 | ||
89 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
90 | ||
91 | struct kvm_vcpu; | |
92 | ||
e6aa9abd JR |
93 | struct nested_state { |
94 | struct vmcb *hsave; | |
95 | u64 hsave_msr; | |
4a810181 | 96 | u64 vm_cr_msr; |
e6aa9abd JR |
97 | u64 vmcb; |
98 | ||
99 | /* These are the merged vectors */ | |
100 | u32 *msrpm; | |
101 | ||
102 | /* gpa pointers to the real vectors */ | |
103 | u64 vmcb_msrpm; | |
ce2ac085 | 104 | u64 vmcb_iopm; |
aad42c64 | 105 | |
cd3ff653 JR |
106 | /* A VMEXIT is required but not yet emulated */ |
107 | bool exit_required; | |
108 | ||
aad42c64 | 109 | /* cache for intercepts of the guest */ |
4ee546b4 | 110 | u32 intercept_cr; |
3aed041a | 111 | u32 intercept_dr; |
aad42c64 JR |
112 | u32 intercept_exceptions; |
113 | u64 intercept; | |
114 | ||
5bd2edc3 JR |
115 | /* Nested Paging related state */ |
116 | u64 nested_cr3; | |
e6aa9abd JR |
117 | }; |
118 | ||
323c3d80 JR |
119 | #define MSRPM_OFFSETS 16 |
120 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
121 | ||
2b036c6b BO |
122 | /* |
123 | * Set osvw_len to higher value when updated Revision Guides | |
124 | * are published and we know what the new status bits are | |
125 | */ | |
126 | static uint64_t osvw_len = 4, osvw_status; | |
127 | ||
6c8166a7 AK |
128 | struct vcpu_svm { |
129 | struct kvm_vcpu vcpu; | |
130 | struct vmcb *vmcb; | |
131 | unsigned long vmcb_pa; | |
132 | struct svm_cpu_data *svm_data; | |
133 | uint64_t asid_generation; | |
134 | uint64_t sysenter_esp; | |
135 | uint64_t sysenter_eip; | |
136 | ||
137 | u64 next_rip; | |
138 | ||
139 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
afe9e66f | 140 | struct { |
dacccfdd AK |
141 | u16 fs; |
142 | u16 gs; | |
143 | u16 ldt; | |
afe9e66f AK |
144 | u64 gs_base; |
145 | } host; | |
6c8166a7 AK |
146 | |
147 | u32 *msrpm; | |
6c8166a7 | 148 | |
bd3d1ec3 AK |
149 | ulong nmi_iret_rip; |
150 | ||
e6aa9abd | 151 | struct nested_state nested; |
6be7d306 JK |
152 | |
153 | bool nmi_singlestep; | |
66b7138f JK |
154 | |
155 | unsigned int3_injected; | |
156 | unsigned long int3_rip; | |
631bc487 | 157 | u32 apf_reason; |
fbc0db76 JR |
158 | |
159 | u64 tsc_ratio; | |
6c8166a7 AK |
160 | }; |
161 | ||
fbc0db76 JR |
162 | static DEFINE_PER_CPU(u64, current_tsc_ratio); |
163 | #define TSC_RATIO_DEFAULT 0x0100000000ULL | |
164 | ||
455716fa JR |
165 | #define MSR_INVALID 0xffffffffU |
166 | ||
09941fbb | 167 | static const struct svm_direct_access_msrs { |
ac72a9b7 JR |
168 | u32 index; /* Index of the MSR */ |
169 | bool always; /* True if intercept is always on */ | |
170 | } direct_access_msrs[] = { | |
8c06585d | 171 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
172 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
173 | #ifdef CONFIG_X86_64 | |
174 | { .index = MSR_GS_BASE, .always = true }, | |
175 | { .index = MSR_FS_BASE, .always = true }, | |
176 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
177 | { .index = MSR_LSTAR, .always = true }, | |
178 | { .index = MSR_CSTAR, .always = true }, | |
179 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
180 | #endif | |
181 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, | |
182 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
183 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
184 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
185 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
186 | }; |
187 | ||
709ddebf JR |
188 | /* enable NPT for AMD64 and X86 with PAE */ |
189 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
190 | static bool npt_enabled = true; | |
191 | #else | |
e0231715 | 192 | static bool npt_enabled; |
709ddebf | 193 | #endif |
6c7dac72 | 194 | |
e2358851 DB |
195 | /* allow nested paging (virtualized MMU) for all guests */ |
196 | static int npt = true; | |
6c7dac72 | 197 | module_param(npt, int, S_IRUGO); |
e3da3acd | 198 | |
e2358851 DB |
199 | /* allow nested virtualization in KVM/SVM */ |
200 | static int nested = true; | |
236de055 AG |
201 | module_param(nested, int, S_IRUGO); |
202 | ||
44874f84 | 203 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 204 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 205 | |
410e4d57 | 206 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 207 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 208 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
209 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
210 | bool has_error_code, u32 error_code); | |
92a1f12d | 211 | static u64 __scale_tsc(u64 ratio, u64 tsc); |
cf74a78b | 212 | |
8d28fec4 | 213 | enum { |
116a0a23 JR |
214 | VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, |
215 | pause filter count */ | |
f56838e4 | 216 | VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ |
d48086d1 | 217 | VMCB_ASID, /* ASID */ |
decdbf6a | 218 | VMCB_INTR, /* int_ctl, int_vector */ |
b2747166 | 219 | VMCB_NPT, /* npt_en, nCR3, gPAT */ |
dcca1a65 | 220 | VMCB_CR, /* CR0, CR3, CR4, EFER */ |
72214b96 | 221 | VMCB_DR, /* DR6, DR7 */ |
17a703cb | 222 | VMCB_DT, /* GDT, IDT */ |
060d0c9a | 223 | VMCB_SEG, /* CS, DS, SS, ES, CPL */ |
0574dec0 | 224 | VMCB_CR2, /* CR2 only */ |
b53ba3f9 | 225 | VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ |
8d28fec4 RJ |
226 | VMCB_DIRTY_MAX, |
227 | }; | |
228 | ||
0574dec0 JR |
229 | /* TPR and CR2 are always written before VMRUN */ |
230 | #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) | |
8d28fec4 RJ |
231 | |
232 | static inline void mark_all_dirty(struct vmcb *vmcb) | |
233 | { | |
234 | vmcb->control.clean = 0; | |
235 | } | |
236 | ||
237 | static inline void mark_all_clean(struct vmcb *vmcb) | |
238 | { | |
239 | vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) | |
240 | & ~VMCB_ALWAYS_DIRTY_MASK; | |
241 | } | |
242 | ||
243 | static inline void mark_dirty(struct vmcb *vmcb, int bit) | |
244 | { | |
245 | vmcb->control.clean &= ~(1 << bit); | |
246 | } | |
247 | ||
a2fa3e9f GH |
248 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
249 | { | |
fb3f0f51 | 250 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
251 | } |
252 | ||
384c6368 JR |
253 | static void recalc_intercepts(struct vcpu_svm *svm) |
254 | { | |
255 | struct vmcb_control_area *c, *h; | |
256 | struct nested_state *g; | |
257 | ||
116a0a23 JR |
258 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
259 | ||
384c6368 JR |
260 | if (!is_guest_mode(&svm->vcpu)) |
261 | return; | |
262 | ||
263 | c = &svm->vmcb->control; | |
264 | h = &svm->nested.hsave->control; | |
265 | g = &svm->nested; | |
266 | ||
4ee546b4 | 267 | c->intercept_cr = h->intercept_cr | g->intercept_cr; |
3aed041a | 268 | c->intercept_dr = h->intercept_dr | g->intercept_dr; |
384c6368 JR |
269 | c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions; |
270 | c->intercept = h->intercept | g->intercept; | |
271 | } | |
272 | ||
4ee546b4 RJ |
273 | static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) |
274 | { | |
275 | if (is_guest_mode(&svm->vcpu)) | |
276 | return svm->nested.hsave; | |
277 | else | |
278 | return svm->vmcb; | |
279 | } | |
280 | ||
281 | static inline void set_cr_intercept(struct vcpu_svm *svm, int bit) | |
282 | { | |
283 | struct vmcb *vmcb = get_host_vmcb(svm); | |
284 | ||
285 | vmcb->control.intercept_cr |= (1U << bit); | |
286 | ||
287 | recalc_intercepts(svm); | |
288 | } | |
289 | ||
290 | static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit) | |
291 | { | |
292 | struct vmcb *vmcb = get_host_vmcb(svm); | |
293 | ||
294 | vmcb->control.intercept_cr &= ~(1U << bit); | |
295 | ||
296 | recalc_intercepts(svm); | |
297 | } | |
298 | ||
299 | static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit) | |
300 | { | |
301 | struct vmcb *vmcb = get_host_vmcb(svm); | |
302 | ||
303 | return vmcb->control.intercept_cr & (1U << bit); | |
304 | } | |
305 | ||
3aed041a JR |
306 | static inline void set_dr_intercept(struct vcpu_svm *svm, int bit) |
307 | { | |
308 | struct vmcb *vmcb = get_host_vmcb(svm); | |
309 | ||
310 | vmcb->control.intercept_dr |= (1U << bit); | |
311 | ||
312 | recalc_intercepts(svm); | |
313 | } | |
314 | ||
315 | static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit) | |
316 | { | |
317 | struct vmcb *vmcb = get_host_vmcb(svm); | |
318 | ||
319 | vmcb->control.intercept_dr &= ~(1U << bit); | |
320 | ||
321 | recalc_intercepts(svm); | |
322 | } | |
323 | ||
18c918c5 JR |
324 | static inline void set_exception_intercept(struct vcpu_svm *svm, int bit) |
325 | { | |
326 | struct vmcb *vmcb = get_host_vmcb(svm); | |
327 | ||
328 | vmcb->control.intercept_exceptions |= (1U << bit); | |
329 | ||
330 | recalc_intercepts(svm); | |
331 | } | |
332 | ||
333 | static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit) | |
334 | { | |
335 | struct vmcb *vmcb = get_host_vmcb(svm); | |
336 | ||
337 | vmcb->control.intercept_exceptions &= ~(1U << bit); | |
338 | ||
339 | recalc_intercepts(svm); | |
340 | } | |
341 | ||
8a05a1b8 JR |
342 | static inline void set_intercept(struct vcpu_svm *svm, int bit) |
343 | { | |
344 | struct vmcb *vmcb = get_host_vmcb(svm); | |
345 | ||
346 | vmcb->control.intercept |= (1ULL << bit); | |
347 | ||
348 | recalc_intercepts(svm); | |
349 | } | |
350 | ||
351 | static inline void clr_intercept(struct vcpu_svm *svm, int bit) | |
352 | { | |
353 | struct vmcb *vmcb = get_host_vmcb(svm); | |
354 | ||
355 | vmcb->control.intercept &= ~(1ULL << bit); | |
356 | ||
357 | recalc_intercepts(svm); | |
358 | } | |
359 | ||
2af9194d JR |
360 | static inline void enable_gif(struct vcpu_svm *svm) |
361 | { | |
362 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
363 | } | |
364 | ||
365 | static inline void disable_gif(struct vcpu_svm *svm) | |
366 | { | |
367 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
368 | } | |
369 | ||
370 | static inline bool gif_set(struct vcpu_svm *svm) | |
371 | { | |
372 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
373 | } | |
374 | ||
4866d5e3 | 375 | static unsigned long iopm_base; |
6aa8b732 AK |
376 | |
377 | struct kvm_ldttss_desc { | |
378 | u16 limit0; | |
379 | u16 base0; | |
e0231715 JR |
380 | unsigned base1:8, type:5, dpl:2, p:1; |
381 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
382 | u32 base3; |
383 | u32 zero1; | |
384 | } __attribute__((packed)); | |
385 | ||
386 | struct svm_cpu_data { | |
387 | int cpu; | |
388 | ||
5008fdf5 AK |
389 | u64 asid_generation; |
390 | u32 max_asid; | |
391 | u32 next_asid; | |
6aa8b732 AK |
392 | struct kvm_ldttss_desc *tss_desc; |
393 | ||
394 | struct page *save_area; | |
395 | }; | |
396 | ||
397 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
398 | ||
399 | struct svm_init_data { | |
400 | int cpu; | |
401 | int r; | |
402 | }; | |
403 | ||
09941fbb | 404 | static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; |
6aa8b732 | 405 | |
9d8f549d | 406 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
407 | #define MSRS_RANGE_SIZE 2048 |
408 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
409 | ||
455716fa JR |
410 | static u32 svm_msrpm_offset(u32 msr) |
411 | { | |
412 | u32 offset; | |
413 | int i; | |
414 | ||
415 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
416 | if (msr < msrpm_ranges[i] || | |
417 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
418 | continue; | |
419 | ||
420 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
421 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
422 | ||
423 | /* Now we have the u8 offset - but need the u32 offset */ | |
424 | return offset / 4; | |
425 | } | |
426 | ||
427 | /* MSR not in any range */ | |
428 | return MSR_INVALID; | |
429 | } | |
430 | ||
6aa8b732 AK |
431 | #define MAX_INST_SIZE 15 |
432 | ||
6aa8b732 AK |
433 | static inline void clgi(void) |
434 | { | |
4ecac3fd | 435 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
436 | } |
437 | ||
438 | static inline void stgi(void) | |
439 | { | |
4ecac3fd | 440 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
441 | } |
442 | ||
443 | static inline void invlpga(unsigned long addr, u32 asid) | |
444 | { | |
e0231715 | 445 | asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); |
6aa8b732 AK |
446 | } |
447 | ||
4b16184c JR |
448 | static int get_npt_level(void) |
449 | { | |
450 | #ifdef CONFIG_X86_64 | |
451 | return PT64_ROOT_LEVEL; | |
452 | #else | |
453 | return PT32E_ROOT_LEVEL; | |
454 | #endif | |
455 | } | |
456 | ||
6aa8b732 AK |
457 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
458 | { | |
6dc696d4 | 459 | vcpu->arch.efer = efer; |
709ddebf | 460 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 461 | efer &= ~EFER_LME; |
6aa8b732 | 462 | |
9962d032 | 463 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
dcca1a65 | 464 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
465 | } |
466 | ||
6aa8b732 AK |
467 | static int is_external_interrupt(u32 info) |
468 | { | |
469 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
470 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
471 | } | |
472 | ||
2809f5d2 GC |
473 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
474 | { | |
475 | struct vcpu_svm *svm = to_svm(vcpu); | |
476 | u32 ret = 0; | |
477 | ||
478 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
48005f64 | 479 | ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 GC |
480 | return ret & mask; |
481 | } | |
482 | ||
483 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
484 | { | |
485 | struct vcpu_svm *svm = to_svm(vcpu); | |
486 | ||
487 | if (mask == 0) | |
488 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
489 | else | |
490 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
491 | ||
492 | } | |
493 | ||
6aa8b732 AK |
494 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
495 | { | |
a2fa3e9f GH |
496 | struct vcpu_svm *svm = to_svm(vcpu); |
497 | ||
ea0d66be | 498 | if (svm->vmcb->control.next_rip != 0) { |
fb7eff9c | 499 | WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS)); |
6bc31bdc | 500 | svm->next_rip = svm->vmcb->control.next_rip; |
ea0d66be | 501 | } |
6bc31bdc | 502 | |
a2fa3e9f | 503 | if (!svm->next_rip) { |
51d8b661 | 504 | if (emulate_instruction(vcpu, EMULTYPE_SKIP) != |
f629cf84 GN |
505 | EMULATE_DONE) |
506 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
507 | return; |
508 | } | |
5fdbf976 MT |
509 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
510 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
511 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 512 | |
5fdbf976 | 513 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 514 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
515 | } |
516 | ||
116a4752 | 517 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
518 | bool has_error_code, u32 error_code, |
519 | bool reinject) | |
116a4752 JK |
520 | { |
521 | struct vcpu_svm *svm = to_svm(vcpu); | |
522 | ||
e0231715 JR |
523 | /* |
524 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
525 | * handle the exception | |
526 | */ | |
ce7ddec4 JR |
527 | if (!reinject && |
528 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
529 | return; |
530 | ||
2a6b20b8 | 531 | if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) { |
66b7138f JK |
532 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); |
533 | ||
534 | /* | |
535 | * For guest debugging where we have to reinject #BP if some | |
536 | * INT3 is guest-owned: | |
537 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
538 | * raises a fault that is not intercepted. Still better than | |
539 | * failing in all cases. | |
540 | */ | |
541 | skip_emulated_instruction(&svm->vcpu); | |
542 | rip = kvm_rip_read(&svm->vcpu); | |
543 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
544 | svm->int3_injected = rip - old_rip; | |
545 | } | |
546 | ||
116a4752 JK |
547 | svm->vmcb->control.event_inj = nr |
548 | | SVM_EVTINJ_VALID | |
549 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
550 | | SVM_EVTINJ_TYPE_EXEPT; | |
551 | svm->vmcb->control.event_inj_err = error_code; | |
552 | } | |
553 | ||
67ec6607 JR |
554 | static void svm_init_erratum_383(void) |
555 | { | |
556 | u32 low, high; | |
557 | int err; | |
558 | u64 val; | |
559 | ||
e6ee94d5 | 560 | if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH)) |
67ec6607 JR |
561 | return; |
562 | ||
563 | /* Use _safe variants to not break nested virtualization */ | |
564 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
565 | if (err) | |
566 | return; | |
567 | ||
568 | val |= (1ULL << 47); | |
569 | ||
570 | low = lower_32_bits(val); | |
571 | high = upper_32_bits(val); | |
572 | ||
573 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
574 | ||
575 | erratum_383_found = true; | |
576 | } | |
577 | ||
2b036c6b BO |
578 | static void svm_init_osvw(struct kvm_vcpu *vcpu) |
579 | { | |
580 | /* | |
581 | * Guests should see errata 400 and 415 as fixed (assuming that | |
582 | * HLT and IO instructions are intercepted). | |
583 | */ | |
584 | vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3; | |
585 | vcpu->arch.osvw.status = osvw_status & ~(6ULL); | |
586 | ||
587 | /* | |
588 | * By increasing VCPU's osvw.length to 3 we are telling the guest that | |
589 | * all osvw.status bits inside that length, including bit 0 (which is | |
590 | * reserved for erratum 298), are valid. However, if host processor's | |
591 | * osvw_len is 0 then osvw_status[0] carries no information. We need to | |
592 | * be conservative here and therefore we tell the guest that erratum 298 | |
593 | * is present (because we really don't know). | |
594 | */ | |
595 | if (osvw_len == 0 && boot_cpu_data.x86 == 0x10) | |
596 | vcpu->arch.osvw.status |= 1; | |
597 | } | |
598 | ||
6aa8b732 AK |
599 | static int has_svm(void) |
600 | { | |
63d1142f | 601 | const char *msg; |
6aa8b732 | 602 | |
63d1142f | 603 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 604 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
605 | return 0; |
606 | } | |
607 | ||
6aa8b732 AK |
608 | return 1; |
609 | } | |
610 | ||
611 | static void svm_hardware_disable(void *garbage) | |
612 | { | |
fbc0db76 JR |
613 | /* Make sure we clean up behind us */ |
614 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) | |
615 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
616 | ||
2c8dceeb | 617 | cpu_svm_disable(); |
1018faa6 JR |
618 | |
619 | amd_pmu_disable_virt(); | |
6aa8b732 AK |
620 | } |
621 | ||
10474ae8 | 622 | static int svm_hardware_enable(void *garbage) |
6aa8b732 AK |
623 | { |
624 | ||
0fe1e009 | 625 | struct svm_cpu_data *sd; |
6aa8b732 | 626 | uint64_t efer; |
89a27f4d | 627 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
628 | struct desc_struct *gdt; |
629 | int me = raw_smp_processor_id(); | |
630 | ||
10474ae8 AG |
631 | rdmsrl(MSR_EFER, efer); |
632 | if (efer & EFER_SVME) | |
633 | return -EBUSY; | |
634 | ||
6aa8b732 | 635 | if (!has_svm()) { |
1f5b77f5 | 636 | pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me); |
10474ae8 | 637 | return -EINVAL; |
6aa8b732 | 638 | } |
0fe1e009 | 639 | sd = per_cpu(svm_data, me); |
0fe1e009 | 640 | if (!sd) { |
1f5b77f5 | 641 | pr_err("%s: svm_data is NULL on %d\n", __func__, me); |
10474ae8 | 642 | return -EINVAL; |
6aa8b732 AK |
643 | } |
644 | ||
0fe1e009 TH |
645 | sd->asid_generation = 1; |
646 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
647 | sd->next_asid = sd->max_asid + 1; | |
6aa8b732 | 648 | |
d6ab1ed4 | 649 | native_store_gdt(&gdt_descr); |
89a27f4d | 650 | gdt = (struct desc_struct *)gdt_descr.address; |
0fe1e009 | 651 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 652 | |
9962d032 | 653 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 654 | |
d0316554 | 655 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 656 | |
fbc0db76 JR |
657 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
658 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
659 | __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT; | |
660 | } | |
661 | ||
2b036c6b BO |
662 | |
663 | /* | |
664 | * Get OSVW bits. | |
665 | * | |
666 | * Note that it is possible to have a system with mixed processor | |
667 | * revisions and therefore different OSVW bits. If bits are not the same | |
668 | * on different processors then choose the worst case (i.e. if erratum | |
669 | * is present on one processor and not on another then assume that the | |
670 | * erratum is present everywhere). | |
671 | */ | |
672 | if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) { | |
673 | uint64_t len, status = 0; | |
674 | int err; | |
675 | ||
676 | len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err); | |
677 | if (!err) | |
678 | status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS, | |
679 | &err); | |
680 | ||
681 | if (err) | |
682 | osvw_status = osvw_len = 0; | |
683 | else { | |
684 | if (len < osvw_len) | |
685 | osvw_len = len; | |
686 | osvw_status |= status; | |
687 | osvw_status &= (1ULL << osvw_len) - 1; | |
688 | } | |
689 | } else | |
690 | osvw_status = osvw_len = 0; | |
691 | ||
67ec6607 JR |
692 | svm_init_erratum_383(); |
693 | ||
1018faa6 JR |
694 | amd_pmu_enable_virt(); |
695 | ||
10474ae8 | 696 | return 0; |
6aa8b732 AK |
697 | } |
698 | ||
0da1db75 JR |
699 | static void svm_cpu_uninit(int cpu) |
700 | { | |
0fe1e009 | 701 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 702 | |
0fe1e009 | 703 | if (!sd) |
0da1db75 JR |
704 | return; |
705 | ||
706 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
0fe1e009 TH |
707 | __free_page(sd->save_area); |
708 | kfree(sd); | |
0da1db75 JR |
709 | } |
710 | ||
6aa8b732 AK |
711 | static int svm_cpu_init(int cpu) |
712 | { | |
0fe1e009 | 713 | struct svm_cpu_data *sd; |
6aa8b732 AK |
714 | int r; |
715 | ||
0fe1e009 TH |
716 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
717 | if (!sd) | |
6aa8b732 | 718 | return -ENOMEM; |
0fe1e009 TH |
719 | sd->cpu = cpu; |
720 | sd->save_area = alloc_page(GFP_KERNEL); | |
6aa8b732 | 721 | r = -ENOMEM; |
0fe1e009 | 722 | if (!sd->save_area) |
6aa8b732 AK |
723 | goto err_1; |
724 | ||
0fe1e009 | 725 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
726 | |
727 | return 0; | |
728 | ||
729 | err_1: | |
0fe1e009 | 730 | kfree(sd); |
6aa8b732 AK |
731 | return r; |
732 | ||
733 | } | |
734 | ||
ac72a9b7 JR |
735 | static bool valid_msr_intercept(u32 index) |
736 | { | |
737 | int i; | |
738 | ||
739 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
740 | if (direct_access_msrs[i].index == index) | |
741 | return true; | |
742 | ||
743 | return false; | |
744 | } | |
745 | ||
bfc733a7 RR |
746 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
747 | int read, int write) | |
6aa8b732 | 748 | { |
455716fa JR |
749 | u8 bit_read, bit_write; |
750 | unsigned long tmp; | |
751 | u32 offset; | |
6aa8b732 | 752 | |
ac72a9b7 JR |
753 | /* |
754 | * If this warning triggers extend the direct_access_msrs list at the | |
755 | * beginning of the file | |
756 | */ | |
757 | WARN_ON(!valid_msr_intercept(msr)); | |
758 | ||
455716fa JR |
759 | offset = svm_msrpm_offset(msr); |
760 | bit_read = 2 * (msr & 0x0f); | |
761 | bit_write = 2 * (msr & 0x0f) + 1; | |
762 | tmp = msrpm[offset]; | |
763 | ||
764 | BUG_ON(offset == MSR_INVALID); | |
765 | ||
766 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
767 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
768 | ||
769 | msrpm[offset] = tmp; | |
6aa8b732 AK |
770 | } |
771 | ||
f65c229c | 772 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
773 | { |
774 | int i; | |
775 | ||
f65c229c JR |
776 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
777 | ||
ac72a9b7 JR |
778 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
779 | if (!direct_access_msrs[i].always) | |
780 | continue; | |
781 | ||
782 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
783 | } | |
f65c229c JR |
784 | } |
785 | ||
323c3d80 JR |
786 | static void add_msr_offset(u32 offset) |
787 | { | |
788 | int i; | |
789 | ||
790 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
791 | ||
792 | /* Offset already in list? */ | |
793 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 794 | return; |
323c3d80 JR |
795 | |
796 | /* Slot used by another offset? */ | |
797 | if (msrpm_offsets[i] != MSR_INVALID) | |
798 | continue; | |
799 | ||
800 | /* Add offset to list */ | |
801 | msrpm_offsets[i] = offset; | |
802 | ||
803 | return; | |
6aa8b732 | 804 | } |
323c3d80 JR |
805 | |
806 | /* | |
807 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
808 | * increase MSRPM_OFFSETS in this case. | |
809 | */ | |
bfc733a7 | 810 | BUG(); |
6aa8b732 AK |
811 | } |
812 | ||
323c3d80 | 813 | static void init_msrpm_offsets(void) |
f65c229c | 814 | { |
323c3d80 | 815 | int i; |
f65c229c | 816 | |
323c3d80 JR |
817 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
818 | ||
819 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
820 | u32 offset; | |
821 | ||
822 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
823 | BUG_ON(offset == MSR_INVALID); | |
824 | ||
825 | add_msr_offset(offset); | |
826 | } | |
f65c229c JR |
827 | } |
828 | ||
24e09cbf JR |
829 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
830 | { | |
831 | u32 *msrpm = svm->msrpm; | |
832 | ||
833 | svm->vmcb->control.lbr_ctl = 1; | |
834 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
835 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
836 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
837 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
838 | } | |
839 | ||
840 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
841 | { | |
842 | u32 *msrpm = svm->msrpm; | |
843 | ||
844 | svm->vmcb->control.lbr_ctl = 0; | |
845 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
846 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
847 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
848 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
849 | } | |
850 | ||
6aa8b732 AK |
851 | static __init int svm_hardware_setup(void) |
852 | { | |
853 | int cpu; | |
854 | struct page *iopm_pages; | |
f65c229c | 855 | void *iopm_va; |
6aa8b732 AK |
856 | int r; |
857 | ||
6aa8b732 AK |
858 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
859 | ||
860 | if (!iopm_pages) | |
861 | return -ENOMEM; | |
c8681339 AL |
862 | |
863 | iopm_va = page_address(iopm_pages); | |
864 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
865 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
866 | ||
323c3d80 JR |
867 | init_msrpm_offsets(); |
868 | ||
50a37eb4 JR |
869 | if (boot_cpu_has(X86_FEATURE_NX)) |
870 | kvm_enable_efer_bits(EFER_NX); | |
871 | ||
1b2fd70c AG |
872 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
873 | kvm_enable_efer_bits(EFER_FFXSR); | |
874 | ||
92a1f12d JR |
875 | if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
876 | u64 max; | |
877 | ||
878 | kvm_has_tsc_control = true; | |
879 | ||
880 | /* | |
881 | * Make sure the user can only configure tsc_khz values that | |
882 | * fit into a signed integer. | |
883 | * A min value is not calculated needed because it will always | |
884 | * be 1 on all machines and a value of 0 is used to disable | |
885 | * tsc-scaling for the vcpu. | |
886 | */ | |
887 | max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX)); | |
888 | ||
889 | kvm_max_guest_tsc_khz = max; | |
890 | } | |
891 | ||
236de055 AG |
892 | if (nested) { |
893 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 894 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
895 | } |
896 | ||
3230bb47 | 897 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
898 | r = svm_cpu_init(cpu); |
899 | if (r) | |
f65c229c | 900 | goto err; |
6aa8b732 | 901 | } |
33bd6a0b | 902 | |
2a6b20b8 | 903 | if (!boot_cpu_has(X86_FEATURE_NPT)) |
e3da3acd JR |
904 | npt_enabled = false; |
905 | ||
6c7dac72 JR |
906 | if (npt_enabled && !npt) { |
907 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
908 | npt_enabled = false; | |
909 | } | |
910 | ||
18552672 | 911 | if (npt_enabled) { |
e3da3acd | 912 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 913 | kvm_enable_tdp(); |
5f4cb662 JR |
914 | } else |
915 | kvm_disable_tdp(); | |
e3da3acd | 916 | |
6aa8b732 AK |
917 | return 0; |
918 | ||
f65c229c | 919 | err: |
6aa8b732 AK |
920 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
921 | iopm_base = 0; | |
922 | return r; | |
923 | } | |
924 | ||
925 | static __exit void svm_hardware_unsetup(void) | |
926 | { | |
0da1db75 JR |
927 | int cpu; |
928 | ||
3230bb47 | 929 | for_each_possible_cpu(cpu) |
0da1db75 JR |
930 | svm_cpu_uninit(cpu); |
931 | ||
6aa8b732 | 932 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 933 | iopm_base = 0; |
6aa8b732 AK |
934 | } |
935 | ||
936 | static void init_seg(struct vmcb_seg *seg) | |
937 | { | |
938 | seg->selector = 0; | |
939 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 940 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
941 | seg->limit = 0xffff; |
942 | seg->base = 0; | |
943 | } | |
944 | ||
945 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
946 | { | |
947 | seg->selector = 0; | |
948 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
949 | seg->limit = 0xffff; | |
950 | seg->base = 0; | |
951 | } | |
952 | ||
fbc0db76 JR |
953 | static u64 __scale_tsc(u64 ratio, u64 tsc) |
954 | { | |
955 | u64 mult, frac, _tsc; | |
956 | ||
957 | mult = ratio >> 32; | |
958 | frac = ratio & ((1ULL << 32) - 1); | |
959 | ||
960 | _tsc = tsc; | |
961 | _tsc *= mult; | |
962 | _tsc += (tsc >> 32) * frac; | |
963 | _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32; | |
964 | ||
965 | return _tsc; | |
966 | } | |
967 | ||
968 | static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) | |
969 | { | |
970 | struct vcpu_svm *svm = to_svm(vcpu); | |
971 | u64 _tsc = tsc; | |
972 | ||
973 | if (svm->tsc_ratio != TSC_RATIO_DEFAULT) | |
974 | _tsc = __scale_tsc(svm->tsc_ratio, tsc); | |
975 | ||
976 | return _tsc; | |
977 | } | |
978 | ||
cc578287 | 979 | static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
4051b188 JR |
980 | { |
981 | struct vcpu_svm *svm = to_svm(vcpu); | |
982 | u64 ratio; | |
983 | u64 khz; | |
984 | ||
cc578287 ZA |
985 | /* Guest TSC same frequency as host TSC? */ |
986 | if (!scale) { | |
987 | svm->tsc_ratio = TSC_RATIO_DEFAULT; | |
4051b188 | 988 | return; |
cc578287 | 989 | } |
4051b188 | 990 | |
cc578287 ZA |
991 | /* TSC scaling supported? */ |
992 | if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) { | |
993 | if (user_tsc_khz > tsc_khz) { | |
994 | vcpu->arch.tsc_catchup = 1; | |
995 | vcpu->arch.tsc_always_catchup = 1; | |
996 | } else | |
997 | WARN(1, "user requested TSC rate below hardware speed\n"); | |
4051b188 JR |
998 | return; |
999 | } | |
1000 | ||
1001 | khz = user_tsc_khz; | |
1002 | ||
1003 | /* TSC scaling required - calculate ratio */ | |
1004 | ratio = khz << 32; | |
1005 | do_div(ratio, tsc_khz); | |
1006 | ||
1007 | if (ratio == 0 || ratio & TSC_RATIO_RSVD) { | |
1008 | WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n", | |
1009 | user_tsc_khz); | |
1010 | return; | |
1011 | } | |
4051b188 JR |
1012 | svm->tsc_ratio = ratio; |
1013 | } | |
1014 | ||
ba904635 WA |
1015 | static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu) |
1016 | { | |
1017 | struct vcpu_svm *svm = to_svm(vcpu); | |
1018 | ||
1019 | return svm->vmcb->control.tsc_offset; | |
1020 | } | |
1021 | ||
f4e1b3c8 ZA |
1022 | static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
1023 | { | |
1024 | struct vcpu_svm *svm = to_svm(vcpu); | |
1025 | u64 g_tsc_offset = 0; | |
1026 | ||
2030753d | 1027 | if (is_guest_mode(vcpu)) { |
f4e1b3c8 ZA |
1028 | g_tsc_offset = svm->vmcb->control.tsc_offset - |
1029 | svm->nested.hsave->control.tsc_offset; | |
1030 | svm->nested.hsave->control.tsc_offset = offset; | |
1031 | } | |
1032 | ||
1033 | svm->vmcb->control.tsc_offset = offset + g_tsc_offset; | |
116a0a23 JR |
1034 | |
1035 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); | |
f4e1b3c8 ZA |
1036 | } |
1037 | ||
f1e2b260 | 1038 | static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host) |
e48672fa ZA |
1039 | { |
1040 | struct vcpu_svm *svm = to_svm(vcpu); | |
1041 | ||
f1e2b260 MT |
1042 | WARN_ON(adjustment < 0); |
1043 | if (host) | |
1044 | adjustment = svm_scale_tsc(vcpu, adjustment); | |
1045 | ||
e48672fa | 1046 | svm->vmcb->control.tsc_offset += adjustment; |
2030753d | 1047 | if (is_guest_mode(vcpu)) |
e48672fa | 1048 | svm->nested.hsave->control.tsc_offset += adjustment; |
116a0a23 | 1049 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
e48672fa ZA |
1050 | } |
1051 | ||
857e4099 JR |
1052 | static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
1053 | { | |
1054 | u64 tsc; | |
1055 | ||
1056 | tsc = svm_scale_tsc(vcpu, native_read_tsc()); | |
1057 | ||
1058 | return target_tsc - tsc; | |
1059 | } | |
1060 | ||
e6101a96 | 1061 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 1062 | { |
e6101a96 JR |
1063 | struct vmcb_control_area *control = &svm->vmcb->control; |
1064 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 1065 | |
bff78274 | 1066 | svm->vcpu.fpu_active = 1; |
4ee546b4 | 1067 | svm->vcpu.arch.hflags = 0; |
bff78274 | 1068 | |
4ee546b4 RJ |
1069 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1070 | set_cr_intercept(svm, INTERCEPT_CR3_READ); | |
1071 | set_cr_intercept(svm, INTERCEPT_CR4_READ); | |
1072 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
1073 | set_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
1074 | set_cr_intercept(svm, INTERCEPT_CR4_WRITE); | |
1075 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
6aa8b732 | 1076 | |
3aed041a JR |
1077 | set_dr_intercept(svm, INTERCEPT_DR0_READ); |
1078 | set_dr_intercept(svm, INTERCEPT_DR1_READ); | |
1079 | set_dr_intercept(svm, INTERCEPT_DR2_READ); | |
1080 | set_dr_intercept(svm, INTERCEPT_DR3_READ); | |
1081 | set_dr_intercept(svm, INTERCEPT_DR4_READ); | |
1082 | set_dr_intercept(svm, INTERCEPT_DR5_READ); | |
1083 | set_dr_intercept(svm, INTERCEPT_DR6_READ); | |
1084 | set_dr_intercept(svm, INTERCEPT_DR7_READ); | |
1085 | ||
1086 | set_dr_intercept(svm, INTERCEPT_DR0_WRITE); | |
1087 | set_dr_intercept(svm, INTERCEPT_DR1_WRITE); | |
1088 | set_dr_intercept(svm, INTERCEPT_DR2_WRITE); | |
1089 | set_dr_intercept(svm, INTERCEPT_DR3_WRITE); | |
1090 | set_dr_intercept(svm, INTERCEPT_DR4_WRITE); | |
1091 | set_dr_intercept(svm, INTERCEPT_DR5_WRITE); | |
1092 | set_dr_intercept(svm, INTERCEPT_DR6_WRITE); | |
1093 | set_dr_intercept(svm, INTERCEPT_DR7_WRITE); | |
6aa8b732 | 1094 | |
18c918c5 JR |
1095 | set_exception_intercept(svm, PF_VECTOR); |
1096 | set_exception_intercept(svm, UD_VECTOR); | |
1097 | set_exception_intercept(svm, MC_VECTOR); | |
6aa8b732 | 1098 | |
8a05a1b8 JR |
1099 | set_intercept(svm, INTERCEPT_INTR); |
1100 | set_intercept(svm, INTERCEPT_NMI); | |
1101 | set_intercept(svm, INTERCEPT_SMI); | |
1102 | set_intercept(svm, INTERCEPT_SELECTIVE_CR0); | |
332b56e4 | 1103 | set_intercept(svm, INTERCEPT_RDPMC); |
8a05a1b8 JR |
1104 | set_intercept(svm, INTERCEPT_CPUID); |
1105 | set_intercept(svm, INTERCEPT_INVD); | |
1106 | set_intercept(svm, INTERCEPT_HLT); | |
1107 | set_intercept(svm, INTERCEPT_INVLPG); | |
1108 | set_intercept(svm, INTERCEPT_INVLPGA); | |
1109 | set_intercept(svm, INTERCEPT_IOIO_PROT); | |
1110 | set_intercept(svm, INTERCEPT_MSR_PROT); | |
1111 | set_intercept(svm, INTERCEPT_TASK_SWITCH); | |
1112 | set_intercept(svm, INTERCEPT_SHUTDOWN); | |
1113 | set_intercept(svm, INTERCEPT_VMRUN); | |
1114 | set_intercept(svm, INTERCEPT_VMMCALL); | |
1115 | set_intercept(svm, INTERCEPT_VMLOAD); | |
1116 | set_intercept(svm, INTERCEPT_VMSAVE); | |
1117 | set_intercept(svm, INTERCEPT_STGI); | |
1118 | set_intercept(svm, INTERCEPT_CLGI); | |
1119 | set_intercept(svm, INTERCEPT_SKINIT); | |
1120 | set_intercept(svm, INTERCEPT_WBINVD); | |
1121 | set_intercept(svm, INTERCEPT_MONITOR); | |
1122 | set_intercept(svm, INTERCEPT_MWAIT); | |
81dd35d4 | 1123 | set_intercept(svm, INTERCEPT_XSETBV); |
6aa8b732 AK |
1124 | |
1125 | control->iopm_base_pa = iopm_base; | |
f65c229c | 1126 | control->msrpm_base_pa = __pa(svm->msrpm); |
6aa8b732 AK |
1127 | control->int_ctl = V_INTR_MASKING_MASK; |
1128 | ||
1129 | init_seg(&save->es); | |
1130 | init_seg(&save->ss); | |
1131 | init_seg(&save->ds); | |
1132 | init_seg(&save->fs); | |
1133 | init_seg(&save->gs); | |
1134 | ||
1135 | save->cs.selector = 0xf000; | |
04b66839 | 1136 | save->cs.base = 0xffff0000; |
6aa8b732 AK |
1137 | /* Executable/Readable Code Segment */ |
1138 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
1139 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
1140 | save->cs.limit = 0xffff; | |
6aa8b732 AK |
1141 | |
1142 | save->gdtr.limit = 0xffff; | |
1143 | save->idtr.limit = 0xffff; | |
1144 | ||
1145 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
1146 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
1147 | ||
eaa48512 | 1148 | svm_set_efer(&svm->vcpu, 0); |
d77c26fc | 1149 | save->dr6 = 0xffff0ff0; |
f6e78475 | 1150 | kvm_set_rflags(&svm->vcpu, 2); |
6aa8b732 | 1151 | save->rip = 0x0000fff0; |
5fdbf976 | 1152 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 1153 | |
e0231715 JR |
1154 | /* |
1155 | * This is the guest-visible cr0 value. | |
18fa000a | 1156 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
6aa8b732 | 1157 | */ |
678041ad MT |
1158 | svm->vcpu.arch.cr0 = 0; |
1159 | (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); | |
18fa000a | 1160 | |
66aee91a | 1161 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 1162 | /* rdx = ?? */ |
709ddebf JR |
1163 | |
1164 | if (npt_enabled) { | |
1165 | /* Setup VMCB for Nested Paging */ | |
1166 | control->nested_ctl = 1; | |
8a05a1b8 | 1167 | clr_intercept(svm, INTERCEPT_INVLPG); |
18c918c5 | 1168 | clr_exception_intercept(svm, PF_VECTOR); |
4ee546b4 RJ |
1169 | clr_cr_intercept(svm, INTERCEPT_CR3_READ); |
1170 | clr_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
709ddebf | 1171 | save->g_pat = 0x0007040600070406ULL; |
709ddebf JR |
1172 | save->cr3 = 0; |
1173 | save->cr4 = 0; | |
1174 | } | |
f40f6a45 | 1175 | svm->asid_generation = 0; |
1371d904 | 1176 | |
e6aa9abd | 1177 | svm->nested.vmcb = 0; |
2af9194d JR |
1178 | svm->vcpu.arch.hflags = 0; |
1179 | ||
2a6b20b8 | 1180 | if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { |
565d0998 | 1181 | control->pause_filter_count = 3000; |
8a05a1b8 | 1182 | set_intercept(svm, INTERCEPT_PAUSE); |
565d0998 ML |
1183 | } |
1184 | ||
8d28fec4 RJ |
1185 | mark_all_dirty(svm->vmcb); |
1186 | ||
2af9194d | 1187 | enable_gif(svm); |
6aa8b732 AK |
1188 | } |
1189 | ||
57f252f2 | 1190 | static void svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
1191 | { |
1192 | struct vcpu_svm *svm = to_svm(vcpu); | |
66f7b72e JS |
1193 | u32 dummy; |
1194 | u32 eax = 1; | |
04d2cc77 | 1195 | |
e6101a96 | 1196 | init_vmcb(svm); |
70433389 | 1197 | |
66f7b72e JS |
1198 | kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy); |
1199 | kvm_register_write(vcpu, VCPU_REGS_RDX, eax); | |
04d2cc77 AK |
1200 | } |
1201 | ||
fb3f0f51 | 1202 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 1203 | { |
a2fa3e9f | 1204 | struct vcpu_svm *svm; |
6aa8b732 | 1205 | struct page *page; |
f65c229c | 1206 | struct page *msrpm_pages; |
b286d5d8 | 1207 | struct page *hsave_page; |
3d6368ef | 1208 | struct page *nested_msrpm_pages; |
fb3f0f51 | 1209 | int err; |
6aa8b732 | 1210 | |
c16f862d | 1211 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
1212 | if (!svm) { |
1213 | err = -ENOMEM; | |
1214 | goto out; | |
1215 | } | |
1216 | ||
fbc0db76 JR |
1217 | svm->tsc_ratio = TSC_RATIO_DEFAULT; |
1218 | ||
fb3f0f51 RR |
1219 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); |
1220 | if (err) | |
1221 | goto free_svm; | |
1222 | ||
b7af4043 | 1223 | err = -ENOMEM; |
6aa8b732 | 1224 | page = alloc_page(GFP_KERNEL); |
b7af4043 | 1225 | if (!page) |
fb3f0f51 | 1226 | goto uninit; |
6aa8b732 | 1227 | |
f65c229c JR |
1228 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); |
1229 | if (!msrpm_pages) | |
b7af4043 | 1230 | goto free_page1; |
3d6368ef AG |
1231 | |
1232 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
1233 | if (!nested_msrpm_pages) | |
b7af4043 | 1234 | goto free_page2; |
f65c229c | 1235 | |
b286d5d8 AG |
1236 | hsave_page = alloc_page(GFP_KERNEL); |
1237 | if (!hsave_page) | |
b7af4043 TY |
1238 | goto free_page3; |
1239 | ||
e6aa9abd | 1240 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 1241 | |
b7af4043 TY |
1242 | svm->msrpm = page_address(msrpm_pages); |
1243 | svm_vcpu_init_msrpm(svm->msrpm); | |
1244 | ||
e6aa9abd | 1245 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 1246 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 1247 | |
a2fa3e9f GH |
1248 | svm->vmcb = page_address(page); |
1249 | clear_page(svm->vmcb); | |
1250 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
1251 | svm->asid_generation = 0; | |
e6101a96 | 1252 | init_vmcb(svm); |
a2fa3e9f | 1253 | |
ad312c7c | 1254 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 1255 | if (kvm_vcpu_is_bsp(&svm->vcpu)) |
ad312c7c | 1256 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 1257 | |
2b036c6b BO |
1258 | svm_init_osvw(&svm->vcpu); |
1259 | ||
fb3f0f51 | 1260 | return &svm->vcpu; |
36241b8c | 1261 | |
b7af4043 TY |
1262 | free_page3: |
1263 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
1264 | free_page2: | |
1265 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
1266 | free_page1: | |
1267 | __free_page(page); | |
fb3f0f51 RR |
1268 | uninit: |
1269 | kvm_vcpu_uninit(&svm->vcpu); | |
1270 | free_svm: | |
a4770347 | 1271 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
1272 | out: |
1273 | return ERR_PTR(err); | |
6aa8b732 AK |
1274 | } |
1275 | ||
1276 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
1277 | { | |
a2fa3e9f GH |
1278 | struct vcpu_svm *svm = to_svm(vcpu); |
1279 | ||
fb3f0f51 | 1280 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 1281 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
1282 | __free_page(virt_to_page(svm->nested.hsave)); |
1283 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 1284 | kvm_vcpu_uninit(vcpu); |
a4770347 | 1285 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
1286 | } |
1287 | ||
15ad7146 | 1288 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 1289 | { |
a2fa3e9f | 1290 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 1291 | int i; |
0cc5064d | 1292 | |
0cc5064d | 1293 | if (unlikely(cpu != vcpu->cpu)) { |
4b656b12 | 1294 | svm->asid_generation = 0; |
8d28fec4 | 1295 | mark_all_dirty(svm->vmcb); |
0cc5064d | 1296 | } |
94dfbdb3 | 1297 | |
82ca2d10 AK |
1298 | #ifdef CONFIG_X86_64 |
1299 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); | |
1300 | #endif | |
dacccfdd AK |
1301 | savesegment(fs, svm->host.fs); |
1302 | savesegment(gs, svm->host.gs); | |
1303 | svm->host.ldt = kvm_read_ldt(); | |
1304 | ||
94dfbdb3 | 1305 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1306 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
fbc0db76 JR |
1307 | |
1308 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR) && | |
1309 | svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) { | |
1310 | __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio; | |
1311 | wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio); | |
1312 | } | |
6aa8b732 AK |
1313 | } |
1314 | ||
1315 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
1316 | { | |
a2fa3e9f | 1317 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
1318 | int i; |
1319 | ||
e1beb1d3 | 1320 | ++vcpu->stat.host_state_reload; |
dacccfdd AK |
1321 | kvm_load_ldt(svm->host.ldt); |
1322 | #ifdef CONFIG_X86_64 | |
1323 | loadsegment(fs, svm->host.fs); | |
dacccfdd | 1324 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs); |
893a5ab6 | 1325 | load_gs_index(svm->host.gs); |
dacccfdd | 1326 | #else |
831ca609 | 1327 | #ifdef CONFIG_X86_32_LAZY_GS |
dacccfdd | 1328 | loadsegment(gs, svm->host.gs); |
831ca609 | 1329 | #endif |
dacccfdd | 1330 | #endif |
94dfbdb3 | 1331 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1332 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1333 | } |
1334 | ||
ea5e97e8 KW |
1335 | static void svm_update_cpl(struct kvm_vcpu *vcpu) |
1336 | { | |
1337 | struct vcpu_svm *svm = to_svm(vcpu); | |
1338 | int cpl; | |
1339 | ||
1340 | if (!is_protmode(vcpu)) | |
1341 | cpl = 0; | |
1342 | else if (svm->vmcb->save.rflags & X86_EFLAGS_VM) | |
1343 | cpl = 3; | |
1344 | else | |
1345 | cpl = svm->vmcb->save.cs.selector & 0x3; | |
1346 | ||
1347 | svm->vmcb->save.cpl = cpl; | |
1348 | } | |
1349 | ||
6aa8b732 AK |
1350 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
1351 | { | |
a2fa3e9f | 1352 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
1353 | } |
1354 | ||
1355 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
1356 | { | |
4cee4798 KW |
1357 | unsigned long old_rflags = to_svm(vcpu)->vmcb->save.rflags; |
1358 | ||
a2fa3e9f | 1359 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
4cee4798 KW |
1360 | if ((old_rflags ^ rflags) & X86_EFLAGS_VM) |
1361 | svm_update_cpl(vcpu); | |
6aa8b732 AK |
1362 | } |
1363 | ||
6de4f3ad AK |
1364 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
1365 | { | |
1366 | switch (reg) { | |
1367 | case VCPU_EXREG_PDPTR: | |
1368 | BUG_ON(!npt_enabled); | |
9f8fe504 | 1369 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
6de4f3ad AK |
1370 | break; |
1371 | default: | |
1372 | BUG(); | |
1373 | } | |
1374 | } | |
1375 | ||
f0b85051 AG |
1376 | static void svm_set_vintr(struct vcpu_svm *svm) |
1377 | { | |
8a05a1b8 | 1378 | set_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1379 | } |
1380 | ||
1381 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
1382 | { | |
8a05a1b8 | 1383 | clr_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1384 | } |
1385 | ||
6aa8b732 AK |
1386 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
1387 | { | |
a2fa3e9f | 1388 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
1389 | |
1390 | switch (seg) { | |
1391 | case VCPU_SREG_CS: return &save->cs; | |
1392 | case VCPU_SREG_DS: return &save->ds; | |
1393 | case VCPU_SREG_ES: return &save->es; | |
1394 | case VCPU_SREG_FS: return &save->fs; | |
1395 | case VCPU_SREG_GS: return &save->gs; | |
1396 | case VCPU_SREG_SS: return &save->ss; | |
1397 | case VCPU_SREG_TR: return &save->tr; | |
1398 | case VCPU_SREG_LDTR: return &save->ldtr; | |
1399 | } | |
1400 | BUG(); | |
8b6d44c7 | 1401 | return NULL; |
6aa8b732 AK |
1402 | } |
1403 | ||
1404 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1405 | { | |
1406 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1407 | ||
1408 | return s->base; | |
1409 | } | |
1410 | ||
1411 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
1412 | struct kvm_segment *var, int seg) | |
1413 | { | |
1414 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1415 | ||
1416 | var->base = s->base; | |
1417 | var->limit = s->limit; | |
1418 | var->selector = s->selector; | |
1419 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
1420 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
1421 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
1422 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
1423 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
1424 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
1425 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
1426 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
25022acc | 1427 | |
e0231715 JR |
1428 | /* |
1429 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
1430 | * for cross vendor migration purposes by "not present" |
1431 | */ | |
1432 | var->unusable = !var->present || (var->type == 0); | |
1433 | ||
1fbdc7a5 AP |
1434 | switch (seg) { |
1435 | case VCPU_SREG_CS: | |
1436 | /* | |
1437 | * SVM always stores 0 for the 'G' bit in the CS selector in | |
1438 | * the VMCB on a VMEXIT. This hurts cross-vendor migration: | |
1439 | * Intel's VMENTRY has a check on the 'G' bit. | |
1440 | */ | |
25022acc | 1441 | var->g = s->limit > 0xfffff; |
1fbdc7a5 AP |
1442 | break; |
1443 | case VCPU_SREG_TR: | |
1444 | /* | |
1445 | * Work around a bug where the busy flag in the tr selector | |
1446 | * isn't exposed | |
1447 | */ | |
c0d09828 | 1448 | var->type |= 0x2; |
1fbdc7a5 AP |
1449 | break; |
1450 | case VCPU_SREG_DS: | |
1451 | case VCPU_SREG_ES: | |
1452 | case VCPU_SREG_FS: | |
1453 | case VCPU_SREG_GS: | |
1454 | /* | |
1455 | * The accessed bit must always be set in the segment | |
1456 | * descriptor cache, although it can be cleared in the | |
1457 | * descriptor, the cached bit always remains at 1. Since | |
1458 | * Intel has a check on this, set it here to support | |
1459 | * cross-vendor migration. | |
1460 | */ | |
1461 | if (!var->unusable) | |
1462 | var->type |= 0x1; | |
1463 | break; | |
b586eb02 | 1464 | case VCPU_SREG_SS: |
e0231715 JR |
1465 | /* |
1466 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
1467 | * descriptor is left as 1, although the whole segment has |
1468 | * been made unusable. Clear it here to pass an Intel VMX | |
1469 | * entry check when cross vendor migrating. | |
1470 | */ | |
1471 | if (var->unusable) | |
1472 | var->db = 0; | |
1473 | break; | |
1fbdc7a5 | 1474 | } |
6aa8b732 AK |
1475 | } |
1476 | ||
2e4d2653 IE |
1477 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
1478 | { | |
1479 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
1480 | ||
1481 | return save->cpl; | |
1482 | } | |
1483 | ||
89a27f4d | 1484 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1485 | { |
a2fa3e9f GH |
1486 | struct vcpu_svm *svm = to_svm(vcpu); |
1487 | ||
89a27f4d GN |
1488 | dt->size = svm->vmcb->save.idtr.limit; |
1489 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
1490 | } |
1491 | ||
89a27f4d | 1492 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1493 | { |
a2fa3e9f GH |
1494 | struct vcpu_svm *svm = to_svm(vcpu); |
1495 | ||
89a27f4d GN |
1496 | svm->vmcb->save.idtr.limit = dt->size; |
1497 | svm->vmcb->save.idtr.base = dt->address ; | |
17a703cb | 1498 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1499 | } |
1500 | ||
89a27f4d | 1501 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1502 | { |
a2fa3e9f GH |
1503 | struct vcpu_svm *svm = to_svm(vcpu); |
1504 | ||
89a27f4d GN |
1505 | dt->size = svm->vmcb->save.gdtr.limit; |
1506 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
1507 | } |
1508 | ||
89a27f4d | 1509 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1510 | { |
a2fa3e9f GH |
1511 | struct vcpu_svm *svm = to_svm(vcpu); |
1512 | ||
89a27f4d GN |
1513 | svm->vmcb->save.gdtr.limit = dt->size; |
1514 | svm->vmcb->save.gdtr.base = dt->address ; | |
17a703cb | 1515 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1516 | } |
1517 | ||
e8467fda AK |
1518 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
1519 | { | |
1520 | } | |
1521 | ||
aff48baa AK |
1522 | static void svm_decache_cr3(struct kvm_vcpu *vcpu) |
1523 | { | |
1524 | } | |
1525 | ||
25c4c276 | 1526 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
1527 | { |
1528 | } | |
1529 | ||
d225157b AK |
1530 | static void update_cr0_intercept(struct vcpu_svm *svm) |
1531 | { | |
1532 | ulong gcr0 = svm->vcpu.arch.cr0; | |
1533 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
1534 | ||
1535 | if (!svm->vcpu.fpu_active) | |
1536 | *hcr0 |= SVM_CR0_SELECTIVE_MASK; | |
1537 | else | |
1538 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) | |
1539 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
1540 | ||
dcca1a65 | 1541 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b AK |
1542 | |
1543 | if (gcr0 == *hcr0 && svm->vcpu.fpu_active) { | |
4ee546b4 RJ |
1544 | clr_cr_intercept(svm, INTERCEPT_CR0_READ); |
1545 | clr_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b | 1546 | } else { |
4ee546b4 RJ |
1547 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1548 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b AK |
1549 | } |
1550 | } | |
1551 | ||
6aa8b732 AK |
1552 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1553 | { | |
a2fa3e9f GH |
1554 | struct vcpu_svm *svm = to_svm(vcpu); |
1555 | ||
05b3e0c2 | 1556 | #ifdef CONFIG_X86_64 |
f6801dff | 1557 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 1558 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 1559 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 1560 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1561 | } |
1562 | ||
d77c26fc | 1563 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 1564 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 1565 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
1566 | } |
1567 | } | |
1568 | #endif | |
ad312c7c | 1569 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
1570 | |
1571 | if (!npt_enabled) | |
1572 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 AK |
1573 | |
1574 | if (!vcpu->fpu_active) | |
334df50a | 1575 | cr0 |= X86_CR0_TS; |
709ddebf JR |
1576 | /* |
1577 | * re-enable caching here because the QEMU bios | |
1578 | * does not do it - this results in some delay at | |
1579 | * reboot | |
1580 | */ | |
1581 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 1582 | svm->vmcb->save.cr0 = cr0; |
dcca1a65 | 1583 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 1584 | update_cr0_intercept(svm); |
6aa8b732 AK |
1585 | } |
1586 | ||
5e1746d6 | 1587 | static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 1588 | { |
6394b649 | 1589 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
e5eab0ce JR |
1590 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
1591 | ||
5e1746d6 NHE |
1592 | if (cr4 & X86_CR4_VMXE) |
1593 | return 1; | |
1594 | ||
e5eab0ce | 1595 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) |
f40f6a45 | 1596 | svm_flush_tlb(vcpu); |
6394b649 | 1597 | |
ec077263 JR |
1598 | vcpu->arch.cr4 = cr4; |
1599 | if (!npt_enabled) | |
1600 | cr4 |= X86_CR4_PAE; | |
6394b649 | 1601 | cr4 |= host_cr4_mce; |
ec077263 | 1602 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
dcca1a65 | 1603 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
5e1746d6 | 1604 | return 0; |
6aa8b732 AK |
1605 | } |
1606 | ||
1607 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
1608 | struct kvm_segment *var, int seg) | |
1609 | { | |
a2fa3e9f | 1610 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1611 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
1612 | ||
1613 | s->base = var->base; | |
1614 | s->limit = var->limit; | |
1615 | s->selector = var->selector; | |
1616 | if (var->unusable) | |
1617 | s->attrib = 0; | |
1618 | else { | |
1619 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
1620 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
1621 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
1622 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
1623 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
1624 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
1625 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
1626 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
1627 | } | |
1628 | if (seg == VCPU_SREG_CS) | |
ea5e97e8 | 1629 | svm_update_cpl(vcpu); |
6aa8b732 | 1630 | |
060d0c9a | 1631 | mark_dirty(svm->vmcb, VMCB_SEG); |
6aa8b732 AK |
1632 | } |
1633 | ||
c8639010 | 1634 | static void update_db_bp_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 1635 | { |
d0bfb940 JK |
1636 | struct vcpu_svm *svm = to_svm(vcpu); |
1637 | ||
18c918c5 JR |
1638 | clr_exception_intercept(svm, DB_VECTOR); |
1639 | clr_exception_intercept(svm, BP_VECTOR); | |
44c11430 | 1640 | |
6be7d306 | 1641 | if (svm->nmi_singlestep) |
18c918c5 | 1642 | set_exception_intercept(svm, DB_VECTOR); |
44c11430 | 1643 | |
d0bfb940 JK |
1644 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
1645 | if (vcpu->guest_debug & | |
1646 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
18c918c5 | 1647 | set_exception_intercept(svm, DB_VECTOR); |
d0bfb940 | 1648 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
18c918c5 | 1649 | set_exception_intercept(svm, BP_VECTOR); |
d0bfb940 JK |
1650 | } else |
1651 | vcpu->guest_debug = 0; | |
44c11430 GN |
1652 | } |
1653 | ||
0fe1e009 | 1654 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 1655 | { |
0fe1e009 TH |
1656 | if (sd->next_asid > sd->max_asid) { |
1657 | ++sd->asid_generation; | |
1658 | sd->next_asid = 1; | |
a2fa3e9f | 1659 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
1660 | } |
1661 | ||
0fe1e009 TH |
1662 | svm->asid_generation = sd->asid_generation; |
1663 | svm->vmcb->control.asid = sd->next_asid++; | |
d48086d1 JR |
1664 | |
1665 | mark_dirty(svm->vmcb, VMCB_ASID); | |
6aa8b732 AK |
1666 | } |
1667 | ||
020df079 | 1668 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 1669 | { |
42dbaa5a | 1670 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 1671 | |
020df079 | 1672 | svm->vmcb->save.dr7 = value; |
72214b96 | 1673 | mark_dirty(svm->vmcb, VMCB_DR); |
6aa8b732 AK |
1674 | } |
1675 | ||
851ba692 | 1676 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 1677 | { |
631bc487 | 1678 | u64 fault_address = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1679 | u32 error_code; |
631bc487 | 1680 | int r = 1; |
6aa8b732 | 1681 | |
631bc487 GN |
1682 | switch (svm->apf_reason) { |
1683 | default: | |
1684 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 | 1685 | |
631bc487 GN |
1686 | trace_kvm_page_fault(fault_address, error_code); |
1687 | if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu)) | |
1688 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
dc25e89e AP |
1689 | r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code, |
1690 | svm->vmcb->control.insn_bytes, | |
1691 | svm->vmcb->control.insn_len); | |
631bc487 GN |
1692 | break; |
1693 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
1694 | svm->apf_reason = 0; | |
1695 | local_irq_disable(); | |
1696 | kvm_async_pf_task_wait(fault_address); | |
1697 | local_irq_enable(); | |
1698 | break; | |
1699 | case KVM_PV_REASON_PAGE_READY: | |
1700 | svm->apf_reason = 0; | |
1701 | local_irq_disable(); | |
1702 | kvm_async_pf_task_wake(fault_address); | |
1703 | local_irq_enable(); | |
1704 | break; | |
1705 | } | |
1706 | return r; | |
6aa8b732 AK |
1707 | } |
1708 | ||
851ba692 | 1709 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 1710 | { |
851ba692 AK |
1711 | struct kvm_run *kvm_run = svm->vcpu.run; |
1712 | ||
d0bfb940 | 1713 | if (!(svm->vcpu.guest_debug & |
44c11430 | 1714 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 1715 | !svm->nmi_singlestep) { |
d0bfb940 JK |
1716 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
1717 | return 1; | |
1718 | } | |
44c11430 | 1719 | |
6be7d306 JK |
1720 | if (svm->nmi_singlestep) { |
1721 | svm->nmi_singlestep = false; | |
44c11430 GN |
1722 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) |
1723 | svm->vmcb->save.rflags &= | |
1724 | ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
c8639010 | 1725 | update_db_bp_intercept(&svm->vcpu); |
44c11430 GN |
1726 | } |
1727 | ||
1728 | if (svm->vcpu.guest_debug & | |
e0231715 | 1729 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
1730 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1731 | kvm_run->debug.arch.pc = | |
1732 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1733 | kvm_run->debug.arch.exception = DB_VECTOR; | |
1734 | return 0; | |
1735 | } | |
1736 | ||
1737 | return 1; | |
d0bfb940 JK |
1738 | } |
1739 | ||
851ba692 | 1740 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 1741 | { |
851ba692 AK |
1742 | struct kvm_run *kvm_run = svm->vcpu.run; |
1743 | ||
d0bfb940 JK |
1744 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1745 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1746 | kvm_run->debug.arch.exception = BP_VECTOR; | |
1747 | return 0; | |
1748 | } | |
1749 | ||
851ba692 | 1750 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
1751 | { |
1752 | int er; | |
1753 | ||
51d8b661 | 1754 | er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1755 | if (er != EMULATE_DONE) |
7ee5d940 | 1756 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1757 | return 1; |
1758 | } | |
1759 | ||
6b52d186 | 1760 | static void svm_fpu_activate(struct kvm_vcpu *vcpu) |
7807fa6c | 1761 | { |
6b52d186 | 1762 | struct vcpu_svm *svm = to_svm(vcpu); |
66a562f7 | 1763 | |
18c918c5 | 1764 | clr_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 1765 | |
e756fc62 | 1766 | svm->vcpu.fpu_active = 1; |
d225157b | 1767 | update_cr0_intercept(svm); |
6b52d186 | 1768 | } |
a2fa3e9f | 1769 | |
6b52d186 AK |
1770 | static int nm_interception(struct vcpu_svm *svm) |
1771 | { | |
1772 | svm_fpu_activate(&svm->vcpu); | |
a2fa3e9f | 1773 | return 1; |
7807fa6c AL |
1774 | } |
1775 | ||
67ec6607 JR |
1776 | static bool is_erratum_383(void) |
1777 | { | |
1778 | int err, i; | |
1779 | u64 value; | |
1780 | ||
1781 | if (!erratum_383_found) | |
1782 | return false; | |
1783 | ||
1784 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
1785 | if (err) | |
1786 | return false; | |
1787 | ||
1788 | /* Bit 62 may or may not be set for this mce */ | |
1789 | value &= ~(1ULL << 62); | |
1790 | ||
1791 | if (value != 0xb600000000010015ULL) | |
1792 | return false; | |
1793 | ||
1794 | /* Clear MCi_STATUS registers */ | |
1795 | for (i = 0; i < 6; ++i) | |
1796 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
1797 | ||
1798 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
1799 | if (!err) { | |
1800 | u32 low, high; | |
1801 | ||
1802 | value &= ~(1ULL << 2); | |
1803 | low = lower_32_bits(value); | |
1804 | high = upper_32_bits(value); | |
1805 | ||
1806 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
1807 | } | |
1808 | ||
1809 | /* Flush tlb to evict multi-match entries */ | |
1810 | __flush_tlb_all(); | |
1811 | ||
1812 | return true; | |
1813 | } | |
1814 | ||
fe5913e4 | 1815 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 1816 | { |
67ec6607 JR |
1817 | if (is_erratum_383()) { |
1818 | /* | |
1819 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
1820 | * guest. | |
1821 | */ | |
1822 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
1823 | ||
a8eeb04a | 1824 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
1825 | |
1826 | return; | |
1827 | } | |
1828 | ||
53371b50 JR |
1829 | /* |
1830 | * On an #MC intercept the MCE handler is not called automatically in | |
1831 | * the host. So do it by hand here. | |
1832 | */ | |
1833 | asm volatile ( | |
1834 | "int $0x12\n"); | |
1835 | /* not sure if we ever come back to this point */ | |
1836 | ||
fe5913e4 JR |
1837 | return; |
1838 | } | |
1839 | ||
1840 | static int mc_interception(struct vcpu_svm *svm) | |
1841 | { | |
53371b50 JR |
1842 | return 1; |
1843 | } | |
1844 | ||
851ba692 | 1845 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 1846 | { |
851ba692 AK |
1847 | struct kvm_run *kvm_run = svm->vcpu.run; |
1848 | ||
46fe4ddd JR |
1849 | /* |
1850 | * VMCB is undefined after a SHUTDOWN intercept | |
1851 | * so reinitialize it. | |
1852 | */ | |
a2fa3e9f | 1853 | clear_page(svm->vmcb); |
e6101a96 | 1854 | init_vmcb(svm); |
46fe4ddd JR |
1855 | |
1856 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1857 | return 0; | |
1858 | } | |
1859 | ||
851ba692 | 1860 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 1861 | { |
cf8f70bf | 1862 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 1863 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
34c33d16 | 1864 | int size, in, string; |
039576c0 | 1865 | unsigned port; |
6aa8b732 | 1866 | |
e756fc62 | 1867 | ++svm->vcpu.stat.io_exits; |
e70669ab | 1868 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 1869 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
cf8f70bf | 1870 | if (string || in) |
51d8b661 | 1871 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
cf8f70bf | 1872 | |
039576c0 AK |
1873 | port = io_info >> 16; |
1874 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 1875 | svm->next_rip = svm->vmcb->control.exit_info_2; |
e93f36bc | 1876 | skip_emulated_instruction(&svm->vcpu); |
cf8f70bf GN |
1877 | |
1878 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
1879 | } |
1880 | ||
851ba692 | 1881 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
1882 | { |
1883 | return 1; | |
1884 | } | |
1885 | ||
851ba692 | 1886 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
1887 | { |
1888 | ++svm->vcpu.stat.irq_exits; | |
1889 | return 1; | |
1890 | } | |
1891 | ||
851ba692 | 1892 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
1893 | { |
1894 | return 1; | |
1895 | } | |
1896 | ||
851ba692 | 1897 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 1898 | { |
5fdbf976 | 1899 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 RR |
1900 | skip_emulated_instruction(&svm->vcpu); |
1901 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1902 | } |
1903 | ||
851ba692 | 1904 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 1905 | { |
5fdbf976 | 1906 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
e756fc62 | 1907 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1908 | kvm_emulate_hypercall(&svm->vcpu); |
1909 | return 1; | |
02e235bc AK |
1910 | } |
1911 | ||
5bd2edc3 JR |
1912 | static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) |
1913 | { | |
1914 | struct vcpu_svm *svm = to_svm(vcpu); | |
1915 | ||
1916 | return svm->nested.nested_cr3; | |
1917 | } | |
1918 | ||
e4e517b4 AK |
1919 | static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index) |
1920 | { | |
1921 | struct vcpu_svm *svm = to_svm(vcpu); | |
1922 | u64 cr3 = svm->nested.nested_cr3; | |
1923 | u64 pdpte; | |
1924 | int ret; | |
1925 | ||
1926 | ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte, | |
1927 | offset_in_page(cr3) + index * 8, 8); | |
1928 | if (ret) | |
1929 | return 0; | |
1930 | return pdpte; | |
1931 | } | |
1932 | ||
5bd2edc3 JR |
1933 | static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu, |
1934 | unsigned long root) | |
1935 | { | |
1936 | struct vcpu_svm *svm = to_svm(vcpu); | |
1937 | ||
1938 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 1939 | mark_dirty(svm->vmcb, VMCB_NPT); |
f40f6a45 | 1940 | svm_flush_tlb(vcpu); |
5bd2edc3 JR |
1941 | } |
1942 | ||
6389ee94 AK |
1943 | static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, |
1944 | struct x86_exception *fault) | |
5bd2edc3 JR |
1945 | { |
1946 | struct vcpu_svm *svm = to_svm(vcpu); | |
1947 | ||
1948 | svm->vmcb->control.exit_code = SVM_EXIT_NPF; | |
1949 | svm->vmcb->control.exit_code_hi = 0; | |
6389ee94 AK |
1950 | svm->vmcb->control.exit_info_1 = fault->error_code; |
1951 | svm->vmcb->control.exit_info_2 = fault->address; | |
5bd2edc3 JR |
1952 | |
1953 | nested_svm_vmexit(svm); | |
1954 | } | |
1955 | ||
4b16184c JR |
1956 | static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) |
1957 | { | |
1958 | int r; | |
1959 | ||
1960 | r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu); | |
1961 | ||
1962 | vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3; | |
1963 | vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3; | |
e4e517b4 | 1964 | vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr; |
4b16184c JR |
1965 | vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit; |
1966 | vcpu->arch.mmu.shadow_root_level = get_npt_level(); | |
1967 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
1968 | ||
1969 | return r; | |
1970 | } | |
1971 | ||
1972 | static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
1973 | { | |
1974 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
1975 | } | |
1976 | ||
c0725420 AG |
1977 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
1978 | { | |
f6801dff | 1979 | if (!(svm->vcpu.arch.efer & EFER_SVME) |
c0725420 AG |
1980 | || !is_paging(&svm->vcpu)) { |
1981 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
1982 | return 1; | |
1983 | } | |
1984 | ||
1985 | if (svm->vmcb->save.cpl) { | |
1986 | kvm_inject_gp(&svm->vcpu, 0); | |
1987 | return 1; | |
1988 | } | |
1989 | ||
1990 | return 0; | |
1991 | } | |
1992 | ||
cf74a78b AG |
1993 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
1994 | bool has_error_code, u32 error_code) | |
1995 | { | |
b8e88bc8 JR |
1996 | int vmexit; |
1997 | ||
2030753d | 1998 | if (!is_guest_mode(&svm->vcpu)) |
0295ad7d | 1999 | return 0; |
cf74a78b | 2000 | |
0295ad7d JR |
2001 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
2002 | svm->vmcb->control.exit_code_hi = 0; | |
2003 | svm->vmcb->control.exit_info_1 = error_code; | |
2004 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
2005 | ||
b8e88bc8 JR |
2006 | vmexit = nested_svm_intercept(svm); |
2007 | if (vmexit == NESTED_EXIT_DONE) | |
2008 | svm->nested.exit_required = true; | |
2009 | ||
2010 | return vmexit; | |
cf74a78b AG |
2011 | } |
2012 | ||
8fe54654 JR |
2013 | /* This function returns true if it is save to enable the irq window */ |
2014 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 2015 | { |
2030753d | 2016 | if (!is_guest_mode(&svm->vcpu)) |
8fe54654 | 2017 | return true; |
cf74a78b | 2018 | |
26666957 | 2019 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 2020 | return true; |
cf74a78b | 2021 | |
26666957 | 2022 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 2023 | return false; |
cf74a78b | 2024 | |
a0a07cd2 GN |
2025 | /* |
2026 | * if vmexit was already requested (by intercepted exception | |
2027 | * for instance) do not overwrite it with "external interrupt" | |
2028 | * vmexit. | |
2029 | */ | |
2030 | if (svm->nested.exit_required) | |
2031 | return false; | |
2032 | ||
197717d5 JR |
2033 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
2034 | svm->vmcb->control.exit_info_1 = 0; | |
2035 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 2036 | |
cd3ff653 JR |
2037 | if (svm->nested.intercept & 1ULL) { |
2038 | /* | |
2039 | * The #vmexit can't be emulated here directly because this | |
c5ec2e56 | 2040 | * code path runs with irqs and preemption disabled. A |
cd3ff653 JR |
2041 | * #vmexit emulation might sleep. Only signal request for |
2042 | * the #vmexit here. | |
2043 | */ | |
2044 | svm->nested.exit_required = true; | |
236649de | 2045 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 2046 | return false; |
cf74a78b AG |
2047 | } |
2048 | ||
8fe54654 | 2049 | return true; |
cf74a78b AG |
2050 | } |
2051 | ||
887f500c JR |
2052 | /* This function returns true if it is save to enable the nmi window */ |
2053 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
2054 | { | |
2030753d | 2055 | if (!is_guest_mode(&svm->vcpu)) |
887f500c JR |
2056 | return true; |
2057 | ||
2058 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
2059 | return true; | |
2060 | ||
2061 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
2062 | svm->nested.exit_required = true; | |
2063 | ||
2064 | return false; | |
cf74a78b AG |
2065 | } |
2066 | ||
7597f129 | 2067 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) |
34f80cfa JR |
2068 | { |
2069 | struct page *page; | |
2070 | ||
6c3bd3d7 JR |
2071 | might_sleep(); |
2072 | ||
34f80cfa | 2073 | page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT); |
34f80cfa JR |
2074 | if (is_error_page(page)) |
2075 | goto error; | |
2076 | ||
7597f129 JR |
2077 | *_page = page; |
2078 | ||
2079 | return kmap(page); | |
34f80cfa JR |
2080 | |
2081 | error: | |
34f80cfa JR |
2082 | kvm_inject_gp(&svm->vcpu, 0); |
2083 | ||
2084 | return NULL; | |
2085 | } | |
2086 | ||
7597f129 | 2087 | static void nested_svm_unmap(struct page *page) |
34f80cfa | 2088 | { |
7597f129 | 2089 | kunmap(page); |
34f80cfa JR |
2090 | kvm_release_page_dirty(page); |
2091 | } | |
34f80cfa | 2092 | |
ce2ac085 JR |
2093 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
2094 | { | |
2095 | unsigned port; | |
2096 | u8 val, bit; | |
2097 | u64 gpa; | |
34f80cfa | 2098 | |
ce2ac085 JR |
2099 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
2100 | return NESTED_EXIT_HOST; | |
34f80cfa | 2101 | |
ce2ac085 JR |
2102 | port = svm->vmcb->control.exit_info_1 >> 16; |
2103 | gpa = svm->nested.vmcb_iopm + (port / 8); | |
2104 | bit = port % 8; | |
2105 | val = 0; | |
2106 | ||
2107 | if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1)) | |
2108 | val &= (1 << bit); | |
2109 | ||
2110 | return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; | |
34f80cfa JR |
2111 | } |
2112 | ||
d2477826 | 2113 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 2114 | { |
0d6b3537 JR |
2115 | u32 offset, msr, value; |
2116 | int write, mask; | |
4c2161ae | 2117 | |
3d62d9aa | 2118 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 2119 | return NESTED_EXIT_HOST; |
3d62d9aa | 2120 | |
0d6b3537 JR |
2121 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
2122 | offset = svm_msrpm_offset(msr); | |
2123 | write = svm->vmcb->control.exit_info_1 & 1; | |
2124 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 2125 | |
0d6b3537 JR |
2126 | if (offset == MSR_INVALID) |
2127 | return NESTED_EXIT_DONE; | |
4c2161ae | 2128 | |
0d6b3537 JR |
2129 | /* Offset is in 32 bit units but need in 8 bit units */ |
2130 | offset *= 4; | |
4c2161ae | 2131 | |
0d6b3537 JR |
2132 | if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4)) |
2133 | return NESTED_EXIT_DONE; | |
3d62d9aa | 2134 | |
0d6b3537 | 2135 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
2136 | } |
2137 | ||
410e4d57 | 2138 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 2139 | { |
cf74a78b | 2140 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 2141 | |
410e4d57 JR |
2142 | switch (exit_code) { |
2143 | case SVM_EXIT_INTR: | |
2144 | case SVM_EXIT_NMI: | |
ff47a49b | 2145 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 2146 | return NESTED_EXIT_HOST; |
410e4d57 | 2147 | case SVM_EXIT_NPF: |
e0231715 | 2148 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
2149 | if (npt_enabled) |
2150 | return NESTED_EXIT_HOST; | |
2151 | break; | |
410e4d57 | 2152 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
631bc487 GN |
2153 | /* When we're shadowing, trap PFs, but not async PF */ |
2154 | if (!npt_enabled && svm->apf_reason == 0) | |
410e4d57 JR |
2155 | return NESTED_EXIT_HOST; |
2156 | break; | |
66a562f7 JR |
2157 | case SVM_EXIT_EXCP_BASE + NM_VECTOR: |
2158 | nm_interception(svm); | |
2159 | break; | |
410e4d57 JR |
2160 | default: |
2161 | break; | |
cf74a78b AG |
2162 | } |
2163 | ||
410e4d57 JR |
2164 | return NESTED_EXIT_CONTINUE; |
2165 | } | |
2166 | ||
2167 | /* | |
2168 | * If this function returns true, this #vmexit was already handled | |
2169 | */ | |
b8e88bc8 | 2170 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
2171 | { |
2172 | u32 exit_code = svm->vmcb->control.exit_code; | |
2173 | int vmexit = NESTED_EXIT_HOST; | |
2174 | ||
cf74a78b | 2175 | switch (exit_code) { |
9c4e40b9 | 2176 | case SVM_EXIT_MSR: |
3d62d9aa | 2177 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 2178 | break; |
ce2ac085 JR |
2179 | case SVM_EXIT_IOIO: |
2180 | vmexit = nested_svm_intercept_ioio(svm); | |
2181 | break; | |
4ee546b4 RJ |
2182 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: { |
2183 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0); | |
2184 | if (svm->nested.intercept_cr & bit) | |
410e4d57 | 2185 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2186 | break; |
2187 | } | |
3aed041a JR |
2188 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: { |
2189 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0); | |
2190 | if (svm->nested.intercept_dr & bit) | |
410e4d57 | 2191 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2192 | break; |
2193 | } | |
2194 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
2195 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
aad42c64 | 2196 | if (svm->nested.intercept_exceptions & excp_bits) |
410e4d57 | 2197 | vmexit = NESTED_EXIT_DONE; |
631bc487 GN |
2198 | /* async page fault always cause vmexit */ |
2199 | else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) && | |
2200 | svm->apf_reason != 0) | |
2201 | vmexit = NESTED_EXIT_DONE; | |
cf74a78b AG |
2202 | break; |
2203 | } | |
228070b1 JR |
2204 | case SVM_EXIT_ERR: { |
2205 | vmexit = NESTED_EXIT_DONE; | |
2206 | break; | |
2207 | } | |
cf74a78b AG |
2208 | default: { |
2209 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 2210 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 2211 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2212 | } |
2213 | } | |
2214 | ||
b8e88bc8 JR |
2215 | return vmexit; |
2216 | } | |
2217 | ||
2218 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
2219 | { | |
2220 | int vmexit; | |
2221 | ||
2222 | vmexit = nested_svm_intercept(svm); | |
2223 | ||
2224 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 2225 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
2226 | |
2227 | return vmexit; | |
cf74a78b AG |
2228 | } |
2229 | ||
0460a979 JR |
2230 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
2231 | { | |
2232 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
2233 | struct vmcb_control_area *from = &from_vmcb->control; | |
2234 | ||
4ee546b4 | 2235 | dst->intercept_cr = from->intercept_cr; |
3aed041a | 2236 | dst->intercept_dr = from->intercept_dr; |
0460a979 JR |
2237 | dst->intercept_exceptions = from->intercept_exceptions; |
2238 | dst->intercept = from->intercept; | |
2239 | dst->iopm_base_pa = from->iopm_base_pa; | |
2240 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
2241 | dst->tsc_offset = from->tsc_offset; | |
2242 | dst->asid = from->asid; | |
2243 | dst->tlb_ctl = from->tlb_ctl; | |
2244 | dst->int_ctl = from->int_ctl; | |
2245 | dst->int_vector = from->int_vector; | |
2246 | dst->int_state = from->int_state; | |
2247 | dst->exit_code = from->exit_code; | |
2248 | dst->exit_code_hi = from->exit_code_hi; | |
2249 | dst->exit_info_1 = from->exit_info_1; | |
2250 | dst->exit_info_2 = from->exit_info_2; | |
2251 | dst->exit_int_info = from->exit_int_info; | |
2252 | dst->exit_int_info_err = from->exit_int_info_err; | |
2253 | dst->nested_ctl = from->nested_ctl; | |
2254 | dst->event_inj = from->event_inj; | |
2255 | dst->event_inj_err = from->event_inj_err; | |
2256 | dst->nested_cr3 = from->nested_cr3; | |
2257 | dst->lbr_ctl = from->lbr_ctl; | |
2258 | } | |
2259 | ||
34f80cfa | 2260 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 2261 | { |
34f80cfa | 2262 | struct vmcb *nested_vmcb; |
e6aa9abd | 2263 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 2264 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2265 | struct page *page; |
cf74a78b | 2266 | |
17897f36 JR |
2267 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
2268 | vmcb->control.exit_info_1, | |
2269 | vmcb->control.exit_info_2, | |
2270 | vmcb->control.exit_int_info, | |
e097e5ff SH |
2271 | vmcb->control.exit_int_info_err, |
2272 | KVM_ISA_SVM); | |
17897f36 | 2273 | |
7597f129 | 2274 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); |
34f80cfa JR |
2275 | if (!nested_vmcb) |
2276 | return 1; | |
2277 | ||
2030753d JR |
2278 | /* Exit Guest-Mode */ |
2279 | leave_guest_mode(&svm->vcpu); | |
06fc7772 JR |
2280 | svm->nested.vmcb = 0; |
2281 | ||
cf74a78b | 2282 | /* Give the current vmcb to the guest */ |
33740e40 JR |
2283 | disable_gif(svm); |
2284 | ||
2285 | nested_vmcb->save.es = vmcb->save.es; | |
2286 | nested_vmcb->save.cs = vmcb->save.cs; | |
2287 | nested_vmcb->save.ss = vmcb->save.ss; | |
2288 | nested_vmcb->save.ds = vmcb->save.ds; | |
2289 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
2290 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
3f6a9d16 | 2291 | nested_vmcb->save.efer = svm->vcpu.arch.efer; |
cdbbdc12 | 2292 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
9f8fe504 | 2293 | nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu); |
33740e40 | 2294 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 2295 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2296 | nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu); |
33740e40 JR |
2297 | nested_vmcb->save.rip = vmcb->save.rip; |
2298 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
2299 | nested_vmcb->save.rax = vmcb->save.rax; | |
2300 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
2301 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
2302 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
2303 | ||
2304 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
2305 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
2306 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
2307 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
2308 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
2309 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
2310 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
2311 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
2312 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
7a190667 | 2313 | nested_vmcb->control.next_rip = vmcb->control.next_rip; |
8d23c466 AG |
2314 | |
2315 | /* | |
2316 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
2317 | * to make sure that we do not lose injected events. So check event_inj | |
2318 | * here and copy it to exit_int_info if it is valid. | |
2319 | * Exit_int_info and event_inj can't be both valid because the case | |
2320 | * below only happens on a VMRUN instruction intercept which has | |
2321 | * no valid exit_int_info set. | |
2322 | */ | |
2323 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
2324 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
2325 | ||
2326 | nc->exit_int_info = vmcb->control.event_inj; | |
2327 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
2328 | } | |
2329 | ||
33740e40 JR |
2330 | nested_vmcb->control.tlb_ctl = 0; |
2331 | nested_vmcb->control.event_inj = 0; | |
2332 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
2333 | |
2334 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
2335 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
2336 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
2337 | ||
cf74a78b | 2338 | /* Restore the original control entries */ |
0460a979 | 2339 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 2340 | |
219b65dc AG |
2341 | kvm_clear_exception_queue(&svm->vcpu); |
2342 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b | 2343 | |
4b16184c JR |
2344 | svm->nested.nested_cr3 = 0; |
2345 | ||
cf74a78b AG |
2346 | /* Restore selected save entries */ |
2347 | svm->vmcb->save.es = hsave->save.es; | |
2348 | svm->vmcb->save.cs = hsave->save.cs; | |
2349 | svm->vmcb->save.ss = hsave->save.ss; | |
2350 | svm->vmcb->save.ds = hsave->save.ds; | |
2351 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
2352 | svm->vmcb->save.idtr = hsave->save.idtr; | |
f6e78475 | 2353 | kvm_set_rflags(&svm->vcpu, hsave->save.rflags); |
cf74a78b AG |
2354 | svm_set_efer(&svm->vcpu, hsave->save.efer); |
2355 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
2356 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
2357 | if (npt_enabled) { | |
2358 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
2359 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
2360 | } else { | |
2390218b | 2361 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b AG |
2362 | } |
2363 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
2364 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
2365 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
2366 | svm->vmcb->save.dr7 = 0; | |
2367 | svm->vmcb->save.cpl = 0; | |
2368 | svm->vmcb->control.exit_int_info = 0; | |
2369 | ||
8d28fec4 RJ |
2370 | mark_all_dirty(svm->vmcb); |
2371 | ||
7597f129 | 2372 | nested_svm_unmap(page); |
cf74a78b | 2373 | |
4b16184c | 2374 | nested_svm_uninit_mmu_context(&svm->vcpu); |
cf74a78b AG |
2375 | kvm_mmu_reset_context(&svm->vcpu); |
2376 | kvm_mmu_load(&svm->vcpu); | |
2377 | ||
2378 | return 0; | |
2379 | } | |
3d6368ef | 2380 | |
9738b2c9 | 2381 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 2382 | { |
323c3d80 JR |
2383 | /* |
2384 | * This function merges the msr permission bitmaps of kvm and the | |
c5ec2e56 | 2385 | * nested vmcb. It is optimized in that it only merges the parts where |
323c3d80 JR |
2386 | * the kvm msr permission bitmap may contain zero bits |
2387 | */ | |
3d6368ef | 2388 | int i; |
9738b2c9 | 2389 | |
323c3d80 JR |
2390 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
2391 | return true; | |
9738b2c9 | 2392 | |
323c3d80 JR |
2393 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
2394 | u32 value, p; | |
2395 | u64 offset; | |
9738b2c9 | 2396 | |
323c3d80 JR |
2397 | if (msrpm_offsets[i] == 0xffffffff) |
2398 | break; | |
3d6368ef | 2399 | |
0d6b3537 JR |
2400 | p = msrpm_offsets[i]; |
2401 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 JR |
2402 | |
2403 | if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4)) | |
2404 | return false; | |
2405 | ||
2406 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
2407 | } | |
3d6368ef | 2408 | |
323c3d80 | 2409 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); |
9738b2c9 JR |
2410 | |
2411 | return true; | |
3d6368ef AG |
2412 | } |
2413 | ||
52c65a30 JR |
2414 | static bool nested_vmcb_checks(struct vmcb *vmcb) |
2415 | { | |
2416 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
2417 | return false; | |
2418 | ||
dbe77584 JR |
2419 | if (vmcb->control.asid == 0) |
2420 | return false; | |
2421 | ||
4b16184c JR |
2422 | if (vmcb->control.nested_ctl && !npt_enabled) |
2423 | return false; | |
2424 | ||
52c65a30 JR |
2425 | return true; |
2426 | } | |
2427 | ||
9738b2c9 | 2428 | static bool nested_svm_vmrun(struct vcpu_svm *svm) |
3d6368ef | 2429 | { |
9738b2c9 | 2430 | struct vmcb *nested_vmcb; |
e6aa9abd | 2431 | struct vmcb *hsave = svm->nested.hsave; |
defbba56 | 2432 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2433 | struct page *page; |
06fc7772 | 2434 | u64 vmcb_gpa; |
3d6368ef | 2435 | |
06fc7772 | 2436 | vmcb_gpa = svm->vmcb->save.rax; |
3d6368ef | 2437 | |
7597f129 | 2438 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9738b2c9 JR |
2439 | if (!nested_vmcb) |
2440 | return false; | |
2441 | ||
52c65a30 JR |
2442 | if (!nested_vmcb_checks(nested_vmcb)) { |
2443 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
2444 | nested_vmcb->control.exit_code_hi = 0; | |
2445 | nested_vmcb->control.exit_info_1 = 0; | |
2446 | nested_vmcb->control.exit_info_2 = 0; | |
2447 | ||
2448 | nested_svm_unmap(page); | |
2449 | ||
2450 | return false; | |
2451 | } | |
2452 | ||
b75f4eb3 | 2453 | trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa, |
0ac406de JR |
2454 | nested_vmcb->save.rip, |
2455 | nested_vmcb->control.int_ctl, | |
2456 | nested_vmcb->control.event_inj, | |
2457 | nested_vmcb->control.nested_ctl); | |
2458 | ||
4ee546b4 RJ |
2459 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, |
2460 | nested_vmcb->control.intercept_cr >> 16, | |
2e554e8d JR |
2461 | nested_vmcb->control.intercept_exceptions, |
2462 | nested_vmcb->control.intercept); | |
2463 | ||
3d6368ef | 2464 | /* Clear internal status */ |
219b65dc AG |
2465 | kvm_clear_exception_queue(&svm->vcpu); |
2466 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3d6368ef | 2467 | |
e0231715 JR |
2468 | /* |
2469 | * Save the old vmcb, so we don't need to pick what we save, but can | |
2470 | * restore everything when a VMEXIT occurs | |
2471 | */ | |
defbba56 JR |
2472 | hsave->save.es = vmcb->save.es; |
2473 | hsave->save.cs = vmcb->save.cs; | |
2474 | hsave->save.ss = vmcb->save.ss; | |
2475 | hsave->save.ds = vmcb->save.ds; | |
2476 | hsave->save.gdtr = vmcb->save.gdtr; | |
2477 | hsave->save.idtr = vmcb->save.idtr; | |
f6801dff | 2478 | hsave->save.efer = svm->vcpu.arch.efer; |
4d4ec087 | 2479 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); |
defbba56 | 2480 | hsave->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2481 | hsave->save.rflags = kvm_get_rflags(&svm->vcpu); |
b75f4eb3 | 2482 | hsave->save.rip = kvm_rip_read(&svm->vcpu); |
defbba56 JR |
2483 | hsave->save.rsp = vmcb->save.rsp; |
2484 | hsave->save.rax = vmcb->save.rax; | |
2485 | if (npt_enabled) | |
2486 | hsave->save.cr3 = vmcb->save.cr3; | |
2487 | else | |
9f8fe504 | 2488 | hsave->save.cr3 = kvm_read_cr3(&svm->vcpu); |
defbba56 | 2489 | |
0460a979 | 2490 | copy_vmcb_control_area(hsave, vmcb); |
3d6368ef | 2491 | |
f6e78475 | 2492 | if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF) |
3d6368ef AG |
2493 | svm->vcpu.arch.hflags |= HF_HIF_MASK; |
2494 | else | |
2495 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
2496 | ||
4b16184c JR |
2497 | if (nested_vmcb->control.nested_ctl) { |
2498 | kvm_mmu_unload(&svm->vcpu); | |
2499 | svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; | |
2500 | nested_svm_init_mmu_context(&svm->vcpu); | |
2501 | } | |
2502 | ||
3d6368ef AG |
2503 | /* Load the nested guest state */ |
2504 | svm->vmcb->save.es = nested_vmcb->save.es; | |
2505 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
2506 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
2507 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
2508 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
2509 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
f6e78475 | 2510 | kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags); |
3d6368ef AG |
2511 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); |
2512 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
2513 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
2514 | if (npt_enabled) { | |
2515 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
2516 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 2517 | } else |
2390218b | 2518 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
2519 | |
2520 | /* Guest paging mode is active - reset mmu */ | |
2521 | kvm_mmu_reset_context(&svm->vcpu); | |
2522 | ||
defbba56 | 2523 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
2524 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
2525 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
2526 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
e0231715 | 2527 | |
3d6368ef AG |
2528 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
2529 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
2530 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
2531 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
2532 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
2533 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
2534 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
2535 | ||
f7138538 | 2536 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 2537 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 2538 | |
aad42c64 | 2539 | /* cache intercepts */ |
4ee546b4 | 2540 | svm->nested.intercept_cr = nested_vmcb->control.intercept_cr; |
3aed041a | 2541 | svm->nested.intercept_dr = nested_vmcb->control.intercept_dr; |
aad42c64 JR |
2542 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; |
2543 | svm->nested.intercept = nested_vmcb->control.intercept; | |
2544 | ||
f40f6a45 | 2545 | svm_flush_tlb(&svm->vcpu); |
3d6368ef | 2546 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
2547 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
2548 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
2549 | else | |
2550 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
2551 | ||
88ab24ad JR |
2552 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
2553 | /* We only want the cr8 intercept bits of the guest */ | |
4ee546b4 RJ |
2554 | clr_cr_intercept(svm, INTERCEPT_CR8_READ); |
2555 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
88ab24ad JR |
2556 | } |
2557 | ||
0d945bd9 | 2558 | /* We don't want to see VMMCALLs from a nested guest */ |
8a05a1b8 | 2559 | clr_intercept(svm, INTERCEPT_VMMCALL); |
0d945bd9 | 2560 | |
88ab24ad | 2561 | svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl; |
3d6368ef AG |
2562 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
2563 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
2564 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
2565 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
2566 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
2567 | ||
7597f129 | 2568 | nested_svm_unmap(page); |
9738b2c9 | 2569 | |
2030753d JR |
2570 | /* Enter Guest-Mode */ |
2571 | enter_guest_mode(&svm->vcpu); | |
2572 | ||
384c6368 JR |
2573 | /* |
2574 | * Merge guest and host intercepts - must be called with vcpu in | |
2575 | * guest-mode to take affect here | |
2576 | */ | |
2577 | recalc_intercepts(svm); | |
2578 | ||
06fc7772 | 2579 | svm->nested.vmcb = vmcb_gpa; |
9738b2c9 | 2580 | |
2af9194d | 2581 | enable_gif(svm); |
3d6368ef | 2582 | |
8d28fec4 RJ |
2583 | mark_all_dirty(svm->vmcb); |
2584 | ||
9738b2c9 | 2585 | return true; |
3d6368ef AG |
2586 | } |
2587 | ||
9966bf68 | 2588 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
2589 | { |
2590 | to_vmcb->save.fs = from_vmcb->save.fs; | |
2591 | to_vmcb->save.gs = from_vmcb->save.gs; | |
2592 | to_vmcb->save.tr = from_vmcb->save.tr; | |
2593 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
2594 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
2595 | to_vmcb->save.star = from_vmcb->save.star; | |
2596 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
2597 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
2598 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
2599 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
2600 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
2601 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
2602 | } |
2603 | ||
851ba692 | 2604 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 2605 | { |
9966bf68 | 2606 | struct vmcb *nested_vmcb; |
7597f129 | 2607 | struct page *page; |
9966bf68 | 2608 | |
5542675b AG |
2609 | if (nested_svm_check_permissions(svm)) |
2610 | return 1; | |
2611 | ||
7597f129 | 2612 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2613 | if (!nested_vmcb) |
2614 | return 1; | |
2615 | ||
e3e9ed3d JR |
2616 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
2617 | skip_emulated_instruction(&svm->vcpu); | |
2618 | ||
9966bf68 | 2619 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); |
7597f129 | 2620 | nested_svm_unmap(page); |
5542675b AG |
2621 | |
2622 | return 1; | |
2623 | } | |
2624 | ||
851ba692 | 2625 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 2626 | { |
9966bf68 | 2627 | struct vmcb *nested_vmcb; |
7597f129 | 2628 | struct page *page; |
9966bf68 | 2629 | |
5542675b AG |
2630 | if (nested_svm_check_permissions(svm)) |
2631 | return 1; | |
2632 | ||
7597f129 | 2633 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2634 | if (!nested_vmcb) |
2635 | return 1; | |
2636 | ||
e3e9ed3d JR |
2637 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
2638 | skip_emulated_instruction(&svm->vcpu); | |
2639 | ||
9966bf68 | 2640 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); |
7597f129 | 2641 | nested_svm_unmap(page); |
5542675b AG |
2642 | |
2643 | return 1; | |
2644 | } | |
2645 | ||
851ba692 | 2646 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 2647 | { |
3d6368ef AG |
2648 | if (nested_svm_check_permissions(svm)) |
2649 | return 1; | |
2650 | ||
b75f4eb3 RJ |
2651 | /* Save rip after vmrun instruction */ |
2652 | kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3); | |
3d6368ef | 2653 | |
9738b2c9 | 2654 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
2655 | return 1; |
2656 | ||
9738b2c9 | 2657 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
2658 | goto failed; |
2659 | ||
2660 | return 1; | |
2661 | ||
2662 | failed: | |
2663 | ||
2664 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
2665 | svm->vmcb->control.exit_code_hi = 0; | |
2666 | svm->vmcb->control.exit_info_1 = 0; | |
2667 | svm->vmcb->control.exit_info_2 = 0; | |
2668 | ||
2669 | nested_svm_vmexit(svm); | |
3d6368ef AG |
2670 | |
2671 | return 1; | |
2672 | } | |
2673 | ||
851ba692 | 2674 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2675 | { |
2676 | if (nested_svm_check_permissions(svm)) | |
2677 | return 1; | |
2678 | ||
2679 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2680 | skip_emulated_instruction(&svm->vcpu); | |
3842d135 | 2681 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
1371d904 | 2682 | |
2af9194d | 2683 | enable_gif(svm); |
1371d904 AG |
2684 | |
2685 | return 1; | |
2686 | } | |
2687 | ||
851ba692 | 2688 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2689 | { |
2690 | if (nested_svm_check_permissions(svm)) | |
2691 | return 1; | |
2692 | ||
2693 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2694 | skip_emulated_instruction(&svm->vcpu); | |
2695 | ||
2af9194d | 2696 | disable_gif(svm); |
1371d904 AG |
2697 | |
2698 | /* After a CLGI no interrupts should come */ | |
2699 | svm_clear_vintr(svm); | |
2700 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
2701 | ||
decdbf6a JR |
2702 | mark_dirty(svm->vmcb, VMCB_INTR); |
2703 | ||
1371d904 AG |
2704 | return 1; |
2705 | } | |
2706 | ||
851ba692 | 2707 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
2708 | { |
2709 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 2710 | |
ec1ff790 JR |
2711 | trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX], |
2712 | vcpu->arch.regs[VCPU_REGS_RAX]); | |
2713 | ||
ff092385 AG |
2714 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
2715 | kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]); | |
2716 | ||
2717 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2718 | skip_emulated_instruction(&svm->vcpu); | |
2719 | return 1; | |
2720 | } | |
2721 | ||
532a46b9 JR |
2722 | static int skinit_interception(struct vcpu_svm *svm) |
2723 | { | |
2724 | trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]); | |
2725 | ||
2726 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2727 | return 1; | |
2728 | } | |
2729 | ||
81dd35d4 JR |
2730 | static int xsetbv_interception(struct vcpu_svm *svm) |
2731 | { | |
2732 | u64 new_bv = kvm_read_edx_eax(&svm->vcpu); | |
2733 | u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); | |
2734 | ||
2735 | if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) { | |
2736 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2737 | skip_emulated_instruction(&svm->vcpu); | |
2738 | } | |
2739 | ||
2740 | return 1; | |
2741 | } | |
2742 | ||
851ba692 | 2743 | static int invalid_op_interception(struct vcpu_svm *svm) |
6aa8b732 | 2744 | { |
7ee5d940 | 2745 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
2746 | return 1; |
2747 | } | |
2748 | ||
851ba692 | 2749 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 2750 | { |
37817f29 | 2751 | u16 tss_selector; |
64a7ec06 GN |
2752 | int reason; |
2753 | int int_type = svm->vmcb->control.exit_int_info & | |
2754 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 2755 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
2756 | uint32_t type = |
2757 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
2758 | uint32_t idt_v = | |
2759 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
2760 | bool has_error_code = false; |
2761 | u32 error_code = 0; | |
37817f29 IE |
2762 | |
2763 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 2764 | |
37817f29 IE |
2765 | if (svm->vmcb->control.exit_info_2 & |
2766 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
2767 | reason = TASK_SWITCH_IRET; |
2768 | else if (svm->vmcb->control.exit_info_2 & | |
2769 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
2770 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 2771 | else if (idt_v) |
64a7ec06 GN |
2772 | reason = TASK_SWITCH_GATE; |
2773 | else | |
2774 | reason = TASK_SWITCH_CALL; | |
2775 | ||
fe8e7f83 GN |
2776 | if (reason == TASK_SWITCH_GATE) { |
2777 | switch (type) { | |
2778 | case SVM_EXITINTINFO_TYPE_NMI: | |
2779 | svm->vcpu.arch.nmi_injected = false; | |
2780 | break; | |
2781 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
2782 | if (svm->vmcb->control.exit_info_2 & |
2783 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
2784 | has_error_code = true; | |
2785 | error_code = | |
2786 | (u32)svm->vmcb->control.exit_info_2; | |
2787 | } | |
fe8e7f83 GN |
2788 | kvm_clear_exception_queue(&svm->vcpu); |
2789 | break; | |
2790 | case SVM_EXITINTINFO_TYPE_INTR: | |
2791 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2792 | break; | |
2793 | default: | |
2794 | break; | |
2795 | } | |
2796 | } | |
64a7ec06 | 2797 | |
8317c298 GN |
2798 | if (reason != TASK_SWITCH_GATE || |
2799 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
2800 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
2801 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
2802 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 | 2803 | |
7f3d35fd KW |
2804 | if (int_type != SVM_EXITINTINFO_TYPE_SOFT) |
2805 | int_vec = -1; | |
2806 | ||
2807 | if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason, | |
acb54517 GN |
2808 | has_error_code, error_code) == EMULATE_FAIL) { |
2809 | svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
2810 | svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
2811 | svm->vcpu.run->internal.ndata = 0; | |
2812 | return 0; | |
2813 | } | |
2814 | return 1; | |
6aa8b732 AK |
2815 | } |
2816 | ||
851ba692 | 2817 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 2818 | { |
5fdbf976 | 2819 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2820 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 2821 | return 1; |
6aa8b732 AK |
2822 | } |
2823 | ||
851ba692 | 2824 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
2825 | { |
2826 | ++svm->vcpu.stat.nmi_window_exits; | |
8a05a1b8 | 2827 | clr_intercept(svm, INTERCEPT_IRET); |
44c11430 | 2828 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
bd3d1ec3 | 2829 | svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu); |
95ba8273 GN |
2830 | return 1; |
2831 | } | |
2832 | ||
851ba692 | 2833 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 2834 | { |
df4f3108 AP |
2835 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) |
2836 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; | |
2837 | ||
2838 | kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1); | |
2839 | skip_emulated_instruction(&svm->vcpu); | |
2840 | return 1; | |
a7052897 MT |
2841 | } |
2842 | ||
851ba692 | 2843 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 2844 | { |
51d8b661 | 2845 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; |
6aa8b732 AK |
2846 | } |
2847 | ||
332b56e4 AK |
2848 | static int rdpmc_interception(struct vcpu_svm *svm) |
2849 | { | |
2850 | int err; | |
2851 | ||
2852 | if (!static_cpu_has(X86_FEATURE_NRIPS)) | |
2853 | return emulate_on_interception(svm); | |
2854 | ||
2855 | err = kvm_rdpmc(&svm->vcpu); | |
2856 | kvm_complete_insn_gp(&svm->vcpu, err); | |
2857 | ||
2858 | return 1; | |
2859 | } | |
2860 | ||
628afd2a JR |
2861 | bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val) |
2862 | { | |
2863 | unsigned long cr0 = svm->vcpu.arch.cr0; | |
2864 | bool ret = false; | |
2865 | u64 intercept; | |
2866 | ||
2867 | intercept = svm->nested.intercept; | |
2868 | ||
2869 | if (!is_guest_mode(&svm->vcpu) || | |
2870 | (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))) | |
2871 | return false; | |
2872 | ||
2873 | cr0 &= ~SVM_CR0_SELECTIVE_MASK; | |
2874 | val &= ~SVM_CR0_SELECTIVE_MASK; | |
2875 | ||
2876 | if (cr0 ^ val) { | |
2877 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
2878 | ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE); | |
2879 | } | |
2880 | ||
2881 | return ret; | |
2882 | } | |
2883 | ||
7ff76d58 AP |
2884 | #define CR_VALID (1ULL << 63) |
2885 | ||
2886 | static int cr_interception(struct vcpu_svm *svm) | |
2887 | { | |
2888 | int reg, cr; | |
2889 | unsigned long val; | |
2890 | int err; | |
2891 | ||
2892 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
2893 | return emulate_on_interception(svm); | |
2894 | ||
2895 | if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) | |
2896 | return emulate_on_interception(svm); | |
2897 | ||
2898 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
2899 | cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0; | |
2900 | ||
2901 | err = 0; | |
2902 | if (cr >= 16) { /* mov to cr */ | |
2903 | cr -= 16; | |
2904 | val = kvm_register_read(&svm->vcpu, reg); | |
2905 | switch (cr) { | |
2906 | case 0: | |
628afd2a JR |
2907 | if (!check_selective_cr0_intercepted(svm, val)) |
2908 | err = kvm_set_cr0(&svm->vcpu, val); | |
977b2d03 JR |
2909 | else |
2910 | return 1; | |
2911 | ||
7ff76d58 AP |
2912 | break; |
2913 | case 3: | |
2914 | err = kvm_set_cr3(&svm->vcpu, val); | |
2915 | break; | |
2916 | case 4: | |
2917 | err = kvm_set_cr4(&svm->vcpu, val); | |
2918 | break; | |
2919 | case 8: | |
2920 | err = kvm_set_cr8(&svm->vcpu, val); | |
2921 | break; | |
2922 | default: | |
2923 | WARN(1, "unhandled write to CR%d", cr); | |
2924 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2925 | return 1; | |
2926 | } | |
2927 | } else { /* mov from cr */ | |
2928 | switch (cr) { | |
2929 | case 0: | |
2930 | val = kvm_read_cr0(&svm->vcpu); | |
2931 | break; | |
2932 | case 2: | |
2933 | val = svm->vcpu.arch.cr2; | |
2934 | break; | |
2935 | case 3: | |
9f8fe504 | 2936 | val = kvm_read_cr3(&svm->vcpu); |
7ff76d58 AP |
2937 | break; |
2938 | case 4: | |
2939 | val = kvm_read_cr4(&svm->vcpu); | |
2940 | break; | |
2941 | case 8: | |
2942 | val = kvm_get_cr8(&svm->vcpu); | |
2943 | break; | |
2944 | default: | |
2945 | WARN(1, "unhandled read from CR%d", cr); | |
2946 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2947 | return 1; | |
2948 | } | |
2949 | kvm_register_write(&svm->vcpu, reg, val); | |
2950 | } | |
2951 | kvm_complete_insn_gp(&svm->vcpu, err); | |
2952 | ||
2953 | return 1; | |
2954 | } | |
2955 | ||
cae3797a AP |
2956 | static int dr_interception(struct vcpu_svm *svm) |
2957 | { | |
2958 | int reg, dr; | |
2959 | unsigned long val; | |
2960 | int err; | |
2961 | ||
2962 | if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
2963 | return emulate_on_interception(svm); | |
2964 | ||
2965 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
2966 | dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0; | |
2967 | ||
2968 | if (dr >= 16) { /* mov to DRn */ | |
2969 | val = kvm_register_read(&svm->vcpu, reg); | |
2970 | kvm_set_dr(&svm->vcpu, dr - 16, val); | |
2971 | } else { | |
2972 | err = kvm_get_dr(&svm->vcpu, dr, &val); | |
2973 | if (!err) | |
2974 | kvm_register_write(&svm->vcpu, reg, val); | |
2975 | } | |
2976 | ||
2c46d2ae JR |
2977 | skip_emulated_instruction(&svm->vcpu); |
2978 | ||
cae3797a AP |
2979 | return 1; |
2980 | } | |
2981 | ||
851ba692 | 2982 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 2983 | { |
851ba692 | 2984 | struct kvm_run *kvm_run = svm->vcpu.run; |
eea1cff9 | 2985 | int r; |
851ba692 | 2986 | |
0a5fff19 GN |
2987 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
2988 | /* instruction emulation calls kvm_set_cr8() */ | |
7ff76d58 | 2989 | r = cr_interception(svm); |
c516a4c1 | 2990 | if (irqchip_in_kernel(svm->vcpu.kvm)) |
7ff76d58 | 2991 | return r; |
0a5fff19 | 2992 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
7ff76d58 | 2993 | return r; |
1d075434 JR |
2994 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2995 | return 0; | |
2996 | } | |
2997 | ||
886b470c | 2998 | u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
d5c1785d NHE |
2999 | { |
3000 | struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu)); | |
3001 | return vmcb->control.tsc_offset + | |
886b470c | 3002 | svm_scale_tsc(vcpu, host_tsc); |
d5c1785d NHE |
3003 | } |
3004 | ||
6aa8b732 AK |
3005 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
3006 | { | |
a2fa3e9f GH |
3007 | struct vcpu_svm *svm = to_svm(vcpu); |
3008 | ||
6aa8b732 | 3009 | switch (ecx) { |
af24a4e4 | 3010 | case MSR_IA32_TSC: { |
45133eca | 3011 | *data = svm->vmcb->control.tsc_offset + |
fbc0db76 JR |
3012 | svm_scale_tsc(vcpu, native_read_tsc()); |
3013 | ||
6aa8b732 AK |
3014 | break; |
3015 | } | |
8c06585d | 3016 | case MSR_STAR: |
a2fa3e9f | 3017 | *data = svm->vmcb->save.star; |
6aa8b732 | 3018 | break; |
0e859cac | 3019 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3020 | case MSR_LSTAR: |
a2fa3e9f | 3021 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
3022 | break; |
3023 | case MSR_CSTAR: | |
a2fa3e9f | 3024 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
3025 | break; |
3026 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 3027 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
3028 | break; |
3029 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 3030 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
3031 | break; |
3032 | #endif | |
3033 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 3034 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
3035 | break; |
3036 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 3037 | *data = svm->sysenter_eip; |
6aa8b732 AK |
3038 | break; |
3039 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 3040 | *data = svm->sysenter_esp; |
6aa8b732 | 3041 | break; |
e0231715 JR |
3042 | /* |
3043 | * Nobody will change the following 5 values in the VMCB so we can | |
3044 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
3045 | * implemented. | |
3046 | */ | |
a2938c80 JR |
3047 | case MSR_IA32_DEBUGCTLMSR: |
3048 | *data = svm->vmcb->save.dbgctl; | |
3049 | break; | |
3050 | case MSR_IA32_LASTBRANCHFROMIP: | |
3051 | *data = svm->vmcb->save.br_from; | |
3052 | break; | |
3053 | case MSR_IA32_LASTBRANCHTOIP: | |
3054 | *data = svm->vmcb->save.br_to; | |
3055 | break; | |
3056 | case MSR_IA32_LASTINTFROMIP: | |
3057 | *data = svm->vmcb->save.last_excp_from; | |
3058 | break; | |
3059 | case MSR_IA32_LASTINTTOIP: | |
3060 | *data = svm->vmcb->save.last_excp_to; | |
3061 | break; | |
b286d5d8 | 3062 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 3063 | *data = svm->nested.hsave_msr; |
b286d5d8 | 3064 | break; |
eb6f302e | 3065 | case MSR_VM_CR: |
4a810181 | 3066 | *data = svm->nested.vm_cr_msr; |
eb6f302e | 3067 | break; |
c8a73f18 AG |
3068 | case MSR_IA32_UCODE_REV: |
3069 | *data = 0x01000065; | |
3070 | break; | |
6aa8b732 | 3071 | default: |
3bab1f5d | 3072 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
3073 | } |
3074 | return 0; | |
3075 | } | |
3076 | ||
851ba692 | 3077 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3078 | { |
ad312c7c | 3079 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
3080 | u64 data; |
3081 | ||
59200273 AK |
3082 | if (svm_get_msr(&svm->vcpu, ecx, &data)) { |
3083 | trace_kvm_msr_read_ex(ecx); | |
c1a5d4f9 | 3084 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 | 3085 | } else { |
229456fc | 3086 | trace_kvm_msr_read(ecx, data); |
af9ca2d7 | 3087 | |
5fdbf976 | 3088 | svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff; |
ad312c7c | 3089 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
5fdbf976 | 3090 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 3091 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
3092 | } |
3093 | return 1; | |
3094 | } | |
3095 | ||
4a810181 JR |
3096 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
3097 | { | |
3098 | struct vcpu_svm *svm = to_svm(vcpu); | |
3099 | int svm_dis, chg_mask; | |
3100 | ||
3101 | if (data & ~SVM_VM_CR_VALID_MASK) | |
3102 | return 1; | |
3103 | ||
3104 | chg_mask = SVM_VM_CR_VALID_MASK; | |
3105 | ||
3106 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
3107 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
3108 | ||
3109 | svm->nested.vm_cr_msr &= ~chg_mask; | |
3110 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
3111 | ||
3112 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
3113 | ||
3114 | /* check for svm_disable while efer.svme is set */ | |
3115 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
3116 | return 1; | |
3117 | ||
3118 | return 0; | |
3119 | } | |
3120 | ||
8fe8ab46 | 3121 | static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
6aa8b732 | 3122 | { |
a2fa3e9f GH |
3123 | struct vcpu_svm *svm = to_svm(vcpu); |
3124 | ||
8fe8ab46 WA |
3125 | u32 ecx = msr->index; |
3126 | u64 data = msr->data; | |
6aa8b732 | 3127 | switch (ecx) { |
f4e1b3c8 | 3128 | case MSR_IA32_TSC: |
8fe8ab46 | 3129 | kvm_write_tsc(vcpu, msr); |
6aa8b732 | 3130 | break; |
8c06585d | 3131 | case MSR_STAR: |
a2fa3e9f | 3132 | svm->vmcb->save.star = data; |
6aa8b732 | 3133 | break; |
49b14f24 | 3134 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3135 | case MSR_LSTAR: |
a2fa3e9f | 3136 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
3137 | break; |
3138 | case MSR_CSTAR: | |
a2fa3e9f | 3139 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
3140 | break; |
3141 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 3142 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
3143 | break; |
3144 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 3145 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
3146 | break; |
3147 | #endif | |
3148 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 3149 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
3150 | break; |
3151 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 3152 | svm->sysenter_eip = data; |
a2fa3e9f | 3153 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
3154 | break; |
3155 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 3156 | svm->sysenter_esp = data; |
a2fa3e9f | 3157 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 3158 | break; |
a2938c80 | 3159 | case MSR_IA32_DEBUGCTLMSR: |
2a6b20b8 | 3160 | if (!boot_cpu_has(X86_FEATURE_LBRV)) { |
a737f256 CD |
3161 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", |
3162 | __func__, data); | |
24e09cbf JR |
3163 | break; |
3164 | } | |
3165 | if (data & DEBUGCTL_RESERVED_BITS) | |
3166 | return 1; | |
3167 | ||
3168 | svm->vmcb->save.dbgctl = data; | |
b53ba3f9 | 3169 | mark_dirty(svm->vmcb, VMCB_LBR); |
24e09cbf JR |
3170 | if (data & (1ULL<<0)) |
3171 | svm_enable_lbrv(svm); | |
3172 | else | |
3173 | svm_disable_lbrv(svm); | |
a2938c80 | 3174 | break; |
b286d5d8 | 3175 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 3176 | svm->nested.hsave_msr = data; |
62b9abaa | 3177 | break; |
3c5d0a44 | 3178 | case MSR_VM_CR: |
4a810181 | 3179 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 3180 | case MSR_VM_IGNNE: |
a737f256 | 3181 | vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
3c5d0a44 | 3182 | break; |
6aa8b732 | 3183 | default: |
8fe8ab46 | 3184 | return kvm_set_msr_common(vcpu, msr); |
6aa8b732 AK |
3185 | } |
3186 | return 0; | |
3187 | } | |
3188 | ||
851ba692 | 3189 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3190 | { |
8fe8ab46 | 3191 | struct msr_data msr; |
ad312c7c | 3192 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
5fdbf976 | 3193 | u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u) |
ad312c7c | 3194 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
af9ca2d7 | 3195 | |
8fe8ab46 WA |
3196 | msr.data = data; |
3197 | msr.index = ecx; | |
3198 | msr.host_initiated = false; | |
af9ca2d7 | 3199 | |
5fdbf976 | 3200 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
ea306147 | 3201 | if (kvm_set_msr(&svm->vcpu, &msr)) { |
59200273 | 3202 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 3203 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 AK |
3204 | } else { |
3205 | trace_kvm_msr_write(ecx, data); | |
e756fc62 | 3206 | skip_emulated_instruction(&svm->vcpu); |
59200273 | 3207 | } |
6aa8b732 AK |
3208 | return 1; |
3209 | } | |
3210 | ||
851ba692 | 3211 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3212 | { |
e756fc62 | 3213 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 3214 | return wrmsr_interception(svm); |
6aa8b732 | 3215 | else |
851ba692 | 3216 | return rdmsr_interception(svm); |
6aa8b732 AK |
3217 | } |
3218 | ||
851ba692 | 3219 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 3220 | { |
851ba692 AK |
3221 | struct kvm_run *kvm_run = svm->vcpu.run; |
3222 | ||
3842d135 | 3223 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
f0b85051 | 3224 | svm_clear_vintr(svm); |
85f455f7 | 3225 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
decdbf6a | 3226 | mark_dirty(svm->vmcb, VMCB_INTR); |
675acb75 | 3227 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
3228 | /* |
3229 | * If the user space waits to inject interrupts, exit as soon as | |
3230 | * possible | |
3231 | */ | |
8061823a GN |
3232 | if (!irqchip_in_kernel(svm->vcpu.kvm) && |
3233 | kvm_run->request_interrupt_window && | |
3234 | !kvm_cpu_has_interrupt(&svm->vcpu)) { | |
c1150d8c DL |
3235 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
3236 | return 0; | |
3237 | } | |
3238 | ||
3239 | return 1; | |
3240 | } | |
3241 | ||
565d0998 ML |
3242 | static int pause_interception(struct vcpu_svm *svm) |
3243 | { | |
3244 | kvm_vcpu_on_spin(&(svm->vcpu)); | |
3245 | return 1; | |
3246 | } | |
3247 | ||
09941fbb | 3248 | static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = { |
7ff76d58 AP |
3249 | [SVM_EXIT_READ_CR0] = cr_interception, |
3250 | [SVM_EXIT_READ_CR3] = cr_interception, | |
3251 | [SVM_EXIT_READ_CR4] = cr_interception, | |
3252 | [SVM_EXIT_READ_CR8] = cr_interception, | |
d225157b | 3253 | [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, |
628afd2a | 3254 | [SVM_EXIT_WRITE_CR0] = cr_interception, |
7ff76d58 AP |
3255 | [SVM_EXIT_WRITE_CR3] = cr_interception, |
3256 | [SVM_EXIT_WRITE_CR4] = cr_interception, | |
e0231715 | 3257 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
cae3797a AP |
3258 | [SVM_EXIT_READ_DR0] = dr_interception, |
3259 | [SVM_EXIT_READ_DR1] = dr_interception, | |
3260 | [SVM_EXIT_READ_DR2] = dr_interception, | |
3261 | [SVM_EXIT_READ_DR3] = dr_interception, | |
3262 | [SVM_EXIT_READ_DR4] = dr_interception, | |
3263 | [SVM_EXIT_READ_DR5] = dr_interception, | |
3264 | [SVM_EXIT_READ_DR6] = dr_interception, | |
3265 | [SVM_EXIT_READ_DR7] = dr_interception, | |
3266 | [SVM_EXIT_WRITE_DR0] = dr_interception, | |
3267 | [SVM_EXIT_WRITE_DR1] = dr_interception, | |
3268 | [SVM_EXIT_WRITE_DR2] = dr_interception, | |
3269 | [SVM_EXIT_WRITE_DR3] = dr_interception, | |
3270 | [SVM_EXIT_WRITE_DR4] = dr_interception, | |
3271 | [SVM_EXIT_WRITE_DR5] = dr_interception, | |
3272 | [SVM_EXIT_WRITE_DR6] = dr_interception, | |
3273 | [SVM_EXIT_WRITE_DR7] = dr_interception, | |
d0bfb940 JK |
3274 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
3275 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 3276 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 JR |
3277 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
3278 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, | |
3279 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, | |
3280 | [SVM_EXIT_INTR] = intr_interception, | |
c47f098d | 3281 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
3282 | [SVM_EXIT_SMI] = nop_on_interception, |
3283 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 3284 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
332b56e4 | 3285 | [SVM_EXIT_RDPMC] = rdpmc_interception, |
6aa8b732 | 3286 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 3287 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 3288 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 3289 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 3290 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 3291 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 3292 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 3293 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
3294 | [SVM_EXIT_MSR] = msr_interception, |
3295 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 3296 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 3297 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 3298 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
3299 | [SVM_EXIT_VMLOAD] = vmload_interception, |
3300 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
3301 | [SVM_EXIT_STGI] = stgi_interception, |
3302 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 3303 | [SVM_EXIT_SKINIT] = skinit_interception, |
cf5a94d1 | 3304 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
3305 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
3306 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
81dd35d4 | 3307 | [SVM_EXIT_XSETBV] = xsetbv_interception, |
709ddebf | 3308 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
3309 | }; |
3310 | ||
ae8cc059 | 3311 | static void dump_vmcb(struct kvm_vcpu *vcpu) |
3f10c846 JR |
3312 | { |
3313 | struct vcpu_svm *svm = to_svm(vcpu); | |
3314 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3315 | struct vmcb_save_area *save = &svm->vmcb->save; | |
3316 | ||
3317 | pr_err("VMCB Control Area:\n"); | |
ae8cc059 JP |
3318 | pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff); |
3319 | pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16); | |
3320 | pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff); | |
3321 | pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16); | |
3322 | pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions); | |
3323 | pr_err("%-20s%016llx\n", "intercepts:", control->intercept); | |
3324 | pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count); | |
3325 | pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa); | |
3326 | pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa); | |
3327 | pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset); | |
3328 | pr_err("%-20s%d\n", "asid:", control->asid); | |
3329 | pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl); | |
3330 | pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl); | |
3331 | pr_err("%-20s%08x\n", "int_vector:", control->int_vector); | |
3332 | pr_err("%-20s%08x\n", "int_state:", control->int_state); | |
3333 | pr_err("%-20s%08x\n", "exit_code:", control->exit_code); | |
3334 | pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1); | |
3335 | pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2); | |
3336 | pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info); | |
3337 | pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err); | |
3338 | pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl); | |
3339 | pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3); | |
3340 | pr_err("%-20s%08x\n", "event_inj:", control->event_inj); | |
3341 | pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err); | |
3342 | pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl); | |
3343 | pr_err("%-20s%016llx\n", "next_rip:", control->next_rip); | |
3f10c846 | 3344 | pr_err("VMCB State Save Area:\n"); |
ae8cc059 JP |
3345 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", |
3346 | "es:", | |
3347 | save->es.selector, save->es.attrib, | |
3348 | save->es.limit, save->es.base); | |
3349 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3350 | "cs:", | |
3351 | save->cs.selector, save->cs.attrib, | |
3352 | save->cs.limit, save->cs.base); | |
3353 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3354 | "ss:", | |
3355 | save->ss.selector, save->ss.attrib, | |
3356 | save->ss.limit, save->ss.base); | |
3357 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3358 | "ds:", | |
3359 | save->ds.selector, save->ds.attrib, | |
3360 | save->ds.limit, save->ds.base); | |
3361 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3362 | "fs:", | |
3363 | save->fs.selector, save->fs.attrib, | |
3364 | save->fs.limit, save->fs.base); | |
3365 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3366 | "gs:", | |
3367 | save->gs.selector, save->gs.attrib, | |
3368 | save->gs.limit, save->gs.base); | |
3369 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3370 | "gdtr:", | |
3371 | save->gdtr.selector, save->gdtr.attrib, | |
3372 | save->gdtr.limit, save->gdtr.base); | |
3373 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3374 | "ldtr:", | |
3375 | save->ldtr.selector, save->ldtr.attrib, | |
3376 | save->ldtr.limit, save->ldtr.base); | |
3377 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3378 | "idtr:", | |
3379 | save->idtr.selector, save->idtr.attrib, | |
3380 | save->idtr.limit, save->idtr.base); | |
3381 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3382 | "tr:", | |
3383 | save->tr.selector, save->tr.attrib, | |
3384 | save->tr.limit, save->tr.base); | |
3f10c846 JR |
3385 | pr_err("cpl: %d efer: %016llx\n", |
3386 | save->cpl, save->efer); | |
ae8cc059 JP |
3387 | pr_err("%-15s %016llx %-13s %016llx\n", |
3388 | "cr0:", save->cr0, "cr2:", save->cr2); | |
3389 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3390 | "cr3:", save->cr3, "cr4:", save->cr4); | |
3391 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3392 | "dr6:", save->dr6, "dr7:", save->dr7); | |
3393 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3394 | "rip:", save->rip, "rflags:", save->rflags); | |
3395 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3396 | "rsp:", save->rsp, "rax:", save->rax); | |
3397 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3398 | "star:", save->star, "lstar:", save->lstar); | |
3399 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3400 | "cstar:", save->cstar, "sfmask:", save->sfmask); | |
3401 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3402 | "kernel_gs_base:", save->kernel_gs_base, | |
3403 | "sysenter_cs:", save->sysenter_cs); | |
3404 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3405 | "sysenter_esp:", save->sysenter_esp, | |
3406 | "sysenter_eip:", save->sysenter_eip); | |
3407 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3408 | "gpat:", save->g_pat, "dbgctl:", save->dbgctl); | |
3409 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3410 | "br_from:", save->br_from, "br_to:", save->br_to); | |
3411 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3412 | "excp_from:", save->last_excp_from, | |
3413 | "excp_to:", save->last_excp_to); | |
3f10c846 JR |
3414 | } |
3415 | ||
586f9607 AK |
3416 | static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
3417 | { | |
3418 | struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; | |
3419 | ||
3420 | *info1 = control->exit_info_1; | |
3421 | *info2 = control->exit_info_2; | |
3422 | } | |
3423 | ||
851ba692 | 3424 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 3425 | { |
04d2cc77 | 3426 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 3427 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 3428 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 3429 | |
4ee546b4 | 3430 | if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE)) |
2be4fc7a JR |
3431 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
3432 | if (npt_enabled) | |
3433 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 3434 | |
cd3ff653 JR |
3435 | if (unlikely(svm->nested.exit_required)) { |
3436 | nested_svm_vmexit(svm); | |
3437 | svm->nested.exit_required = false; | |
3438 | ||
3439 | return 1; | |
3440 | } | |
3441 | ||
2030753d | 3442 | if (is_guest_mode(vcpu)) { |
410e4d57 JR |
3443 | int vmexit; |
3444 | ||
d8cabddf JR |
3445 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
3446 | svm->vmcb->control.exit_info_1, | |
3447 | svm->vmcb->control.exit_info_2, | |
3448 | svm->vmcb->control.exit_int_info, | |
e097e5ff SH |
3449 | svm->vmcb->control.exit_int_info_err, |
3450 | KVM_ISA_SVM); | |
d8cabddf | 3451 | |
410e4d57 JR |
3452 | vmexit = nested_svm_exit_special(svm); |
3453 | ||
3454 | if (vmexit == NESTED_EXIT_CONTINUE) | |
3455 | vmexit = nested_svm_exit_handled(svm); | |
3456 | ||
3457 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 3458 | return 1; |
cf74a78b AG |
3459 | } |
3460 | ||
a5c3832d JR |
3461 | svm_complete_interrupts(svm); |
3462 | ||
04d2cc77 AK |
3463 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
3464 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
3465 | kvm_run->fail_entry.hardware_entry_failure_reason | |
3466 | = svm->vmcb->control.exit_code; | |
3f10c846 JR |
3467 | pr_err("KVM: FAILED VMRUN WITH VMCB:\n"); |
3468 | dump_vmcb(vcpu); | |
04d2cc77 AK |
3469 | return 0; |
3470 | } | |
3471 | ||
a2fa3e9f | 3472 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 3473 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
55c5e464 JR |
3474 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH && |
3475 | exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI) | |
6614c7d0 | 3476 | printk(KERN_ERR "%s: unexpected exit_int_info 0x%x " |
6aa8b732 | 3477 | "exit_code 0x%x\n", |
b8688d51 | 3478 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
3479 | exit_code); |
3480 | ||
9d8f549d | 3481 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 3482 | || !svm_exit_handlers[exit_code]) { |
e56b9c47 MT |
3483 | WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_code); |
3484 | kvm_queue_exception(vcpu, UD_VECTOR); | |
3485 | return 1; | |
6aa8b732 AK |
3486 | } |
3487 | ||
851ba692 | 3488 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
3489 | } |
3490 | ||
3491 | static void reload_tss(struct kvm_vcpu *vcpu) | |
3492 | { | |
3493 | int cpu = raw_smp_processor_id(); | |
3494 | ||
0fe1e009 TH |
3495 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
3496 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
3497 | load_TR_desc(); |
3498 | } | |
3499 | ||
e756fc62 | 3500 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
3501 | { |
3502 | int cpu = raw_smp_processor_id(); | |
3503 | ||
0fe1e009 | 3504 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 3505 | |
4b656b12 | 3506 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
3507 | if (svm->asid_generation != sd->asid_generation) |
3508 | new_asid(svm, sd); | |
6aa8b732 AK |
3509 | } |
3510 | ||
95ba8273 GN |
3511 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
3512 | { | |
3513 | struct vcpu_svm *svm = to_svm(vcpu); | |
3514 | ||
3515 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
3516 | vcpu->arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3517 | set_intercept(svm, INTERCEPT_IRET); |
95ba8273 GN |
3518 | ++vcpu->stat.nmi_injections; |
3519 | } | |
6aa8b732 | 3520 | |
85f455f7 | 3521 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
3522 | { |
3523 | struct vmcb_control_area *control; | |
3524 | ||
e756fc62 | 3525 | control = &svm->vmcb->control; |
85f455f7 | 3526 | control->int_vector = irq; |
6aa8b732 AK |
3527 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
3528 | control->int_ctl |= V_IRQ_MASK | | |
3529 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
decdbf6a | 3530 | mark_dirty(svm->vmcb, VMCB_INTR); |
6aa8b732 AK |
3531 | } |
3532 | ||
66fd3f7f | 3533 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
3534 | { |
3535 | struct vcpu_svm *svm = to_svm(vcpu); | |
3536 | ||
2af9194d | 3537 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 3538 | |
9fb2d2b4 GN |
3539 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
3540 | ++vcpu->stat.irq_injections; | |
3541 | ||
219b65dc AG |
3542 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
3543 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
3544 | } |
3545 | ||
95ba8273 | 3546 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
3547 | { |
3548 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 3549 | |
2030753d | 3550 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3551 | return; |
3552 | ||
c516a4c1 RK |
3553 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
3554 | ||
95ba8273 | 3555 | if (irr == -1) |
aaacfc9a JR |
3556 | return; |
3557 | ||
95ba8273 | 3558 | if (tpr >= irr) |
4ee546b4 | 3559 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
95ba8273 | 3560 | } |
aaacfc9a | 3561 | |
8d14695f YZ |
3562 | static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) |
3563 | { | |
3564 | return; | |
3565 | } | |
3566 | ||
c7c9c56c YZ |
3567 | static int svm_vm_has_apicv(struct kvm *kvm) |
3568 | { | |
3569 | return 0; | |
3570 | } | |
3571 | ||
3572 | static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) | |
3573 | { | |
3574 | return; | |
3575 | } | |
3576 | ||
3577 | static void svm_hwapic_isr_update(struct kvm *kvm, int isr) | |
3578 | { | |
3579 | return; | |
3580 | } | |
3581 | ||
a20ed54d YZ |
3582 | static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu) |
3583 | { | |
3584 | return; | |
3585 | } | |
3586 | ||
95ba8273 GN |
3587 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
3588 | { | |
3589 | struct vcpu_svm *svm = to_svm(vcpu); | |
3590 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
3591 | int ret; |
3592 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
3593 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3594 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
3595 | ||
3596 | return ret; | |
aaacfc9a JR |
3597 | } |
3598 | ||
3cfc3092 JK |
3599 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
3600 | { | |
3601 | struct vcpu_svm *svm = to_svm(vcpu); | |
3602 | ||
3603 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3604 | } | |
3605 | ||
3606 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
3607 | { | |
3608 | struct vcpu_svm *svm = to_svm(vcpu); | |
3609 | ||
3610 | if (masked) { | |
3611 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3612 | set_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3613 | } else { |
3614 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
8a05a1b8 | 3615 | clr_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3616 | } |
3617 | } | |
3618 | ||
78646121 GN |
3619 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
3620 | { | |
3621 | struct vcpu_svm *svm = to_svm(vcpu); | |
3622 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
3623 | int ret; |
3624 | ||
3625 | if (!gif_set(svm) || | |
3626 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
3627 | return 0; | |
3628 | ||
f6e78475 | 3629 | ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF); |
7fcdb510 | 3630 | |
2030753d | 3631 | if (is_guest_mode(vcpu)) |
7fcdb510 JR |
3632 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); |
3633 | ||
3634 | return ret; | |
78646121 GN |
3635 | } |
3636 | ||
730dca42 | 3637 | static int enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 3638 | { |
219b65dc | 3639 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 3640 | |
e0231715 JR |
3641 | /* |
3642 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
3643 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
3644 | * get that intercept, this function will be called again though and | |
3645 | * we'll get the vintr intercept. | |
3646 | */ | |
8fe54654 | 3647 | if (gif_set(svm) && nested_svm_intr(svm)) { |
219b65dc AG |
3648 | svm_set_vintr(svm); |
3649 | svm_inject_irq(svm, 0x0); | |
3650 | } | |
730dca42 | 3651 | return 0; |
85f455f7 ED |
3652 | } |
3653 | ||
03b28f81 | 3654 | static int enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 3655 | { |
04d2cc77 | 3656 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 3657 | |
44c11430 GN |
3658 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
3659 | == HF_NMI_MASK) | |
03b28f81 | 3660 | return 0; /* IRET will cause a vm exit */ |
44c11430 | 3661 | |
e0231715 JR |
3662 | /* |
3663 | * Something prevents NMI from been injected. Single step over possible | |
3664 | * problem (IRET or exception injection or interrupt shadow) | |
3665 | */ | |
6be7d306 | 3666 | svm->nmi_singlestep = true; |
44c11430 | 3667 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
c8639010 | 3668 | update_db_bp_intercept(vcpu); |
03b28f81 | 3669 | return 0; |
c1150d8c DL |
3670 | } |
3671 | ||
cbc94022 IE |
3672 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
3673 | { | |
3674 | return 0; | |
3675 | } | |
3676 | ||
d9e368d6 AK |
3677 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
3678 | { | |
38e5e92f JR |
3679 | struct vcpu_svm *svm = to_svm(vcpu); |
3680 | ||
3681 | if (static_cpu_has(X86_FEATURE_FLUSHBYASID)) | |
3682 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; | |
3683 | else | |
3684 | svm->asid_generation--; | |
d9e368d6 AK |
3685 | } |
3686 | ||
04d2cc77 AK |
3687 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
3688 | { | |
3689 | } | |
3690 | ||
d7bf8221 JR |
3691 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
3692 | { | |
3693 | struct vcpu_svm *svm = to_svm(vcpu); | |
3694 | ||
2030753d | 3695 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3696 | return; |
3697 | ||
4ee546b4 | 3698 | if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) { |
d7bf8221 | 3699 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; |
615d5193 | 3700 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
3701 | } |
3702 | } | |
3703 | ||
649d6864 JR |
3704 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
3705 | { | |
3706 | struct vcpu_svm *svm = to_svm(vcpu); | |
3707 | u64 cr8; | |
3708 | ||
2030753d | 3709 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3710 | return; |
3711 | ||
649d6864 JR |
3712 | cr8 = kvm_get_cr8(vcpu); |
3713 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
3714 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
3715 | } | |
3716 | ||
9222be18 GN |
3717 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
3718 | { | |
3719 | u8 vector; | |
3720 | int type; | |
3721 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
3722 | unsigned int3_injected = svm->int3_injected; |
3723 | ||
3724 | svm->int3_injected = 0; | |
9222be18 | 3725 | |
bd3d1ec3 AK |
3726 | /* |
3727 | * If we've made progress since setting HF_IRET_MASK, we've | |
3728 | * executed an IRET and can allow NMI injection. | |
3729 | */ | |
3730 | if ((svm->vcpu.arch.hflags & HF_IRET_MASK) | |
3731 | && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) { | |
44c11430 | 3732 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); |
3842d135 AK |
3733 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3734 | } | |
44c11430 | 3735 | |
9222be18 GN |
3736 | svm->vcpu.arch.nmi_injected = false; |
3737 | kvm_clear_exception_queue(&svm->vcpu); | |
3738 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3739 | ||
3740 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
3741 | return; | |
3742 | ||
3842d135 AK |
3743 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3744 | ||
9222be18 GN |
3745 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; |
3746 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
3747 | ||
3748 | switch (type) { | |
3749 | case SVM_EXITINTINFO_TYPE_NMI: | |
3750 | svm->vcpu.arch.nmi_injected = true; | |
3751 | break; | |
3752 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
3753 | /* |
3754 | * In case of software exceptions, do not reinject the vector, | |
3755 | * but re-execute the instruction instead. Rewind RIP first | |
3756 | * if we emulated INT3 before. | |
3757 | */ | |
3758 | if (kvm_exception_is_soft(vector)) { | |
3759 | if (vector == BP_VECTOR && int3_injected && | |
3760 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
3761 | kvm_rip_write(&svm->vcpu, | |
3762 | kvm_rip_read(&svm->vcpu) - | |
3763 | int3_injected); | |
9222be18 | 3764 | break; |
66b7138f | 3765 | } |
9222be18 GN |
3766 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
3767 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 3768 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
3769 | |
3770 | } else | |
ce7ddec4 | 3771 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
3772 | break; |
3773 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 3774 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
3775 | break; |
3776 | default: | |
3777 | break; | |
3778 | } | |
3779 | } | |
3780 | ||
b463a6f7 AK |
3781 | static void svm_cancel_injection(struct kvm_vcpu *vcpu) |
3782 | { | |
3783 | struct vcpu_svm *svm = to_svm(vcpu); | |
3784 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3785 | ||
3786 | control->exit_int_info = control->event_inj; | |
3787 | control->exit_int_info_err = control->event_inj_err; | |
3788 | control->event_inj = 0; | |
3789 | svm_complete_interrupts(svm); | |
3790 | } | |
3791 | ||
851ba692 | 3792 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 3793 | { |
a2fa3e9f | 3794 | struct vcpu_svm *svm = to_svm(vcpu); |
d9e368d6 | 3795 | |
2041a06a JR |
3796 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
3797 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
3798 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
3799 | ||
cd3ff653 JR |
3800 | /* |
3801 | * A vmexit emulation is required before the vcpu can be executed | |
3802 | * again. | |
3803 | */ | |
3804 | if (unlikely(svm->nested.exit_required)) | |
3805 | return; | |
3806 | ||
e756fc62 | 3807 | pre_svm_run(svm); |
6aa8b732 | 3808 | |
649d6864 JR |
3809 | sync_lapic_to_cr8(vcpu); |
3810 | ||
cda0ffdd | 3811 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 3812 | |
04d2cc77 AK |
3813 | clgi(); |
3814 | ||
3815 | local_irq_enable(); | |
36241b8c | 3816 | |
6aa8b732 | 3817 | asm volatile ( |
7454766f AK |
3818 | "push %%" _ASM_BP "; \n\t" |
3819 | "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t" | |
3820 | "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t" | |
3821 | "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t" | |
3822 | "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t" | |
3823 | "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t" | |
3824 | "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 3825 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3826 | "mov %c[r8](%[svm]), %%r8 \n\t" |
3827 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
3828 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
3829 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
3830 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
3831 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
3832 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
3833 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
3834 | #endif |
3835 | ||
6aa8b732 | 3836 | /* Enter guest mode */ |
7454766f AK |
3837 | "push %%" _ASM_AX " \n\t" |
3838 | "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t" | |
4ecac3fd AK |
3839 | __ex(SVM_VMLOAD) "\n\t" |
3840 | __ex(SVM_VMRUN) "\n\t" | |
3841 | __ex(SVM_VMSAVE) "\n\t" | |
7454766f | 3842 | "pop %%" _ASM_AX " \n\t" |
6aa8b732 AK |
3843 | |
3844 | /* Save guest registers, load host registers */ | |
7454766f AK |
3845 | "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t" |
3846 | "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t" | |
3847 | "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t" | |
3848 | "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t" | |
3849 | "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t" | |
3850 | "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 3851 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3852 | "mov %%r8, %c[r8](%[svm]) \n\t" |
3853 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
3854 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
3855 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
3856 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
3857 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
3858 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
3859 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 3860 | #endif |
7454766f | 3861 | "pop %%" _ASM_BP |
6aa8b732 | 3862 | : |
fb3f0f51 | 3863 | : [svm]"a"(svm), |
6aa8b732 | 3864 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
3865 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
3866 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
3867 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
3868 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
3869 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
3870 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 3871 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
3872 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
3873 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
3874 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
3875 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
3876 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
3877 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
3878 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
3879 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 3880 | #endif |
54a08c04 LV |
3881 | : "cc", "memory" |
3882 | #ifdef CONFIG_X86_64 | |
7454766f | 3883 | , "rbx", "rcx", "rdx", "rsi", "rdi" |
54a08c04 | 3884 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
7454766f AK |
3885 | #else |
3886 | , "ebx", "ecx", "edx", "esi", "edi" | |
54a08c04 LV |
3887 | #endif |
3888 | ); | |
6aa8b732 | 3889 | |
82ca2d10 AK |
3890 | #ifdef CONFIG_X86_64 |
3891 | wrmsrl(MSR_GS_BASE, svm->host.gs_base); | |
3892 | #else | |
dacccfdd | 3893 | loadsegment(fs, svm->host.fs); |
831ca609 AK |
3894 | #ifndef CONFIG_X86_32_LAZY_GS |
3895 | loadsegment(gs, svm->host.gs); | |
3896 | #endif | |
9581d442 | 3897 | #endif |
6aa8b732 AK |
3898 | |
3899 | reload_tss(vcpu); | |
3900 | ||
56ba47dd AK |
3901 | local_irq_disable(); |
3902 | ||
13c34e07 AK |
3903 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
3904 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
3905 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
3906 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
3907 | ||
1e2b1dd7 JK |
3908 | trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM); |
3909 | ||
3781c01c JR |
3910 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) |
3911 | kvm_before_handle_nmi(&svm->vcpu); | |
3912 | ||
3913 | stgi(); | |
3914 | ||
3915 | /* Any pending NMI will happen here */ | |
3916 | ||
3917 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) | |
3918 | kvm_after_handle_nmi(&svm->vcpu); | |
3919 | ||
d7bf8221 JR |
3920 | sync_cr8_to_lapic(vcpu); |
3921 | ||
a2fa3e9f | 3922 | svm->next_rip = 0; |
9222be18 | 3923 | |
38e5e92f JR |
3924 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
3925 | ||
631bc487 GN |
3926 | /* if exit due to PF check for async PF */ |
3927 | if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
3928 | svm->apf_reason = kvm_read_and_reset_pf_reason(); | |
3929 | ||
6de4f3ad AK |
3930 | if (npt_enabled) { |
3931 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
3932 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
3933 | } | |
fe5913e4 JR |
3934 | |
3935 | /* | |
3936 | * We need to handle MC intercepts here before the vcpu has a chance to | |
3937 | * change the physical cpu | |
3938 | */ | |
3939 | if (unlikely(svm->vmcb->control.exit_code == | |
3940 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
3941 | svm_handle_mce(svm); | |
8d28fec4 RJ |
3942 | |
3943 | mark_all_clean(svm->vmcb); | |
6aa8b732 AK |
3944 | } |
3945 | ||
6aa8b732 AK |
3946 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3947 | { | |
a2fa3e9f GH |
3948 | struct vcpu_svm *svm = to_svm(vcpu); |
3949 | ||
3950 | svm->vmcb->save.cr3 = root; | |
dcca1a65 | 3951 | mark_dirty(svm->vmcb, VMCB_CR); |
f40f6a45 | 3952 | svm_flush_tlb(vcpu); |
6aa8b732 AK |
3953 | } |
3954 | ||
1c97f0a0 JR |
3955 | static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3956 | { | |
3957 | struct vcpu_svm *svm = to_svm(vcpu); | |
3958 | ||
3959 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 3960 | mark_dirty(svm->vmcb, VMCB_NPT); |
1c97f0a0 JR |
3961 | |
3962 | /* Also sync guest cr3 here in case we live migrate */ | |
9f8fe504 | 3963 | svm->vmcb->save.cr3 = kvm_read_cr3(vcpu); |
dcca1a65 | 3964 | mark_dirty(svm->vmcb, VMCB_CR); |
1c97f0a0 | 3965 | |
f40f6a45 | 3966 | svm_flush_tlb(vcpu); |
1c97f0a0 JR |
3967 | } |
3968 | ||
6aa8b732 AK |
3969 | static int is_disabled(void) |
3970 | { | |
6031a61c JR |
3971 | u64 vm_cr; |
3972 | ||
3973 | rdmsrl(MSR_VM_CR, vm_cr); | |
3974 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
3975 | return 1; | |
3976 | ||
6aa8b732 AK |
3977 | return 0; |
3978 | } | |
3979 | ||
102d8325 IM |
3980 | static void |
3981 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
3982 | { | |
3983 | /* | |
3984 | * Patch in the VMMCALL instruction: | |
3985 | */ | |
3986 | hypercall[0] = 0x0f; | |
3987 | hypercall[1] = 0x01; | |
3988 | hypercall[2] = 0xd9; | |
102d8325 IM |
3989 | } |
3990 | ||
002c7f7c YS |
3991 | static void svm_check_processor_compat(void *rtn) |
3992 | { | |
3993 | *(int *)rtn = 0; | |
3994 | } | |
3995 | ||
774ead3a AK |
3996 | static bool svm_cpu_has_accelerated_tpr(void) |
3997 | { | |
3998 | return false; | |
3999 | } | |
4000 | ||
4b12f0de | 4001 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 SY |
4002 | { |
4003 | return 0; | |
4004 | } | |
4005 | ||
0e851880 SY |
4006 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
4007 | { | |
4008 | } | |
4009 | ||
d4330ef2 JR |
4010 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
4011 | { | |
c2c63a49 | 4012 | switch (func) { |
4c62a2dc JR |
4013 | case 0x80000001: |
4014 | if (nested) | |
4015 | entry->ecx |= (1 << 2); /* Set SVM bit */ | |
4016 | break; | |
c2c63a49 JR |
4017 | case 0x8000000A: |
4018 | entry->eax = 1; /* SVM revision 1 */ | |
4019 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
4020 | ASID emulation to nested SVM */ | |
4021 | entry->ecx = 0; /* Reserved */ | |
7a190667 JR |
4022 | entry->edx = 0; /* Per default do not support any |
4023 | additional features */ | |
4024 | ||
4025 | /* Support next_rip if host supports it */ | |
2a6b20b8 | 4026 | if (boot_cpu_has(X86_FEATURE_NRIPS)) |
7a190667 | 4027 | entry->edx |= SVM_FEATURE_NRIP; |
c2c63a49 | 4028 | |
3d4aeaad JR |
4029 | /* Support NPT for the guest if enabled */ |
4030 | if (npt_enabled) | |
4031 | entry->edx |= SVM_FEATURE_NPT; | |
4032 | ||
c2c63a49 JR |
4033 | break; |
4034 | } | |
d4330ef2 JR |
4035 | } |
4036 | ||
17cc3935 | 4037 | static int svm_get_lpage_level(void) |
344f414f | 4038 | { |
17cc3935 | 4039 | return PT_PDPE_LEVEL; |
344f414f JR |
4040 | } |
4041 | ||
4e47c7a6 SY |
4042 | static bool svm_rdtscp_supported(void) |
4043 | { | |
4044 | return false; | |
4045 | } | |
4046 | ||
ad756a16 MJ |
4047 | static bool svm_invpcid_supported(void) |
4048 | { | |
4049 | return false; | |
4050 | } | |
4051 | ||
f5f48ee1 SY |
4052 | static bool svm_has_wbinvd_exit(void) |
4053 | { | |
4054 | return true; | |
4055 | } | |
4056 | ||
02daab21 AK |
4057 | static void svm_fpu_deactivate(struct kvm_vcpu *vcpu) |
4058 | { | |
4059 | struct vcpu_svm *svm = to_svm(vcpu); | |
4060 | ||
18c918c5 | 4061 | set_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 4062 | update_cr0_intercept(svm); |
02daab21 AK |
4063 | } |
4064 | ||
8061252e | 4065 | #define PRE_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 4066 | .stage = X86_ICPT_PRE_EXCEPT, } |
cfec82cb | 4067 | #define POST_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 4068 | .stage = X86_ICPT_POST_EXCEPT, } |
d7eb8203 | 4069 | #define POST_MEM(exit) { .exit_code = (exit), \ |
40e19b51 | 4070 | .stage = X86_ICPT_POST_MEMACCESS, } |
cfec82cb | 4071 | |
09941fbb | 4072 | static const struct __x86_intercept { |
cfec82cb JR |
4073 | u32 exit_code; |
4074 | enum x86_intercept_stage stage; | |
cfec82cb JR |
4075 | } x86_intercept_map[] = { |
4076 | [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0), | |
4077 | [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4078 | [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4079 | [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4080 | [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0), | |
3b88e41a JR |
4081 | [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0), |
4082 | [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0), | |
dee6bb70 JR |
4083 | [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ), |
4084 | [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ), | |
4085 | [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE), | |
4086 | [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE), | |
4087 | [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ), | |
4088 | [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ), | |
4089 | [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE), | |
4090 | [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE), | |
01de8b09 JR |
4091 | [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN), |
4092 | [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL), | |
4093 | [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD), | |
4094 | [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE), | |
4095 | [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI), | |
4096 | [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI), | |
4097 | [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT), | |
4098 | [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA), | |
d7eb8203 JR |
4099 | [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP), |
4100 | [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR), | |
4101 | [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT), | |
8061252e JR |
4102 | [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG), |
4103 | [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD), | |
4104 | [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD), | |
4105 | [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR), | |
4106 | [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC), | |
4107 | [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR), | |
4108 | [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC), | |
4109 | [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID), | |
4110 | [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM), | |
bf608f88 JR |
4111 | [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE), |
4112 | [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF), | |
4113 | [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF), | |
4114 | [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT), | |
4115 | [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET), | |
4116 | [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP), | |
4117 | [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT), | |
f6511935 JR |
4118 | [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO), |
4119 | [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO), | |
4120 | [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO), | |
4121 | [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO), | |
cfec82cb JR |
4122 | }; |
4123 | ||
8061252e | 4124 | #undef PRE_EX |
cfec82cb | 4125 | #undef POST_EX |
d7eb8203 | 4126 | #undef POST_MEM |
cfec82cb | 4127 | |
8a76d7f2 JR |
4128 | static int svm_check_intercept(struct kvm_vcpu *vcpu, |
4129 | struct x86_instruction_info *info, | |
4130 | enum x86_intercept_stage stage) | |
4131 | { | |
cfec82cb JR |
4132 | struct vcpu_svm *svm = to_svm(vcpu); |
4133 | int vmexit, ret = X86EMUL_CONTINUE; | |
4134 | struct __x86_intercept icpt_info; | |
4135 | struct vmcb *vmcb = svm->vmcb; | |
4136 | ||
4137 | if (info->intercept >= ARRAY_SIZE(x86_intercept_map)) | |
4138 | goto out; | |
4139 | ||
4140 | icpt_info = x86_intercept_map[info->intercept]; | |
4141 | ||
40e19b51 | 4142 | if (stage != icpt_info.stage) |
cfec82cb JR |
4143 | goto out; |
4144 | ||
4145 | switch (icpt_info.exit_code) { | |
4146 | case SVM_EXIT_READ_CR0: | |
4147 | if (info->intercept == x86_intercept_cr_read) | |
4148 | icpt_info.exit_code += info->modrm_reg; | |
4149 | break; | |
4150 | case SVM_EXIT_WRITE_CR0: { | |
4151 | unsigned long cr0, val; | |
4152 | u64 intercept; | |
4153 | ||
4154 | if (info->intercept == x86_intercept_cr_write) | |
4155 | icpt_info.exit_code += info->modrm_reg; | |
4156 | ||
4157 | if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0) | |
4158 | break; | |
4159 | ||
4160 | intercept = svm->nested.intercept; | |
4161 | ||
4162 | if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))) | |
4163 | break; | |
4164 | ||
4165 | cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK; | |
4166 | val = info->src_val & ~SVM_CR0_SELECTIVE_MASK; | |
4167 | ||
4168 | if (info->intercept == x86_intercept_lmsw) { | |
4169 | cr0 &= 0xfUL; | |
4170 | val &= 0xfUL; | |
4171 | /* lmsw can't clear PE - catch this here */ | |
4172 | if (cr0 & X86_CR0_PE) | |
4173 | val |= X86_CR0_PE; | |
4174 | } | |
4175 | ||
4176 | if (cr0 ^ val) | |
4177 | icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
4178 | ||
4179 | break; | |
4180 | } | |
3b88e41a JR |
4181 | case SVM_EXIT_READ_DR0: |
4182 | case SVM_EXIT_WRITE_DR0: | |
4183 | icpt_info.exit_code += info->modrm_reg; | |
4184 | break; | |
8061252e JR |
4185 | case SVM_EXIT_MSR: |
4186 | if (info->intercept == x86_intercept_wrmsr) | |
4187 | vmcb->control.exit_info_1 = 1; | |
4188 | else | |
4189 | vmcb->control.exit_info_1 = 0; | |
4190 | break; | |
bf608f88 JR |
4191 | case SVM_EXIT_PAUSE: |
4192 | /* | |
4193 | * We get this for NOP only, but pause | |
4194 | * is rep not, check this here | |
4195 | */ | |
4196 | if (info->rep_prefix != REPE_PREFIX) | |
4197 | goto out; | |
f6511935 JR |
4198 | case SVM_EXIT_IOIO: { |
4199 | u64 exit_info; | |
4200 | u32 bytes; | |
4201 | ||
4202 | exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16; | |
4203 | ||
4204 | if (info->intercept == x86_intercept_in || | |
4205 | info->intercept == x86_intercept_ins) { | |
4206 | exit_info |= SVM_IOIO_TYPE_MASK; | |
4207 | bytes = info->src_bytes; | |
4208 | } else { | |
4209 | bytes = info->dst_bytes; | |
4210 | } | |
4211 | ||
4212 | if (info->intercept == x86_intercept_outs || | |
4213 | info->intercept == x86_intercept_ins) | |
4214 | exit_info |= SVM_IOIO_STR_MASK; | |
4215 | ||
4216 | if (info->rep_prefix) | |
4217 | exit_info |= SVM_IOIO_REP_MASK; | |
4218 | ||
4219 | bytes = min(bytes, 4u); | |
4220 | ||
4221 | exit_info |= bytes << SVM_IOIO_SIZE_SHIFT; | |
4222 | ||
4223 | exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1); | |
4224 | ||
4225 | vmcb->control.exit_info_1 = exit_info; | |
4226 | vmcb->control.exit_info_2 = info->next_rip; | |
4227 | ||
4228 | break; | |
4229 | } | |
cfec82cb JR |
4230 | default: |
4231 | break; | |
4232 | } | |
4233 | ||
ea0d66be BD |
4234 | /* TODO: Advertise NRIPS to guest hypervisor unconditionally */ |
4235 | if (static_cpu_has(X86_FEATURE_NRIPS)) | |
4236 | vmcb->control.next_rip = info->next_rip; | |
cfec82cb JR |
4237 | vmcb->control.exit_code = icpt_info.exit_code; |
4238 | vmexit = nested_svm_exit_handled(svm); | |
4239 | ||
4240 | ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED | |
4241 | : X86EMUL_CONTINUE; | |
4242 | ||
4243 | out: | |
4244 | return ret; | |
8a76d7f2 JR |
4245 | } |
4246 | ||
a547c6db YZ |
4247 | static void svm_handle_external_intr(struct kvm_vcpu *vcpu) |
4248 | { | |
4249 | local_irq_enable(); | |
4250 | } | |
4251 | ||
cbdd1bea | 4252 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
4253 | .cpu_has_kvm_support = has_svm, |
4254 | .disabled_by_bios = is_disabled, | |
4255 | .hardware_setup = svm_hardware_setup, | |
4256 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 4257 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
4258 | .hardware_enable = svm_hardware_enable, |
4259 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 4260 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
4261 | |
4262 | .vcpu_create = svm_create_vcpu, | |
4263 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 4264 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 4265 | |
04d2cc77 | 4266 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
4267 | .vcpu_load = svm_vcpu_load, |
4268 | .vcpu_put = svm_vcpu_put, | |
4269 | ||
c8639010 | 4270 | .update_db_bp_intercept = update_db_bp_intercept, |
6aa8b732 AK |
4271 | .get_msr = svm_get_msr, |
4272 | .set_msr = svm_set_msr, | |
4273 | .get_segment_base = svm_get_segment_base, | |
4274 | .get_segment = svm_get_segment, | |
4275 | .set_segment = svm_set_segment, | |
2e4d2653 | 4276 | .get_cpl = svm_get_cpl, |
1747fb71 | 4277 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 4278 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
aff48baa | 4279 | .decache_cr3 = svm_decache_cr3, |
25c4c276 | 4280 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 4281 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
4282 | .set_cr3 = svm_set_cr3, |
4283 | .set_cr4 = svm_set_cr4, | |
4284 | .set_efer = svm_set_efer, | |
4285 | .get_idt = svm_get_idt, | |
4286 | .set_idt = svm_set_idt, | |
4287 | .get_gdt = svm_get_gdt, | |
4288 | .set_gdt = svm_set_gdt, | |
020df079 | 4289 | .set_dr7 = svm_set_dr7, |
6de4f3ad | 4290 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
4291 | .get_rflags = svm_get_rflags, |
4292 | .set_rflags = svm_set_rflags, | |
6b52d186 | 4293 | .fpu_activate = svm_fpu_activate, |
02daab21 | 4294 | .fpu_deactivate = svm_fpu_deactivate, |
6aa8b732 | 4295 | |
6aa8b732 | 4296 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 4297 | |
6aa8b732 | 4298 | .run = svm_vcpu_run, |
04d2cc77 | 4299 | .handle_exit = handle_exit, |
6aa8b732 | 4300 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
4301 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
4302 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 4303 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 4304 | .set_irq = svm_set_irq, |
95ba8273 | 4305 | .set_nmi = svm_inject_nmi, |
298101da | 4306 | .queue_exception = svm_queue_exception, |
b463a6f7 | 4307 | .cancel_injection = svm_cancel_injection, |
78646121 | 4308 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 4309 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
4310 | .get_nmi_mask = svm_get_nmi_mask, |
4311 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
4312 | .enable_nmi_window = enable_nmi_window, |
4313 | .enable_irq_window = enable_irq_window, | |
4314 | .update_cr8_intercept = update_cr8_intercept, | |
8d14695f | 4315 | .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode, |
c7c9c56c YZ |
4316 | .vm_has_apicv = svm_vm_has_apicv, |
4317 | .load_eoi_exitmap = svm_load_eoi_exitmap, | |
4318 | .hwapic_isr_update = svm_hwapic_isr_update, | |
a20ed54d | 4319 | .sync_pir_to_irr = svm_sync_pir_to_irr, |
cbc94022 IE |
4320 | |
4321 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 4322 | .get_tdp_level = get_npt_level, |
4b12f0de | 4323 | .get_mt_mask = svm_get_mt_mask, |
229456fc | 4324 | |
586f9607 | 4325 | .get_exit_info = svm_get_exit_info, |
586f9607 | 4326 | |
17cc3935 | 4327 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
4328 | |
4329 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
4330 | |
4331 | .rdtscp_supported = svm_rdtscp_supported, | |
ad756a16 | 4332 | .invpcid_supported = svm_invpcid_supported, |
d4330ef2 JR |
4333 | |
4334 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
4335 | |
4336 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
99e3e30a | 4337 | |
4051b188 | 4338 | .set_tsc_khz = svm_set_tsc_khz, |
ba904635 | 4339 | .read_tsc_offset = svm_read_tsc_offset, |
99e3e30a | 4340 | .write_tsc_offset = svm_write_tsc_offset, |
e48672fa | 4341 | .adjust_tsc_offset = svm_adjust_tsc_offset, |
857e4099 | 4342 | .compute_tsc_offset = svm_compute_tsc_offset, |
d5c1785d | 4343 | .read_l1_tsc = svm_read_l1_tsc, |
1c97f0a0 JR |
4344 | |
4345 | .set_tdp_cr3 = set_tdp_cr3, | |
8a76d7f2 JR |
4346 | |
4347 | .check_intercept = svm_check_intercept, | |
a547c6db | 4348 | .handle_external_intr = svm_handle_external_intr, |
6aa8b732 AK |
4349 | }; |
4350 | ||
4351 | static int __init svm_init(void) | |
4352 | { | |
cb498ea2 | 4353 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 4354 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
4355 | } |
4356 | ||
4357 | static void __exit svm_exit(void) | |
4358 | { | |
cb498ea2 | 4359 | kvm_exit(); |
6aa8b732 AK |
4360 | } |
4361 | ||
4362 | module_init(svm_init) | |
4363 | module_exit(svm_exit) |