projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: VMX: Clean up DR6 emulation
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
6aa8b732 29
e495606d 30#include <asm/desc.h>
6aa8b732 31
63d1142f 32#include <asm/virtext.h>
229456fc 33#include "trace.h"
63d1142f 34
4ecac3fd
AK		 35#define __ex(x) __kvm_handle_fault_on_reboot(x)
36
6aa8b732
AK		 37MODULE_AUTHOR("Qumranet");
38MODULE_LICENSE("GPL");
39
40#define IOPM_ALLOC_ORDER 2
41#define MSRPM_ALLOC_ORDER 1
42
6aa8b732
AK		 43#define SEG_TYPE_LDT 2
44#define SEG_TYPE_BUSY_TSS16 3
45
80b7706e
JR		 46#define SVM_FEATURE_NPT (1 << 0)
47#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 48#define SVM_FEATURE_SVML (1 << 2)
565d0998 49#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 50
410e4d57
JR		 51#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
52#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
53#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
54
24e09cbf
JR		 55#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
56
6c8166a7
AK		 57static const u32 host_save_user_msrs[] = {
58#ifdef CONFIG_X86_64
59 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
60 MSR_FS_BASE,
61#endif
62 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
63};
64
65#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
66
67struct kvm_vcpu;
68
e6aa9abd
JR		 69struct nested_state {
70 struct vmcb *hsave;
71 u64 hsave_msr;
72 u64 vmcb;
73
74 /* These are the merged vectors */
75 u32 *msrpm;
76
77 /* gpa pointers to the real vectors */
78 u64 vmcb_msrpm;
aad42c64 79
cd3ff653
JR		 80 /* A VMEXIT is required but not yet emulated */
81 bool exit_required;
82
aad42c64
JR		 83 /* cache for intercepts of the guest */
84 u16 intercept_cr_read;
85 u16 intercept_cr_write;
86 u16 intercept_dr_read;
87 u16 intercept_dr_write;
88 u32 intercept_exceptions;
89 u64 intercept;
90
e6aa9abd
JR		 91};
92
6c8166a7
AK		 93struct vcpu_svm {
94 struct kvm_vcpu vcpu;
95 struct vmcb *vmcb;
96 unsigned long vmcb_pa;
97 struct svm_cpu_data *svm_data;
98 uint64_t asid_generation;
99 uint64_t sysenter_esp;
100 uint64_t sysenter_eip;
101
102 u64 next_rip;
103
104 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
105 u64 host_gs_base;
6c8166a7
AK		 106
107 u32 *msrpm;
6c8166a7 108
e6aa9abd 109 struct nested_state nested;
6be7d306
JK		 110
111 bool nmi_singlestep;
6c8166a7
AK		 112};
113
709ddebf
JR		 114/* enable NPT for AMD64 and X86 with PAE */
115#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
116static bool npt_enabled = true;
117#else
e3da3acd 118static bool npt_enabled = false;
709ddebf 119#endif
6c7dac72
JR		 120static int npt = 1;
121
122module_param(npt, int, S_IRUGO);
e3da3acd 123
4b6e4dca 124static int nested = 1;
236de055
AG		 125module_param(nested, int, S_IRUGO);
126
44874f84 127static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 128static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 129
410e4d57 130static int nested_svm_exit_handled(struct vcpu_svm *svm);
cf74a78b 131static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 132static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
133 bool has_error_code, u32 error_code);
134
a2fa3e9f
GH		 135static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
136{
fb3f0f51 137 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 138}
139
3d6368ef
AG		 140static inline bool is_nested(struct vcpu_svm *svm)
141{
e6aa9abd 142 return svm->nested.vmcb;
3d6368ef
AG		 143}
144
2af9194d
JR		 145static inline void enable_gif(struct vcpu_svm *svm)
146{
147 svm->vcpu.arch.hflags |= HF_GIF_MASK;
148}
149
150static inline void disable_gif(struct vcpu_svm *svm)
151{
152 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
153}
154
155static inline bool gif_set(struct vcpu_svm *svm)
156{
157 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
158}
159
4866d5e3 160static unsigned long iopm_base;
6aa8b732
AK		 161
162struct kvm_ldttss_desc {
163 u16 limit0;
164 u16 base0;
165 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
166 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
167 u32 base3;
168 u32 zero1;
169} __attribute__((packed));
170
171struct svm_cpu_data {
172 int cpu;
173
5008fdf5
AK		 174 u64 asid_generation;
175 u32 max_asid;
176 u32 next_asid;
6aa8b732
AK		 177 struct kvm_ldttss_desc *tss_desc;
178
179 struct page *save_area;
180};
181
182static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 183static uint32_t svm_features;
6aa8b732
AK		 184
185struct svm_init_data {
186 int cpu;
187 int r;
188};
189
190static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
191
9d8f549d 192#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 193#define MSRS_RANGE_SIZE 2048
194#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
195
196#define MAX_INST_SIZE 15
197
80b7706e
JR		 198static inline u32 svm_has(u32 feat)
199{
200 return svm_features & feat;
201}
202
6aa8b732
AK		 203static inline void clgi(void)
204{
4ecac3fd 205 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 206}
207
208static inline void stgi(void)
209{
4ecac3fd 210 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 211}
212
213static inline void invlpga(unsigned long addr, u32 asid)
214{
4ecac3fd 215 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 216}
217
6aa8b732
AK		 218static inline void force_new_asid(struct kvm_vcpu *vcpu)
219{
a2fa3e9f 220 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 221}
222
223static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
224{
225 force_new_asid(vcpu);
226}
227
228static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
229{
709ddebf 230 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 231 efer &= ~EFER_LME;
6aa8b732 232
9962d032 233 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
ad312c7c 234 vcpu->arch.shadow_efer = efer;
6aa8b732
AK		 235}
236
298101da
AK		 237static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
238 bool has_error_code, u32 error_code)
239{
240 struct vcpu_svm *svm = to_svm(vcpu);
241
cf74a78b
AG		 242 /* If we are within a nested VM we'd better #VMEXIT and let the
243 guest handle the exception */
244 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
245 return;
246
298101da
AK		 247 svm->vmcb->control.event_inj = nr
248 | SVM_EVTINJ_VALID
249 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
250 | SVM_EVTINJ_TYPE_EXEPT;
251 svm->vmcb->control.event_inj_err = error_code;
252}
253
6aa8b732
AK		 254static int is_external_interrupt(u32 info)
255{
256 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
257 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
258}
259
2809f5d2
GC		 260static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
261{
262 struct vcpu_svm *svm = to_svm(vcpu);
263 u32 ret = 0;
264
265 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
266 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
267 return ret & mask;
268}
269
270static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
271{
272 struct vcpu_svm *svm = to_svm(vcpu);
273
274 if (mask == 0)
275 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
276 else
277 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
278
279}
280
6aa8b732
AK		 281static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
282{
a2fa3e9f
GH		 283 struct vcpu_svm *svm = to_svm(vcpu);
284
285 if (!svm->next_rip) {
851ba692 286 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 287 EMULATE_DONE)
288 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 289 return;
290 }
5fdbf976
MT		 291 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
292 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
293 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 294
5fdbf976 295 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 296 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 297}
298
299static int has_svm(void)
300{
63d1142f 301 const char *msg;
6aa8b732 302
63d1142f 303 if (!cpu_has_svm(&msg)) {
ff81ff10 304 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 305 return 0;
306 }
307
6aa8b732
AK		 308 return 1;
309}
310
311static void svm_hardware_disable(void *garbage)
312{
2c8dceeb 313 cpu_svm_disable();
6aa8b732
AK		 314}
315
10474ae8 316static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 317{
318
0fe1e009 319 struct svm_cpu_data *sd;
6aa8b732 320 uint64_t efer;
b792c344 321 struct descriptor_table gdt_descr;
6aa8b732
AK		 322 struct desc_struct *gdt;
323 int me = raw_smp_processor_id();
324
10474ae8
AG		 325 rdmsrl(MSR_EFER, efer);
326 if (efer & EFER_SVME)
327 return -EBUSY;
328
6aa8b732 329 if (!has_svm()) {
e6732a5a
ZA		 330 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
331 me);
10474ae8 332 return -EINVAL;
6aa8b732 333 }
0fe1e009 334 sd = per_cpu(svm_data, me);
6aa8b732 335
0fe1e009 336 if (!sd) {
e6732a5a 337 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 338 me);
10474ae8 339 return -EINVAL;
6aa8b732
AK		 340 }
341
0fe1e009
TH		 342 sd->asid_generation = 1;
343 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
344 sd->next_asid = sd->max_asid + 1;
6aa8b732 345
b792c344
AM		 346 kvm_get_gdt(&gdt_descr);
347 gdt = (struct desc_struct *)gdt_descr.base;
0fe1e009 348 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 349
9962d032 350 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 351
d0316554 352 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8
AG		 353
354 return 0;
6aa8b732
AK		 355}
356
0da1db75
JR		 357static void svm_cpu_uninit(int cpu)
358{
0fe1e009 359 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 360
0fe1e009 361 if (!sd)
0da1db75
JR		 362 return;
363
364 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 365 __free_page(sd->save_area);
366 kfree(sd);
0da1db75
JR		 367}
368
6aa8b732
AK		 369static int svm_cpu_init(int cpu)
370{
0fe1e009 371 struct svm_cpu_data *sd;
6aa8b732
AK		 372 int r;
373
0fe1e009
TH		 374 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
375 if (!sd)
6aa8b732 376 return -ENOMEM;
0fe1e009
TH		 377 sd->cpu = cpu;
378 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 379 r = -ENOMEM;
0fe1e009 380 if (!sd->save_area)
6aa8b732
AK		 381 goto err_1;
382
0fe1e009 383 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 384
385 return 0;
386
387err_1:
0fe1e009 388 kfree(sd);
6aa8b732
AK		 389 return r;
390
391}
392
bfc733a7
RR		 393static void set_msr_interception(u32 *msrpm, unsigned msr,
394 int read, int write)
6aa8b732
AK		 395{
396 int i;
397
398 for (i = 0; i < NUM_MSR_MAPS; i++) {
399 if (msr >= msrpm_ranges[i] &&
400 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
401 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
402 msrpm_ranges[i]) * 2;
403
404 u32 *base = msrpm + (msr_offset / 32);
405 u32 msr_shift = msr_offset % 32;
406 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
407 *base = (*base & ~(0x3 << msr_shift)) |
408 (mask << msr_shift);
bfc733a7 409 return;
6aa8b732
AK		 410 }
411 }
bfc733a7 412 BUG();
6aa8b732
AK		 413}
414
f65c229c
JR		 415static void svm_vcpu_init_msrpm(u32 *msrpm)
416{
417 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
418
419#ifdef CONFIG_X86_64
420 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
421 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
422 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
423 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
424 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
425 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
426#endif
427 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
428 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
f65c229c
JR		 429}
430
24e09cbf
JR		 431static void svm_enable_lbrv(struct vcpu_svm *svm)
432{
433 u32 *msrpm = svm->msrpm;
434
435 svm->vmcb->control.lbr_ctl = 1;
436 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
437 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
438 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
439 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
440}
441
442static void svm_disable_lbrv(struct vcpu_svm *svm)
443{
444 u32 *msrpm = svm->msrpm;
445
446 svm->vmcb->control.lbr_ctl = 0;
447 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
448 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
449 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
450 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
451}
452
6aa8b732
AK		 453static __init int svm_hardware_setup(void)
454{
455 int cpu;
456 struct page *iopm_pages;
f65c229c 457 void *iopm_va;
6aa8b732
AK		 458 int r;
459
6aa8b732
AK		 460 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
461
462 if (!iopm_pages)
463 return -ENOMEM;
c8681339
AL		 464
465 iopm_va = page_address(iopm_pages);
466 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 467 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
468
50a37eb4
JR		 469 if (boot_cpu_has(X86_FEATURE_NX))
470 kvm_enable_efer_bits(EFER_NX);
471
1b2fd70c
AG		 472 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
473 kvm_enable_efer_bits(EFER_FFXSR);
474
236de055
AG		 475 if (nested) {
476 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
477 kvm_enable_efer_bits(EFER_SVME);
478 }
479
3230bb47 480 for_each_possible_cpu(cpu) {
6aa8b732
AK		 481 r = svm_cpu_init(cpu);
482 if (r)
f65c229c 483 goto err;
6aa8b732 484 }
33bd6a0b
JR		 485
486 svm_features = cpuid_edx(SVM_CPUID_FUNC);
487
e3da3acd
JR		 488 if (!svm_has(SVM_FEATURE_NPT))
489 npt_enabled = false;
490
6c7dac72
JR		 491 if (npt_enabled && !npt) {
492 printk(KERN_INFO "kvm: Nested Paging disabled\n");
493 npt_enabled = false;
494 }
495
18552672 496 if (npt_enabled) {
e3da3acd 497 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 498 kvm_enable_tdp();
5f4cb662
JR		 499 } else
500 kvm_disable_tdp();
e3da3acd 501
6aa8b732
AK		 502 return 0;
503
f65c229c 504err:
6aa8b732
AK		 505 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
506 iopm_base = 0;
507 return r;
508}
509
510static __exit void svm_hardware_unsetup(void)
511{
0da1db75
JR		 512 int cpu;
513
3230bb47 514 for_each_possible_cpu(cpu)
0da1db75
JR		 515 svm_cpu_uninit(cpu);
516
6aa8b732 517 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 518 iopm_base = 0;
6aa8b732
AK		 519}
520
521static void init_seg(struct vmcb_seg *seg)
522{
523 seg->selector = 0;
524 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
525 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
526 seg->limit = 0xffff;
527 seg->base = 0;
528}
529
530static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
531{
532 seg->selector = 0;
533 seg->attrib = SVM_SELECTOR_P_MASK | type;
534 seg->limit = 0xffff;
535 seg->base = 0;
536}
537
e6101a96 538static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 539{
e6101a96
JR		 540 struct vmcb_control_area *control = &svm->vmcb->control;
541 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 542
bff78274
AK		 543 svm->vcpu.fpu_active = 1;
544
6aa8b732
AK		 545 control->intercept_cr_read = INTERCEPT_CR0_MASK |
546 INTERCEPT_CR3_MASK |
649d6864 547 INTERCEPT_CR4_MASK;
6aa8b732
AK		 548
549 control->intercept_cr_write = INTERCEPT_CR0_MASK |
550 INTERCEPT_CR3_MASK |
80a8119c
AK		 551 INTERCEPT_CR4_MASK |
552 INTERCEPT_CR8_MASK;
6aa8b732
AK		 553
554 control->intercept_dr_read = INTERCEPT_DR0_MASK |
555 INTERCEPT_DR1_MASK |
556 INTERCEPT_DR2_MASK |
557 INTERCEPT_DR3_MASK;
558
559 control->intercept_dr_write = INTERCEPT_DR0_MASK |
560 INTERCEPT_DR1_MASK |
561 INTERCEPT_DR2_MASK |
562 INTERCEPT_DR3_MASK |
563 INTERCEPT_DR5_MASK |
564 INTERCEPT_DR7_MASK;
565
7aa81cc0 566 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 567 (1 << UD_VECTOR) |
568 (1 << MC_VECTOR);
6aa8b732
AK		 569
570
571 control->intercept = (1ULL << INTERCEPT_INTR) |
572 (1ULL << INTERCEPT_NMI) |
0152527b 573 (1ULL << INTERCEPT_SMI) |
d225157b 574 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 575 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 576 (1ULL << INTERCEPT_INVD) |
6aa8b732 577 (1ULL << INTERCEPT_HLT) |
a7052897 578 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 579 (1ULL << INTERCEPT_INVLPGA) |
580 (1ULL << INTERCEPT_IOIO_PROT) |
581 (1ULL << INTERCEPT_MSR_PROT) |
582 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 583 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 584 (1ULL << INTERCEPT_VMRUN) |
585 (1ULL << INTERCEPT_VMMCALL) |
586 (1ULL << INTERCEPT_VMLOAD) |
587 (1ULL << INTERCEPT_VMSAVE) |
588 (1ULL << INTERCEPT_STGI) |
589 (1ULL << INTERCEPT_CLGI) |
916ce236 590 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 591 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 592 (1ULL << INTERCEPT_MONITOR) |
593 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 594
595 control->iopm_base_pa = iopm_base;
f65c229c 596 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 597 control->tsc_offset = 0;
6aa8b732
AK		 598 control->int_ctl = V_INTR_MASKING_MASK;
599
600 init_seg(&save->es);
601 init_seg(&save->ss);
602 init_seg(&save->ds);
603 init_seg(&save->fs);
604 init_seg(&save->gs);
605
606 save->cs.selector = 0xf000;
607 /* Executable/Readable Code Segment */
608 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
609 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
610 save->cs.limit = 0xffff;
d92899a0
AK		 611 /*
612 * cs.base should really be 0xffff0000, but vmx can't handle that, so
613 * be consistent with it.
614 *
615 * Replace when we have real mode working for vmx.
616 */
617 save->cs.base = 0xf0000;
6aa8b732
AK		 618
619 save->gdtr.limit = 0xffff;
620 save->idtr.limit = 0xffff;
621
622 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
623 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
624
9962d032 625 save->efer = EFER_SVME;
d77c26fc 626 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 627 save->dr7 = 0x400;
628 save->rflags = 2;
629 save->rip = 0x0000fff0;
5fdbf976 630 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 631
18fa000a
EH		 632 /* This is the guest-visible cr0 value.
633 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 634 */
18fa000a
EH		 635 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
636 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
637
66aee91a 638 save->cr4 = X86_CR4_PAE;
6aa8b732 639 /* rdx = ?? */
709ddebf
JR		 640
641 if (npt_enabled) {
642 /* Setup VMCB for Nested Paging */
643 control->nested_ctl = 1;
a7052897
MT		 644 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
645 (1ULL << INTERCEPT_INVLPG));
709ddebf 646 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 647 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
648 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 649 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 650 save->cr3 = 0;
651 save->cr4 = 0;
652 }
a79d2f18 653 force_new_asid(&svm->vcpu);
1371d904 654
e6aa9abd 655 svm->nested.vmcb = 0;
2af9194d
JR		 656 svm->vcpu.arch.hflags = 0;
657
565d0998
ML		 658 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
659 control->pause_filter_count = 3000;
660 control->intercept |= (1ULL << INTERCEPT_PAUSE);
661 }
662
2af9194d 663 enable_gif(svm);
6aa8b732
AK		 664}
665
e00c8cf2 666static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 667{
668 struct vcpu_svm *svm = to_svm(vcpu);
669
e6101a96 670 init_vmcb(svm);
70433389 671
c5af89b6 672 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 673 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 674 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
675 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 676 }
5fdbf976
MT		 677 vcpu->arch.regs_avail = ~0;
678 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 679
680 return 0;
04d2cc77
AK		 681}
682
fb3f0f51 683static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 684{
a2fa3e9f 685 struct vcpu_svm *svm;
6aa8b732 686 struct page *page;
f65c229c 687 struct page *msrpm_pages;
b286d5d8 688 struct page *hsave_page;
3d6368ef 689 struct page *nested_msrpm_pages;
fb3f0f51 690 int err;
6aa8b732 691
c16f862d 692 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 693 if (!svm) {
694 err = -ENOMEM;
695 goto out;
696 }
697
698 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
699 if (err)
700 goto free_svm;
701
6aa8b732 702 page = alloc_page(GFP_KERNEL);
fb3f0f51
RR		 703 if (!page) {
704 err = -ENOMEM;
705 goto uninit;
706 }
6aa8b732 707
f65c229c
JR		 708 err = -ENOMEM;
709 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
710 if (!msrpm_pages)
711 goto uninit;
3d6368ef
AG		 712
713 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
714 if (!nested_msrpm_pages)
715 goto uninit;
716
f65c229c
JR		 717 svm->msrpm = page_address(msrpm_pages);
718 svm_vcpu_init_msrpm(svm->msrpm);
719
b286d5d8
AG		 720 hsave_page = alloc_page(GFP_KERNEL);
721 if (!hsave_page)
722 goto uninit;
e6aa9abd 723 svm->nested.hsave = page_address(hsave_page);
b286d5d8 724
e6aa9abd 725 svm->nested.msrpm = page_address(nested_msrpm_pages);
3d6368ef 726
a2fa3e9f
GH		 727 svm->vmcb = page_address(page);
728 clear_page(svm->vmcb);
729 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
730 svm->asid_generation = 0;
e6101a96 731 init_vmcb(svm);
a2fa3e9f 732
fb3f0f51 733 fx_init(&svm->vcpu);
ad312c7c 734 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 735 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 736 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 737
fb3f0f51 738 return &svm->vcpu;
36241b8c 739
fb3f0f51
RR		 740uninit:
741 kvm_vcpu_uninit(&svm->vcpu);
742free_svm:
a4770347 743 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 744out:
745 return ERR_PTR(err);
6aa8b732
AK		 746}
747
748static void svm_free_vcpu(struct kvm_vcpu *vcpu)
749{
a2fa3e9f
GH		 750 struct vcpu_svm *svm = to_svm(vcpu);
751
fb3f0f51 752 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 753 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 754 __free_page(virt_to_page(svm->nested.hsave));
755 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 756 kvm_vcpu_uninit(vcpu);
a4770347 757 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 758}
759
15ad7146 760static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 761{
a2fa3e9f 762 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 763 int i;
0cc5064d 764
0cc5064d 765 if (unlikely(cpu != vcpu->cpu)) {
e935d48e 766 u64 delta;
0cc5064d 767
953899b6
JR		 768 if (check_tsc_unstable()) {
769 /*
770 * Make sure that the guest sees a monotonically
771 * increasing TSC.
772 */
773 delta = vcpu->arch.host_tsc - native_read_tsc();
774 svm->vmcb->control.tsc_offset += delta;
775 if (is_nested(svm))
776 svm->nested.hsave->control.tsc_offset += delta;
777 }
0cc5064d 778 vcpu->cpu = cpu;
2f599714 779 kvm_migrate_timers(vcpu);
4b656b12 780 svm->asid_generation = 0;
0cc5064d 781 }
94dfbdb3
AL		 782
783 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 784 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 785}
786
787static void svm_vcpu_put(struct kvm_vcpu *vcpu)
788{
a2fa3e9f 789 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 790 int i;
791
e1beb1d3 792 ++vcpu->stat.host_state_reload;
94dfbdb3 793 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 794 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 795
e935d48e 796 vcpu->arch.host_tsc = native_read_tsc();
6aa8b732
AK		 797}
798
6aa8b732
AK		 799static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
800{
a2fa3e9f 801 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 802}
803
804static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
805{
a2fa3e9f 806 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 807}
808
6de4f3ad
AK		 809static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
810{
811 switch (reg) {
812 case VCPU_EXREG_PDPTR:
813 BUG_ON(!npt_enabled);
814 load_pdptrs(vcpu, vcpu->arch.cr3);
815 break;
816 default:
817 BUG();
818 }
819}
820
f0b85051
AG		 821static void svm_set_vintr(struct vcpu_svm *svm)
822{
823 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
824}
825
826static void svm_clear_vintr(struct vcpu_svm *svm)
827{
828 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
829}
830
6aa8b732
AK		 831static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
832{
a2fa3e9f 833 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 834
835 switch (seg) {
836 case VCPU_SREG_CS: return &save->cs;
837 case VCPU_SREG_DS: return &save->ds;
838 case VCPU_SREG_ES: return &save->es;
839 case VCPU_SREG_FS: return &save->fs;
840 case VCPU_SREG_GS: return &save->gs;
841 case VCPU_SREG_SS: return &save->ss;
842 case VCPU_SREG_TR: return &save->tr;
843 case VCPU_SREG_LDTR: return &save->ldtr;
844 }
845 BUG();
8b6d44c7 846 return NULL;
6aa8b732
AK		 847}
848
849static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
850{
851 struct vmcb_seg *s = svm_seg(vcpu, seg);
852
853 return s->base;
854}
855
856static void svm_get_segment(struct kvm_vcpu *vcpu,
857 struct kvm_segment *var, int seg)
858{
859 struct vmcb_seg *s = svm_seg(vcpu, seg);
860
861 var->base = s->base;
862 var->limit = s->limit;
863 var->selector = s->selector;
864 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
865 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
866 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
867 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
868 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
869 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
870 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
871 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 872
19bca6ab
AP		 873 /* AMD's VMCB does not have an explicit unusable field, so emulate it
874 * for cross vendor migration purposes by "not present"
875 */
876 var->unusable = !var->present || (var->type == 0);
877
1fbdc7a5
AP		 878 switch (seg) {
879 case VCPU_SREG_CS:
880 /*
881 * SVM always stores 0 for the 'G' bit in the CS selector in
882 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
883 * Intel's VMENTRY has a check on the 'G' bit.
884 */
25022acc 885 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 886 break;
887 case VCPU_SREG_TR:
888 /*
889 * Work around a bug where the busy flag in the tr selector
890 * isn't exposed
891 */
c0d09828 892 var->type |= 0x2;
1fbdc7a5
AP		 893 break;
894 case VCPU_SREG_DS:
895 case VCPU_SREG_ES:
896 case VCPU_SREG_FS:
897 case VCPU_SREG_GS:
898 /*
899 * The accessed bit must always be set in the segment
900 * descriptor cache, although it can be cleared in the
901 * descriptor, the cached bit always remains at 1. Since
902 * Intel has a check on this, set it here to support
903 * cross-vendor migration.
904 */
905 if (!var->unusable)
906 var->type |= 0x1;
907 break;
b586eb02
AP		 908 case VCPU_SREG_SS:
909 /* On AMD CPUs sometimes the DB bit in the segment
910 * descriptor is left as 1, although the whole segment has
911 * been made unusable. Clear it here to pass an Intel VMX
912 * entry check when cross vendor migrating.
913 */
914 if (var->unusable)
915 var->db = 0;
916 break;
1fbdc7a5 917 }
6aa8b732
AK		 918}
919
2e4d2653
IE		 920static int svm_get_cpl(struct kvm_vcpu *vcpu)
921{
922 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
923
924 return save->cpl;
925}
926
6aa8b732
AK		 927static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
928{
a2fa3e9f
GH		 929 struct vcpu_svm *svm = to_svm(vcpu);
930
931 dt->limit = svm->vmcb->save.idtr.limit;
932 dt->base = svm->vmcb->save.idtr.base;
6aa8b732
AK		 933}
934
935static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
936{
a2fa3e9f
GH		 937 struct vcpu_svm *svm = to_svm(vcpu);
938
939 svm->vmcb->save.idtr.limit = dt->limit;
940 svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 941}
942
943static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
944{
a2fa3e9f
GH		 945 struct vcpu_svm *svm = to_svm(vcpu);
946
947 dt->limit = svm->vmcb->save.gdtr.limit;
948 dt->base = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 949}
950
951static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
952{
a2fa3e9f
GH		 953 struct vcpu_svm *svm = to_svm(vcpu);
954
955 svm->vmcb->save.gdtr.limit = dt->limit;
956 svm->vmcb->save.gdtr.base = dt->base ;
6aa8b732
AK		 957}
958
e8467fda
AK		 959static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
960{
961}
962
25c4c276 963static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 964{
965}
966
d225157b
AK		 967static void update_cr0_intercept(struct vcpu_svm *svm)
968{
969 ulong gcr0 = svm->vcpu.arch.cr0;
970 u64 *hcr0 = &svm->vmcb->save.cr0;
971
972 if (!svm->vcpu.fpu_active)
973 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
974 else
975 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
976 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
977
978
979 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
980 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
981 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
982 } else {
983 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
984 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
985 }
986}
987
6aa8b732
AK		 988static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
989{
a2fa3e9f
GH		 990 struct vcpu_svm *svm = to_svm(vcpu);
991
05b3e0c2 992#ifdef CONFIG_X86_64
ad312c7c 993 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 994 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
ad312c7c 995 vcpu->arch.shadow_efer |= EFER_LMA;
2b5203ee 996 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 997 }
998
d77c26fc 999 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
ad312c7c 1000 vcpu->arch.shadow_efer &= ~EFER_LMA;
2b5203ee 1001 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1002 }
1003 }
1004#endif
ad312c7c 1005 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1006
1007 if (!npt_enabled)
1008 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1009
1010 if (!vcpu->fpu_active)
334df50a 1011 cr0 |= X86_CR0_TS;
709ddebf
JR		 1012 /*
1013 * re-enable caching here because the QEMU bios
1014 * does not do it - this results in some delay at
1015 * reboot
1016 */
1017 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1018 svm->vmcb->save.cr0 = cr0;
d225157b 1019 update_cr0_intercept(svm);
6aa8b732
AK		 1020}
1021
1022static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1023{
6394b649 1024 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1025 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1026
1027 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1028 force_new_asid(vcpu);
6394b649 1029
ec077263
JR		 1030 vcpu->arch.cr4 = cr4;
1031 if (!npt_enabled)
1032 cr4 |= X86_CR4_PAE;
6394b649 1033 cr4 |= host_cr4_mce;
ec077263 1034 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1035}
1036
1037static void svm_set_segment(struct kvm_vcpu *vcpu,
1038 struct kvm_segment *var, int seg)
1039{
a2fa3e9f 1040 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1041 struct vmcb_seg *s = svm_seg(vcpu, seg);
1042
1043 s->base = var->base;
1044 s->limit = var->limit;
1045 s->selector = var->selector;
1046 if (var->unusable)
1047 s->attrib = 0;
1048 else {
1049 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1050 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1051 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1052 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1053 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1054 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1055 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1056 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1057 }
1058 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1059 svm->vmcb->save.cpl
1060 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1061 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1062
1063}
1064
44c11430 1065static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1066{
d0bfb940
JK		 1067 struct vcpu_svm *svm = to_svm(vcpu);
1068
d0bfb940
JK		 1069 svm->vmcb->control.intercept_exceptions &=
1070 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1071
6be7d306 1072 if (svm->nmi_singlestep)
44c11430
GN		 1073 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1074
d0bfb940
JK		 1075 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1076 if (vcpu->guest_debug &
1077 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1078 svm->vmcb->control.intercept_exceptions |=
1079 1 << DB_VECTOR;
1080 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1081 svm->vmcb->control.intercept_exceptions |=
1082 1 << BP_VECTOR;
1083 } else
1084 vcpu->guest_debug = 0;
44c11430
GN		 1085}
1086
355be0b9 1087static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1088{
44c11430
GN		 1089 struct vcpu_svm *svm = to_svm(vcpu);
1090
ae675ef0
JK		 1091 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1092 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1093 else
1094 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1095
355be0b9 1096 update_db_intercept(vcpu);
6aa8b732
AK		 1097}
1098
1099static void load_host_msrs(struct kvm_vcpu *vcpu)
1100{
94dfbdb3 1101#ifdef CONFIG_X86_64
a2fa3e9f 1102 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1103#endif
6aa8b732
AK		 1104}
1105
1106static void save_host_msrs(struct kvm_vcpu *vcpu)
1107{
94dfbdb3 1108#ifdef CONFIG_X86_64
a2fa3e9f 1109 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1110#endif
6aa8b732
AK		 1111}
1112
0fe1e009 1113static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1114{
0fe1e009
TH		 1115 if (sd->next_asid > sd->max_asid) {
1116 ++sd->asid_generation;
1117 sd->next_asid = 1;
a2fa3e9f 1118 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1119 }
1120
0fe1e009
TH		 1121 svm->asid_generation = sd->asid_generation;
1122 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1123}
1124
6aa8b732
AK		 1125static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1126{
42dbaa5a
JK		 1127 struct vcpu_svm *svm = to_svm(vcpu);
1128 unsigned long val;
1129
1130 switch (dr) {
1131 case 0 ... 3:
1132 val = vcpu->arch.db[dr];
1133 break;
1134 case 6:
1135 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1136 val = vcpu->arch.dr6;
1137 else
1138 val = svm->vmcb->save.dr6;
1139 break;
1140 case 7:
1141 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1142 val = vcpu->arch.dr7;
1143 else
1144 val = svm->vmcb->save.dr7;
1145 break;
1146 default:
1147 val = 0;
1148 }
1149
af9ca2d7 1150 return val;
6aa8b732
AK		 1151}
1152
1153static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1154 int *exception)
1155{
a2fa3e9f
GH		 1156 struct vcpu_svm *svm = to_svm(vcpu);
1157
42dbaa5a 1158 *exception = 0;
6aa8b732
AK		 1159
1160 switch (dr) {
1161 case 0 ... 3:
42dbaa5a
JK		 1162 vcpu->arch.db[dr] = value;
1163 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1164 vcpu->arch.eff_db[dr] = value;
6aa8b732
AK		 1165 return;
1166 case 4 ... 5:
42dbaa5a 1167 if (vcpu->arch.cr4 & X86_CR4_DE)
6aa8b732 1168 *exception = UD_VECTOR;
42dbaa5a
JK		 1169 return;
1170 case 6:
1171 if (value & 0xffffffff00000000ULL) {
1172 *exception = GP_VECTOR;
6aa8b732
AK		 1173 return;
1174 }
42dbaa5a
JK		 1175 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1176 return;
1177 case 7:
1178 if (value & 0xffffffff00000000ULL) {
6aa8b732
AK		 1179 *exception = GP_VECTOR;
1180 return;
1181 }
42dbaa5a
JK		 1182 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1183 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1184 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1185 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1186 }
6aa8b732 1187 return;
6aa8b732 1188 default:
42dbaa5a 1189 /* FIXME: Possible case? */
6aa8b732 1190 printk(KERN_DEBUG "%s: unexpected dr %u\n",
b8688d51 1191 __func__, dr);
6aa8b732
AK		 1192 *exception = UD_VECTOR;
1193 return;
1194 }
1195}
1196
851ba692 1197static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1198{
6aa8b732
AK		 1199 u64 fault_address;
1200 u32 error_code;
6aa8b732 1201
a2fa3e9f
GH		 1202 fault_address = svm->vmcb->control.exit_info_2;
1203 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1204
229456fc 1205 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1206 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1207 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1208 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1209}
1210
851ba692 1211static int db_interception(struct vcpu_svm *svm)
d0bfb940 1212{
851ba692
AK		 1213 struct kvm_run *kvm_run = svm->vcpu.run;
1214
d0bfb940 1215 if (!(svm->vcpu.guest_debug &
44c11430 1216 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1217 !svm->nmi_singlestep) {
d0bfb940
JK		 1218 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1219 return 1;
1220 }
44c11430 1221
6be7d306
JK		 1222 if (svm->nmi_singlestep) {
1223 svm->nmi_singlestep = false;
44c11430
GN		 1224 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1225 svm->vmcb->save.rflags &=
1226 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1227 update_db_intercept(&svm->vcpu);
1228 }
1229
1230 if (svm->vcpu.guest_debug &
1231 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1232 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1233 kvm_run->debug.arch.pc =
1234 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1235 kvm_run->debug.arch.exception = DB_VECTOR;
1236 return 0;
1237 }
1238
1239 return 1;
d0bfb940
JK		 1240}
1241
851ba692 1242static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1243{
851ba692
AK		 1244 struct kvm_run *kvm_run = svm->vcpu.run;
1245
d0bfb940
JK		 1246 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1247 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1248 kvm_run->debug.arch.exception = BP_VECTOR;
1249 return 0;
1250}
1251
851ba692 1252static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1253{
1254 int er;
1255
851ba692 1256 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1257 if (er != EMULATE_DONE)
7ee5d940 1258 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1259 return 1;
1260}
1261
851ba692 1262static int nm_interception(struct vcpu_svm *svm)
7807fa6c 1263{
a2fa3e9f 1264 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
e756fc62 1265 svm->vcpu.fpu_active = 1;
d225157b 1266 update_cr0_intercept(svm);
a2fa3e9f
GH		 1267
1268 return 1;
7807fa6c
AL		 1269}
1270
851ba692 1271static int mc_interception(struct vcpu_svm *svm)
53371b50
JR		 1272{
1273 /*
1274 * On an #MC intercept the MCE handler is not called automatically in
1275 * the host. So do it by hand here.
1276 */
1277 asm volatile (
1278 "int $0x12\n");
1279 /* not sure if we ever come back to this point */
1280
1281 return 1;
1282}
1283
851ba692 1284static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1285{
851ba692
AK		 1286 struct kvm_run *kvm_run = svm->vcpu.run;
1287
46fe4ddd
JR		 1288 /*
1289 * VMCB is undefined after a SHUTDOWN intercept
1290 * so reinitialize it.
1291 */
a2fa3e9f 1292 clear_page(svm->vmcb);
e6101a96 1293 init_vmcb(svm);
46fe4ddd
JR		 1294
1295 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1296 return 0;
1297}
1298
851ba692 1299static int io_interception(struct vcpu_svm *svm)
6aa8b732 1300{
d77c26fc 1301 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1302 int size, in, string;
039576c0 1303 unsigned port;
6aa8b732 1304
e756fc62 1305 ++svm->vcpu.stat.io_exits;
6aa8b732 1306
a2fa3e9f 1307 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1308
e70669ab
LV		 1309 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1310
1311 if (string) {
3427318f 1312 if (emulate_instruction(&svm->vcpu,
851ba692 1313 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1314 return 0;
1315 return 1;
1316 }
1317
039576c0
AK		 1318 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1319 port = io_info >> 16;
1320 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1321
e93f36bc 1322 skip_emulated_instruction(&svm->vcpu);
851ba692 1323 return kvm_emulate_pio(&svm->vcpu, in, size, port);
6aa8b732
AK		 1324}
1325
851ba692 1326static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1327{
1328 return 1;
1329}
1330
851ba692 1331static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1332{
1333 ++svm->vcpu.stat.irq_exits;
1334 return 1;
1335}
1336
851ba692 1337static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1338{
1339 return 1;
1340}
1341
851ba692 1342static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1343{
5fdbf976 1344 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1345 skip_emulated_instruction(&svm->vcpu);
1346 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1347}
1348
851ba692 1349static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1350{
5fdbf976 1351 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1352 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1353 kvm_emulate_hypercall(&svm->vcpu);
1354 return 1;
02e235bc
AK		 1355}
1356
c0725420
AG		 1357static int nested_svm_check_permissions(struct vcpu_svm *svm)
1358{
1359 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1360 || !is_paging(&svm->vcpu)) {
1361 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1362 return 1;
1363 }
1364
1365 if (svm->vmcb->save.cpl) {
1366 kvm_inject_gp(&svm->vcpu, 0);
1367 return 1;
1368 }
1369
1370 return 0;
1371}
1372
cf74a78b
AG		 1373static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1374 bool has_error_code, u32 error_code)
1375{
0295ad7d
JR		 1376 if (!is_nested(svm))
1377 return 0;
cf74a78b 1378
0295ad7d
JR		 1379 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1380 svm->vmcb->control.exit_code_hi = 0;
1381 svm->vmcb->control.exit_info_1 = error_code;
1382 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1383
410e4d57 1384 return nested_svm_exit_handled(svm);
cf74a78b
AG		 1385}
1386
1387static inline int nested_svm_intr(struct vcpu_svm *svm)
1388{
26666957
JR		 1389 if (!is_nested(svm))
1390 return 0;
cf74a78b 1391
26666957
JR		 1392 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1393 return 0;
cf74a78b 1394
26666957
JR		 1395 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1396 return 0;
cf74a78b 1397
26666957
JR		 1398 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1399
cd3ff653
JR		 1400 if (svm->nested.intercept & 1ULL) {
1401 /*
1402 * The #vmexit can't be emulated here directly because this
1403 * code path runs with irqs and preemtion disabled. A
1404 * #vmexit emulation might sleep. Only signal request for
1405 * the #vmexit here.
1406 */
1407 svm->nested.exit_required = true;
236649de 1408 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
26666957 1409 return 1;
cf74a78b
AG		 1410 }
1411
1412 return 0;
1413}
1414
34f80cfa
JR		 1415static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1416{
1417 struct page *page;
1418
34f80cfa 1419 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1420 if (is_error_page(page))
1421 goto error;
1422
1423 return kmap_atomic(page, idx);
1424
1425error:
1426 kvm_release_page_clean(page);
1427 kvm_inject_gp(&svm->vcpu, 0);
1428
1429 return NULL;
1430}
1431
1432static void nested_svm_unmap(void *addr, enum km_type idx)
1433{
1434 struct page *page;
1435
1436 if (!addr)
1437 return;
1438
1439 page = kmap_atomic_to_page(addr);
1440
1441 kunmap_atomic(addr, idx);
1442 kvm_release_page_dirty(page);
1443}
1444
3d62d9aa 1445static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1446{
4c2161ae 1447 u32 param = svm->vmcb->control.exit_info_1 & 1;
3d62d9aa
JR		 1448 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1449 bool ret = false;
1450 u32 t0, t1;
1451 u8 *msrpm;
4c2161ae 1452
3d62d9aa
JR		 1453 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1454 return false;
1455
1456 msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1457
1458 if (!msrpm)
1459 goto out;
4c2161ae
JR		 1460
1461 switch (msr) {
1462 case 0 ... 0x1fff:
1463 t0 = (msr * 2) % 8;
1464 t1 = msr / 8;
1465 break;
1466 case 0xc0000000 ... 0xc0001fff:
1467 t0 = (8192 + msr - 0xc0000000) * 2;
1468 t1 = (t0 / 8);
1469 t0 %= 8;
1470 break;
1471 case 0xc0010000 ... 0xc0011fff:
1472 t0 = (16384 + msr - 0xc0010000) * 2;
1473 t1 = (t0 / 8);
1474 t0 %= 8;
1475 break;
1476 default:
3d62d9aa
JR		 1477 ret = true;
1478 goto out;
4c2161ae 1479 }
4c2161ae 1480
3d62d9aa
JR		 1481 ret = msrpm[t1] & ((1 << param) << t0);
1482
1483out:
1484 nested_svm_unmap(msrpm, KM_USER0);
1485
1486 return ret;
4c2161ae
JR		 1487}
1488
410e4d57 1489static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1490{
cf74a78b 1491 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1492
410e4d57
JR		 1493 switch (exit_code) {
1494 case SVM_EXIT_INTR:
1495 case SVM_EXIT_NMI:
1496 return NESTED_EXIT_HOST;
cf74a78b 1497 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1498 case SVM_EXIT_NPF:
1499 if (npt_enabled)
1500 return NESTED_EXIT_HOST;
1501 break;
1502 /* When we're shadowing, trap PFs */
1503 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1504 if (!npt_enabled)
1505 return NESTED_EXIT_HOST;
1506 break;
1507 default:
1508 break;
cf74a78b
AG		 1509 }
1510
410e4d57
JR		 1511 return NESTED_EXIT_CONTINUE;
1512}
1513
1514/*
1515 * If this function returns true, this #vmexit was already handled
1516 */
1517static int nested_svm_exit_handled(struct vcpu_svm *svm)
1518{
1519 u32 exit_code = svm->vmcb->control.exit_code;
1520 int vmexit = NESTED_EXIT_HOST;
1521
cf74a78b 1522 switch (exit_code) {
9c4e40b9 1523 case SVM_EXIT_MSR:
3d62d9aa 1524 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1525 break;
cf74a78b
AG		 1526 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1527 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1528 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1529 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1530 break;
1531 }
1532 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1533 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1534 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1535 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1536 break;
1537 }
1538 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1539 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1540 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1541 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1542 break;
1543 }
1544 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1545 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1546 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1547 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1548 break;
1549 }
1550 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1551 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1552 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1553 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1554 break;
1555 }
1556 default: {
1557 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1558 if (svm->nested.intercept & exit_bits)
410e4d57 1559 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1560 }
1561 }
1562
410e4d57 1563 if (vmexit == NESTED_EXIT_DONE) {
9c4e40b9
JR		 1564 nested_svm_vmexit(svm);
1565 }
1566
1567 return vmexit;
cf74a78b
AG		 1568}
1569
0460a979
JR		 1570static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1571{
1572 struct vmcb_control_area *dst = &dst_vmcb->control;
1573 struct vmcb_control_area *from = &from_vmcb->control;
1574
1575 dst->intercept_cr_read = from->intercept_cr_read;
1576 dst->intercept_cr_write = from->intercept_cr_write;
1577 dst->intercept_dr_read = from->intercept_dr_read;
1578 dst->intercept_dr_write = from->intercept_dr_write;
1579 dst->intercept_exceptions = from->intercept_exceptions;
1580 dst->intercept = from->intercept;
1581 dst->iopm_base_pa = from->iopm_base_pa;
1582 dst->msrpm_base_pa = from->msrpm_base_pa;
1583 dst->tsc_offset = from->tsc_offset;
1584 dst->asid = from->asid;
1585 dst->tlb_ctl = from->tlb_ctl;
1586 dst->int_ctl = from->int_ctl;
1587 dst->int_vector = from->int_vector;
1588 dst->int_state = from->int_state;
1589 dst->exit_code = from->exit_code;
1590 dst->exit_code_hi = from->exit_code_hi;
1591 dst->exit_info_1 = from->exit_info_1;
1592 dst->exit_info_2 = from->exit_info_2;
1593 dst->exit_int_info = from->exit_int_info;
1594 dst->exit_int_info_err = from->exit_int_info_err;
1595 dst->nested_ctl = from->nested_ctl;
1596 dst->event_inj = from->event_inj;
1597 dst->event_inj_err = from->event_inj_err;
1598 dst->nested_cr3 = from->nested_cr3;
1599 dst->lbr_ctl = from->lbr_ctl;
1600}
1601
34f80cfa 1602static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1603{
34f80cfa 1604 struct vmcb *nested_vmcb;
e6aa9abd 1605 struct vmcb *hsave = svm->nested.hsave;
33740e40 1606 struct vmcb *vmcb = svm->vmcb;
cf74a78b 1607
17897f36
JR		 1608 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1609 vmcb->control.exit_info_1,
1610 vmcb->control.exit_info_2,
1611 vmcb->control.exit_int_info,
1612 vmcb->control.exit_int_info_err);
1613
34f80cfa
JR		 1614 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1615 if (!nested_vmcb)
1616 return 1;
1617
cf74a78b 1618 /* Give the current vmcb to the guest */
33740e40
JR		 1619 disable_gif(svm);
1620
1621 nested_vmcb->save.es = vmcb->save.es;
1622 nested_vmcb->save.cs = vmcb->save.cs;
1623 nested_vmcb->save.ss = vmcb->save.ss;
1624 nested_vmcb->save.ds = vmcb->save.ds;
1625 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1626 nested_vmcb->save.idtr = vmcb->save.idtr;
1627 if (npt_enabled)
1628 nested_vmcb->save.cr3 = vmcb->save.cr3;
1629 nested_vmcb->save.cr2 = vmcb->save.cr2;
1630 nested_vmcb->save.rflags = vmcb->save.rflags;
1631 nested_vmcb->save.rip = vmcb->save.rip;
1632 nested_vmcb->save.rsp = vmcb->save.rsp;
1633 nested_vmcb->save.rax = vmcb->save.rax;
1634 nested_vmcb->save.dr7 = vmcb->save.dr7;
1635 nested_vmcb->save.dr6 = vmcb->save.dr6;
1636 nested_vmcb->save.cpl = vmcb->save.cpl;
1637
1638 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1639 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1640 nested_vmcb->control.int_state = vmcb->control.int_state;
1641 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1642 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1643 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1644 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1645 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1646 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
8d23c466
AG		 1647
1648 /*
1649 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1650 * to make sure that we do not lose injected events. So check event_inj
1651 * here and copy it to exit_int_info if it is valid.
1652 * Exit_int_info and event_inj can't be both valid because the case
1653 * below only happens on a VMRUN instruction intercept which has
1654 * no valid exit_int_info set.
1655 */
1656 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1657 struct vmcb_control_area *nc = &nested_vmcb->control;
1658
1659 nc->exit_int_info = vmcb->control.event_inj;
1660 nc->exit_int_info_err = vmcb->control.event_inj_err;
1661 }
1662
33740e40
JR		 1663 nested_vmcb->control.tlb_ctl = 0;
1664 nested_vmcb->control.event_inj = 0;
1665 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1666
1667 /* We always set V_INTR_MASKING and remember the old value in hflags */
1668 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1669 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1670
cf74a78b 1671 /* Restore the original control entries */
0460a979 1672 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1673
219b65dc
AG		 1674 kvm_clear_exception_queue(&svm->vcpu);
1675 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1676
1677 /* Restore selected save entries */
1678 svm->vmcb->save.es = hsave->save.es;
1679 svm->vmcb->save.cs = hsave->save.cs;
1680 svm->vmcb->save.ss = hsave->save.ss;
1681 svm->vmcb->save.ds = hsave->save.ds;
1682 svm->vmcb->save.gdtr = hsave->save.gdtr;
1683 svm->vmcb->save.idtr = hsave->save.idtr;
1684 svm->vmcb->save.rflags = hsave->save.rflags;
1685 svm_set_efer(&svm->vcpu, hsave->save.efer);
1686 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1687 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1688 if (npt_enabled) {
1689 svm->vmcb->save.cr3 = hsave->save.cr3;
1690 svm->vcpu.arch.cr3 = hsave->save.cr3;
1691 } else {
1692 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1693 }
1694 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1695 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1696 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1697 svm->vmcb->save.dr7 = 0;
1698 svm->vmcb->save.cpl = 0;
1699 svm->vmcb->control.exit_int_info = 0;
1700
cf74a78b 1701 /* Exit nested SVM mode */
e6aa9abd 1702 svm->nested.vmcb = 0;
cf74a78b 1703
34f80cfa 1704 nested_svm_unmap(nested_vmcb, KM_USER0);
cf74a78b
AG		 1705
1706 kvm_mmu_reset_context(&svm->vcpu);
1707 kvm_mmu_load(&svm->vcpu);
1708
1709 return 0;
1710}
3d6368ef 1711
9738b2c9 1712static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1713{
9738b2c9 1714 u32 *nested_msrpm;
3d6368ef 1715 int i;
9738b2c9
JR		 1716
1717 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1718 if (!nested_msrpm)
1719 return false;
1720
3d6368ef 1721 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
e6aa9abd 1722 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
9738b2c9 1723
e6aa9abd 1724 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
3d6368ef 1725
9738b2c9
JR		 1726 nested_svm_unmap(nested_msrpm, KM_USER0);
1727
1728 return true;
3d6368ef
AG		 1729}
1730
9738b2c9 1731static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 1732{
9738b2c9 1733 struct vmcb *nested_vmcb;
e6aa9abd 1734 struct vmcb *hsave = svm->nested.hsave;
defbba56 1735 struct vmcb *vmcb = svm->vmcb;
3d6368ef 1736
9738b2c9
JR		 1737 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1738 if (!nested_vmcb)
1739 return false;
1740
3d6368ef 1741 /* nested_vmcb is our indicator if nested SVM is activated */
e6aa9abd 1742 svm->nested.vmcb = svm->vmcb->save.rax;
3d6368ef 1743
0ac406de
JR		 1744 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1745 nested_vmcb->save.rip,
1746 nested_vmcb->control.int_ctl,
1747 nested_vmcb->control.event_inj,
1748 nested_vmcb->control.nested_ctl);
1749
3d6368ef 1750 /* Clear internal status */
219b65dc
AG		 1751 kvm_clear_exception_queue(&svm->vcpu);
1752 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef
AG		 1753
1754 /* Save the old vmcb, so we don't need to pick what we save, but
1755 can restore everything when a VMEXIT occurs */
defbba56
JR		 1756 hsave->save.es = vmcb->save.es;
1757 hsave->save.cs = vmcb->save.cs;
1758 hsave->save.ss = vmcb->save.ss;
1759 hsave->save.ds = vmcb->save.ds;
1760 hsave->save.gdtr = vmcb->save.gdtr;
1761 hsave->save.idtr = vmcb->save.idtr;
1762 hsave->save.efer = svm->vcpu.arch.shadow_efer;
4d4ec087 1763 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 1764 hsave->save.cr4 = svm->vcpu.arch.cr4;
1765 hsave->save.rflags = vmcb->save.rflags;
1766 hsave->save.rip = svm->next_rip;
1767 hsave->save.rsp = vmcb->save.rsp;
1768 hsave->save.rax = vmcb->save.rax;
1769 if (npt_enabled)
1770 hsave->save.cr3 = vmcb->save.cr3;
1771 else
1772 hsave->save.cr3 = svm->vcpu.arch.cr3;
1773
0460a979 1774 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 1775
1776 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1777 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1778 else
1779 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1780
1781 /* Load the nested guest state */
1782 svm->vmcb->save.es = nested_vmcb->save.es;
1783 svm->vmcb->save.cs = nested_vmcb->save.cs;
1784 svm->vmcb->save.ss = nested_vmcb->save.ss;
1785 svm->vmcb->save.ds = nested_vmcb->save.ds;
1786 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1787 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1788 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1789 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1790 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1791 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1792 if (npt_enabled) {
1793 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1794 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1795 } else {
1796 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1797 kvm_mmu_reset_context(&svm->vcpu);
1798 }
defbba56 1799 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 1800 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1801 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1802 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1803 /* In case we don't even reach vcpu_run, the fields are not updated */
1804 svm->vmcb->save.rax = nested_vmcb->save.rax;
1805 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1806 svm->vmcb->save.rip = nested_vmcb->save.rip;
1807 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1808 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1809 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1810
1811 /* We don't want a nested guest to be more powerful than the guest,
1812 so all intercepts are ORed */
1813 svm->vmcb->control.intercept_cr_read |=
1814 nested_vmcb->control.intercept_cr_read;
1815 svm->vmcb->control.intercept_cr_write |=
1816 nested_vmcb->control.intercept_cr_write;
1817 svm->vmcb->control.intercept_dr_read |=
1818 nested_vmcb->control.intercept_dr_read;
1819 svm->vmcb->control.intercept_dr_write |=
1820 nested_vmcb->control.intercept_dr_write;
1821 svm->vmcb->control.intercept_exceptions |=
1822 nested_vmcb->control.intercept_exceptions;
1823
1824 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1825
e6aa9abd 1826 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
3d6368ef 1827
aad42c64
JR		 1828 /* cache intercepts */
1829 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1830 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1831 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1832 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1833 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1834 svm->nested.intercept = nested_vmcb->control.intercept;
1835
3d6368ef 1836 force_new_asid(&svm->vcpu);
3d6368ef 1837 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 1838 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1839 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1840 else
1841 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1842
3d6368ef
AG		 1843 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1844 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1845 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 1846 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1847 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1848
9738b2c9
JR		 1849 nested_svm_unmap(nested_vmcb, KM_USER0);
1850
2af9194d 1851 enable_gif(svm);
3d6368ef 1852
9738b2c9 1853 return true;
3d6368ef
AG		 1854}
1855
9966bf68 1856static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 1857{
1858 to_vmcb->save.fs = from_vmcb->save.fs;
1859 to_vmcb->save.gs = from_vmcb->save.gs;
1860 to_vmcb->save.tr = from_vmcb->save.tr;
1861 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1862 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1863 to_vmcb->save.star = from_vmcb->save.star;
1864 to_vmcb->save.lstar = from_vmcb->save.lstar;
1865 to_vmcb->save.cstar = from_vmcb->save.cstar;
1866 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1867 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1868 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1869 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 1870}
1871
851ba692 1872static int vmload_interception(struct vcpu_svm *svm)
5542675b 1873{
9966bf68
JR		 1874 struct vmcb *nested_vmcb;
1875
5542675b
AG		 1876 if (nested_svm_check_permissions(svm))
1877 return 1;
1878
1879 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1880 skip_emulated_instruction(&svm->vcpu);
1881
9966bf68
JR		 1882 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1883 if (!nested_vmcb)
1884 return 1;
1885
1886 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1887 nested_svm_unmap(nested_vmcb, KM_USER0);
5542675b
AG		 1888
1889 return 1;
1890}
1891
851ba692 1892static int vmsave_interception(struct vcpu_svm *svm)
5542675b 1893{
9966bf68
JR		 1894 struct vmcb *nested_vmcb;
1895
5542675b
AG		 1896 if (nested_svm_check_permissions(svm))
1897 return 1;
1898
1899 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1900 skip_emulated_instruction(&svm->vcpu);
1901
9966bf68
JR		 1902 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1903 if (!nested_vmcb)
1904 return 1;
1905
1906 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1907 nested_svm_unmap(nested_vmcb, KM_USER0);
5542675b
AG		 1908
1909 return 1;
1910}
1911
851ba692 1912static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 1913{
3d6368ef
AG		 1914 if (nested_svm_check_permissions(svm))
1915 return 1;
1916
1917 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1918 skip_emulated_instruction(&svm->vcpu);
1919
9738b2c9 1920 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 1921 return 1;
1922
9738b2c9 1923 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 1924 goto failed;
1925
1926 return 1;
1927
1928failed:
1929
1930 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
1931 svm->vmcb->control.exit_code_hi = 0;
1932 svm->vmcb->control.exit_info_1 = 0;
1933 svm->vmcb->control.exit_info_2 = 0;
1934
1935 nested_svm_vmexit(svm);
3d6368ef
AG		 1936
1937 return 1;
1938}
1939
851ba692 1940static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 1941{
1942 if (nested_svm_check_permissions(svm))
1943 return 1;
1944
1945 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1946 skip_emulated_instruction(&svm->vcpu);
1947
2af9194d 1948 enable_gif(svm);
1371d904
AG		 1949
1950 return 1;
1951}
1952
851ba692 1953static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 1954{
1955 if (nested_svm_check_permissions(svm))
1956 return 1;
1957
1958 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1959 skip_emulated_instruction(&svm->vcpu);
1960
2af9194d 1961 disable_gif(svm);
1371d904
AG		 1962
1963 /* After a CLGI no interrupts should come */
1964 svm_clear_vintr(svm);
1965 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1966
1967 return 1;
1968}
1969
851ba692 1970static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 1971{
1972 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 1973
ec1ff790
JR		 1974 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
1975 vcpu->arch.regs[VCPU_REGS_RAX]);
1976
ff092385
AG		 1977 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1978 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1979
1980 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1981 skip_emulated_instruction(&svm->vcpu);
1982 return 1;
1983}
1984
532a46b9
JR		 1985static int skinit_interception(struct vcpu_svm *svm)
1986{
1987 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
1988
1989 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1990 return 1;
1991}
1992
851ba692 1993static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 1994{
7ee5d940 1995 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 1996 return 1;
1997}
1998
851ba692 1999static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2000{
37817f29 2001 u16 tss_selector;
64a7ec06
GN		 2002 int reason;
2003 int int_type = svm->vmcb->control.exit_int_info &
2004 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2005 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2006 uint32_t type =
2007 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2008 uint32_t idt_v =
2009 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 2010
2011 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2012
37817f29
IE		 2013 if (svm->vmcb->control.exit_info_2 &
2014 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2015 reason = TASK_SWITCH_IRET;
2016 else if (svm->vmcb->control.exit_info_2 &
2017 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2018 reason = TASK_SWITCH_JMP;
fe8e7f83 2019 else if (idt_v)
64a7ec06
GN		 2020 reason = TASK_SWITCH_GATE;
2021 else
2022 reason = TASK_SWITCH_CALL;
2023
fe8e7f83
GN		 2024 if (reason == TASK_SWITCH_GATE) {
2025 switch (type) {
2026 case SVM_EXITINTINFO_TYPE_NMI:
2027 svm->vcpu.arch.nmi_injected = false;
2028 break;
2029 case SVM_EXITINTINFO_TYPE_EXEPT:
2030 kvm_clear_exception_queue(&svm->vcpu);
2031 break;
2032 case SVM_EXITINTINFO_TYPE_INTR:
2033 kvm_clear_interrupt_queue(&svm->vcpu);
2034 break;
2035 default:
2036 break;
2037 }
2038 }
64a7ec06 2039
8317c298
GN		 2040 if (reason != TASK_SWITCH_GATE ||
2041 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2042 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2043 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2044 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2045
2046 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2047}
2048
851ba692 2049static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2050{
5fdbf976 2051 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2052 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2053 return 1;
6aa8b732
AK		 2054}
2055
851ba692 2056static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2057{
2058 ++svm->vcpu.stat.nmi_window_exits;
2059 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2060 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2061 return 1;
2062}
2063
851ba692 2064static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2065{
851ba692 2066 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
a7052897
MT		 2067 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2068 return 1;
2069}
2070
851ba692 2071static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2072{
851ba692 2073 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
b8688d51 2074 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2075 return 1;
2076}
2077
851ba692 2078static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2079{
851ba692
AK		 2080 struct kvm_run *kvm_run = svm->vcpu.run;
2081
0a5fff19
GN		 2082 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2083 /* instruction emulation calls kvm_set_cr8() */
851ba692 2084 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2085 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2086 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2087 return 1;
95ba8273 2088 }
0a5fff19
GN		 2089 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2090 return 1;
1d075434
JR		 2091 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2092 return 0;
2093}
2094
6aa8b732
AK		 2095static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2096{
a2fa3e9f
GH		 2097 struct vcpu_svm *svm = to_svm(vcpu);
2098
6aa8b732 2099 switch (ecx) {
af24a4e4 2100 case MSR_IA32_TSC: {
20824f30 2101 u64 tsc_offset;
6aa8b732 2102
20824f30
JR		 2103 if (is_nested(svm))
2104 tsc_offset = svm->nested.hsave->control.tsc_offset;
2105 else
2106 tsc_offset = svm->vmcb->control.tsc_offset;
2107
2108 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2109 break;
2110 }
0e859cac 2111 case MSR_K6_STAR:
a2fa3e9f 2112 *data = svm->vmcb->save.star;
6aa8b732 2113 break;
0e859cac 2114#ifdef CONFIG_X86_64
6aa8b732 2115 case MSR_LSTAR:
a2fa3e9f 2116 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2117 break;
2118 case MSR_CSTAR:
a2fa3e9f 2119 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2120 break;
2121 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2122 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2123 break;
2124 case MSR_SYSCALL_MASK:
a2fa3e9f 2125 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2126 break;
2127#endif
2128 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2129 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2130 break;
2131 case MSR_IA32_SYSENTER_EIP:
017cb99e 2132 *data = svm->sysenter_eip;
6aa8b732
AK		 2133 break;
2134 case MSR_IA32_SYSENTER_ESP:
017cb99e 2135 *data = svm->sysenter_esp;
6aa8b732 2136 break;
a2938c80
JR		 2137 /* Nobody will change the following 5 values in the VMCB so
2138 we can safely return them on rdmsr. They will always be 0
2139 until LBRV is implemented. */
2140 case MSR_IA32_DEBUGCTLMSR:
2141 *data = svm->vmcb->save.dbgctl;
2142 break;
2143 case MSR_IA32_LASTBRANCHFROMIP:
2144 *data = svm->vmcb->save.br_from;
2145 break;
2146 case MSR_IA32_LASTBRANCHTOIP:
2147 *data = svm->vmcb->save.br_to;
2148 break;
2149 case MSR_IA32_LASTINTFROMIP:
2150 *data = svm->vmcb->save.last_excp_from;
2151 break;
2152 case MSR_IA32_LASTINTTOIP:
2153 *data = svm->vmcb->save.last_excp_to;
2154 break;
b286d5d8 2155 case MSR_VM_HSAVE_PA:
e6aa9abd 2156 *data = svm->nested.hsave_msr;
b286d5d8 2157 break;
eb6f302e
JR		 2158 case MSR_VM_CR:
2159 *data = 0;
2160 break;
c8a73f18
AG		 2161 case MSR_IA32_UCODE_REV:
2162 *data = 0x01000065;
2163 break;
6aa8b732 2164 default:
3bab1f5d 2165 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2166 }
2167 return 0;
2168}
2169
851ba692 2170static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2171{
ad312c7c 2172 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2173 u64 data;
2174
e756fc62 2175 if (svm_get_msr(&svm->vcpu, ecx, &data))
c1a5d4f9 2176 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2177 else {
229456fc 2178 trace_kvm_msr_read(ecx, data);
af9ca2d7 2179
5fdbf976 2180 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2181 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2182 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2183 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2184 }
2185 return 1;
2186}
2187
2188static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2189{
a2fa3e9f
GH		 2190 struct vcpu_svm *svm = to_svm(vcpu);
2191
6aa8b732 2192 switch (ecx) {
af24a4e4 2193 case MSR_IA32_TSC: {
20824f30
JR		 2194 u64 tsc_offset = data - native_read_tsc();
2195 u64 g_tsc_offset = 0;
2196
2197 if (is_nested(svm)) {
2198 g_tsc_offset = svm->vmcb->control.tsc_offset -
2199 svm->nested.hsave->control.tsc_offset;
2200 svm->nested.hsave->control.tsc_offset = tsc_offset;
2201 }
2202
2203 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
6aa8b732 2204
6aa8b732
AK		 2205 break;
2206 }
0e859cac 2207 case MSR_K6_STAR:
a2fa3e9f 2208 svm->vmcb->save.star = data;
6aa8b732 2209 break;
49b14f24 2210#ifdef CONFIG_X86_64
6aa8b732 2211 case MSR_LSTAR:
a2fa3e9f 2212 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2213 break;
2214 case MSR_CSTAR:
a2fa3e9f 2215 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2216 break;
2217 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2218 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2219 break;
2220 case MSR_SYSCALL_MASK:
a2fa3e9f 2221 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2222 break;
2223#endif
2224 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2225 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2226 break;
2227 case MSR_IA32_SYSENTER_EIP:
017cb99e 2228 svm->sysenter_eip = data;
a2fa3e9f 2229 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2230 break;
2231 case MSR_IA32_SYSENTER_ESP:
017cb99e 2232 svm->sysenter_esp = data;
a2fa3e9f 2233 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2234 break;
a2938c80 2235 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2236 if (!svm_has(SVM_FEATURE_LBRV)) {
2237 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2238 __func__, data);
24e09cbf
JR		 2239 break;
2240 }
2241 if (data & DEBUGCTL_RESERVED_BITS)
2242 return 1;
2243
2244 svm->vmcb->save.dbgctl = data;
2245 if (data & (1ULL<<0))
2246 svm_enable_lbrv(svm);
2247 else
2248 svm_disable_lbrv(svm);
a2938c80 2249 break;
b286d5d8 2250 case MSR_VM_HSAVE_PA:
e6aa9abd 2251 svm->nested.hsave_msr = data;
62b9abaa 2252 break;
3c5d0a44
AG		 2253 case MSR_VM_CR:
2254 case MSR_VM_IGNNE:
3c5d0a44
AG		 2255 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2256 break;
6aa8b732 2257 default:
3bab1f5d 2258 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2259 }
2260 return 0;
2261}
2262
851ba692 2263static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2264{
ad312c7c 2265 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2266 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2267 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2268
229456fc 2269 trace_kvm_msr_write(ecx, data);
af9ca2d7 2270
5fdbf976 2271 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2272 if (svm_set_msr(&svm->vcpu, ecx, data))
c1a5d4f9 2273 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2274 else
e756fc62 2275 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2276 return 1;
2277}
2278
851ba692 2279static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2280{
e756fc62 2281 if (svm->vmcb->control.exit_info_1)
851ba692 2282 return wrmsr_interception(svm);
6aa8b732 2283 else
851ba692 2284 return rdmsr_interception(svm);
6aa8b732
AK		 2285}
2286
851ba692 2287static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2288{
851ba692
AK		 2289 struct kvm_run *kvm_run = svm->vcpu.run;
2290
f0b85051 2291 svm_clear_vintr(svm);
85f455f7 2292 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2293 /*
2294 * If the user space waits to inject interrupts, exit as soon as
2295 * possible
2296 */
8061823a
GN		 2297 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2298 kvm_run->request_interrupt_window &&
2299 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2300 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2301 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2302 return 0;
2303 }
2304
2305 return 1;
2306}
2307
565d0998
ML		 2308static int pause_interception(struct vcpu_svm *svm)
2309{
2310 kvm_vcpu_on_spin(&(svm->vcpu));
2311 return 1;
2312}
2313
851ba692 2314static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
6aa8b732
AK		 2315 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2316 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2317 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2318 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2319 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
6aa8b732
AK		 2320 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2321 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2322 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2323 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2324 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2325 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2326 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2327 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2328 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2329 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2330 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2331 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2332 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2333 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2334 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2335 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2336 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2337 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2338 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2339 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2340 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2341 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2342 [SVM_EXIT_SMI] = nop_on_interception,
2343 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2344 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2345 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2346 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2347 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2348 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2349 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2350 [SVM_EXIT_HLT] = halt_interception,
a7052897 2351 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2352 [SVM_EXIT_INVLPGA] = invlpga_interception,
6aa8b732
AK		 2353 [SVM_EXIT_IOIO] = io_interception,
2354 [SVM_EXIT_MSR] = msr_interception,
2355 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2356 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2357 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2358 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2359 [SVM_EXIT_VMLOAD] = vmload_interception,
2360 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2361 [SVM_EXIT_STGI] = stgi_interception,
2362 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2363 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2364 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2365 [SVM_EXIT_MONITOR] = invalid_op_interception,
2366 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2367 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2368};
2369
851ba692 2370static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2371{
04d2cc77 2372 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2373 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2374 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2375
229456fc 2376 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
af9ca2d7 2377
cd3ff653
JR		 2378 if (unlikely(svm->nested.exit_required)) {
2379 nested_svm_vmexit(svm);
2380 svm->nested.exit_required = false;
2381
2382 return 1;
2383 }
2384
cf74a78b 2385 if (is_nested(svm)) {
410e4d57
JR		 2386 int vmexit;
2387
d8cabddf
JR		 2388 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2389 svm->vmcb->control.exit_info_1,
2390 svm->vmcb->control.exit_info_2,
2391 svm->vmcb->control.exit_int_info,
2392 svm->vmcb->control.exit_int_info_err);
2393
410e4d57
JR		 2394 vmexit = nested_svm_exit_special(svm);
2395
2396 if (vmexit == NESTED_EXIT_CONTINUE)
2397 vmexit = nested_svm_exit_handled(svm);
2398
2399 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2400 return 1;
cf74a78b
AG		 2401 }
2402
a5c3832d
JR		 2403 svm_complete_interrupts(svm);
2404
888f9f3e 2405 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
709ddebf 2406 vcpu->arch.cr0 = svm->vmcb->save.cr0;
888f9f3e 2407 if (npt_enabled)
709ddebf 2408 vcpu->arch.cr3 = svm->vmcb->save.cr3;
04d2cc77
AK		 2409
2410 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2411 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2412 kvm_run->fail_entry.hardware_entry_failure_reason
2413 = svm->vmcb->control.exit_code;
2414 return 0;
2415 }
2416
a2fa3e9f 2417 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2418 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2419 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2420 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2421 "exit_code 0x%x\n",
b8688d51 2422 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2423 exit_code);
2424
9d8f549d 2425 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2426 || !svm_exit_handlers[exit_code]) {
6aa8b732 2427 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2428 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2429 return 0;
2430 }
2431
851ba692 2432 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2433}
2434
2435static void reload_tss(struct kvm_vcpu *vcpu)
2436{
2437 int cpu = raw_smp_processor_id();
2438
0fe1e009
TH		 2439 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2440 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2441 load_TR_desc();
2442}
2443
e756fc62 2444static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2445{
2446 int cpu = raw_smp_processor_id();
2447
0fe1e009 2448 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2449
a2fa3e9f 2450 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2451 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2452 if (svm->asid_generation != sd->asid_generation)
2453 new_asid(svm, sd);
6aa8b732
AK		 2454}
2455
95ba8273
GN		 2456static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2457{
2458 struct vcpu_svm *svm = to_svm(vcpu);
2459
2460 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2461 vcpu->arch.hflags |= HF_NMI_MASK;
2462 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2463 ++vcpu->stat.nmi_injections;
2464}
6aa8b732 2465
85f455f7 2466static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2467{
2468 struct vmcb_control_area *control;
2469
229456fc 2470 trace_kvm_inj_virq(irq);
af9ca2d7 2471
fa89a817 2472 ++svm->vcpu.stat.irq_injections;
e756fc62 2473 control = &svm->vmcb->control;
85f455f7 2474 control->int_vector = irq;
6aa8b732
AK		 2475 control->int_ctl &= ~V_INTR_PRIO_MASK;
2476 control->int_ctl |= V_IRQ_MASK |
2477 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2478}
2479
66fd3f7f 2480static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2481{
2482 struct vcpu_svm *svm = to_svm(vcpu);
2483
2af9194d 2484 BUG_ON(!(gif_set(svm)));
cf74a78b 2485
219b65dc
AG		 2486 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2487 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2488}
2489
95ba8273 2490static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2491{
2492 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2493
95ba8273 2494 if (irr == -1)
aaacfc9a
JR		 2495 return;
2496
95ba8273
GN		 2497 if (tpr >= irr)
2498 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2499}
aaacfc9a 2500
95ba8273
GN		 2501static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2502{
2503 struct vcpu_svm *svm = to_svm(vcpu);
2504 struct vmcb *vmcb = svm->vmcb;
2505 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2506 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2507}
2508
3cfc3092
JK		 2509static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2510{
2511 struct vcpu_svm *svm = to_svm(vcpu);
2512
2513 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2514}
2515
2516static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2517{
2518 struct vcpu_svm *svm = to_svm(vcpu);
2519
2520 if (masked) {
2521 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2522 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2523 } else {
2524 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2525 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2526 }
2527}
2528
78646121
GN		 2529static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2530{
2531 struct vcpu_svm *svm = to_svm(vcpu);
2532 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 2533 int ret;
2534
2535 if (!gif_set(svm) ||
2536 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2537 return 0;
2538
2539 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2540
2541 if (is_nested(svm))
2542 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2543
2544 return ret;
78646121
GN		 2545}
2546
9222be18 2547static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2548{
219b65dc 2549 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc
AG		 2550
2551 nested_svm_intr(svm);
2552
2553 /* In case GIF=0 we can't rely on the CPU to tell us when
2554 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2555 * The next time we get that intercept, this function will be
2556 * called again though and we'll get the vintr intercept. */
2af9194d 2557 if (gif_set(svm)) {
219b65dc
AG		 2558 svm_set_vintr(svm);
2559 svm_inject_irq(svm, 0x0);
2560 }
85f455f7
ED		 2561}
2562
95ba8273 2563static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2564{
04d2cc77 2565 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2566
44c11430
GN		 2567 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2568 == HF_NMI_MASK)
2569 return; /* IRET will cause a vm exit */
2570
2571 /* Something prevents NMI from been injected. Single step over
2572 possible problem (IRET or exception injection or interrupt
2573 shadow) */
6be7d306 2574 svm->nmi_singlestep = true;
44c11430
GN		 2575 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2576 update_db_intercept(vcpu);
c1150d8c
DL		 2577}
2578
cbc94022
IE		 2579static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2580{
2581 return 0;
2582}
2583
d9e368d6
AK		 2584static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2585{
2586 force_new_asid(vcpu);
2587}
2588
04d2cc77
AK		 2589static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2590{
2591}
2592
d7bf8221
JR		 2593static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2594{
2595 struct vcpu_svm *svm = to_svm(vcpu);
2596
2597 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2598 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2599 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2600 }
2601}
2602
649d6864
JR		 2603static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2604{
2605 struct vcpu_svm *svm = to_svm(vcpu);
2606 u64 cr8;
2607
649d6864
JR		 2608 cr8 = kvm_get_cr8(vcpu);
2609 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2610 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2611}
2612
9222be18
GN		 2613static void svm_complete_interrupts(struct vcpu_svm *svm)
2614{
2615 u8 vector;
2616 int type;
2617 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2618
44c11430
GN		 2619 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2620 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2621
9222be18
GN		 2622 svm->vcpu.arch.nmi_injected = false;
2623 kvm_clear_exception_queue(&svm->vcpu);
2624 kvm_clear_interrupt_queue(&svm->vcpu);
2625
2626 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2627 return;
2628
2629 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2630 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2631
2632 switch (type) {
2633 case SVM_EXITINTINFO_TYPE_NMI:
2634 svm->vcpu.arch.nmi_injected = true;
2635 break;
2636 case SVM_EXITINTINFO_TYPE_EXEPT:
2637 /* In case of software exception do not reinject an exception
2638 vector, but re-execute and instruction instead */
219b65dc
AG		 2639 if (is_nested(svm))
2640 break;
66fd3f7f 2641 if (kvm_exception_is_soft(vector))
9222be18
GN		 2642 break;
2643 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2644 u32 err = svm->vmcb->control.exit_int_info_err;
2645 kvm_queue_exception_e(&svm->vcpu, vector, err);
2646
2647 } else
2648 kvm_queue_exception(&svm->vcpu, vector);
2649 break;
2650 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2651 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2652 break;
2653 default:
2654 break;
2655 }
2656}
2657
80e31d4f
AK		 2658#ifdef CONFIG_X86_64
2659#define R "r"
2660#else
2661#define R "e"
2662#endif
2663
851ba692 2664static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 2665{
a2fa3e9f 2666 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2667 u16 fs_selector;
2668 u16 gs_selector;
2669 u16 ldt_selector;
d9e368d6 2670
cd3ff653
JR		 2671 /*
2672 * A vmexit emulation is required before the vcpu can be executed
2673 * again.
2674 */
2675 if (unlikely(svm->nested.exit_required))
2676 return;
2677
5fdbf976
MT		 2678 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2679 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2680 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2681
e756fc62 2682 pre_svm_run(svm);
6aa8b732 2683
649d6864
JR		 2684 sync_lapic_to_cr8(vcpu);
2685
6aa8b732 2686 save_host_msrs(vcpu);
d6e88aec
AK		 2687 fs_selector = kvm_read_fs();
2688 gs_selector = kvm_read_gs();
2689 ldt_selector = kvm_read_ldt();
cda0ffdd 2690 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2691 /* required for live migration with NPT */
2692 if (npt_enabled)
2693 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2694
04d2cc77
AK		 2695 clgi();
2696
2697 local_irq_enable();
36241b8c 2698
6aa8b732 2699 asm volatile (
80e31d4f
AK		 2700 "push %%"R"bp; \n\t"
2701 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2702 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2703 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2704 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2705 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2706 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2707#ifdef CONFIG_X86_64
fb3f0f51
RR		 2708 "mov %c[r8](%[svm]), %%r8 \n\t"
2709 "mov %c[r9](%[svm]), %%r9 \n\t"
2710 "mov %c[r10](%[svm]), %%r10 \n\t"
2711 "mov %c[r11](%[svm]), %%r11 \n\t"
2712 "mov %c[r12](%[svm]), %%r12 \n\t"
2713 "mov %c[r13](%[svm]), %%r13 \n\t"
2714 "mov %c[r14](%[svm]), %%r14 \n\t"
2715 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2716#endif
2717
6aa8b732 2718 /* Enter guest mode */
80e31d4f
AK		 2719 "push %%"R"ax \n\t"
2720 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2721 __ex(SVM_VMLOAD) "\n\t"
2722 __ex(SVM_VMRUN) "\n\t"
2723 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2724 "pop %%"R"ax \n\t"
6aa8b732
AK		 2725
2726 /* Save guest registers, load host registers */
80e31d4f
AK		 2727 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2728 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2729 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2730 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2731 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2732 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2733#ifdef CONFIG_X86_64
fb3f0f51
RR		 2734 "mov %%r8, %c[r8](%[svm]) \n\t"
2735 "mov %%r9, %c[r9](%[svm]) \n\t"
2736 "mov %%r10, %c[r10](%[svm]) \n\t"
2737 "mov %%r11, %c[r11](%[svm]) \n\t"
2738 "mov %%r12, %c[r12](%[svm]) \n\t"
2739 "mov %%r13, %c[r13](%[svm]) \n\t"
2740 "mov %%r14, %c[r14](%[svm]) \n\t"
2741 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2742#endif
80e31d4f 2743 "pop %%"R"bp"
6aa8b732 2744 :
fb3f0f51 2745 : [svm]"a"(svm),
6aa8b732 2746 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2747 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2748 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2749 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2750 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2751 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2752 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2753#ifdef CONFIG_X86_64
ad312c7c
ZX		 2754 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2755 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2756 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2757 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2758 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2759 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2760 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2761 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2762#endif
54a08c04 2763 : "cc", "memory"
80e31d4f 2764 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2765#ifdef CONFIG_X86_64
54a08c04
LV		 2766 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2767#endif
2768 );
6aa8b732 2769
ad312c7c 2770 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2771 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2772 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2773 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2774
d6e88aec
AK		 2775 kvm_load_fs(fs_selector);
2776 kvm_load_gs(gs_selector);
2777 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2778 load_host_msrs(vcpu);
2779
2780 reload_tss(vcpu);
2781
56ba47dd
AK		 2782 local_irq_disable();
2783
2784 stgi();
2785
d7bf8221
JR		 2786 sync_cr8_to_lapic(vcpu);
2787
a2fa3e9f 2788 svm->next_rip = 0;
9222be18 2789
6de4f3ad
AK		 2790 if (npt_enabled) {
2791 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2792 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2793 }
6aa8b732
AK		 2794}
2795
80e31d4f
AK		 2796#undef R
2797
6aa8b732
AK		 2798static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2799{
a2fa3e9f
GH		 2800 struct vcpu_svm *svm = to_svm(vcpu);
2801
709ddebf
JR		 2802 if (npt_enabled) {
2803 svm->vmcb->control.nested_cr3 = root;
2804 force_new_asid(vcpu);
2805 return;
2806 }
2807
a2fa3e9f 2808 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 2809 force_new_asid(vcpu);
2810}
2811
6aa8b732
AK		 2812static int is_disabled(void)
2813{
6031a61c
JR		 2814 u64 vm_cr;
2815
2816 rdmsrl(MSR_VM_CR, vm_cr);
2817 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2818 return 1;
2819
6aa8b732
AK		 2820 return 0;
2821}
2822
102d8325
IM		 2823static void
2824svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2825{
2826 /*
2827 * Patch in the VMMCALL instruction:
2828 */
2829 hypercall[0] = 0x0f;
2830 hypercall[1] = 0x01;
2831 hypercall[2] = 0xd9;
102d8325
IM		 2832}
2833
002c7f7c
YS		 2834static void svm_check_processor_compat(void *rtn)
2835{
2836 *(int *)rtn = 0;
2837}
2838
774ead3a
AK		 2839static bool svm_cpu_has_accelerated_tpr(void)
2840{
2841 return false;
2842}
2843
67253af5
SY		 2844static int get_npt_level(void)
2845{
2846#ifdef CONFIG_X86_64
2847 return PT64_ROOT_LEVEL;
2848#else
2849 return PT32E_ROOT_LEVEL;
2850#endif
2851}
2852
4b12f0de 2853static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 2854{
2855 return 0;
2856}
2857
0e851880
SY		 2858static void svm_cpuid_update(struct kvm_vcpu *vcpu)
2859{
2860}
2861
229456fc
MT		 2862static const struct trace_print_flags svm_exit_reasons_str[] = {
2863 { SVM_EXIT_READ_CR0, "read_cr0" },
2864 { SVM_EXIT_READ_CR3, "read_cr3" },
2865 { SVM_EXIT_READ_CR4, "read_cr4" },
2866 { SVM_EXIT_READ_CR8, "read_cr8" },
2867 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2868 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2869 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2870 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2871 { SVM_EXIT_READ_DR0, "read_dr0" },
2872 { SVM_EXIT_READ_DR1, "read_dr1" },
2873 { SVM_EXIT_READ_DR2, "read_dr2" },
2874 { SVM_EXIT_READ_DR3, "read_dr3" },
2875 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2876 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2877 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2878 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2879 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2880 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2881 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2882 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2883 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2884 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2885 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2886 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2887 { SVM_EXIT_INTR, "interrupt" },
2888 { SVM_EXIT_NMI, "nmi" },
2889 { SVM_EXIT_SMI, "smi" },
2890 { SVM_EXIT_INIT, "init" },
2891 { SVM_EXIT_VINTR, "vintr" },
2892 { SVM_EXIT_CPUID, "cpuid" },
2893 { SVM_EXIT_INVD, "invd" },
2894 { SVM_EXIT_HLT, "hlt" },
2895 { SVM_EXIT_INVLPG, "invlpg" },
2896 { SVM_EXIT_INVLPGA, "invlpga" },
2897 { SVM_EXIT_IOIO, "io" },
2898 { SVM_EXIT_MSR, "msr" },
2899 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2900 { SVM_EXIT_SHUTDOWN, "shutdown" },
2901 { SVM_EXIT_VMRUN, "vmrun" },
2902 { SVM_EXIT_VMMCALL, "hypercall" },
2903 { SVM_EXIT_VMLOAD, "vmload" },
2904 { SVM_EXIT_VMSAVE, "vmsave" },
2905 { SVM_EXIT_STGI, "stgi" },
2906 { SVM_EXIT_CLGI, "clgi" },
2907 { SVM_EXIT_SKINIT, "skinit" },
2908 { SVM_EXIT_WBINVD, "wbinvd" },
2909 { SVM_EXIT_MONITOR, "monitor" },
2910 { SVM_EXIT_MWAIT, "mwait" },
2911 { SVM_EXIT_NPF, "npf" },
2912 { -1, NULL }
2913};
2914
17cc3935 2915static int svm_get_lpage_level(void)
344f414f 2916{
17cc3935 2917 return PT_PDPE_LEVEL;
344f414f
JR		 2918}
2919
4e47c7a6
SY		 2920static bool svm_rdtscp_supported(void)
2921{
2922 return false;
2923}
2924
02daab21
AK		 2925static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
2926{
2927 struct vcpu_svm *svm = to_svm(vcpu);
2928
d225157b 2929 update_cr0_intercept(svm);
02daab21 2930 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
02daab21
AK		 2931}
2932
cbdd1bea 2933static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 2934 .cpu_has_kvm_support = has_svm,
2935 .disabled_by_bios = is_disabled,
2936 .hardware_setup = svm_hardware_setup,
2937 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 2938 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 2939 .hardware_enable = svm_hardware_enable,
2940 .hardware_disable = svm_hardware_disable,
774ead3a 2941 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 2942
2943 .vcpu_create = svm_create_vcpu,
2944 .vcpu_free = svm_free_vcpu,
04d2cc77 2945 .vcpu_reset = svm_vcpu_reset,
6aa8b732 2946
04d2cc77 2947 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 2948 .vcpu_load = svm_vcpu_load,
2949 .vcpu_put = svm_vcpu_put,
2950
2951 .set_guest_debug = svm_guest_debug,
2952 .get_msr = svm_get_msr,
2953 .set_msr = svm_set_msr,
2954 .get_segment_base = svm_get_segment_base,
2955 .get_segment = svm_get_segment,
2956 .set_segment = svm_set_segment,
2e4d2653 2957 .get_cpl = svm_get_cpl,
1747fb71 2958 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 2959 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 2960 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 2961 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 2962 .set_cr3 = svm_set_cr3,
2963 .set_cr4 = svm_set_cr4,
2964 .set_efer = svm_set_efer,
2965 .get_idt = svm_get_idt,
2966 .set_idt = svm_set_idt,
2967 .get_gdt = svm_get_gdt,
2968 .set_gdt = svm_set_gdt,
2969 .get_dr = svm_get_dr,
2970 .set_dr = svm_set_dr,
6de4f3ad 2971 .cache_reg = svm_cache_reg,
6aa8b732
AK		 2972 .get_rflags = svm_get_rflags,
2973 .set_rflags = svm_set_rflags,
02daab21 2974 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 2975
6aa8b732 2976 .tlb_flush = svm_flush_tlb,
6aa8b732 2977
6aa8b732 2978 .run = svm_vcpu_run,
04d2cc77 2979 .handle_exit = handle_exit,
6aa8b732 2980 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 2981 .set_interrupt_shadow = svm_set_interrupt_shadow,
2982 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 2983 .patch_hypercall = svm_patch_hypercall,
2a8067f1 2984 .set_irq = svm_set_irq,
95ba8273 2985 .set_nmi = svm_inject_nmi,
298101da 2986 .queue_exception = svm_queue_exception,
78646121 2987 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 2988 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 2989 .get_nmi_mask = svm_get_nmi_mask,
2990 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 2991 .enable_nmi_window = enable_nmi_window,
2992 .enable_irq_window = enable_irq_window,
2993 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 2994
2995 .set_tss_addr = svm_set_tss_addr,
67253af5 2996 .get_tdp_level = get_npt_level,
4b12f0de 2997 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 2998
2999 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3000 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3001
3002 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3003
3004 .rdtscp_supported = svm_rdtscp_supported,
6aa8b732
AK		 3005};
3006
3007static int __init svm_init(void)
3008{
cb498ea2 3009 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 3010 THIS_MODULE);
6aa8b732
AK		 3011}
3012
3013static void __exit svm_exit(void)
3014{
cb498ea2 3015 kvm_exit();
6aa8b732
AK		 3016}
3017
3018module_init(svm_init)
3019module_exit(svm_exit)
kernel source for telekom puls (alcatel/mediatek)