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KVM: SVM: Use svm_flush_tlb instead of force_new_asid
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
9611c187 7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
edf88417
AK		 17#include <linux/kvm_host.h>
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
5fdbf976 21#include "kvm_cache_regs.h"
fe4c7b19 22#include "x86.h"
e495606d 23
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/vmalloc.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
6aa8b732 31
67ec6607 32#include <asm/tlbflush.h>
e495606d 33#include <asm/desc.h>
631bc487 34#include <asm/kvm_para.h>
6aa8b732 35
63d1142f 36#include <asm/virtext.h>
229456fc 37#include "trace.h"
63d1142f 38
4ecac3fd
AK		 39#define __ex(x) __kvm_handle_fault_on_reboot(x)
40
6aa8b732
AK		 41MODULE_AUTHOR("Qumranet");
42MODULE_LICENSE("GPL");
43
44#define IOPM_ALLOC_ORDER 2
45#define MSRPM_ALLOC_ORDER 1
46
6aa8b732
AK		 47#define SEG_TYPE_LDT 2
48#define SEG_TYPE_BUSY_TSS16 3
49
6bc31bdc
AP		 50#define SVM_FEATURE_NPT (1 << 0)
51#define SVM_FEATURE_LBRV (1 << 1)
52#define SVM_FEATURE_SVML (1 << 2)
53#define SVM_FEATURE_NRIP (1 << 3)
54#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 55
410e4d57
JR		 56#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
59
24e09cbf
JR		 60#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
61
67ec6607
JR		 62static bool erratum_383_found __read_mostly;
63
6c8166a7
AK		 64static const u32 host_save_user_msrs[] = {
65#ifdef CONFIG_X86_64
66 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
67 MSR_FS_BASE,
68#endif
69 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
70};
71
72#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
73
74struct kvm_vcpu;
75
e6aa9abd
JR		 76struct nested_state {
77 struct vmcb *hsave;
78 u64 hsave_msr;
4a810181 79 u64 vm_cr_msr;
e6aa9abd
JR		 80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
ce2ac085 87 u64 vmcb_iopm;
aad42c64 88
cd3ff653
JR		 89 /* A VMEXIT is required but not yet emulated */
90 bool exit_required;
91
cda00082
JR		 92 /*
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
95 */
96 unsigned long vmexit_rip;
97 unsigned long vmexit_rsp;
98 unsigned long vmexit_rax;
99
aad42c64 100 /* cache for intercepts of the guest */
4ee546b4 101 u32 intercept_cr;
3aed041a 102 u32 intercept_dr;
aad42c64
JR		 103 u32 intercept_exceptions;
104 u64 intercept;
105
5bd2edc3
JR		 106 /* Nested Paging related state */
107 u64 nested_cr3;
e6aa9abd
JR		 108};
109
323c3d80
JR		 110#define MSRPM_OFFSETS 16
111static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
112
6c8166a7
AK		 113struct vcpu_svm {
114 struct kvm_vcpu vcpu;
115 struct vmcb *vmcb;
116 unsigned long vmcb_pa;
117 struct svm_cpu_data *svm_data;
118 uint64_t asid_generation;
119 uint64_t sysenter_esp;
120 uint64_t sysenter_eip;
121
122 u64 next_rip;
123
124 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
afe9e66f 125 struct {
dacccfdd
AK		 126 u16 fs;
127 u16 gs;
128 u16 ldt;
afe9e66f
AK		 129 u64 gs_base;
130 } host;
6c8166a7
AK		 131
132 u32 *msrpm;
6c8166a7 133
e6aa9abd 134 struct nested_state nested;
6be7d306
JK		 135
136 bool nmi_singlestep;
66b7138f
JK		 137
138 unsigned int3_injected;
139 unsigned long int3_rip;
631bc487 140 u32 apf_reason;
6c8166a7
AK		 141};
142
455716fa
JR		 143#define MSR_INVALID 0xffffffffU
144
ac72a9b7
JR		 145static struct svm_direct_access_msrs {
146 u32 index; /* Index of the MSR */
147 bool always; /* True if intercept is always on */
148} direct_access_msrs[] = {
8c06585d 149 { .index = MSR_STAR, .always = true },
ac72a9b7
JR		 150 { .index = MSR_IA32_SYSENTER_CS, .always = true },
151#ifdef CONFIG_X86_64
152 { .index = MSR_GS_BASE, .always = true },
153 { .index = MSR_FS_BASE, .always = true },
154 { .index = MSR_KERNEL_GS_BASE, .always = true },
155 { .index = MSR_LSTAR, .always = true },
156 { .index = MSR_CSTAR, .always = true },
157 { .index = MSR_SYSCALL_MASK, .always = true },
158#endif
159 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
160 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
161 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
162 { .index = MSR_IA32_LASTINTTOIP, .always = false },
163 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 164};
165
709ddebf
JR		 166/* enable NPT for AMD64 and X86 with PAE */
167#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
168static bool npt_enabled = true;
169#else
e0231715 170static bool npt_enabled;
709ddebf 171#endif
6c7dac72
JR		 172static int npt = 1;
173
174module_param(npt, int, S_IRUGO);
e3da3acd 175
4b6e4dca 176static int nested = 1;
236de055
AG		 177module_param(nested, int, S_IRUGO);
178
44874f84 179static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 180static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 181
410e4d57 182static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 183static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 184static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 185static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
186 bool has_error_code, u32 error_code);
187
8d28fec4 188enum {
116a0a23
JR		 189 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
190 pause filter count */
f56838e4 191 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
d48086d1 192 VMCB_ASID, /* ASID */
decdbf6a 193 VMCB_INTR, /* int_ctl, int_vector */
b2747166 194 VMCB_NPT, /* npt_en, nCR3, gPAT */
dcca1a65 195 VMCB_CR, /* CR0, CR3, CR4, EFER */
72214b96 196 VMCB_DR, /* DR6, DR7 */
17a703cb 197 VMCB_DT, /* GDT, IDT */
060d0c9a 198 VMCB_SEG, /* CS, DS, SS, ES, CPL */
0574dec0 199 VMCB_CR2, /* CR2 only */
b53ba3f9 200 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
8d28fec4
RJ		 201 VMCB_DIRTY_MAX,
202};
203
0574dec0
JR		 204/* TPR and CR2 are always written before VMRUN */
205#define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
8d28fec4
RJ		 206
207static inline void mark_all_dirty(struct vmcb *vmcb)
208{
209 vmcb->control.clean = 0;
210}
211
212static inline void mark_all_clean(struct vmcb *vmcb)
213{
214 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
215 & ~VMCB_ALWAYS_DIRTY_MASK;
216}
217
218static inline void mark_dirty(struct vmcb *vmcb, int bit)
219{
220 vmcb->control.clean &= ~(1 << bit);
221}
222
a2fa3e9f
GH		 223static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
224{
fb3f0f51 225 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 226}
227
384c6368
JR		 228static void recalc_intercepts(struct vcpu_svm *svm)
229{
230 struct vmcb_control_area *c, *h;
231 struct nested_state *g;
232
116a0a23
JR		 233 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
234
384c6368
JR		 235 if (!is_guest_mode(&svm->vcpu))
236 return;
237
238 c = &svm->vmcb->control;
239 h = &svm->nested.hsave->control;
240 g = &svm->nested;
241
4ee546b4 242 c->intercept_cr = h->intercept_cr | g->intercept_cr;
3aed041a 243 c->intercept_dr = h->intercept_dr | g->intercept_dr;
384c6368
JR		 244 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
245 c->intercept = h->intercept | g->intercept;
246}
247
4ee546b4
RJ		 248static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
249{
250 if (is_guest_mode(&svm->vcpu))
251 return svm->nested.hsave;
252 else
253 return svm->vmcb;
254}
255
256static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
257{
258 struct vmcb *vmcb = get_host_vmcb(svm);
259
260 vmcb->control.intercept_cr |= (1U << bit);
261
262 recalc_intercepts(svm);
263}
264
265static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
266{
267 struct vmcb *vmcb = get_host_vmcb(svm);
268
269 vmcb->control.intercept_cr &= ~(1U << bit);
270
271 recalc_intercepts(svm);
272}
273
274static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
275{
276 struct vmcb *vmcb = get_host_vmcb(svm);
277
278 return vmcb->control.intercept_cr & (1U << bit);
279}
280
3aed041a
JR		 281static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
282{
283 struct vmcb *vmcb = get_host_vmcb(svm);
284
285 vmcb->control.intercept_dr |= (1U << bit);
286
287 recalc_intercepts(svm);
288}
289
290static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
291{
292 struct vmcb *vmcb = get_host_vmcb(svm);
293
294 vmcb->control.intercept_dr &= ~(1U << bit);
295
296 recalc_intercepts(svm);
297}
298
18c918c5
JR		 299static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
300{
301 struct vmcb *vmcb = get_host_vmcb(svm);
302
303 vmcb->control.intercept_exceptions |= (1U << bit);
304
305 recalc_intercepts(svm);
306}
307
308static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
309{
310 struct vmcb *vmcb = get_host_vmcb(svm);
311
312 vmcb->control.intercept_exceptions &= ~(1U << bit);
313
314 recalc_intercepts(svm);
315}
316
8a05a1b8
JR		 317static inline void set_intercept(struct vcpu_svm *svm, int bit)
318{
319 struct vmcb *vmcb = get_host_vmcb(svm);
320
321 vmcb->control.intercept |= (1ULL << bit);
322
323 recalc_intercepts(svm);
324}
325
326static inline void clr_intercept(struct vcpu_svm *svm, int bit)
327{
328 struct vmcb *vmcb = get_host_vmcb(svm);
329
330 vmcb->control.intercept &= ~(1ULL << bit);
331
332 recalc_intercepts(svm);
333}
334
2af9194d
JR		 335static inline void enable_gif(struct vcpu_svm *svm)
336{
337 svm->vcpu.arch.hflags |= HF_GIF_MASK;
338}
339
340static inline void disable_gif(struct vcpu_svm *svm)
341{
342 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
343}
344
345static inline bool gif_set(struct vcpu_svm *svm)
346{
347 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
348}
349
4866d5e3 350static unsigned long iopm_base;
6aa8b732
AK		 351
352struct kvm_ldttss_desc {
353 u16 limit0;
354 u16 base0;
e0231715
JR		 355 unsigned base1:8, type:5, dpl:2, p:1;
356 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 357 u32 base3;
358 u32 zero1;
359} __attribute__((packed));
360
361struct svm_cpu_data {
362 int cpu;
363
5008fdf5
AK		 364 u64 asid_generation;
365 u32 max_asid;
366 u32 next_asid;
6aa8b732
AK		 367 struct kvm_ldttss_desc *tss_desc;
368
369 struct page *save_area;
370};
371
372static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 373static uint32_t svm_features;
6aa8b732
AK		 374
375struct svm_init_data {
376 int cpu;
377 int r;
378};
379
380static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
381
9d8f549d 382#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 383#define MSRS_RANGE_SIZE 2048
384#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
385
455716fa
JR		 386static u32 svm_msrpm_offset(u32 msr)
387{
388 u32 offset;
389 int i;
390
391 for (i = 0; i < NUM_MSR_MAPS; i++) {
392 if (msr < msrpm_ranges[i] ||
393 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
394 continue;
395
396 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
397 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
398
399 /* Now we have the u8 offset - but need the u32 offset */
400 return offset / 4;
401 }
402
403 /* MSR not in any range */
404 return MSR_INVALID;
405}
406
6aa8b732
AK		 407#define MAX_INST_SIZE 15
408
6aa8b732
AK		 409static inline void clgi(void)
410{
4ecac3fd 411 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 412}
413
414static inline void stgi(void)
415{
4ecac3fd 416 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 417}
418
419static inline void invlpga(unsigned long addr, u32 asid)
420{
e0231715 421 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 422}
423
4b16184c
JR		 424static int get_npt_level(void)
425{
426#ifdef CONFIG_X86_64
427 return PT64_ROOT_LEVEL;
428#else
429 return PT32E_ROOT_LEVEL;
430#endif
431}
432
6aa8b732
AK		 433static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
434{
6dc696d4 435 vcpu->arch.efer = efer;
709ddebf 436 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 437 efer &= ~EFER_LME;
6aa8b732 438
9962d032 439 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
dcca1a65 440 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
6aa8b732
AK		 441}
442
6aa8b732
AK		 443static int is_external_interrupt(u32 info)
444{
445 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
446 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
447}
448
2809f5d2
GC		 449static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
450{
451 struct vcpu_svm *svm = to_svm(vcpu);
452 u32 ret = 0;
453
454 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 455 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 456 return ret & mask;
457}
458
459static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
460{
461 struct vcpu_svm *svm = to_svm(vcpu);
462
463 if (mask == 0)
464 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
465 else
466 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
467
468}
469
6aa8b732
AK		 470static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
471{
a2fa3e9f
GH		 472 struct vcpu_svm *svm = to_svm(vcpu);
473
6bc31bdc
AP		 474 if (svm->vmcb->control.next_rip != 0)
475 svm->next_rip = svm->vmcb->control.next_rip;
476
a2fa3e9f 477 if (!svm->next_rip) {
851ba692 478 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 479 EMULATE_DONE)
480 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 481 return;
482 }
5fdbf976
MT		 483 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
484 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
485 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 486
5fdbf976 487 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 488 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 489}
490
116a4752 491static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 492 bool has_error_code, u32 error_code,
493 bool reinject)
116a4752
JK		 494{
495 struct vcpu_svm *svm = to_svm(vcpu);
496
e0231715
JR		 497 /*
498 * If we are within a nested VM we'd better #VMEXIT and let the guest
499 * handle the exception
500 */
ce7ddec4
JR		 501 if (!reinject &&
502 nested_svm_check_exception(svm, nr, has_error_code, error_code))
116a4752
JK		 503 return;
504
2a6b20b8 505 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
66b7138f
JK		 506 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
507
508 /*
509 * For guest debugging where we have to reinject #BP if some
510 * INT3 is guest-owned:
511 * Emulate nRIP by moving RIP forward. Will fail if injection
512 * raises a fault that is not intercepted. Still better than
513 * failing in all cases.
514 */
515 skip_emulated_instruction(&svm->vcpu);
516 rip = kvm_rip_read(&svm->vcpu);
517 svm->int3_rip = rip + svm->vmcb->save.cs.base;
518 svm->int3_injected = rip - old_rip;
519 }
520
116a4752
JK		 521 svm->vmcb->control.event_inj = nr
522 | SVM_EVTINJ_VALID
523 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
524 | SVM_EVTINJ_TYPE_EXEPT;
525 svm->vmcb->control.event_inj_err = error_code;
526}
527
67ec6607
JR		 528static void svm_init_erratum_383(void)
529{
530 u32 low, high;
531 int err;
532 u64 val;
533
1be85a6d 534 if (!cpu_has_amd_erratum(amd_erratum_383))
67ec6607
JR		 535 return;
536
537 /* Use _safe variants to not break nested virtualization */
538 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
539 if (err)
540 return;
541
542 val |= (1ULL << 47);
543
544 low = lower_32_bits(val);
545 high = upper_32_bits(val);
546
547 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
548
549 erratum_383_found = true;
550}
551
6aa8b732
AK		 552static int has_svm(void)
553{
63d1142f 554 const char *msg;
6aa8b732 555
63d1142f 556 if (!cpu_has_svm(&msg)) {
ff81ff10 557 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 558 return 0;
559 }
560
6aa8b732
AK		 561 return 1;
562}
563
564static void svm_hardware_disable(void *garbage)
565{
2c8dceeb 566 cpu_svm_disable();
6aa8b732
AK		 567}
568
10474ae8 569static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 570{
571
0fe1e009 572 struct svm_cpu_data *sd;
6aa8b732 573 uint64_t efer;
89a27f4d 574 struct desc_ptr gdt_descr;
6aa8b732
AK		 575 struct desc_struct *gdt;
576 int me = raw_smp_processor_id();
577
10474ae8
AG		 578 rdmsrl(MSR_EFER, efer);
579 if (efer & EFER_SVME)
580 return -EBUSY;
581
6aa8b732 582 if (!has_svm()) {
e6732a5a
ZA		 583 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
584 me);
10474ae8 585 return -EINVAL;
6aa8b732 586 }
0fe1e009 587 sd = per_cpu(svm_data, me);
6aa8b732 588
0fe1e009 589 if (!sd) {
e6732a5a 590 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 591 me);
10474ae8 592 return -EINVAL;
6aa8b732
AK		 593 }
594
0fe1e009
TH		 595 sd->asid_generation = 1;
596 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
597 sd->next_asid = sd->max_asid + 1;
6aa8b732 598
d6ab1ed4 599 native_store_gdt(&gdt_descr);
89a27f4d 600 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 601 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 602
9962d032 603 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 604
d0316554 605 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8 606
67ec6607
JR		 607 svm_init_erratum_383();
608
10474ae8 609 return 0;
6aa8b732
AK		 610}
611
0da1db75
JR		 612static void svm_cpu_uninit(int cpu)
613{
0fe1e009 614 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 615
0fe1e009 616 if (!sd)
0da1db75
JR		 617 return;
618
619 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 620 __free_page(sd->save_area);
621 kfree(sd);
0da1db75
JR		 622}
623
6aa8b732
AK		 624static int svm_cpu_init(int cpu)
625{
0fe1e009 626 struct svm_cpu_data *sd;
6aa8b732
AK		 627 int r;
628
0fe1e009
TH		 629 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
630 if (!sd)
6aa8b732 631 return -ENOMEM;
0fe1e009
TH		 632 sd->cpu = cpu;
633 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 634 r = -ENOMEM;
0fe1e009 635 if (!sd->save_area)
6aa8b732
AK		 636 goto err_1;
637
0fe1e009 638 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 639
640 return 0;
641
642err_1:
0fe1e009 643 kfree(sd);
6aa8b732
AK		 644 return r;
645
646}
647
ac72a9b7
JR		 648static bool valid_msr_intercept(u32 index)
649{
650 int i;
651
652 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
653 if (direct_access_msrs[i].index == index)
654 return true;
655
656 return false;
657}
658
bfc733a7
RR		 659static void set_msr_interception(u32 *msrpm, unsigned msr,
660 int read, int write)
6aa8b732 661{
455716fa
JR		 662 u8 bit_read, bit_write;
663 unsigned long tmp;
664 u32 offset;
6aa8b732 665
ac72a9b7
JR		 666 /*
667 * If this warning triggers extend the direct_access_msrs list at the
668 * beginning of the file
669 */
670 WARN_ON(!valid_msr_intercept(msr));
671
455716fa
JR		 672 offset = svm_msrpm_offset(msr);
673 bit_read = 2 * (msr & 0x0f);
674 bit_write = 2 * (msr & 0x0f) + 1;
675 tmp = msrpm[offset];
676
677 BUG_ON(offset == MSR_INVALID);
678
679 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
680 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
681
682 msrpm[offset] = tmp;
6aa8b732
AK		 683}
684
f65c229c 685static void svm_vcpu_init_msrpm(u32 *msrpm)
6aa8b732
AK		 686{
687 int i;
688
f65c229c
JR		 689 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
690
ac72a9b7
JR		 691 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
692 if (!direct_access_msrs[i].always)
693 continue;
694
695 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
696 }
f65c229c
JR		 697}
698
323c3d80
JR		 699static void add_msr_offset(u32 offset)
700{
701 int i;
702
703 for (i = 0; i < MSRPM_OFFSETS; ++i) {
704
705 /* Offset already in list? */
706 if (msrpm_offsets[i] == offset)
bfc733a7 707 return;
323c3d80
JR		 708
709 /* Slot used by another offset? */
710 if (msrpm_offsets[i] != MSR_INVALID)
711 continue;
712
713 /* Add offset to list */
714 msrpm_offsets[i] = offset;
715
716 return;
6aa8b732 717 }
323c3d80
JR		 718
719 /*
720 * If this BUG triggers the msrpm_offsets table has an overflow. Just
721 * increase MSRPM_OFFSETS in this case.
722 */
bfc733a7 723 BUG();
6aa8b732
AK		 724}
725
323c3d80 726static void init_msrpm_offsets(void)
f65c229c 727{
323c3d80 728 int i;
f65c229c 729
323c3d80
JR		 730 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
731
732 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
733 u32 offset;
734
735 offset = svm_msrpm_offset(direct_access_msrs[i].index);
736 BUG_ON(offset == MSR_INVALID);
737
738 add_msr_offset(offset);
739 }
f65c229c
JR		 740}
741
24e09cbf
JR		 742static void svm_enable_lbrv(struct vcpu_svm *svm)
743{
744 u32 *msrpm = svm->msrpm;
745
746 svm->vmcb->control.lbr_ctl = 1;
747 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
748 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
749 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
750 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
751}
752
753static void svm_disable_lbrv(struct vcpu_svm *svm)
754{
755 u32 *msrpm = svm->msrpm;
756
757 svm->vmcb->control.lbr_ctl = 0;
758 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
759 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
760 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
761 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
762}
763
6aa8b732
AK		 764static __init int svm_hardware_setup(void)
765{
766 int cpu;
767 struct page *iopm_pages;
f65c229c 768 void *iopm_va;
6aa8b732
AK		 769 int r;
770
6aa8b732
AK		 771 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
772
773 if (!iopm_pages)
774 return -ENOMEM;
c8681339
AL		 775
776 iopm_va = page_address(iopm_pages);
777 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 778 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
779
323c3d80
JR		 780 init_msrpm_offsets();
781
50a37eb4
JR		 782 if (boot_cpu_has(X86_FEATURE_NX))
783 kvm_enable_efer_bits(EFER_NX);
784
1b2fd70c
AG		 785 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
786 kvm_enable_efer_bits(EFER_FFXSR);
787
236de055
AG		 788 if (nested) {
789 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
eec4b140 790 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
236de055
AG		 791 }
792
3230bb47 793 for_each_possible_cpu(cpu) {
6aa8b732
AK		 794 r = svm_cpu_init(cpu);
795 if (r)
f65c229c 796 goto err;
6aa8b732 797 }
33bd6a0b
JR		 798
799 svm_features = cpuid_edx(SVM_CPUID_FUNC);
800
2a6b20b8 801 if (!boot_cpu_has(X86_FEATURE_NPT))
e3da3acd
JR		 802 npt_enabled = false;
803
6c7dac72
JR		 804 if (npt_enabled && !npt) {
805 printk(KERN_INFO "kvm: Nested Paging disabled\n");
806 npt_enabled = false;
807 }
808
18552672 809 if (npt_enabled) {
e3da3acd 810 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 811 kvm_enable_tdp();
5f4cb662
JR		 812 } else
813 kvm_disable_tdp();
e3da3acd 814
6aa8b732
AK		 815 return 0;
816
f65c229c 817err:
6aa8b732
AK		 818 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
819 iopm_base = 0;
820 return r;
821}
822
823static __exit void svm_hardware_unsetup(void)
824{
0da1db75
JR		 825 int cpu;
826
3230bb47 827 for_each_possible_cpu(cpu)
0da1db75
JR		 828 svm_cpu_uninit(cpu);
829
6aa8b732 830 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 831 iopm_base = 0;
6aa8b732
AK		 832}
833
834static void init_seg(struct vmcb_seg *seg)
835{
836 seg->selector = 0;
837 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 838 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 839 seg->limit = 0xffff;
840 seg->base = 0;
841}
842
843static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
844{
845 seg->selector = 0;
846 seg->attrib = SVM_SELECTOR_P_MASK | type;
847 seg->limit = 0xffff;
848 seg->base = 0;
849}
850
f4e1b3c8
ZA		 851static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
852{
853 struct vcpu_svm *svm = to_svm(vcpu);
854 u64 g_tsc_offset = 0;
855
2030753d 856 if (is_guest_mode(vcpu)) {
f4e1b3c8
ZA		 857 g_tsc_offset = svm->vmcb->control.tsc_offset -
858 svm->nested.hsave->control.tsc_offset;
859 svm->nested.hsave->control.tsc_offset = offset;
860 }
861
862 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
116a0a23
JR		 863
864 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
f4e1b3c8
ZA		 865}
866
e48672fa
ZA		 867static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
868{
869 struct vcpu_svm *svm = to_svm(vcpu);
870
871 svm->vmcb->control.tsc_offset += adjustment;
2030753d 872 if (is_guest_mode(vcpu))
e48672fa 873 svm->nested.hsave->control.tsc_offset += adjustment;
116a0a23 874 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
e48672fa
ZA		 875}
876
e6101a96 877static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 878{
e6101a96
JR		 879 struct vmcb_control_area *control = &svm->vmcb->control;
880 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 881
bff78274 882 svm->vcpu.fpu_active = 1;
4ee546b4 883 svm->vcpu.arch.hflags = 0;
bff78274 884
4ee546b4
RJ		 885 set_cr_intercept(svm, INTERCEPT_CR0_READ);
886 set_cr_intercept(svm, INTERCEPT_CR3_READ);
887 set_cr_intercept(svm, INTERCEPT_CR4_READ);
888 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
889 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
890 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
891 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
6aa8b732 892
3aed041a
JR		 893 set_dr_intercept(svm, INTERCEPT_DR0_READ);
894 set_dr_intercept(svm, INTERCEPT_DR1_READ);
895 set_dr_intercept(svm, INTERCEPT_DR2_READ);
896 set_dr_intercept(svm, INTERCEPT_DR3_READ);
897 set_dr_intercept(svm, INTERCEPT_DR4_READ);
898 set_dr_intercept(svm, INTERCEPT_DR5_READ);
899 set_dr_intercept(svm, INTERCEPT_DR6_READ);
900 set_dr_intercept(svm, INTERCEPT_DR7_READ);
901
902 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
903 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
904 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
905 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
906 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
907 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
908 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
909 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
6aa8b732 910
18c918c5
JR		 911 set_exception_intercept(svm, PF_VECTOR);
912 set_exception_intercept(svm, UD_VECTOR);
913 set_exception_intercept(svm, MC_VECTOR);
6aa8b732 914
8a05a1b8
JR		 915 set_intercept(svm, INTERCEPT_INTR);
916 set_intercept(svm, INTERCEPT_NMI);
917 set_intercept(svm, INTERCEPT_SMI);
918 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
919 set_intercept(svm, INTERCEPT_CPUID);
920 set_intercept(svm, INTERCEPT_INVD);
921 set_intercept(svm, INTERCEPT_HLT);
922 set_intercept(svm, INTERCEPT_INVLPG);
923 set_intercept(svm, INTERCEPT_INVLPGA);
924 set_intercept(svm, INTERCEPT_IOIO_PROT);
925 set_intercept(svm, INTERCEPT_MSR_PROT);
926 set_intercept(svm, INTERCEPT_TASK_SWITCH);
927 set_intercept(svm, INTERCEPT_SHUTDOWN);
928 set_intercept(svm, INTERCEPT_VMRUN);
929 set_intercept(svm, INTERCEPT_VMMCALL);
930 set_intercept(svm, INTERCEPT_VMLOAD);
931 set_intercept(svm, INTERCEPT_VMSAVE);
932 set_intercept(svm, INTERCEPT_STGI);
933 set_intercept(svm, INTERCEPT_CLGI);
934 set_intercept(svm, INTERCEPT_SKINIT);
935 set_intercept(svm, INTERCEPT_WBINVD);
936 set_intercept(svm, INTERCEPT_MONITOR);
937 set_intercept(svm, INTERCEPT_MWAIT);
6aa8b732
AK		 938
939 control->iopm_base_pa = iopm_base;
f65c229c 940 control->msrpm_base_pa = __pa(svm->msrpm);
6aa8b732
AK		 941 control->int_ctl = V_INTR_MASKING_MASK;
942
943 init_seg(&save->es);
944 init_seg(&save->ss);
945 init_seg(&save->ds);
946 init_seg(&save->fs);
947 init_seg(&save->gs);
948
949 save->cs.selector = 0xf000;
950 /* Executable/Readable Code Segment */
951 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
952 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
953 save->cs.limit = 0xffff;
d92899a0
AK		 954 /*
955 * cs.base should really be 0xffff0000, but vmx can't handle that, so
956 * be consistent with it.
957 *
958 * Replace when we have real mode working for vmx.
959 */
960 save->cs.base = 0xf0000;
6aa8b732
AK		 961
962 save->gdtr.limit = 0xffff;
963 save->idtr.limit = 0xffff;
964
965 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
966 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
967
eaa48512 968 svm_set_efer(&svm->vcpu, 0);
d77c26fc 969 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 970 save->dr7 = 0x400;
971 save->rflags = 2;
972 save->rip = 0x0000fff0;
5fdbf976 973 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 974
e0231715
JR		 975 /*
976 * This is the guest-visible cr0 value.
18fa000a 977 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 978 */
678041ad
MT		 979 svm->vcpu.arch.cr0 = 0;
980 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
18fa000a 981
66aee91a 982 save->cr4 = X86_CR4_PAE;
6aa8b732 983 /* rdx = ?? */
709ddebf
JR		 984
985 if (npt_enabled) {
986 /* Setup VMCB for Nested Paging */
987 control->nested_ctl = 1;
8a05a1b8
JR		 988 clr_intercept(svm, INTERCEPT_TASK_SWITCH);
989 clr_intercept(svm, INTERCEPT_INVLPG);
18c918c5 990 clr_exception_intercept(svm, PF_VECTOR);
4ee546b4
RJ		 991 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
992 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
709ddebf 993 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 994 save->cr3 = 0;
995 save->cr4 = 0;
996 }
f40f6a45 997 svm->asid_generation = 0;
1371d904 998
e6aa9abd 999 svm->nested.vmcb = 0;
2af9194d
JR		 1000 svm->vcpu.arch.hflags = 0;
1001
2a6b20b8 1002 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
565d0998 1003 control->pause_filter_count = 3000;
8a05a1b8 1004 set_intercept(svm, INTERCEPT_PAUSE);
565d0998
ML		 1005 }
1006
8d28fec4
RJ		 1007 mark_all_dirty(svm->vmcb);
1008
2af9194d 1009 enable_gif(svm);
6aa8b732
AK		 1010}
1011
e00c8cf2 1012static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 1013{
1014 struct vcpu_svm *svm = to_svm(vcpu);
1015
e6101a96 1016 init_vmcb(svm);
70433389 1017
c5af89b6 1018 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 1019 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 1020 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1021 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 1022 }
5fdbf976
MT		 1023 vcpu->arch.regs_avail = ~0;
1024 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 1025
1026 return 0;
04d2cc77
AK		 1027}
1028
fb3f0f51 1029static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 1030{
a2fa3e9f 1031 struct vcpu_svm *svm;
6aa8b732 1032 struct page *page;
f65c229c 1033 struct page *msrpm_pages;
b286d5d8 1034 struct page *hsave_page;
3d6368ef 1035 struct page *nested_msrpm_pages;
fb3f0f51 1036 int err;
6aa8b732 1037
c16f862d 1038 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 1039 if (!svm) {
1040 err = -ENOMEM;
1041 goto out;
1042 }
1043
1044 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1045 if (err)
1046 goto free_svm;
1047
b7af4043 1048 err = -ENOMEM;
6aa8b732 1049 page = alloc_page(GFP_KERNEL);
b7af4043 1050 if (!page)
fb3f0f51 1051 goto uninit;
6aa8b732 1052
f65c229c
JR		 1053 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1054 if (!msrpm_pages)
b7af4043 1055 goto free_page1;
3d6368ef
AG		 1056
1057 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1058 if (!nested_msrpm_pages)
b7af4043 1059 goto free_page2;
f65c229c 1060
b286d5d8
AG		 1061 hsave_page = alloc_page(GFP_KERNEL);
1062 if (!hsave_page)
b7af4043
TY		 1063 goto free_page3;
1064
e6aa9abd 1065 svm->nested.hsave = page_address(hsave_page);
b286d5d8 1066
b7af4043
TY		 1067 svm->msrpm = page_address(msrpm_pages);
1068 svm_vcpu_init_msrpm(svm->msrpm);
1069
e6aa9abd 1070 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 1071 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 1072
a2fa3e9f
GH		 1073 svm->vmcb = page_address(page);
1074 clear_page(svm->vmcb);
1075 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1076 svm->asid_generation = 0;
e6101a96 1077 init_vmcb(svm);
99e3e30a 1078 kvm_write_tsc(&svm->vcpu, 0);
a2fa3e9f 1079
10ab25cd
JK		 1080 err = fx_init(&svm->vcpu);
1081 if (err)
1082 goto free_page4;
1083
ad312c7c 1084 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 1085 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 1086 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 1087
fb3f0f51 1088 return &svm->vcpu;
36241b8c 1089
10ab25cd
JK		 1090free_page4:
1091 __free_page(hsave_page);
b7af4043
TY		 1092free_page3:
1093 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1094free_page2:
1095 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1096free_page1:
1097 __free_page(page);
fb3f0f51
RR		 1098uninit:
1099 kvm_vcpu_uninit(&svm->vcpu);
1100free_svm:
a4770347 1101 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 1102out:
1103 return ERR_PTR(err);
6aa8b732
AK		 1104}
1105
1106static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1107{
a2fa3e9f
GH		 1108 struct vcpu_svm *svm = to_svm(vcpu);
1109
fb3f0f51 1110 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 1111 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 1112 __free_page(virt_to_page(svm->nested.hsave));
1113 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 1114 kvm_vcpu_uninit(vcpu);
a4770347 1115 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 1116}
1117
15ad7146 1118static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1119{
a2fa3e9f 1120 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 1121 int i;
0cc5064d 1122
0cc5064d 1123 if (unlikely(cpu != vcpu->cpu)) {
4b656b12 1124 svm->asid_generation = 0;
8d28fec4 1125 mark_all_dirty(svm->vmcb);
0cc5064d 1126 }
94dfbdb3 1127
82ca2d10
AK		 1128#ifdef CONFIG_X86_64
1129 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1130#endif
dacccfdd
AK		 1131 savesegment(fs, svm->host.fs);
1132 savesegment(gs, svm->host.gs);
1133 svm->host.ldt = kvm_read_ldt();
1134
94dfbdb3 1135 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1136 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 1137}
1138
1139static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1140{
a2fa3e9f 1141 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 1142 int i;
1143
e1beb1d3 1144 ++vcpu->stat.host_state_reload;
dacccfdd
AK		 1145 kvm_load_ldt(svm->host.ldt);
1146#ifdef CONFIG_X86_64
1147 loadsegment(fs, svm->host.fs);
1148 load_gs_index(svm->host.gs);
1149 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1150#else
1151 loadsegment(gs, svm->host.gs);
1152#endif
94dfbdb3 1153 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1154 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 1155}
1156
6aa8b732
AK		 1157static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1158{
a2fa3e9f 1159 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 1160}
1161
1162static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1163{
a2fa3e9f 1164 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 1165}
1166
6de4f3ad
AK		 1167static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1168{
1169 switch (reg) {
1170 case VCPU_EXREG_PDPTR:
1171 BUG_ON(!npt_enabled);
ff03a073 1172 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
6de4f3ad
AK		 1173 break;
1174 default:
1175 BUG();
1176 }
1177}
1178
f0b85051
AG		 1179static void svm_set_vintr(struct vcpu_svm *svm)
1180{
8a05a1b8 1181 set_intercept(svm, INTERCEPT_VINTR);
f0b85051
AG		 1182}
1183
1184static void svm_clear_vintr(struct vcpu_svm *svm)
1185{
8a05a1b8 1186 clr_intercept(svm, INTERCEPT_VINTR);
f0b85051
AG		 1187}
1188
6aa8b732
AK		 1189static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1190{
a2fa3e9f 1191 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 1192
1193 switch (seg) {
1194 case VCPU_SREG_CS: return &save->cs;
1195 case VCPU_SREG_DS: return &save->ds;
1196 case VCPU_SREG_ES: return &save->es;
1197 case VCPU_SREG_FS: return &save->fs;
1198 case VCPU_SREG_GS: return &save->gs;
1199 case VCPU_SREG_SS: return &save->ss;
1200 case VCPU_SREG_TR: return &save->tr;
1201 case VCPU_SREG_LDTR: return &save->ldtr;
1202 }
1203 BUG();
8b6d44c7 1204 return NULL;
6aa8b732
AK		 1205}
1206
1207static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1208{
1209 struct vmcb_seg *s = svm_seg(vcpu, seg);
1210
1211 return s->base;
1212}
1213
1214static void svm_get_segment(struct kvm_vcpu *vcpu,
1215 struct kvm_segment *var, int seg)
1216{
1217 struct vmcb_seg *s = svm_seg(vcpu, seg);
1218
1219 var->base = s->base;
1220 var->limit = s->limit;
1221 var->selector = s->selector;
1222 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1223 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1224 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1225 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1226 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1227 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1228 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1229 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 1230
e0231715
JR		 1231 /*
1232 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1233 * for cross vendor migration purposes by "not present"
1234 */
1235 var->unusable = !var->present || (var->type == 0);
1236
1fbdc7a5
AP		 1237 switch (seg) {
1238 case VCPU_SREG_CS:
1239 /*
1240 * SVM always stores 0 for the 'G' bit in the CS selector in
1241 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1242 * Intel's VMENTRY has a check on the 'G' bit.
1243 */
25022acc 1244 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 1245 break;
1246 case VCPU_SREG_TR:
1247 /*
1248 * Work around a bug where the busy flag in the tr selector
1249 * isn't exposed
1250 */
c0d09828 1251 var->type |= 0x2;
1fbdc7a5
AP		 1252 break;
1253 case VCPU_SREG_DS:
1254 case VCPU_SREG_ES:
1255 case VCPU_SREG_FS:
1256 case VCPU_SREG_GS:
1257 /*
1258 * The accessed bit must always be set in the segment
1259 * descriptor cache, although it can be cleared in the
1260 * descriptor, the cached bit always remains at 1. Since
1261 * Intel has a check on this, set it here to support
1262 * cross-vendor migration.
1263 */
1264 if (!var->unusable)
1265 var->type |= 0x1;
1266 break;
b586eb02 1267 case VCPU_SREG_SS:
e0231715
JR		 1268 /*
1269 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1270 * descriptor is left as 1, although the whole segment has
1271 * been made unusable. Clear it here to pass an Intel VMX
1272 * entry check when cross vendor migrating.
1273 */
1274 if (var->unusable)
1275 var->db = 0;
1276 break;
1fbdc7a5 1277 }
6aa8b732
AK		 1278}
1279
2e4d2653
IE		 1280static int svm_get_cpl(struct kvm_vcpu *vcpu)
1281{
1282 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1283
1284 return save->cpl;
1285}
1286
89a27f4d 1287static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1288{
a2fa3e9f
GH		 1289 struct vcpu_svm *svm = to_svm(vcpu);
1290
89a27f4d
GN		 1291 dt->size = svm->vmcb->save.idtr.limit;
1292 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1293}
1294
89a27f4d 1295static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1296{
a2fa3e9f
GH		 1297 struct vcpu_svm *svm = to_svm(vcpu);
1298
89a27f4d
GN		 1299 svm->vmcb->save.idtr.limit = dt->size;
1300 svm->vmcb->save.idtr.base = dt->address ;
17a703cb 1301 mark_dirty(svm->vmcb, VMCB_DT);
6aa8b732
AK		 1302}
1303
89a27f4d 1304static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1305{
a2fa3e9f
GH		 1306 struct vcpu_svm *svm = to_svm(vcpu);
1307
89a27f4d
GN		 1308 dt->size = svm->vmcb->save.gdtr.limit;
1309 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1310}
1311
89a27f4d 1312static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1313{
a2fa3e9f
GH		 1314 struct vcpu_svm *svm = to_svm(vcpu);
1315
89a27f4d
GN		 1316 svm->vmcb->save.gdtr.limit = dt->size;
1317 svm->vmcb->save.gdtr.base = dt->address ;
17a703cb 1318 mark_dirty(svm->vmcb, VMCB_DT);
6aa8b732
AK		 1319}
1320
e8467fda
AK		 1321static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1322{
1323}
1324
25c4c276 1325static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1326{
1327}
1328
d225157b
AK		 1329static void update_cr0_intercept(struct vcpu_svm *svm)
1330{
1331 ulong gcr0 = svm->vcpu.arch.cr0;
1332 u64 *hcr0 = &svm->vmcb->save.cr0;
1333
1334 if (!svm->vcpu.fpu_active)
1335 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1336 else
1337 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1338 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1339
dcca1a65 1340 mark_dirty(svm->vmcb, VMCB_CR);
d225157b
AK		 1341
1342 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
4ee546b4
RJ		 1343 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1344 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
d225157b 1345 } else {
4ee546b4
RJ		 1346 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1347 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
d225157b
AK		 1348 }
1349}
1350
6aa8b732
AK		 1351static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1352{
a2fa3e9f
GH		 1353 struct vcpu_svm *svm = to_svm(vcpu);
1354
2030753d 1355 if (is_guest_mode(vcpu)) {
7f5d8b56
JR		 1356 /*
1357 * We are here because we run in nested mode, the host kvm
1358 * intercepts cr0 writes but the l1 hypervisor does not.
1359 * But the L1 hypervisor may intercept selective cr0 writes.
1360 * This needs to be checked here.
1361 */
1362 unsigned long old, new;
1363
1364 /* Remove bits that would trigger a real cr0 write intercept */
1365 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1366 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1367
1368 if (old == new) {
1369 /* cr0 write with ts and mp unchanged */
1370 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
cda00082
JR		 1371 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1372 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1373 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1374 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7f5d8b56 1375 return;
cda00082 1376 }
7f5d8b56
JR		 1377 }
1378 }
1379
05b3e0c2 1380#ifdef CONFIG_X86_64
f6801dff 1381 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1382 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1383 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1384 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1385 }
1386
d77c26fc 1387 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1388 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1389 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1390 }
1391 }
1392#endif
ad312c7c 1393 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1394
1395 if (!npt_enabled)
1396 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1397
1398 if (!vcpu->fpu_active)
334df50a 1399 cr0 |= X86_CR0_TS;
709ddebf
JR		 1400 /*
1401 * re-enable caching here because the QEMU bios
1402 * does not do it - this results in some delay at
1403 * reboot
1404 */
1405 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1406 svm->vmcb->save.cr0 = cr0;
dcca1a65 1407 mark_dirty(svm->vmcb, VMCB_CR);
d225157b 1408 update_cr0_intercept(svm);
6aa8b732
AK		 1409}
1410
1411static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1412{
6394b649 1413 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1414 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1415
1416 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
f40f6a45 1417 svm_flush_tlb(vcpu);
6394b649 1418
ec077263
JR		 1419 vcpu->arch.cr4 = cr4;
1420 if (!npt_enabled)
1421 cr4 |= X86_CR4_PAE;
6394b649 1422 cr4 |= host_cr4_mce;
ec077263 1423 to_svm(vcpu)->vmcb->save.cr4 = cr4;
dcca1a65 1424 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
6aa8b732
AK		 1425}
1426
1427static void svm_set_segment(struct kvm_vcpu *vcpu,
1428 struct kvm_segment *var, int seg)
1429{
a2fa3e9f 1430 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1431 struct vmcb_seg *s = svm_seg(vcpu, seg);
1432
1433 s->base = var->base;
1434 s->limit = var->limit;
1435 s->selector = var->selector;
1436 if (var->unusable)
1437 s->attrib = 0;
1438 else {
1439 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1440 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1441 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1442 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1443 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1444 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1445 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1446 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1447 }
1448 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1449 svm->vmcb->save.cpl
1450 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1451 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1452
060d0c9a 1453 mark_dirty(svm->vmcb, VMCB_SEG);
6aa8b732
AK		 1454}
1455
44c11430 1456static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1457{
d0bfb940
JK		 1458 struct vcpu_svm *svm = to_svm(vcpu);
1459
18c918c5
JR		 1460 clr_exception_intercept(svm, DB_VECTOR);
1461 clr_exception_intercept(svm, BP_VECTOR);
44c11430 1462
6be7d306 1463 if (svm->nmi_singlestep)
18c918c5 1464 set_exception_intercept(svm, DB_VECTOR);
44c11430 1465
d0bfb940
JK		 1466 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1467 if (vcpu->guest_debug &
1468 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
18c918c5 1469 set_exception_intercept(svm, DB_VECTOR);
d0bfb940 1470 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
18c918c5 1471 set_exception_intercept(svm, BP_VECTOR);
d0bfb940
JK		 1472 } else
1473 vcpu->guest_debug = 0;
44c11430
GN		 1474}
1475
355be0b9 1476static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1477{
44c11430
GN		 1478 struct vcpu_svm *svm = to_svm(vcpu);
1479
ae675ef0
JK		 1480 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1481 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1482 else
1483 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1484
72214b96
JR		 1485 mark_dirty(svm->vmcb, VMCB_DR);
1486
355be0b9 1487 update_db_intercept(vcpu);
6aa8b732
AK		 1488}
1489
0fe1e009 1490static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1491{
0fe1e009
TH		 1492 if (sd->next_asid > sd->max_asid) {
1493 ++sd->asid_generation;
1494 sd->next_asid = 1;
a2fa3e9f 1495 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1496 }
1497
0fe1e009
TH		 1498 svm->asid_generation = sd->asid_generation;
1499 svm->vmcb->control.asid = sd->next_asid++;
d48086d1
JR		 1500
1501 mark_dirty(svm->vmcb, VMCB_ASID);
6aa8b732
AK		 1502}
1503
020df079 1504static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1505{
42dbaa5a 1506 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1507
020df079 1508 svm->vmcb->save.dr7 = value;
72214b96 1509 mark_dirty(svm->vmcb, VMCB_DR);
6aa8b732
AK		 1510}
1511
851ba692 1512static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1513{
631bc487 1514 u64 fault_address = svm->vmcb->control.exit_info_2;
6aa8b732 1515 u32 error_code;
631bc487 1516 int r = 1;
6aa8b732 1517
631bc487
GN		 1518 switch (svm->apf_reason) {
1519 default:
1520 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1521
631bc487
GN		 1522 trace_kvm_page_fault(fault_address, error_code);
1523 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1524 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1525 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1526 break;
1527 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1528 svm->apf_reason = 0;
1529 local_irq_disable();
1530 kvm_async_pf_task_wait(fault_address);
1531 local_irq_enable();
1532 break;
1533 case KVM_PV_REASON_PAGE_READY:
1534 svm->apf_reason = 0;
1535 local_irq_disable();
1536 kvm_async_pf_task_wake(fault_address);
1537 local_irq_enable();
1538 break;
1539 }
1540 return r;
6aa8b732
AK		 1541}
1542
851ba692 1543static int db_interception(struct vcpu_svm *svm)
d0bfb940 1544{
851ba692
AK		 1545 struct kvm_run *kvm_run = svm->vcpu.run;
1546
d0bfb940 1547 if (!(svm->vcpu.guest_debug &
44c11430 1548 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1549 !svm->nmi_singlestep) {
d0bfb940
JK		 1550 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1551 return 1;
1552 }
44c11430 1553
6be7d306
JK		 1554 if (svm->nmi_singlestep) {
1555 svm->nmi_singlestep = false;
44c11430
GN		 1556 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1557 svm->vmcb->save.rflags &=
1558 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1559 update_db_intercept(&svm->vcpu);
1560 }
1561
1562 if (svm->vcpu.guest_debug &
e0231715 1563 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1564 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1565 kvm_run->debug.arch.pc =
1566 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1567 kvm_run->debug.arch.exception = DB_VECTOR;
1568 return 0;
1569 }
1570
1571 return 1;
d0bfb940
JK		 1572}
1573
851ba692 1574static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1575{
851ba692
AK		 1576 struct kvm_run *kvm_run = svm->vcpu.run;
1577
d0bfb940
JK		 1578 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1579 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1580 kvm_run->debug.arch.exception = BP_VECTOR;
1581 return 0;
1582}
1583
851ba692 1584static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1585{
1586 int er;
1587
851ba692 1588 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1589 if (er != EMULATE_DONE)
7ee5d940 1590 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1591 return 1;
1592}
1593
6b52d186 1594static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1595{
6b52d186 1596 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7 1597
18c918c5 1598 clr_exception_intercept(svm, NM_VECTOR);
66a562f7 1599
e756fc62 1600 svm->vcpu.fpu_active = 1;
d225157b 1601 update_cr0_intercept(svm);
6b52d186 1602}
a2fa3e9f 1603
6b52d186
AK		 1604static int nm_interception(struct vcpu_svm *svm)
1605{
1606 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1607 return 1;
7807fa6c
AL		 1608}
1609
67ec6607
JR		 1610static bool is_erratum_383(void)
1611{
1612 int err, i;
1613 u64 value;
1614
1615 if (!erratum_383_found)
1616 return false;
1617
1618 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1619 if (err)
1620 return false;
1621
1622 /* Bit 62 may or may not be set for this mce */
1623 value &= ~(1ULL << 62);
1624
1625 if (value != 0xb600000000010015ULL)
1626 return false;
1627
1628 /* Clear MCi_STATUS registers */
1629 for (i = 0; i < 6; ++i)
1630 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1631
1632 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1633 if (!err) {
1634 u32 low, high;
1635
1636 value &= ~(1ULL << 2);
1637 low = lower_32_bits(value);
1638 high = upper_32_bits(value);
1639
1640 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1641 }
1642
1643 /* Flush tlb to evict multi-match entries */
1644 __flush_tlb_all();
1645
1646 return true;
1647}
1648
fe5913e4 1649static void svm_handle_mce(struct vcpu_svm *svm)
53371b50 1650{
67ec6607
JR		 1651 if (is_erratum_383()) {
1652 /*
1653 * Erratum 383 triggered. Guest state is corrupt so kill the
1654 * guest.
1655 */
1656 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1657
a8eeb04a 1658 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
67ec6607
JR		 1659
1660 return;
1661 }
1662
53371b50
JR		 1663 /*
1664 * On an #MC intercept the MCE handler is not called automatically in
1665 * the host. So do it by hand here.
1666 */
1667 asm volatile (
1668 "int $0x12\n");
1669 /* not sure if we ever come back to this point */
1670
fe5913e4
JR		 1671 return;
1672}
1673
1674static int mc_interception(struct vcpu_svm *svm)
1675{
53371b50
JR		 1676 return 1;
1677}
1678
851ba692 1679static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1680{
851ba692
AK		 1681 struct kvm_run *kvm_run = svm->vcpu.run;
1682
46fe4ddd
JR		 1683 /*
1684 * VMCB is undefined after a SHUTDOWN intercept
1685 * so reinitialize it.
1686 */
a2fa3e9f 1687 clear_page(svm->vmcb);
e6101a96 1688 init_vmcb(svm);
46fe4ddd
JR		 1689
1690 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1691 return 0;
1692}
1693
851ba692 1694static int io_interception(struct vcpu_svm *svm)
6aa8b732 1695{
cf8f70bf 1696 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1697 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1698 int size, in, string;
039576c0 1699 unsigned port;
6aa8b732 1700
e756fc62 1701 ++svm->vcpu.stat.io_exits;
e70669ab 1702 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1703 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
cf8f70bf 1704 if (string || in)
6d77dbfc 1705 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
cf8f70bf 1706
039576c0
AK		 1707 port = io_info >> 16;
1708 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1709 svm->next_rip = svm->vmcb->control.exit_info_2;
e93f36bc 1710 skip_emulated_instruction(&svm->vcpu);
cf8f70bf
GN		 1711
1712 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 1713}
1714
851ba692 1715static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1716{
1717 return 1;
1718}
1719
851ba692 1720static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1721{
1722 ++svm->vcpu.stat.irq_exits;
1723 return 1;
1724}
1725
851ba692 1726static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1727{
1728 return 1;
1729}
1730
851ba692 1731static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1732{
5fdbf976 1733 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1734 skip_emulated_instruction(&svm->vcpu);
1735 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1736}
1737
851ba692 1738static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1739{
5fdbf976 1740 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1741 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1742 kvm_emulate_hypercall(&svm->vcpu);
1743 return 1;
02e235bc
AK		 1744}
1745
5bd2edc3
JR		 1746static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1747{
1748 struct vcpu_svm *svm = to_svm(vcpu);
1749
1750 return svm->nested.nested_cr3;
1751}
1752
1753static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1754 unsigned long root)
1755{
1756 struct vcpu_svm *svm = to_svm(vcpu);
1757
1758 svm->vmcb->control.nested_cr3 = root;
b2747166 1759 mark_dirty(svm->vmcb, VMCB_NPT);
f40f6a45 1760 svm_flush_tlb(vcpu);
5bd2edc3
JR		 1761}
1762
6389ee94
AK		 1763static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1764 struct x86_exception *fault)
5bd2edc3
JR		 1765{
1766 struct vcpu_svm *svm = to_svm(vcpu);
1767
1768 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1769 svm->vmcb->control.exit_code_hi = 0;
6389ee94
AK		 1770 svm->vmcb->control.exit_info_1 = fault->error_code;
1771 svm->vmcb->control.exit_info_2 = fault->address;
5bd2edc3
JR		 1772
1773 nested_svm_vmexit(svm);
1774}
1775
4b16184c
JR		 1776static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1777{
1778 int r;
1779
1780 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1781
1782 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1783 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1784 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1785 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1786 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1787
1788 return r;
1789}
1790
1791static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1792{
1793 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1794}
1795
c0725420
AG		 1796static int nested_svm_check_permissions(struct vcpu_svm *svm)
1797{
f6801dff 1798 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1799 || !is_paging(&svm->vcpu)) {
1800 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1801 return 1;
1802 }
1803
1804 if (svm->vmcb->save.cpl) {
1805 kvm_inject_gp(&svm->vcpu, 0);
1806 return 1;
1807 }
1808
1809 return 0;
1810}
1811
cf74a78b
AG		 1812static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1813 bool has_error_code, u32 error_code)
1814{
b8e88bc8
JR		 1815 int vmexit;
1816
2030753d 1817 if (!is_guest_mode(&svm->vcpu))
0295ad7d 1818 return 0;
cf74a78b 1819
0295ad7d
JR		 1820 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1821 svm->vmcb->control.exit_code_hi = 0;
1822 svm->vmcb->control.exit_info_1 = error_code;
1823 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1824
b8e88bc8
JR		 1825 vmexit = nested_svm_intercept(svm);
1826 if (vmexit == NESTED_EXIT_DONE)
1827 svm->nested.exit_required = true;
1828
1829 return vmexit;
cf74a78b
AG		 1830}
1831
8fe54654
JR		 1832/* This function returns true if it is save to enable the irq window */
1833static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1834{
2030753d 1835 if (!is_guest_mode(&svm->vcpu))
8fe54654 1836 return true;
cf74a78b 1837
26666957 1838 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1839 return true;
cf74a78b 1840
26666957 1841 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1842 return false;
cf74a78b 1843
a0a07cd2
GN		 1844 /*
1845 * if vmexit was already requested (by intercepted exception
1846 * for instance) do not overwrite it with "external interrupt"
1847 * vmexit.
1848 */
1849 if (svm->nested.exit_required)
1850 return false;
1851
197717d5
JR		 1852 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1853 svm->vmcb->control.exit_info_1 = 0;
1854 svm->vmcb->control.exit_info_2 = 0;
26666957 1855
cd3ff653
JR		 1856 if (svm->nested.intercept & 1ULL) {
1857 /*
1858 * The #vmexit can't be emulated here directly because this
1859 * code path runs with irqs and preemtion disabled. A
1860 * #vmexit emulation might sleep. Only signal request for
1861 * the #vmexit here.
1862 */
1863 svm->nested.exit_required = true;
236649de 1864 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1865 return false;
cf74a78b
AG		 1866 }
1867
8fe54654 1868 return true;
cf74a78b
AG		 1869}
1870
887f500c
JR		 1871/* This function returns true if it is save to enable the nmi window */
1872static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1873{
2030753d 1874 if (!is_guest_mode(&svm->vcpu))
887f500c
JR		 1875 return true;
1876
1877 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1878 return true;
1879
1880 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1881 svm->nested.exit_required = true;
1882
1883 return false;
cf74a78b
AG		 1884}
1885
7597f129 1886static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1887{
1888 struct page *page;
1889
6c3bd3d7
JR		 1890 might_sleep();
1891
34f80cfa 1892 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1893 if (is_error_page(page))
1894 goto error;
1895
7597f129
JR		 1896 *_page = page;
1897
1898 return kmap(page);
34f80cfa
JR		 1899
1900error:
1901 kvm_release_page_clean(page);
1902 kvm_inject_gp(&svm->vcpu, 0);
1903
1904 return NULL;
1905}
1906
7597f129 1907static void nested_svm_unmap(struct page *page)
34f80cfa 1908{
7597f129 1909 kunmap(page);
34f80cfa
JR		 1910 kvm_release_page_dirty(page);
1911}
34f80cfa 1912
ce2ac085
JR		 1913static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1914{
1915 unsigned port;
1916 u8 val, bit;
1917 u64 gpa;
34f80cfa 1918
ce2ac085
JR		 1919 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1920 return NESTED_EXIT_HOST;
34f80cfa 1921
ce2ac085
JR		 1922 port = svm->vmcb->control.exit_info_1 >> 16;
1923 gpa = svm->nested.vmcb_iopm + (port / 8);
1924 bit = port % 8;
1925 val = 0;
1926
1927 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1928 val &= (1 << bit);
1929
1930 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
34f80cfa
JR		 1931}
1932
d2477826 1933static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1934{
0d6b3537
JR		 1935 u32 offset, msr, value;
1936 int write, mask;
4c2161ae 1937
3d62d9aa 1938 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 1939 return NESTED_EXIT_HOST;
3d62d9aa 1940
0d6b3537
JR		 1941 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1942 offset = svm_msrpm_offset(msr);
1943 write = svm->vmcb->control.exit_info_1 & 1;
1944 mask = 1 << ((2 * (msr & 0xf)) + write);
3d62d9aa 1945
0d6b3537
JR		 1946 if (offset == MSR_INVALID)
1947 return NESTED_EXIT_DONE;
4c2161ae 1948
0d6b3537
JR		 1949 /* Offset is in 32 bit units but need in 8 bit units */
1950 offset *= 4;
4c2161ae 1951
0d6b3537
JR		 1952 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1953 return NESTED_EXIT_DONE;
3d62d9aa 1954
0d6b3537 1955 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
4c2161ae
JR		 1956}
1957
410e4d57 1958static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1959{
cf74a78b 1960 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1961
410e4d57
JR		 1962 switch (exit_code) {
1963 case SVM_EXIT_INTR:
1964 case SVM_EXIT_NMI:
ff47a49b 1965 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
410e4d57 1966 return NESTED_EXIT_HOST;
410e4d57 1967 case SVM_EXIT_NPF:
e0231715 1968 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1969 if (npt_enabled)
1970 return NESTED_EXIT_HOST;
1971 break;
410e4d57 1972 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
631bc487
GN		 1973 /* When we're shadowing, trap PFs, but not async PF */
1974 if (!npt_enabled && svm->apf_reason == 0)
410e4d57
JR		 1975 return NESTED_EXIT_HOST;
1976 break;
66a562f7
JR		 1977 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1978 nm_interception(svm);
1979 break;
410e4d57
JR		 1980 default:
1981 break;
cf74a78b
AG		 1982 }
1983
410e4d57
JR		 1984 return NESTED_EXIT_CONTINUE;
1985}
1986
1987/*
1988 * If this function returns true, this #vmexit was already handled
1989 */
b8e88bc8 1990static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1991{
1992 u32 exit_code = svm->vmcb->control.exit_code;
1993 int vmexit = NESTED_EXIT_HOST;
1994
cf74a78b 1995 switch (exit_code) {
9c4e40b9 1996 case SVM_EXIT_MSR:
3d62d9aa 1997 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1998 break;
ce2ac085
JR		 1999 case SVM_EXIT_IOIO:
2000 vmexit = nested_svm_intercept_ioio(svm);
2001 break;
4ee546b4
RJ		 2002 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2003 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2004 if (svm->nested.intercept_cr & bit)
410e4d57 2005 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 2006 break;
2007 }
3aed041a
JR		 2008 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2009 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2010 if (svm->nested.intercept_dr & bit)
410e4d57 2011 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 2012 break;
2013 }
2014 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2015 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 2016 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 2017 vmexit = NESTED_EXIT_DONE;
631bc487
GN		 2018 /* async page fault always cause vmexit */
2019 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2020 svm->apf_reason != 0)
2021 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 2022 break;
2023 }
228070b1
JR		 2024 case SVM_EXIT_ERR: {
2025 vmexit = NESTED_EXIT_DONE;
2026 break;
2027 }
cf74a78b
AG		 2028 default: {
2029 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 2030 if (svm->nested.intercept & exit_bits)
410e4d57 2031 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 2032 }
2033 }
2034
b8e88bc8
JR		 2035 return vmexit;
2036}
2037
2038static int nested_svm_exit_handled(struct vcpu_svm *svm)
2039{
2040 int vmexit;
2041
2042 vmexit = nested_svm_intercept(svm);
2043
2044 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 2045 nested_svm_vmexit(svm);
9c4e40b9
JR		 2046
2047 return vmexit;
cf74a78b
AG		 2048}
2049
0460a979
JR		 2050static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2051{
2052 struct vmcb_control_area *dst = &dst_vmcb->control;
2053 struct vmcb_control_area *from = &from_vmcb->control;
2054
4ee546b4 2055 dst->intercept_cr = from->intercept_cr;
3aed041a 2056 dst->intercept_dr = from->intercept_dr;
0460a979
JR		 2057 dst->intercept_exceptions = from->intercept_exceptions;
2058 dst->intercept = from->intercept;
2059 dst->iopm_base_pa = from->iopm_base_pa;
2060 dst->msrpm_base_pa = from->msrpm_base_pa;
2061 dst->tsc_offset = from->tsc_offset;
2062 dst->asid = from->asid;
2063 dst->tlb_ctl = from->tlb_ctl;
2064 dst->int_ctl = from->int_ctl;
2065 dst->int_vector = from->int_vector;
2066 dst->int_state = from->int_state;
2067 dst->exit_code = from->exit_code;
2068 dst->exit_code_hi = from->exit_code_hi;
2069 dst->exit_info_1 = from->exit_info_1;
2070 dst->exit_info_2 = from->exit_info_2;
2071 dst->exit_int_info = from->exit_int_info;
2072 dst->exit_int_info_err = from->exit_int_info_err;
2073 dst->nested_ctl = from->nested_ctl;
2074 dst->event_inj = from->event_inj;
2075 dst->event_inj_err = from->event_inj_err;
2076 dst->nested_cr3 = from->nested_cr3;
2077 dst->lbr_ctl = from->lbr_ctl;
2078}
2079
34f80cfa 2080static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 2081{
34f80cfa 2082 struct vmcb *nested_vmcb;
e6aa9abd 2083 struct vmcb *hsave = svm->nested.hsave;
33740e40 2084 struct vmcb *vmcb = svm->vmcb;
7597f129 2085 struct page *page;
cf74a78b 2086
17897f36
JR		 2087 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2088 vmcb->control.exit_info_1,
2089 vmcb->control.exit_info_2,
2090 vmcb->control.exit_int_info,
2091 vmcb->control.exit_int_info_err);
2092
7597f129 2093 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 2094 if (!nested_vmcb)
2095 return 1;
2096
2030753d
JR		 2097 /* Exit Guest-Mode */
2098 leave_guest_mode(&svm->vcpu);
06fc7772
JR		 2099 svm->nested.vmcb = 0;
2100
cf74a78b 2101 /* Give the current vmcb to the guest */
33740e40
JR		 2102 disable_gif(svm);
2103
2104 nested_vmcb->save.es = vmcb->save.es;
2105 nested_vmcb->save.cs = vmcb->save.cs;
2106 nested_vmcb->save.ss = vmcb->save.ss;
2107 nested_vmcb->save.ds = vmcb->save.ds;
2108 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2109 nested_vmcb->save.idtr = vmcb->save.idtr;
3f6a9d16 2110 nested_vmcb->save.efer = svm->vcpu.arch.efer;
cdbbdc12 2111 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2be4fc7a 2112 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 2113 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 2114 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 2115 nested_vmcb->save.rflags = vmcb->save.rflags;
2116 nested_vmcb->save.rip = vmcb->save.rip;
2117 nested_vmcb->save.rsp = vmcb->save.rsp;
2118 nested_vmcb->save.rax = vmcb->save.rax;
2119 nested_vmcb->save.dr7 = vmcb->save.dr7;
2120 nested_vmcb->save.dr6 = vmcb->save.dr6;
2121 nested_vmcb->save.cpl = vmcb->save.cpl;
2122
2123 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2124 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2125 nested_vmcb->control.int_state = vmcb->control.int_state;
2126 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2127 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2128 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2129 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2130 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2131 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
7a190667 2132 nested_vmcb->control.next_rip = vmcb->control.next_rip;
8d23c466
AG		 2133
2134 /*
2135 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2136 * to make sure that we do not lose injected events. So check event_inj
2137 * here and copy it to exit_int_info if it is valid.
2138 * Exit_int_info and event_inj can't be both valid because the case
2139 * below only happens on a VMRUN instruction intercept which has
2140 * no valid exit_int_info set.
2141 */
2142 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2143 struct vmcb_control_area *nc = &nested_vmcb->control;
2144
2145 nc->exit_int_info = vmcb->control.event_inj;
2146 nc->exit_int_info_err = vmcb->control.event_inj_err;
2147 }
2148
33740e40
JR		 2149 nested_vmcb->control.tlb_ctl = 0;
2150 nested_vmcb->control.event_inj = 0;
2151 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 2152
2153 /* We always set V_INTR_MASKING and remember the old value in hflags */
2154 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2155 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2156
cf74a78b 2157 /* Restore the original control entries */
0460a979 2158 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 2159
219b65dc
AG		 2160 kvm_clear_exception_queue(&svm->vcpu);
2161 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b 2162
4b16184c
JR		 2163 svm->nested.nested_cr3 = 0;
2164
cf74a78b
AG		 2165 /* Restore selected save entries */
2166 svm->vmcb->save.es = hsave->save.es;
2167 svm->vmcb->save.cs = hsave->save.cs;
2168 svm->vmcb->save.ss = hsave->save.ss;
2169 svm->vmcb->save.ds = hsave->save.ds;
2170 svm->vmcb->save.gdtr = hsave->save.gdtr;
2171 svm->vmcb->save.idtr = hsave->save.idtr;
2172 svm->vmcb->save.rflags = hsave->save.rflags;
2173 svm_set_efer(&svm->vcpu, hsave->save.efer);
2174 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2175 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2176 if (npt_enabled) {
2177 svm->vmcb->save.cr3 = hsave->save.cr3;
2178 svm->vcpu.arch.cr3 = hsave->save.cr3;
2179 } else {
2390218b 2180 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
cf74a78b
AG		 2181 }
2182 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2183 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2184 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2185 svm->vmcb->save.dr7 = 0;
2186 svm->vmcb->save.cpl = 0;
2187 svm->vmcb->control.exit_int_info = 0;
2188
8d28fec4
RJ		 2189 mark_all_dirty(svm->vmcb);
2190
7597f129 2191 nested_svm_unmap(page);
cf74a78b 2192
4b16184c 2193 nested_svm_uninit_mmu_context(&svm->vcpu);
cf74a78b
AG		 2194 kvm_mmu_reset_context(&svm->vcpu);
2195 kvm_mmu_load(&svm->vcpu);
2196
2197 return 0;
2198}
3d6368ef 2199
9738b2c9 2200static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 2201{
323c3d80
JR		 2202 /*
2203 * This function merges the msr permission bitmaps of kvm and the
2204 * nested vmcb. It is omptimized in that it only merges the parts where
2205 * the kvm msr permission bitmap may contain zero bits
2206 */
3d6368ef 2207 int i;
9738b2c9 2208
323c3d80
JR		 2209 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2210 return true;
9738b2c9 2211
323c3d80
JR		 2212 for (i = 0; i < MSRPM_OFFSETS; i++) {
2213 u32 value, p;
2214 u64 offset;
9738b2c9 2215
323c3d80
JR		 2216 if (msrpm_offsets[i] == 0xffffffff)
2217 break;
3d6368ef 2218
0d6b3537
JR		 2219 p = msrpm_offsets[i];
2220 offset = svm->nested.vmcb_msrpm + (p * 4);
323c3d80
JR		 2221
2222 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2223 return false;
2224
2225 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2226 }
3d6368ef 2227
323c3d80 2228 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
9738b2c9
JR		 2229
2230 return true;
3d6368ef
AG		 2231}
2232
52c65a30
JR		 2233static bool nested_vmcb_checks(struct vmcb *vmcb)
2234{
2235 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2236 return false;
2237
dbe77584
JR		 2238 if (vmcb->control.asid == 0)
2239 return false;
2240
4b16184c
JR		 2241 if (vmcb->control.nested_ctl && !npt_enabled)
2242 return false;
2243
52c65a30
JR		 2244 return true;
2245}
2246
9738b2c9 2247static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 2248{
9738b2c9 2249 struct vmcb *nested_vmcb;
e6aa9abd 2250 struct vmcb *hsave = svm->nested.hsave;
defbba56 2251 struct vmcb *vmcb = svm->vmcb;
7597f129 2252 struct page *page;
06fc7772 2253 u64 vmcb_gpa;
3d6368ef 2254
06fc7772 2255 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 2256
7597f129 2257 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 2258 if (!nested_vmcb)
2259 return false;
2260
52c65a30
JR		 2261 if (!nested_vmcb_checks(nested_vmcb)) {
2262 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2263 nested_vmcb->control.exit_code_hi = 0;
2264 nested_vmcb->control.exit_info_1 = 0;
2265 nested_vmcb->control.exit_info_2 = 0;
2266
2267 nested_svm_unmap(page);
2268
2269 return false;
2270 }
2271
b75f4eb3 2272 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
0ac406de
JR		 2273 nested_vmcb->save.rip,
2274 nested_vmcb->control.int_ctl,
2275 nested_vmcb->control.event_inj,
2276 nested_vmcb->control.nested_ctl);
2277
4ee546b4
RJ		 2278 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2279 nested_vmcb->control.intercept_cr >> 16,
2e554e8d
JR		 2280 nested_vmcb->control.intercept_exceptions,
2281 nested_vmcb->control.intercept);
2282
3d6368ef 2283 /* Clear internal status */
219b65dc
AG		 2284 kvm_clear_exception_queue(&svm->vcpu);
2285 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 2286
e0231715
JR		 2287 /*
2288 * Save the old vmcb, so we don't need to pick what we save, but can
2289 * restore everything when a VMEXIT occurs
2290 */
defbba56
JR		 2291 hsave->save.es = vmcb->save.es;
2292 hsave->save.cs = vmcb->save.cs;
2293 hsave->save.ss = vmcb->save.ss;
2294 hsave->save.ds = vmcb->save.ds;
2295 hsave->save.gdtr = vmcb->save.gdtr;
2296 hsave->save.idtr = vmcb->save.idtr;
f6801dff 2297 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 2298 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 2299 hsave->save.cr4 = svm->vcpu.arch.cr4;
2300 hsave->save.rflags = vmcb->save.rflags;
b75f4eb3 2301 hsave->save.rip = kvm_rip_read(&svm->vcpu);
defbba56
JR		 2302 hsave->save.rsp = vmcb->save.rsp;
2303 hsave->save.rax = vmcb->save.rax;
2304 if (npt_enabled)
2305 hsave->save.cr3 = vmcb->save.cr3;
2306 else
2307 hsave->save.cr3 = svm->vcpu.arch.cr3;
2308
0460a979 2309 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 2310
2311 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2312 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2313 else
2314 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2315
4b16184c
JR		 2316 if (nested_vmcb->control.nested_ctl) {
2317 kvm_mmu_unload(&svm->vcpu);
2318 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2319 nested_svm_init_mmu_context(&svm->vcpu);
2320 }
2321
3d6368ef
AG		 2322 /* Load the nested guest state */
2323 svm->vmcb->save.es = nested_vmcb->save.es;
2324 svm->vmcb->save.cs = nested_vmcb->save.cs;
2325 svm->vmcb->save.ss = nested_vmcb->save.ss;
2326 svm->vmcb->save.ds = nested_vmcb->save.ds;
2327 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2328 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2329 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2330 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2331 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2332 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2333 if (npt_enabled) {
2334 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2335 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 2336 } else
2390218b 2337 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 2338
2339 /* Guest paging mode is active - reset mmu */
2340 kvm_mmu_reset_context(&svm->vcpu);
2341
defbba56 2342 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 2343 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2344 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2345 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 2346
3d6368ef
AG		 2347 /* In case we don't even reach vcpu_run, the fields are not updated */
2348 svm->vmcb->save.rax = nested_vmcb->save.rax;
2349 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2350 svm->vmcb->save.rip = nested_vmcb->save.rip;
2351 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2352 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2353 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2354
f7138538 2355 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
ce2ac085 2356 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3d6368ef 2357
aad42c64 2358 /* cache intercepts */
4ee546b4 2359 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
3aed041a 2360 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
aad42c64
JR		 2361 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2362 svm->nested.intercept = nested_vmcb->control.intercept;
2363
f40f6a45 2364 svm_flush_tlb(&svm->vcpu);
3d6368ef 2365 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 2366 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2367 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2368 else
2369 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2370
88ab24ad
JR		 2371 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2372 /* We only want the cr8 intercept bits of the guest */
4ee546b4
RJ		 2373 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2374 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
88ab24ad
JR		 2375 }
2376
0d945bd9 2377 /* We don't want to see VMMCALLs from a nested guest */
8a05a1b8 2378 clr_intercept(svm, INTERCEPT_VMMCALL);
0d945bd9 2379
88ab24ad 2380 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2381 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2382 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2383 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2384 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2385 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2386
7597f129 2387 nested_svm_unmap(page);
9738b2c9 2388
2030753d
JR		 2389 /* Enter Guest-Mode */
2390 enter_guest_mode(&svm->vcpu);
2391
384c6368
JR		 2392 /*
2393 * Merge guest and host intercepts - must be called with vcpu in
2394 * guest-mode to take affect here
2395 */
2396 recalc_intercepts(svm);
2397
06fc7772 2398 svm->nested.vmcb = vmcb_gpa;
9738b2c9 2399
2af9194d 2400 enable_gif(svm);
3d6368ef 2401
8d28fec4
RJ		 2402 mark_all_dirty(svm->vmcb);
2403
9738b2c9 2404 return true;
3d6368ef
AG		 2405}
2406
9966bf68 2407static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2408{
2409 to_vmcb->save.fs = from_vmcb->save.fs;
2410 to_vmcb->save.gs = from_vmcb->save.gs;
2411 to_vmcb->save.tr = from_vmcb->save.tr;
2412 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2413 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2414 to_vmcb->save.star = from_vmcb->save.star;
2415 to_vmcb->save.lstar = from_vmcb->save.lstar;
2416 to_vmcb->save.cstar = from_vmcb->save.cstar;
2417 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2418 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2419 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2420 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2421}
2422
851ba692 2423static int vmload_interception(struct vcpu_svm *svm)
5542675b 2424{
9966bf68 2425 struct vmcb *nested_vmcb;
7597f129 2426 struct page *page;
9966bf68 2427
5542675b
AG		 2428 if (nested_svm_check_permissions(svm))
2429 return 1;
2430
2431 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2432 skip_emulated_instruction(&svm->vcpu);
2433
7597f129 2434 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2435 if (!nested_vmcb)
2436 return 1;
2437
2438 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2439 nested_svm_unmap(page);
5542675b
AG		 2440
2441 return 1;
2442}
2443
851ba692 2444static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2445{
9966bf68 2446 struct vmcb *nested_vmcb;
7597f129 2447 struct page *page;
9966bf68 2448
5542675b
AG		 2449 if (nested_svm_check_permissions(svm))
2450 return 1;
2451
2452 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2453 skip_emulated_instruction(&svm->vcpu);
2454
7597f129 2455 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2456 if (!nested_vmcb)
2457 return 1;
2458
2459 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2460 nested_svm_unmap(page);
5542675b
AG		 2461
2462 return 1;
2463}
2464
851ba692 2465static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2466{
3d6368ef
AG		 2467 if (nested_svm_check_permissions(svm))
2468 return 1;
2469
b75f4eb3
RJ		 2470 /* Save rip after vmrun instruction */
2471 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3d6368ef 2472
9738b2c9 2473 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2474 return 1;
2475
9738b2c9 2476 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2477 goto failed;
2478
2479 return 1;
2480
2481failed:
2482
2483 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2484 svm->vmcb->control.exit_code_hi = 0;
2485 svm->vmcb->control.exit_info_1 = 0;
2486 svm->vmcb->control.exit_info_2 = 0;
2487
2488 nested_svm_vmexit(svm);
3d6368ef
AG		 2489
2490 return 1;
2491}
2492
851ba692 2493static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2494{
2495 if (nested_svm_check_permissions(svm))
2496 return 1;
2497
2498 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2499 skip_emulated_instruction(&svm->vcpu);
3842d135 2500 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
1371d904 2501
2af9194d 2502 enable_gif(svm);
1371d904
AG		 2503
2504 return 1;
2505}
2506
851ba692 2507static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2508{
2509 if (nested_svm_check_permissions(svm))
2510 return 1;
2511
2512 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2513 skip_emulated_instruction(&svm->vcpu);
2514
2af9194d 2515 disable_gif(svm);
1371d904
AG		 2516
2517 /* After a CLGI no interrupts should come */
2518 svm_clear_vintr(svm);
2519 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2520
decdbf6a
JR		 2521 mark_dirty(svm->vmcb, VMCB_INTR);
2522
1371d904
AG		 2523 return 1;
2524}
2525
851ba692 2526static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2527{
2528 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2529
ec1ff790
JR		 2530 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2531 vcpu->arch.regs[VCPU_REGS_RAX]);
2532
ff092385
AG		 2533 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2534 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2535
2536 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2537 skip_emulated_instruction(&svm->vcpu);
2538 return 1;
2539}
2540
532a46b9
JR		 2541static int skinit_interception(struct vcpu_svm *svm)
2542{
2543 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2544
2545 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2546 return 1;
2547}
2548
851ba692 2549static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2550{
7ee5d940 2551 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2552 return 1;
2553}
2554
851ba692 2555static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2556{
37817f29 2557 u16 tss_selector;
64a7ec06
GN		 2558 int reason;
2559 int int_type = svm->vmcb->control.exit_int_info &
2560 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2561 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2562 uint32_t type =
2563 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2564 uint32_t idt_v =
2565 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2566 bool has_error_code = false;
2567 u32 error_code = 0;
37817f29
IE		 2568
2569 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2570
37817f29
IE		 2571 if (svm->vmcb->control.exit_info_2 &
2572 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2573 reason = TASK_SWITCH_IRET;
2574 else if (svm->vmcb->control.exit_info_2 &
2575 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2576 reason = TASK_SWITCH_JMP;
fe8e7f83 2577 else if (idt_v)
64a7ec06
GN		 2578 reason = TASK_SWITCH_GATE;
2579 else
2580 reason = TASK_SWITCH_CALL;
2581
fe8e7f83
GN		 2582 if (reason == TASK_SWITCH_GATE) {
2583 switch (type) {
2584 case SVM_EXITINTINFO_TYPE_NMI:
2585 svm->vcpu.arch.nmi_injected = false;
2586 break;
2587 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2588 if (svm->vmcb->control.exit_info_2 &
2589 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2590 has_error_code = true;
2591 error_code =
2592 (u32)svm->vmcb->control.exit_info_2;
2593 }
fe8e7f83
GN		 2594 kvm_clear_exception_queue(&svm->vcpu);
2595 break;
2596 case SVM_EXITINTINFO_TYPE_INTR:
2597 kvm_clear_interrupt_queue(&svm->vcpu);
2598 break;
2599 default:
2600 break;
2601 }
2602 }
64a7ec06 2603
8317c298
GN		 2604 if (reason != TASK_SWITCH_GATE ||
2605 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2606 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2607 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2608 skip_emulated_instruction(&svm->vcpu);
64a7ec06 2609
acb54517
GN		 2610 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2611 has_error_code, error_code) == EMULATE_FAIL) {
2612 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2613 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2614 svm->vcpu.run->internal.ndata = 0;
2615 return 0;
2616 }
2617 return 1;
6aa8b732
AK		 2618}
2619
851ba692 2620static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2621{
5fdbf976 2622 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2623 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2624 return 1;
6aa8b732
AK		 2625}
2626
851ba692 2627static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2628{
2629 ++svm->vcpu.stat.nmi_window_exits;
8a05a1b8 2630 clr_intercept(svm, INTERCEPT_IRET);
44c11430 2631 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2632 return 1;
2633}
2634
851ba692 2635static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2636{
6d77dbfc 2637 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
a7052897
MT		 2638}
2639
851ba692 2640static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2641{
6d77dbfc 2642 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
6aa8b732
AK		 2643}
2644
cda00082
JR		 2645static int cr0_write_interception(struct vcpu_svm *svm)
2646{
2647 struct kvm_vcpu *vcpu = &svm->vcpu;
2648 int r;
2649
2650 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2651
2652 if (svm->nested.vmexit_rip) {
2653 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2654 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2655 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2656 svm->nested.vmexit_rip = 0;
2657 }
2658
2659 return r == EMULATE_DONE;
2660}
2661
851ba692 2662static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2663{
851ba692
AK		 2664 struct kvm_run *kvm_run = svm->vcpu.run;
2665
0a5fff19
GN		 2666 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2667 /* instruction emulation calls kvm_set_cr8() */
851ba692 2668 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273 2669 if (irqchip_in_kernel(svm->vcpu.kvm)) {
4ee546b4 2670 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1d075434 2671 return 1;
95ba8273 2672 }
0a5fff19
GN		 2673 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2674 return 1;
1d075434
JR		 2675 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2676 return 0;
2677}
2678
6aa8b732
AK		 2679static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2680{
a2fa3e9f
GH		 2681 struct vcpu_svm *svm = to_svm(vcpu);
2682
6aa8b732 2683 switch (ecx) {
af24a4e4 2684 case MSR_IA32_TSC: {
4cc70310 2685 struct vmcb *vmcb = get_host_vmcb(svm);
6aa8b732 2686
4cc70310 2687 *data = vmcb->control.tsc_offset + native_read_tsc();
6aa8b732
AK		 2688 break;
2689 }
8c06585d 2690 case MSR_STAR:
a2fa3e9f 2691 *data = svm->vmcb->save.star;
6aa8b732 2692 break;
0e859cac 2693#ifdef CONFIG_X86_64
6aa8b732 2694 case MSR_LSTAR:
a2fa3e9f 2695 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2696 break;
2697 case MSR_CSTAR:
a2fa3e9f 2698 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2699 break;
2700 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2701 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2702 break;
2703 case MSR_SYSCALL_MASK:
a2fa3e9f 2704 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2705 break;
2706#endif
2707 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2708 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2709 break;
2710 case MSR_IA32_SYSENTER_EIP:
017cb99e 2711 *data = svm->sysenter_eip;
6aa8b732
AK		 2712 break;
2713 case MSR_IA32_SYSENTER_ESP:
017cb99e 2714 *data = svm->sysenter_esp;
6aa8b732 2715 break;
e0231715
JR		 2716 /*
2717 * Nobody will change the following 5 values in the VMCB so we can
2718 * safely return them on rdmsr. They will always be 0 until LBRV is
2719 * implemented.
2720 */
a2938c80
JR		 2721 case MSR_IA32_DEBUGCTLMSR:
2722 *data = svm->vmcb->save.dbgctl;
2723 break;
2724 case MSR_IA32_LASTBRANCHFROMIP:
2725 *data = svm->vmcb->save.br_from;
2726 break;
2727 case MSR_IA32_LASTBRANCHTOIP:
2728 *data = svm->vmcb->save.br_to;
2729 break;
2730 case MSR_IA32_LASTINTFROMIP:
2731 *data = svm->vmcb->save.last_excp_from;
2732 break;
2733 case MSR_IA32_LASTINTTOIP:
2734 *data = svm->vmcb->save.last_excp_to;
2735 break;
b286d5d8 2736 case MSR_VM_HSAVE_PA:
e6aa9abd 2737 *data = svm->nested.hsave_msr;
b286d5d8 2738 break;
eb6f302e 2739 case MSR_VM_CR:
4a810181 2740 *data = svm->nested.vm_cr_msr;
eb6f302e 2741 break;
c8a73f18
AG		 2742 case MSR_IA32_UCODE_REV:
2743 *data = 0x01000065;
2744 break;
6aa8b732 2745 default:
3bab1f5d 2746 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2747 }
2748 return 0;
2749}
2750
851ba692 2751static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2752{
ad312c7c 2753 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2754 u64 data;
2755
59200273
AK		 2756 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2757 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2758 kvm_inject_gp(&svm->vcpu, 0);
59200273 2759 } else {
229456fc 2760 trace_kvm_msr_read(ecx, data);
af9ca2d7 2761
5fdbf976 2762 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2763 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2764 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2765 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2766 }
2767 return 1;
2768}
2769
4a810181
JR		 2770static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2771{
2772 struct vcpu_svm *svm = to_svm(vcpu);
2773 int svm_dis, chg_mask;
2774
2775 if (data & ~SVM_VM_CR_VALID_MASK)
2776 return 1;
2777
2778 chg_mask = SVM_VM_CR_VALID_MASK;
2779
2780 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2781 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2782
2783 svm->nested.vm_cr_msr &= ~chg_mask;
2784 svm->nested.vm_cr_msr |= (data & chg_mask);
2785
2786 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2787
2788 /* check for svm_disable while efer.svme is set */
2789 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2790 return 1;
2791
2792 return 0;
2793}
2794
6aa8b732
AK		 2795static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2796{
a2fa3e9f
GH		 2797 struct vcpu_svm *svm = to_svm(vcpu);
2798
6aa8b732 2799 switch (ecx) {
f4e1b3c8 2800 case MSR_IA32_TSC:
99e3e30a 2801 kvm_write_tsc(vcpu, data);
6aa8b732 2802 break;
8c06585d 2803 case MSR_STAR:
a2fa3e9f 2804 svm->vmcb->save.star = data;
6aa8b732 2805 break;
49b14f24 2806#ifdef CONFIG_X86_64
6aa8b732 2807 case MSR_LSTAR:
a2fa3e9f 2808 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2809 break;
2810 case MSR_CSTAR:
a2fa3e9f 2811 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2812 break;
2813 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2814 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2815 break;
2816 case MSR_SYSCALL_MASK:
a2fa3e9f 2817 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2818 break;
2819#endif
2820 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2821 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2822 break;
2823 case MSR_IA32_SYSENTER_EIP:
017cb99e 2824 svm->sysenter_eip = data;
a2fa3e9f 2825 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2826 break;
2827 case MSR_IA32_SYSENTER_ESP:
017cb99e 2828 svm->sysenter_esp = data;
a2fa3e9f 2829 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2830 break;
a2938c80 2831 case MSR_IA32_DEBUGCTLMSR:
2a6b20b8 2832 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
24e09cbf 2833 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2834 __func__, data);
24e09cbf
JR		 2835 break;
2836 }
2837 if (data & DEBUGCTL_RESERVED_BITS)
2838 return 1;
2839
2840 svm->vmcb->save.dbgctl = data;
b53ba3f9 2841 mark_dirty(svm->vmcb, VMCB_LBR);
24e09cbf
JR		 2842 if (data & (1ULL<<0))
2843 svm_enable_lbrv(svm);
2844 else
2845 svm_disable_lbrv(svm);
a2938c80 2846 break;
b286d5d8 2847 case MSR_VM_HSAVE_PA:
e6aa9abd 2848 svm->nested.hsave_msr = data;
62b9abaa 2849 break;
3c5d0a44 2850 case MSR_VM_CR:
4a810181 2851 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2852 case MSR_VM_IGNNE:
3c5d0a44
AG		 2853 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2854 break;
6aa8b732 2855 default:
3bab1f5d 2856 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2857 }
2858 return 0;
2859}
2860
851ba692 2861static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2862{
ad312c7c 2863 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2864 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2865 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2866
af9ca2d7 2867
5fdbf976 2868 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2869 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2870 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2871 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2872 } else {
2873 trace_kvm_msr_write(ecx, data);
e756fc62 2874 skip_emulated_instruction(&svm->vcpu);
59200273 2875 }
6aa8b732
AK		 2876 return 1;
2877}
2878
851ba692 2879static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2880{
e756fc62 2881 if (svm->vmcb->control.exit_info_1)
851ba692 2882 return wrmsr_interception(svm);
6aa8b732 2883 else
851ba692 2884 return rdmsr_interception(svm);
6aa8b732
AK		 2885}
2886
851ba692 2887static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2888{
851ba692
AK		 2889 struct kvm_run *kvm_run = svm->vcpu.run;
2890
3842d135 2891 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
f0b85051 2892 svm_clear_vintr(svm);
85f455f7 2893 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
decdbf6a 2894 mark_dirty(svm->vmcb, VMCB_INTR);
c1150d8c
DL		 2895 /*
2896 * If the user space waits to inject interrupts, exit as soon as
2897 * possible
2898 */
8061823a
GN		 2899 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2900 kvm_run->request_interrupt_window &&
2901 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2902 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2903 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2904 return 0;
2905 }
2906
2907 return 1;
2908}
2909
565d0998
ML		 2910static int pause_interception(struct vcpu_svm *svm)
2911{
2912 kvm_vcpu_on_spin(&(svm->vcpu));
2913 return 1;
2914}
2915
851ba692 2916static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2917 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2918 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2919 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2920 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2921 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
cda00082 2922 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
e0231715
JR		 2923 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2924 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2925 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2926 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2927 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2928 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2929 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2930 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2931 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2932 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2933 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2934 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2935 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2936 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2937 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2938 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2939 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2940 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2941 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2942 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2943 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2944 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2945 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2946 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2947 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2948 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2949 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2950 [SVM_EXIT_SMI] = nop_on_interception,
2951 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2952 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2953 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2954 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2955 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2956 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2957 [SVM_EXIT_HLT] = halt_interception,
a7052897 2958 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2959 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2960 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2961 [SVM_EXIT_MSR] = msr_interception,
2962 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2963 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2964 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2965 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2966 [SVM_EXIT_VMLOAD] = vmload_interception,
2967 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2968 [SVM_EXIT_STGI] = stgi_interception,
2969 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2970 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2971 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2972 [SVM_EXIT_MONITOR] = invalid_op_interception,
2973 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2974 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2975};
2976
3f10c846
JR		 2977void dump_vmcb(struct kvm_vcpu *vcpu)
2978{
2979 struct vcpu_svm *svm = to_svm(vcpu);
2980 struct vmcb_control_area *control = &svm->vmcb->control;
2981 struct vmcb_save_area *save = &svm->vmcb->save;
2982
2983 pr_err("VMCB Control Area:\n");
4ee546b4
RJ		 2984 pr_err("cr_read: %04x\n", control->intercept_cr & 0xffff);
2985 pr_err("cr_write: %04x\n", control->intercept_cr >> 16);
3aed041a
JR		 2986 pr_err("dr_read: %04x\n", control->intercept_dr & 0xffff);
2987 pr_err("dr_write: %04x\n", control->intercept_dr >> 16);
3f10c846
JR		 2988 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2989 pr_err("intercepts: %016llx\n", control->intercept);
2990 pr_err("pause filter count: %d\n", control->pause_filter_count);
2991 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2992 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2993 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2994 pr_err("asid: %d\n", control->asid);
2995 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2996 pr_err("int_ctl: %08x\n", control->int_ctl);
2997 pr_err("int_vector: %08x\n", control->int_vector);
2998 pr_err("int_state: %08x\n", control->int_state);
2999 pr_err("exit_code: %08x\n", control->exit_code);
3000 pr_err("exit_info1: %016llx\n", control->exit_info_1);
3001 pr_err("exit_info2: %016llx\n", control->exit_info_2);
3002 pr_err("exit_int_info: %08x\n", control->exit_int_info);
3003 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
3004 pr_err("nested_ctl: %lld\n", control->nested_ctl);
3005 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
3006 pr_err("event_inj: %08x\n", control->event_inj);
3007 pr_err("event_inj_err: %08x\n", control->event_inj_err);
3008 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
3009 pr_err("next_rip: %016llx\n", control->next_rip);
3010 pr_err("VMCB State Save Area:\n");
3011 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
3012 save->es.selector, save->es.attrib,
3013 save->es.limit, save->es.base);
3014 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
3015 save->cs.selector, save->cs.attrib,
3016 save->cs.limit, save->cs.base);
3017 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
3018 save->ss.selector, save->ss.attrib,
3019 save->ss.limit, save->ss.base);
3020 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
3021 save->ds.selector, save->ds.attrib,
3022 save->ds.limit, save->ds.base);
3023 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
3024 save->fs.selector, save->fs.attrib,
3025 save->fs.limit, save->fs.base);
3026 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
3027 save->gs.selector, save->gs.attrib,
3028 save->gs.limit, save->gs.base);
3029 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
3030 save->gdtr.selector, save->gdtr.attrib,
3031 save->gdtr.limit, save->gdtr.base);
3032 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
3033 save->ldtr.selector, save->ldtr.attrib,
3034 save->ldtr.limit, save->ldtr.base);
3035 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
3036 save->idtr.selector, save->idtr.attrib,
3037 save->idtr.limit, save->idtr.base);
3038 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
3039 save->tr.selector, save->tr.attrib,
3040 save->tr.limit, save->tr.base);
3041 pr_err("cpl: %d efer: %016llx\n",
3042 save->cpl, save->efer);
3043 pr_err("cr0: %016llx cr2: %016llx\n",
3044 save->cr0, save->cr2);
3045 pr_err("cr3: %016llx cr4: %016llx\n",
3046 save->cr3, save->cr4);
3047 pr_err("dr6: %016llx dr7: %016llx\n",
3048 save->dr6, save->dr7);
3049 pr_err("rip: %016llx rflags: %016llx\n",
3050 save->rip, save->rflags);
3051 pr_err("rsp: %016llx rax: %016llx\n",
3052 save->rsp, save->rax);
3053 pr_err("star: %016llx lstar: %016llx\n",
3054 save->star, save->lstar);
3055 pr_err("cstar: %016llx sfmask: %016llx\n",
3056 save->cstar, save->sfmask);
3057 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
3058 save->kernel_gs_base, save->sysenter_cs);
3059 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
3060 save->sysenter_esp, save->sysenter_eip);
3061 pr_err("gpat: %016llx dbgctl: %016llx\n",
3062 save->g_pat, save->dbgctl);
3063 pr_err("br_from: %016llx br_to: %016llx\n",
3064 save->br_from, save->br_to);
3065 pr_err("excp_from: %016llx excp_to: %016llx\n",
3066 save->last_excp_from, save->last_excp_to);
3067
3068}
3069
586f9607
AK		 3070static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3071{
3072 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3073
3074 *info1 = control->exit_info_1;
3075 *info2 = control->exit_info_2;
3076}
3077
851ba692 3078static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3079{
04d2cc77 3080 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 3081 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 3082 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 3083
aa17911e 3084 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
af9ca2d7 3085
4ee546b4 3086 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
2be4fc7a
JR		 3087 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3088 if (npt_enabled)
3089 vcpu->arch.cr3 = svm->vmcb->save.cr3;
af9ca2d7 3090
cd3ff653
JR		 3091 if (unlikely(svm->nested.exit_required)) {
3092 nested_svm_vmexit(svm);
3093 svm->nested.exit_required = false;
3094
3095 return 1;
3096 }
3097
2030753d 3098 if (is_guest_mode(vcpu)) {
410e4d57
JR		 3099 int vmexit;
3100
d8cabddf
JR		 3101 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3102 svm->vmcb->control.exit_info_1,
3103 svm->vmcb->control.exit_info_2,
3104 svm->vmcb->control.exit_int_info,
3105 svm->vmcb->control.exit_int_info_err);
3106
410e4d57
JR		 3107 vmexit = nested_svm_exit_special(svm);
3108
3109 if (vmexit == NESTED_EXIT_CONTINUE)
3110 vmexit = nested_svm_exit_handled(svm);
3111
3112 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 3113 return 1;
cf74a78b
AG		 3114 }
3115
a5c3832d
JR		 3116 svm_complete_interrupts(svm);
3117
04d2cc77
AK		 3118 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3119 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3120 kvm_run->fail_entry.hardware_entry_failure_reason
3121 = svm->vmcb->control.exit_code;
3f10c846
JR		 3122 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3123 dump_vmcb(vcpu);
04d2cc77
AK		 3124 return 0;
3125 }
3126
a2fa3e9f 3127 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 3128 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
55c5e464
JR		 3129 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3130 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
6aa8b732
AK		 3131 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3132 "exit_code 0x%x\n",
b8688d51 3133 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 3134 exit_code);
3135
9d8f549d 3136 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 3137 || !svm_exit_handlers[exit_code]) {
6aa8b732 3138 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 3139 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 3140 return 0;
3141 }
3142
851ba692 3143 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 3144}
3145
3146static void reload_tss(struct kvm_vcpu *vcpu)
3147{
3148 int cpu = raw_smp_processor_id();
3149
0fe1e009
TH		 3150 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3151 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 3152 load_TR_desc();
3153}
3154
e756fc62 3155static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 3156{
3157 int cpu = raw_smp_processor_id();
3158
0fe1e009 3159 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 3160
a2fa3e9f 3161 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 3162 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 3163 if (svm->asid_generation != sd->asid_generation)
3164 new_asid(svm, sd);
6aa8b732
AK		 3165}
3166
95ba8273
GN		 3167static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3168{
3169 struct vcpu_svm *svm = to_svm(vcpu);
3170
3171 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3172 vcpu->arch.hflags |= HF_NMI_MASK;
8a05a1b8 3173 set_intercept(svm, INTERCEPT_IRET);
95ba8273
GN		 3174 ++vcpu->stat.nmi_injections;
3175}
6aa8b732 3176
85f455f7 3177static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 3178{
3179 struct vmcb_control_area *control;
3180
e756fc62 3181 control = &svm->vmcb->control;
85f455f7 3182 control->int_vector = irq;
6aa8b732
AK		 3183 control->int_ctl &= ~V_INTR_PRIO_MASK;
3184 control->int_ctl |= V_IRQ_MASK |
3185 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
decdbf6a 3186 mark_dirty(svm->vmcb, VMCB_INTR);
6aa8b732
AK		 3187}
3188
66fd3f7f 3189static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 3190{
3191 struct vcpu_svm *svm = to_svm(vcpu);
3192
2af9194d 3193 BUG_ON(!(gif_set(svm)));
cf74a78b 3194
9fb2d2b4
GN		 3195 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3196 ++vcpu->stat.irq_injections;
3197
219b65dc
AG		 3198 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3199 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 3200}
3201
95ba8273 3202static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 3203{
3204 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 3205
2030753d 3206 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
88ab24ad
JR		 3207 return;
3208
95ba8273 3209 if (irr == -1)
aaacfc9a
JR		 3210 return;
3211
95ba8273 3212 if (tpr >= irr)
4ee546b4 3213 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
95ba8273 3214}
aaacfc9a 3215
95ba8273
GN		 3216static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3217{
3218 struct vcpu_svm *svm = to_svm(vcpu);
3219 struct vmcb *vmcb = svm->vmcb;
924584cc
JR		 3220 int ret;
3221 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3222 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3223 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3224
3225 return ret;
aaacfc9a
JR		 3226}
3227
3cfc3092
JK		 3228static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3229{
3230 struct vcpu_svm *svm = to_svm(vcpu);
3231
3232 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3233}
3234
3235static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3236{
3237 struct vcpu_svm *svm = to_svm(vcpu);
3238
3239 if (masked) {
3240 svm->vcpu.arch.hflags |= HF_NMI_MASK;
8a05a1b8 3241 set_intercept(svm, INTERCEPT_IRET);
3cfc3092
JK		 3242 } else {
3243 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
8a05a1b8 3244 clr_intercept(svm, INTERCEPT_IRET);
3cfc3092
JK		 3245 }
3246}
3247
78646121
GN		 3248static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3249{
3250 struct vcpu_svm *svm = to_svm(vcpu);
3251 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 3252 int ret;
3253
3254 if (!gif_set(svm) ||
3255 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3256 return 0;
3257
3258 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3259
2030753d 3260 if (is_guest_mode(vcpu))
7fcdb510
JR		 3261 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3262
3263 return ret;
78646121
GN		 3264}
3265
9222be18 3266static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 3267{
219b65dc 3268 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 3269
e0231715
JR		 3270 /*
3271 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3272 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3273 * get that intercept, this function will be called again though and
3274 * we'll get the vintr intercept.
3275 */
8fe54654 3276 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 3277 svm_set_vintr(svm);
3278 svm_inject_irq(svm, 0x0);
3279 }
85f455f7
ED		 3280}
3281
95ba8273 3282static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 3283{
04d2cc77 3284 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 3285
44c11430
GN		 3286 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3287 == HF_NMI_MASK)
3288 return; /* IRET will cause a vm exit */
3289
e0231715
JR		 3290 /*
3291 * Something prevents NMI from been injected. Single step over possible
3292 * problem (IRET or exception injection or interrupt shadow)
3293 */
6be7d306 3294 svm->nmi_singlestep = true;
44c11430
GN		 3295 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3296 update_db_intercept(vcpu);
c1150d8c
DL		 3297}
3298
cbc94022
IE		 3299static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3300{
3301 return 0;
3302}
3303
d9e368d6
AK		 3304static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3305{
f40f6a45 3306 to_svm(vcpu)->asid_generation--;
d9e368d6
AK		 3307}
3308
04d2cc77
AK		 3309static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3310{
3311}
3312
d7bf8221
JR		 3313static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3314{
3315 struct vcpu_svm *svm = to_svm(vcpu);
3316
2030753d 3317 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
88ab24ad
JR		 3318 return;
3319
4ee546b4 3320 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
d7bf8221 3321 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 3322 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 3323 }
3324}
3325
649d6864
JR		 3326static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3327{
3328 struct vcpu_svm *svm = to_svm(vcpu);
3329 u64 cr8;
3330
2030753d 3331 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
88ab24ad
JR		 3332 return;
3333
649d6864
JR		 3334 cr8 = kvm_get_cr8(vcpu);
3335 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3336 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3337}
3338
9222be18
GN		 3339static void svm_complete_interrupts(struct vcpu_svm *svm)
3340{
3341 u8 vector;
3342 int type;
3343 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 3344 unsigned int3_injected = svm->int3_injected;
3345
3346 svm->int3_injected = 0;
9222be18 3347
3842d135 3348 if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
44c11430 3349 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3842d135
AK		 3350 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3351 }
44c11430 3352
9222be18
GN		 3353 svm->vcpu.arch.nmi_injected = false;
3354 kvm_clear_exception_queue(&svm->vcpu);
3355 kvm_clear_interrupt_queue(&svm->vcpu);
3356
3357 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3358 return;
3359
3842d135
AK		 3360 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3361
9222be18
GN		 3362 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3363 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3364
3365 switch (type) {
3366 case SVM_EXITINTINFO_TYPE_NMI:
3367 svm->vcpu.arch.nmi_injected = true;
3368 break;
3369 case SVM_EXITINTINFO_TYPE_EXEPT:
66b7138f
JK		 3370 /*
3371 * In case of software exceptions, do not reinject the vector,
3372 * but re-execute the instruction instead. Rewind RIP first
3373 * if we emulated INT3 before.
3374 */
3375 if (kvm_exception_is_soft(vector)) {
3376 if (vector == BP_VECTOR && int3_injected &&
3377 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3378 kvm_rip_write(&svm->vcpu,
3379 kvm_rip_read(&svm->vcpu) -
3380 int3_injected);
9222be18 3381 break;
66b7138f 3382 }
9222be18
GN		 3383 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3384 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 3385 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 3386
3387 } else
ce7ddec4 3388 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 3389 break;
3390 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 3391 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 3392 break;
3393 default:
3394 break;
3395 }
3396}
3397
b463a6f7
AK		 3398static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3399{
3400 struct vcpu_svm *svm = to_svm(vcpu);
3401 struct vmcb_control_area *control = &svm->vmcb->control;
3402
3403 control->exit_int_info = control->event_inj;
3404 control->exit_int_info_err = control->event_inj_err;
3405 control->event_inj = 0;
3406 svm_complete_interrupts(svm);
3407}
3408
80e31d4f
AK		 3409#ifdef CONFIG_X86_64
3410#define R "r"
3411#else
3412#define R "e"
3413#endif
3414
851ba692 3415static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3416{
a2fa3e9f 3417 struct vcpu_svm *svm = to_svm(vcpu);
d9e368d6 3418
2041a06a
JR		 3419 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3420 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3421 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3422
cd3ff653
JR		 3423 /*
3424 * A vmexit emulation is required before the vcpu can be executed
3425 * again.
3426 */
3427 if (unlikely(svm->nested.exit_required))
3428 return;
3429
e756fc62 3430 pre_svm_run(svm);
6aa8b732 3431
649d6864
JR		 3432 sync_lapic_to_cr8(vcpu);
3433
cda0ffdd 3434 svm->vmcb->save.cr2 = vcpu->arch.cr2;
6aa8b732 3435
04d2cc77
AK		 3436 clgi();
3437
3438 local_irq_enable();
36241b8c 3439
6aa8b732 3440 asm volatile (
80e31d4f
AK		 3441 "push %%"R"bp; \n\t"
3442 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3443 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3444 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3445 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3446 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3447 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 3448#ifdef CONFIG_X86_64
fb3f0f51
RR		 3449 "mov %c[r8](%[svm]), %%r8 \n\t"
3450 "mov %c[r9](%[svm]), %%r9 \n\t"
3451 "mov %c[r10](%[svm]), %%r10 \n\t"
3452 "mov %c[r11](%[svm]), %%r11 \n\t"
3453 "mov %c[r12](%[svm]), %%r12 \n\t"
3454 "mov %c[r13](%[svm]), %%r13 \n\t"
3455 "mov %c[r14](%[svm]), %%r14 \n\t"
3456 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 3457#endif
3458
6aa8b732 3459 /* Enter guest mode */
80e31d4f
AK		 3460 "push %%"R"ax \n\t"
3461 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 3462 __ex(SVM_VMLOAD) "\n\t"
3463 __ex(SVM_VMRUN) "\n\t"
3464 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 3465 "pop %%"R"ax \n\t"
6aa8b732
AK		 3466
3467 /* Save guest registers, load host registers */
80e31d4f
AK		 3468 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3469 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3470 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3471 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3472 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3473 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 3474#ifdef CONFIG_X86_64
fb3f0f51
RR		 3475 "mov %%r8, %c[r8](%[svm]) \n\t"
3476 "mov %%r9, %c[r9](%[svm]) \n\t"
3477 "mov %%r10, %c[r10](%[svm]) \n\t"
3478 "mov %%r11, %c[r11](%[svm]) \n\t"
3479 "mov %%r12, %c[r12](%[svm]) \n\t"
3480 "mov %%r13, %c[r13](%[svm]) \n\t"
3481 "mov %%r14, %c[r14](%[svm]) \n\t"
3482 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 3483#endif
80e31d4f 3484 "pop %%"R"bp"
6aa8b732 3485 :
fb3f0f51 3486 : [svm]"a"(svm),
6aa8b732 3487 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 3488 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3489 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3490 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3491 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3492 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3493 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 3494#ifdef CONFIG_X86_64
ad312c7c
ZX		 3495 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3496 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3497 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3498 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3499 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3500 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3501 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3502 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 3503#endif
54a08c04 3504 : "cc", "memory"
80e31d4f 3505 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 3506#ifdef CONFIG_X86_64
54a08c04
LV		 3507 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3508#endif
3509 );
6aa8b732 3510
82ca2d10
AK		 3511#ifdef CONFIG_X86_64
3512 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3513#else
dacccfdd 3514 loadsegment(fs, svm->host.fs);
9581d442 3515#endif
6aa8b732
AK		 3516
3517 reload_tss(vcpu);
3518
56ba47dd
AK		 3519 local_irq_disable();
3520
3521 stgi();
3522
13c34e07
AK		 3523 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3524 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3525 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3526 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3527
d7bf8221
JR		 3528 sync_cr8_to_lapic(vcpu);
3529
a2fa3e9f 3530 svm->next_rip = 0;
9222be18 3531
631bc487
GN		 3532 /* if exit due to PF check for async PF */
3533 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3534 svm->apf_reason = kvm_read_and_reset_pf_reason();
3535
6de4f3ad
AK		 3536 if (npt_enabled) {
3537 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3538 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3539 }
fe5913e4
JR		 3540
3541 /*
3542 * We need to handle MC intercepts here before the vcpu has a chance to
3543 * change the physical cpu
3544 */
3545 if (unlikely(svm->vmcb->control.exit_code ==
3546 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3547 svm_handle_mce(svm);
8d28fec4
RJ		 3548
3549 mark_all_clean(svm->vmcb);
6aa8b732
AK		 3550}
3551
80e31d4f
AK		 3552#undef R
3553
6aa8b732
AK		 3554static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3555{
a2fa3e9f
GH		 3556 struct vcpu_svm *svm = to_svm(vcpu);
3557
3558 svm->vmcb->save.cr3 = root;
dcca1a65 3559 mark_dirty(svm->vmcb, VMCB_CR);
f40f6a45 3560 svm_flush_tlb(vcpu);
6aa8b732
AK		 3561}
3562
1c97f0a0
JR		 3563static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3564{
3565 struct vcpu_svm *svm = to_svm(vcpu);
3566
3567 svm->vmcb->control.nested_cr3 = root;
b2747166 3568 mark_dirty(svm->vmcb, VMCB_NPT);
1c97f0a0
JR		 3569
3570 /* Also sync guest cr3 here in case we live migrate */
3571 svm->vmcb->save.cr3 = vcpu->arch.cr3;
dcca1a65 3572 mark_dirty(svm->vmcb, VMCB_CR);
1c97f0a0 3573
f40f6a45 3574 svm_flush_tlb(vcpu);
1c97f0a0
JR		 3575}
3576
6aa8b732
AK		 3577static int is_disabled(void)
3578{
6031a61c
JR		 3579 u64 vm_cr;
3580
3581 rdmsrl(MSR_VM_CR, vm_cr);
3582 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3583 return 1;
3584
6aa8b732
AK		 3585 return 0;
3586}
3587
102d8325
IM		 3588static void
3589svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3590{
3591 /*
3592 * Patch in the VMMCALL instruction:
3593 */
3594 hypercall[0] = 0x0f;
3595 hypercall[1] = 0x01;
3596 hypercall[2] = 0xd9;
102d8325
IM		 3597}
3598
002c7f7c
YS		 3599static void svm_check_processor_compat(void *rtn)
3600{
3601 *(int *)rtn = 0;
3602}
3603
774ead3a
AK		 3604static bool svm_cpu_has_accelerated_tpr(void)
3605{
3606 return false;
3607}
3608
4b12f0de 3609static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3610{
3611 return 0;
3612}
3613
0e851880
SY		 3614static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3615{
3616}
3617
d4330ef2
JR		 3618static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3619{
c2c63a49 3620 switch (func) {
24d1b15f
JR		 3621 case 0x00000001:
3622 /* Mask out xsave bit as long as it is not supported by SVM */
3623 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3624 break;
4c62a2dc
JR		 3625 case 0x80000001:
3626 if (nested)
3627 entry->ecx |= (1 << 2); /* Set SVM bit */
3628 break;
c2c63a49
JR		 3629 case 0x8000000A:
3630 entry->eax = 1; /* SVM revision 1 */
3631 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3632 ASID emulation to nested SVM */
3633 entry->ecx = 0; /* Reserved */
7a190667
JR		 3634 entry->edx = 0; /* Per default do not support any
3635 additional features */
3636
3637 /* Support next_rip if host supports it */
2a6b20b8 3638 if (boot_cpu_has(X86_FEATURE_NRIPS))
7a190667 3639 entry->edx |= SVM_FEATURE_NRIP;
c2c63a49 3640
3d4aeaad
JR		 3641 /* Support NPT for the guest if enabled */
3642 if (npt_enabled)
3643 entry->edx |= SVM_FEATURE_NPT;
3644
c2c63a49
JR		 3645 break;
3646 }
d4330ef2
JR		 3647}
3648
229456fc 3649static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 3650 { SVM_EXIT_READ_CR0, "read_cr0" },
3651 { SVM_EXIT_READ_CR3, "read_cr3" },
3652 { SVM_EXIT_READ_CR4, "read_cr4" },
3653 { SVM_EXIT_READ_CR8, "read_cr8" },
3654 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3655 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3656 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3657 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3658 { SVM_EXIT_READ_DR0, "read_dr0" },
3659 { SVM_EXIT_READ_DR1, "read_dr1" },
3660 { SVM_EXIT_READ_DR2, "read_dr2" },
3661 { SVM_EXIT_READ_DR3, "read_dr3" },
3662 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3663 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3664 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3665 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3666 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3667 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3668 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3669 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3670 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3671 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3672 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3673 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3674 { SVM_EXIT_INTR, "interrupt" },
3675 { SVM_EXIT_NMI, "nmi" },
3676 { SVM_EXIT_SMI, "smi" },
3677 { SVM_EXIT_INIT, "init" },
3678 { SVM_EXIT_VINTR, "vintr" },
3679 { SVM_EXIT_CPUID, "cpuid" },
3680 { SVM_EXIT_INVD, "invd" },
3681 { SVM_EXIT_HLT, "hlt" },
3682 { SVM_EXIT_INVLPG, "invlpg" },
3683 { SVM_EXIT_INVLPGA, "invlpga" },
3684 { SVM_EXIT_IOIO, "io" },
3685 { SVM_EXIT_MSR, "msr" },
3686 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3687 { SVM_EXIT_SHUTDOWN, "shutdown" },
3688 { SVM_EXIT_VMRUN, "vmrun" },
3689 { SVM_EXIT_VMMCALL, "hypercall" },
3690 { SVM_EXIT_VMLOAD, "vmload" },
3691 { SVM_EXIT_VMSAVE, "vmsave" },
3692 { SVM_EXIT_STGI, "stgi" },
3693 { SVM_EXIT_CLGI, "clgi" },
3694 { SVM_EXIT_SKINIT, "skinit" },
3695 { SVM_EXIT_WBINVD, "wbinvd" },
3696 { SVM_EXIT_MONITOR, "monitor" },
3697 { SVM_EXIT_MWAIT, "mwait" },
3698 { SVM_EXIT_NPF, "npf" },
3699 { -1, NULL }
3700};
3701
17cc3935 3702static int svm_get_lpage_level(void)
344f414f 3703{
17cc3935 3704 return PT_PDPE_LEVEL;
344f414f
JR		 3705}
3706
4e47c7a6
SY		 3707static bool svm_rdtscp_supported(void)
3708{
3709 return false;
3710}
3711
f5f48ee1
SY		 3712static bool svm_has_wbinvd_exit(void)
3713{
3714 return true;
3715}
3716
02daab21
AK		 3717static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3718{
3719 struct vcpu_svm *svm = to_svm(vcpu);
3720
18c918c5 3721 set_exception_intercept(svm, NM_VECTOR);
66a562f7 3722 update_cr0_intercept(svm);
02daab21
AK		 3723}
3724
cbdd1bea 3725static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3726 .cpu_has_kvm_support = has_svm,
3727 .disabled_by_bios = is_disabled,
3728 .hardware_setup = svm_hardware_setup,
3729 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3730 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3731 .hardware_enable = svm_hardware_enable,
3732 .hardware_disable = svm_hardware_disable,
774ead3a 3733 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3734
3735 .vcpu_create = svm_create_vcpu,
3736 .vcpu_free = svm_free_vcpu,
04d2cc77 3737 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3738
04d2cc77 3739 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3740 .vcpu_load = svm_vcpu_load,
3741 .vcpu_put = svm_vcpu_put,
3742
3743 .set_guest_debug = svm_guest_debug,
3744 .get_msr = svm_get_msr,
3745 .set_msr = svm_set_msr,
3746 .get_segment_base = svm_get_segment_base,
3747 .get_segment = svm_get_segment,
3748 .set_segment = svm_set_segment,
2e4d2653 3749 .get_cpl = svm_get_cpl,
1747fb71 3750 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3751 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3752 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3753 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3754 .set_cr3 = svm_set_cr3,
3755 .set_cr4 = svm_set_cr4,
3756 .set_efer = svm_set_efer,
3757 .get_idt = svm_get_idt,
3758 .set_idt = svm_set_idt,
3759 .get_gdt = svm_get_gdt,
3760 .set_gdt = svm_set_gdt,
020df079 3761 .set_dr7 = svm_set_dr7,
6de4f3ad 3762 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3763 .get_rflags = svm_get_rflags,
3764 .set_rflags = svm_set_rflags,
6b52d186 3765 .fpu_activate = svm_fpu_activate,
02daab21 3766 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3767
6aa8b732 3768 .tlb_flush = svm_flush_tlb,
6aa8b732 3769
6aa8b732 3770 .run = svm_vcpu_run,
04d2cc77 3771 .handle_exit = handle_exit,
6aa8b732 3772 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3773 .set_interrupt_shadow = svm_set_interrupt_shadow,
3774 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3775 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3776 .set_irq = svm_set_irq,
95ba8273 3777 .set_nmi = svm_inject_nmi,
298101da 3778 .queue_exception = svm_queue_exception,
b463a6f7 3779 .cancel_injection = svm_cancel_injection,
78646121 3780 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3781 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3782 .get_nmi_mask = svm_get_nmi_mask,
3783 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3784 .enable_nmi_window = enable_nmi_window,
3785 .enable_irq_window = enable_irq_window,
3786 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3787
3788 .set_tss_addr = svm_set_tss_addr,
67253af5 3789 .get_tdp_level = get_npt_level,
4b12f0de 3790 .get_mt_mask = svm_get_mt_mask,
229456fc 3791
586f9607 3792 .get_exit_info = svm_get_exit_info,
229456fc 3793 .exit_reasons_str = svm_exit_reasons_str,
586f9607 3794
17cc3935 3795 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3796
3797 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3798
3799 .rdtscp_supported = svm_rdtscp_supported,
d4330ef2
JR		 3800
3801 .set_supported_cpuid = svm_set_supported_cpuid,
f5f48ee1
SY		 3802
3803 .has_wbinvd_exit = svm_has_wbinvd_exit,
99e3e30a
ZA		 3804
3805 .write_tsc_offset = svm_write_tsc_offset,
e48672fa 3806 .adjust_tsc_offset = svm_adjust_tsc_offset,
1c97f0a0
JR		 3807
3808 .set_tdp_cr3 = set_tdp_cr3,
6aa8b732
AK		 3809};
3810
3811static int __init svm_init(void)
3812{
cb498ea2 3813 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
0ee75bea 3814 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 3815}
3816
3817static void __exit svm_exit(void)
3818{
cb498ea2 3819 kvm_exit();
6aa8b732
AK		 3820}
3821
3822module_init(svm_init)
3823module_exit(svm_exit)
kernel source for telekom puls (alcatel/mediatek)