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KVM: SVM: Add clean-bit for interrupt state
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
9611c187 7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
edf88417
AK		 17#include <linux/kvm_host.h>
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
5fdbf976 21#include "kvm_cache_regs.h"
fe4c7b19 22#include "x86.h"
e495606d 23
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/vmalloc.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
6aa8b732 31
67ec6607 32#include <asm/tlbflush.h>
e495606d 33#include <asm/desc.h>
631bc487 34#include <asm/kvm_para.h>
6aa8b732 35
63d1142f 36#include <asm/virtext.h>
229456fc 37#include "trace.h"
63d1142f 38
4ecac3fd
AK		 39#define __ex(x) __kvm_handle_fault_on_reboot(x)
40
6aa8b732
AK		 41MODULE_AUTHOR("Qumranet");
42MODULE_LICENSE("GPL");
43
44#define IOPM_ALLOC_ORDER 2
45#define MSRPM_ALLOC_ORDER 1
46
6aa8b732
AK		 47#define SEG_TYPE_LDT 2
48#define SEG_TYPE_BUSY_TSS16 3
49
6bc31bdc
AP		 50#define SVM_FEATURE_NPT (1 << 0)
51#define SVM_FEATURE_LBRV (1 << 1)
52#define SVM_FEATURE_SVML (1 << 2)
53#define SVM_FEATURE_NRIP (1 << 3)
54#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 55
410e4d57
JR		 56#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
59
24e09cbf
JR		 60#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
61
67ec6607
JR		 62static bool erratum_383_found __read_mostly;
63
6c8166a7
AK		 64static const u32 host_save_user_msrs[] = {
65#ifdef CONFIG_X86_64
66 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
67 MSR_FS_BASE,
68#endif
69 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
70};
71
72#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
73
74struct kvm_vcpu;
75
e6aa9abd
JR		 76struct nested_state {
77 struct vmcb *hsave;
78 u64 hsave_msr;
4a810181 79 u64 vm_cr_msr;
e6aa9abd
JR		 80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
ce2ac085 87 u64 vmcb_iopm;
aad42c64 88
cd3ff653
JR		 89 /* A VMEXIT is required but not yet emulated */
90 bool exit_required;
91
cda00082
JR		 92 /*
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
95 */
96 unsigned long vmexit_rip;
97 unsigned long vmexit_rsp;
98 unsigned long vmexit_rax;
99
aad42c64 100 /* cache for intercepts of the guest */
4ee546b4 101 u32 intercept_cr;
3aed041a 102 u32 intercept_dr;
aad42c64
JR		 103 u32 intercept_exceptions;
104 u64 intercept;
105
5bd2edc3
JR		 106 /* Nested Paging related state */
107 u64 nested_cr3;
e6aa9abd
JR		 108};
109
323c3d80
JR		 110#define MSRPM_OFFSETS 16
111static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
112
6c8166a7
AK		 113struct vcpu_svm {
114 struct kvm_vcpu vcpu;
115 struct vmcb *vmcb;
116 unsigned long vmcb_pa;
117 struct svm_cpu_data *svm_data;
118 uint64_t asid_generation;
119 uint64_t sysenter_esp;
120 uint64_t sysenter_eip;
121
122 u64 next_rip;
123
124 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
afe9e66f 125 struct {
dacccfdd
AK		 126 u16 fs;
127 u16 gs;
128 u16 ldt;
afe9e66f
AK		 129 u64 gs_base;
130 } host;
6c8166a7
AK		 131
132 u32 *msrpm;
6c8166a7 133
e6aa9abd 134 struct nested_state nested;
6be7d306
JK		 135
136 bool nmi_singlestep;
66b7138f
JK		 137
138 unsigned int3_injected;
139 unsigned long int3_rip;
631bc487 140 u32 apf_reason;
6c8166a7
AK		 141};
142
455716fa
JR		 143#define MSR_INVALID 0xffffffffU
144
ac72a9b7
JR		 145static struct svm_direct_access_msrs {
146 u32 index; /* Index of the MSR */
147 bool always; /* True if intercept is always on */
148} direct_access_msrs[] = {
8c06585d 149 { .index = MSR_STAR, .always = true },
ac72a9b7
JR		 150 { .index = MSR_IA32_SYSENTER_CS, .always = true },
151#ifdef CONFIG_X86_64
152 { .index = MSR_GS_BASE, .always = true },
153 { .index = MSR_FS_BASE, .always = true },
154 { .index = MSR_KERNEL_GS_BASE, .always = true },
155 { .index = MSR_LSTAR, .always = true },
156 { .index = MSR_CSTAR, .always = true },
157 { .index = MSR_SYSCALL_MASK, .always = true },
158#endif
159 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
160 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
161 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
162 { .index = MSR_IA32_LASTINTTOIP, .always = false },
163 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 164};
165
709ddebf
JR		 166/* enable NPT for AMD64 and X86 with PAE */
167#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
168static bool npt_enabled = true;
169#else
e0231715 170static bool npt_enabled;
709ddebf 171#endif
6c7dac72
JR		 172static int npt = 1;
173
174module_param(npt, int, S_IRUGO);
e3da3acd 175
4b6e4dca 176static int nested = 1;
236de055
AG		 177module_param(nested, int, S_IRUGO);
178
44874f84 179static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 180static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 181
410e4d57 182static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 183static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 184static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 185static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
186 bool has_error_code, u32 error_code);
187
8d28fec4 188enum {
116a0a23
JR		 189 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
190 pause filter count */
f56838e4 191 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
d48086d1 192 VMCB_ASID, /* ASID */
decdbf6a 193 VMCB_INTR, /* int_ctl, int_vector */
8d28fec4
RJ		 194 VMCB_DIRTY_MAX,
195};
196
decdbf6a
JR		 197/* TPR is always written before VMRUN */
198#define VMCB_ALWAYS_DIRTY_MASK (1U << VMCB_INTR)
8d28fec4
RJ		 199
200static inline void mark_all_dirty(struct vmcb *vmcb)
201{
202 vmcb->control.clean = 0;
203}
204
205static inline void mark_all_clean(struct vmcb *vmcb)
206{
207 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
208 & ~VMCB_ALWAYS_DIRTY_MASK;
209}
210
211static inline void mark_dirty(struct vmcb *vmcb, int bit)
212{
213 vmcb->control.clean &= ~(1 << bit);
214}
215
a2fa3e9f
GH		 216static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
217{
fb3f0f51 218 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 219}
220
384c6368
JR		 221static void recalc_intercepts(struct vcpu_svm *svm)
222{
223 struct vmcb_control_area *c, *h;
224 struct nested_state *g;
225
116a0a23
JR		 226 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
227
384c6368
JR		 228 if (!is_guest_mode(&svm->vcpu))
229 return;
230
231 c = &svm->vmcb->control;
232 h = &svm->nested.hsave->control;
233 g = &svm->nested;
234
4ee546b4 235 c->intercept_cr = h->intercept_cr | g->intercept_cr;
3aed041a 236 c->intercept_dr = h->intercept_dr | g->intercept_dr;
384c6368
JR		 237 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
238 c->intercept = h->intercept | g->intercept;
239}
240
4ee546b4
RJ		 241static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
242{
243 if (is_guest_mode(&svm->vcpu))
244 return svm->nested.hsave;
245 else
246 return svm->vmcb;
247}
248
249static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
250{
251 struct vmcb *vmcb = get_host_vmcb(svm);
252
253 vmcb->control.intercept_cr |= (1U << bit);
254
255 recalc_intercepts(svm);
256}
257
258static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
259{
260 struct vmcb *vmcb = get_host_vmcb(svm);
261
262 vmcb->control.intercept_cr &= ~(1U << bit);
263
264 recalc_intercepts(svm);
265}
266
267static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
268{
269 struct vmcb *vmcb = get_host_vmcb(svm);
270
271 return vmcb->control.intercept_cr & (1U << bit);
272}
273
3aed041a
JR		 274static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
275{
276 struct vmcb *vmcb = get_host_vmcb(svm);
277
278 vmcb->control.intercept_dr |= (1U << bit);
279
280 recalc_intercepts(svm);
281}
282
283static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
284{
285 struct vmcb *vmcb = get_host_vmcb(svm);
286
287 vmcb->control.intercept_dr &= ~(1U << bit);
288
289 recalc_intercepts(svm);
290}
291
18c918c5
JR		 292static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
293{
294 struct vmcb *vmcb = get_host_vmcb(svm);
295
296 vmcb->control.intercept_exceptions |= (1U << bit);
297
298 recalc_intercepts(svm);
299}
300
301static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
302{
303 struct vmcb *vmcb = get_host_vmcb(svm);
304
305 vmcb->control.intercept_exceptions &= ~(1U << bit);
306
307 recalc_intercepts(svm);
308}
309
8a05a1b8
JR		 310static inline void set_intercept(struct vcpu_svm *svm, int bit)
311{
312 struct vmcb *vmcb = get_host_vmcb(svm);
313
314 vmcb->control.intercept |= (1ULL << bit);
315
316 recalc_intercepts(svm);
317}
318
319static inline void clr_intercept(struct vcpu_svm *svm, int bit)
320{
321 struct vmcb *vmcb = get_host_vmcb(svm);
322
323 vmcb->control.intercept &= ~(1ULL << bit);
324
325 recalc_intercepts(svm);
326}
327
2af9194d
JR		 328static inline void enable_gif(struct vcpu_svm *svm)
329{
330 svm->vcpu.arch.hflags |= HF_GIF_MASK;
331}
332
333static inline void disable_gif(struct vcpu_svm *svm)
334{
335 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
336}
337
338static inline bool gif_set(struct vcpu_svm *svm)
339{
340 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
341}
342
4866d5e3 343static unsigned long iopm_base;
6aa8b732
AK		 344
345struct kvm_ldttss_desc {
346 u16 limit0;
347 u16 base0;
e0231715
JR		 348 unsigned base1:8, type:5, dpl:2, p:1;
349 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 350 u32 base3;
351 u32 zero1;
352} __attribute__((packed));
353
354struct svm_cpu_data {
355 int cpu;
356
5008fdf5
AK		 357 u64 asid_generation;
358 u32 max_asid;
359 u32 next_asid;
6aa8b732
AK		 360 struct kvm_ldttss_desc *tss_desc;
361
362 struct page *save_area;
363};
364
365static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 366static uint32_t svm_features;
6aa8b732
AK		 367
368struct svm_init_data {
369 int cpu;
370 int r;
371};
372
373static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
374
9d8f549d 375#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 376#define MSRS_RANGE_SIZE 2048
377#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
378
455716fa
JR		 379static u32 svm_msrpm_offset(u32 msr)
380{
381 u32 offset;
382 int i;
383
384 for (i = 0; i < NUM_MSR_MAPS; i++) {
385 if (msr < msrpm_ranges[i] ||
386 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
387 continue;
388
389 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
390 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
391
392 /* Now we have the u8 offset - but need the u32 offset */
393 return offset / 4;
394 }
395
396 /* MSR not in any range */
397 return MSR_INVALID;
398}
399
6aa8b732
AK		 400#define MAX_INST_SIZE 15
401
6aa8b732
AK		 402static inline void clgi(void)
403{
4ecac3fd 404 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 405}
406
407static inline void stgi(void)
408{
4ecac3fd 409 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 410}
411
412static inline void invlpga(unsigned long addr, u32 asid)
413{
e0231715 414 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 415}
416
6aa8b732
AK		 417static inline void force_new_asid(struct kvm_vcpu *vcpu)
418{
a2fa3e9f 419 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 420}
421
422static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
423{
424 force_new_asid(vcpu);
425}
426
4b16184c
JR		 427static int get_npt_level(void)
428{
429#ifdef CONFIG_X86_64
430 return PT64_ROOT_LEVEL;
431#else
432 return PT32E_ROOT_LEVEL;
433#endif
434}
435
6aa8b732
AK		 436static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
437{
6dc696d4 438 vcpu->arch.efer = efer;
709ddebf 439 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 440 efer &= ~EFER_LME;
6aa8b732 441
9962d032 442 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
6aa8b732
AK		 443}
444
6aa8b732
AK		 445static int is_external_interrupt(u32 info)
446{
447 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
448 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
449}
450
2809f5d2
GC		 451static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
452{
453 struct vcpu_svm *svm = to_svm(vcpu);
454 u32 ret = 0;
455
456 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 457 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 458 return ret & mask;
459}
460
461static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
462{
463 struct vcpu_svm *svm = to_svm(vcpu);
464
465 if (mask == 0)
466 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
467 else
468 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
469
470}
471
6aa8b732
AK		 472static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
473{
a2fa3e9f
GH		 474 struct vcpu_svm *svm = to_svm(vcpu);
475
6bc31bdc
AP		 476 if (svm->vmcb->control.next_rip != 0)
477 svm->next_rip = svm->vmcb->control.next_rip;
478
a2fa3e9f 479 if (!svm->next_rip) {
851ba692 480 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 481 EMULATE_DONE)
482 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 483 return;
484 }
5fdbf976
MT		 485 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
486 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
487 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 488
5fdbf976 489 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 490 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 491}
492
116a4752 493static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 494 bool has_error_code, u32 error_code,
495 bool reinject)
116a4752
JK		 496{
497 struct vcpu_svm *svm = to_svm(vcpu);
498
e0231715
JR		 499 /*
500 * If we are within a nested VM we'd better #VMEXIT and let the guest
501 * handle the exception
502 */
ce7ddec4
JR		 503 if (!reinject &&
504 nested_svm_check_exception(svm, nr, has_error_code, error_code))
116a4752
JK		 505 return;
506
2a6b20b8 507 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
66b7138f
JK		 508 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
509
510 /*
511 * For guest debugging where we have to reinject #BP if some
512 * INT3 is guest-owned:
513 * Emulate nRIP by moving RIP forward. Will fail if injection
514 * raises a fault that is not intercepted. Still better than
515 * failing in all cases.
516 */
517 skip_emulated_instruction(&svm->vcpu);
518 rip = kvm_rip_read(&svm->vcpu);
519 svm->int3_rip = rip + svm->vmcb->save.cs.base;
520 svm->int3_injected = rip - old_rip;
521 }
522
116a4752
JK		 523 svm->vmcb->control.event_inj = nr
524 | SVM_EVTINJ_VALID
525 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
526 | SVM_EVTINJ_TYPE_EXEPT;
527 svm->vmcb->control.event_inj_err = error_code;
528}
529
67ec6607
JR		 530static void svm_init_erratum_383(void)
531{
532 u32 low, high;
533 int err;
534 u64 val;
535
1be85a6d 536 if (!cpu_has_amd_erratum(amd_erratum_383))
67ec6607
JR		 537 return;
538
539 /* Use _safe variants to not break nested virtualization */
540 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
541 if (err)
542 return;
543
544 val |= (1ULL << 47);
545
546 low = lower_32_bits(val);
547 high = upper_32_bits(val);
548
549 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
550
551 erratum_383_found = true;
552}
553
6aa8b732
AK		 554static int has_svm(void)
555{
63d1142f 556 const char *msg;
6aa8b732 557
63d1142f 558 if (!cpu_has_svm(&msg)) {
ff81ff10 559 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 560 return 0;
561 }
562
6aa8b732
AK		 563 return 1;
564}
565
566static void svm_hardware_disable(void *garbage)
567{
2c8dceeb 568 cpu_svm_disable();
6aa8b732
AK		 569}
570
10474ae8 571static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 572{
573
0fe1e009 574 struct svm_cpu_data *sd;
6aa8b732 575 uint64_t efer;
89a27f4d 576 struct desc_ptr gdt_descr;
6aa8b732
AK		 577 struct desc_struct *gdt;
578 int me = raw_smp_processor_id();
579
10474ae8
AG		 580 rdmsrl(MSR_EFER, efer);
581 if (efer & EFER_SVME)
582 return -EBUSY;
583
6aa8b732 584 if (!has_svm()) {
e6732a5a
ZA		 585 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
586 me);
10474ae8 587 return -EINVAL;
6aa8b732 588 }
0fe1e009 589 sd = per_cpu(svm_data, me);
6aa8b732 590
0fe1e009 591 if (!sd) {
e6732a5a 592 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 593 me);
10474ae8 594 return -EINVAL;
6aa8b732
AK		 595 }
596
0fe1e009
TH		 597 sd->asid_generation = 1;
598 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
599 sd->next_asid = sd->max_asid + 1;
6aa8b732 600
d6ab1ed4 601 native_store_gdt(&gdt_descr);
89a27f4d 602 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 603 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 604
9962d032 605 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 606
d0316554 607 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8 608
67ec6607
JR		 609 svm_init_erratum_383();
610
10474ae8 611 return 0;
6aa8b732
AK		 612}
613
0da1db75
JR		 614static void svm_cpu_uninit(int cpu)
615{
0fe1e009 616 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 617
0fe1e009 618 if (!sd)
0da1db75
JR		 619 return;
620
621 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 622 __free_page(sd->save_area);
623 kfree(sd);
0da1db75
JR		 624}
625
6aa8b732
AK		 626static int svm_cpu_init(int cpu)
627{
0fe1e009 628 struct svm_cpu_data *sd;
6aa8b732
AK		 629 int r;
630
0fe1e009
TH		 631 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
632 if (!sd)
6aa8b732 633 return -ENOMEM;
0fe1e009
TH		 634 sd->cpu = cpu;
635 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 636 r = -ENOMEM;
0fe1e009 637 if (!sd->save_area)
6aa8b732
AK		 638 goto err_1;
639
0fe1e009 640 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 641
642 return 0;
643
644err_1:
0fe1e009 645 kfree(sd);
6aa8b732
AK		 646 return r;
647
648}
649
ac72a9b7
JR		 650static bool valid_msr_intercept(u32 index)
651{
652 int i;
653
654 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
655 if (direct_access_msrs[i].index == index)
656 return true;
657
658 return false;
659}
660
bfc733a7
RR		 661static void set_msr_interception(u32 *msrpm, unsigned msr,
662 int read, int write)
6aa8b732 663{
455716fa
JR		 664 u8 bit_read, bit_write;
665 unsigned long tmp;
666 u32 offset;
6aa8b732 667
ac72a9b7
JR		 668 /*
669 * If this warning triggers extend the direct_access_msrs list at the
670 * beginning of the file
671 */
672 WARN_ON(!valid_msr_intercept(msr));
673
455716fa
JR		 674 offset = svm_msrpm_offset(msr);
675 bit_read = 2 * (msr & 0x0f);
676 bit_write = 2 * (msr & 0x0f) + 1;
677 tmp = msrpm[offset];
678
679 BUG_ON(offset == MSR_INVALID);
680
681 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
682 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
683
684 msrpm[offset] = tmp;
6aa8b732
AK		 685}
686
f65c229c 687static void svm_vcpu_init_msrpm(u32 *msrpm)
6aa8b732
AK		 688{
689 int i;
690
f65c229c
JR		 691 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
692
ac72a9b7
JR		 693 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
694 if (!direct_access_msrs[i].always)
695 continue;
696
697 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
698 }
f65c229c
JR		 699}
700
323c3d80
JR		 701static void add_msr_offset(u32 offset)
702{
703 int i;
704
705 for (i = 0; i < MSRPM_OFFSETS; ++i) {
706
707 /* Offset already in list? */
708 if (msrpm_offsets[i] == offset)
bfc733a7 709 return;
323c3d80
JR		 710
711 /* Slot used by another offset? */
712 if (msrpm_offsets[i] != MSR_INVALID)
713 continue;
714
715 /* Add offset to list */
716 msrpm_offsets[i] = offset;
717
718 return;
6aa8b732 719 }
323c3d80
JR		 720
721 /*
722 * If this BUG triggers the msrpm_offsets table has an overflow. Just
723 * increase MSRPM_OFFSETS in this case.
724 */
bfc733a7 725 BUG();
6aa8b732
AK		 726}
727
323c3d80 728static void init_msrpm_offsets(void)
f65c229c 729{
323c3d80 730 int i;
f65c229c 731
323c3d80
JR		 732 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
733
734 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
735 u32 offset;
736
737 offset = svm_msrpm_offset(direct_access_msrs[i].index);
738 BUG_ON(offset == MSR_INVALID);
739
740 add_msr_offset(offset);
741 }
f65c229c
JR		 742}
743
24e09cbf
JR		 744static void svm_enable_lbrv(struct vcpu_svm *svm)
745{
746 u32 *msrpm = svm->msrpm;
747
748 svm->vmcb->control.lbr_ctl = 1;
749 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
750 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
751 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
752 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
753}
754
755static void svm_disable_lbrv(struct vcpu_svm *svm)
756{
757 u32 *msrpm = svm->msrpm;
758
759 svm->vmcb->control.lbr_ctl = 0;
760 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
761 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
762 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
763 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
764}
765
6aa8b732
AK		 766static __init int svm_hardware_setup(void)
767{
768 int cpu;
769 struct page *iopm_pages;
f65c229c 770 void *iopm_va;
6aa8b732
AK		 771 int r;
772
6aa8b732
AK		 773 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
774
775 if (!iopm_pages)
776 return -ENOMEM;
c8681339
AL		 777
778 iopm_va = page_address(iopm_pages);
779 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 780 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
781
323c3d80
JR		 782 init_msrpm_offsets();
783
50a37eb4
JR		 784 if (boot_cpu_has(X86_FEATURE_NX))
785 kvm_enable_efer_bits(EFER_NX);
786
1b2fd70c
AG		 787 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
788 kvm_enable_efer_bits(EFER_FFXSR);
789
236de055
AG		 790 if (nested) {
791 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
eec4b140 792 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
236de055
AG		 793 }
794
3230bb47 795 for_each_possible_cpu(cpu) {
6aa8b732
AK		 796 r = svm_cpu_init(cpu);
797 if (r)
f65c229c 798 goto err;
6aa8b732 799 }
33bd6a0b
JR		 800
801 svm_features = cpuid_edx(SVM_CPUID_FUNC);
802
2a6b20b8 803 if (!boot_cpu_has(X86_FEATURE_NPT))
e3da3acd
JR		 804 npt_enabled = false;
805
6c7dac72
JR		 806 if (npt_enabled && !npt) {
807 printk(KERN_INFO "kvm: Nested Paging disabled\n");
808 npt_enabled = false;
809 }
810
18552672 811 if (npt_enabled) {
e3da3acd 812 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 813 kvm_enable_tdp();
5f4cb662
JR		 814 } else
815 kvm_disable_tdp();
e3da3acd 816
6aa8b732
AK		 817 return 0;
818
f65c229c 819err:
6aa8b732
AK		 820 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
821 iopm_base = 0;
822 return r;
823}
824
825static __exit void svm_hardware_unsetup(void)
826{
0da1db75
JR		 827 int cpu;
828
3230bb47 829 for_each_possible_cpu(cpu)
0da1db75
JR		 830 svm_cpu_uninit(cpu);
831
6aa8b732 832 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 833 iopm_base = 0;
6aa8b732
AK		 834}
835
836static void init_seg(struct vmcb_seg *seg)
837{
838 seg->selector = 0;
839 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 840 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 841 seg->limit = 0xffff;
842 seg->base = 0;
843}
844
845static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
846{
847 seg->selector = 0;
848 seg->attrib = SVM_SELECTOR_P_MASK | type;
849 seg->limit = 0xffff;
850 seg->base = 0;
851}
852
f4e1b3c8
ZA		 853static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
854{
855 struct vcpu_svm *svm = to_svm(vcpu);
856 u64 g_tsc_offset = 0;
857
2030753d 858 if (is_guest_mode(vcpu)) {
f4e1b3c8
ZA		 859 g_tsc_offset = svm->vmcb->control.tsc_offset -
860 svm->nested.hsave->control.tsc_offset;
861 svm->nested.hsave->control.tsc_offset = offset;
862 }
863
864 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
116a0a23
JR		 865
866 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
f4e1b3c8
ZA		 867}
868
e48672fa
ZA		 869static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
870{
871 struct vcpu_svm *svm = to_svm(vcpu);
872
873 svm->vmcb->control.tsc_offset += adjustment;
2030753d 874 if (is_guest_mode(vcpu))
e48672fa 875 svm->nested.hsave->control.tsc_offset += adjustment;
116a0a23 876 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
e48672fa
ZA		 877}
878
e6101a96 879static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 880{
e6101a96
JR		 881 struct vmcb_control_area *control = &svm->vmcb->control;
882 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 883
bff78274 884 svm->vcpu.fpu_active = 1;
4ee546b4 885 svm->vcpu.arch.hflags = 0;
bff78274 886
4ee546b4
RJ		 887 set_cr_intercept(svm, INTERCEPT_CR0_READ);
888 set_cr_intercept(svm, INTERCEPT_CR3_READ);
889 set_cr_intercept(svm, INTERCEPT_CR4_READ);
890 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
891 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
892 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
893 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
6aa8b732 894
3aed041a
JR		 895 set_dr_intercept(svm, INTERCEPT_DR0_READ);
896 set_dr_intercept(svm, INTERCEPT_DR1_READ);
897 set_dr_intercept(svm, INTERCEPT_DR2_READ);
898 set_dr_intercept(svm, INTERCEPT_DR3_READ);
899 set_dr_intercept(svm, INTERCEPT_DR4_READ);
900 set_dr_intercept(svm, INTERCEPT_DR5_READ);
901 set_dr_intercept(svm, INTERCEPT_DR6_READ);
902 set_dr_intercept(svm, INTERCEPT_DR7_READ);
903
904 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
905 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
906 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
907 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
908 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
909 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
910 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
911 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
6aa8b732 912
18c918c5
JR		 913 set_exception_intercept(svm, PF_VECTOR);
914 set_exception_intercept(svm, UD_VECTOR);
915 set_exception_intercept(svm, MC_VECTOR);
6aa8b732 916
8a05a1b8
JR		 917 set_intercept(svm, INTERCEPT_INTR);
918 set_intercept(svm, INTERCEPT_NMI);
919 set_intercept(svm, INTERCEPT_SMI);
920 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
921 set_intercept(svm, INTERCEPT_CPUID);
922 set_intercept(svm, INTERCEPT_INVD);
923 set_intercept(svm, INTERCEPT_HLT);
924 set_intercept(svm, INTERCEPT_INVLPG);
925 set_intercept(svm, INTERCEPT_INVLPGA);
926 set_intercept(svm, INTERCEPT_IOIO_PROT);
927 set_intercept(svm, INTERCEPT_MSR_PROT);
928 set_intercept(svm, INTERCEPT_TASK_SWITCH);
929 set_intercept(svm, INTERCEPT_SHUTDOWN);
930 set_intercept(svm, INTERCEPT_VMRUN);
931 set_intercept(svm, INTERCEPT_VMMCALL);
932 set_intercept(svm, INTERCEPT_VMLOAD);
933 set_intercept(svm, INTERCEPT_VMSAVE);
934 set_intercept(svm, INTERCEPT_STGI);
935 set_intercept(svm, INTERCEPT_CLGI);
936 set_intercept(svm, INTERCEPT_SKINIT);
937 set_intercept(svm, INTERCEPT_WBINVD);
938 set_intercept(svm, INTERCEPT_MONITOR);
939 set_intercept(svm, INTERCEPT_MWAIT);
6aa8b732
AK		 940
941 control->iopm_base_pa = iopm_base;
f65c229c 942 control->msrpm_base_pa = __pa(svm->msrpm);
6aa8b732
AK		 943 control->int_ctl = V_INTR_MASKING_MASK;
944
945 init_seg(&save->es);
946 init_seg(&save->ss);
947 init_seg(&save->ds);
948 init_seg(&save->fs);
949 init_seg(&save->gs);
950
951 save->cs.selector = 0xf000;
952 /* Executable/Readable Code Segment */
953 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
954 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
955 save->cs.limit = 0xffff;
d92899a0
AK		 956 /*
957 * cs.base should really be 0xffff0000, but vmx can't handle that, so
958 * be consistent with it.
959 *
960 * Replace when we have real mode working for vmx.
961 */
962 save->cs.base = 0xf0000;
6aa8b732
AK		 963
964 save->gdtr.limit = 0xffff;
965 save->idtr.limit = 0xffff;
966
967 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
968 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
969
eaa48512 970 svm_set_efer(&svm->vcpu, 0);
d77c26fc 971 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 972 save->dr7 = 0x400;
973 save->rflags = 2;
974 save->rip = 0x0000fff0;
5fdbf976 975 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 976
e0231715
JR		 977 /*
978 * This is the guest-visible cr0 value.
18fa000a 979 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 980 */
678041ad
MT		 981 svm->vcpu.arch.cr0 = 0;
982 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
18fa000a 983
66aee91a 984 save->cr4 = X86_CR4_PAE;
6aa8b732 985 /* rdx = ?? */
709ddebf
JR		 986
987 if (npt_enabled) {
988 /* Setup VMCB for Nested Paging */
989 control->nested_ctl = 1;
8a05a1b8
JR		 990 clr_intercept(svm, INTERCEPT_TASK_SWITCH);
991 clr_intercept(svm, INTERCEPT_INVLPG);
18c918c5 992 clr_exception_intercept(svm, PF_VECTOR);
4ee546b4
RJ		 993 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
994 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
709ddebf 995 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 996 save->cr3 = 0;
997 save->cr4 = 0;
998 }
a79d2f18 999 force_new_asid(&svm->vcpu);
1371d904 1000
e6aa9abd 1001 svm->nested.vmcb = 0;
2af9194d
JR		 1002 svm->vcpu.arch.hflags = 0;
1003
2a6b20b8 1004 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
565d0998 1005 control->pause_filter_count = 3000;
8a05a1b8 1006 set_intercept(svm, INTERCEPT_PAUSE);
565d0998
ML		 1007 }
1008
8d28fec4
RJ		 1009 mark_all_dirty(svm->vmcb);
1010
2af9194d 1011 enable_gif(svm);
6aa8b732
AK		 1012}
1013
e00c8cf2 1014static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 1015{
1016 struct vcpu_svm *svm = to_svm(vcpu);
1017
e6101a96 1018 init_vmcb(svm);
70433389 1019
c5af89b6 1020 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 1021 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 1022 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1023 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 1024 }
5fdbf976
MT		 1025 vcpu->arch.regs_avail = ~0;
1026 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 1027
1028 return 0;
04d2cc77
AK		 1029}
1030
fb3f0f51 1031static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 1032{
a2fa3e9f 1033 struct vcpu_svm *svm;
6aa8b732 1034 struct page *page;
f65c229c 1035 struct page *msrpm_pages;
b286d5d8 1036 struct page *hsave_page;
3d6368ef 1037 struct page *nested_msrpm_pages;
fb3f0f51 1038 int err;
6aa8b732 1039
c16f862d 1040 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 1041 if (!svm) {
1042 err = -ENOMEM;
1043 goto out;
1044 }
1045
1046 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1047 if (err)
1048 goto free_svm;
1049
b7af4043 1050 err = -ENOMEM;
6aa8b732 1051 page = alloc_page(GFP_KERNEL);
b7af4043 1052 if (!page)
fb3f0f51 1053 goto uninit;
6aa8b732 1054
f65c229c
JR		 1055 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1056 if (!msrpm_pages)
b7af4043 1057 goto free_page1;
3d6368ef
AG		 1058
1059 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1060 if (!nested_msrpm_pages)
b7af4043 1061 goto free_page2;
f65c229c 1062
b286d5d8
AG		 1063 hsave_page = alloc_page(GFP_KERNEL);
1064 if (!hsave_page)
b7af4043
TY		 1065 goto free_page3;
1066
e6aa9abd 1067 svm->nested.hsave = page_address(hsave_page);
b286d5d8 1068
b7af4043
TY		 1069 svm->msrpm = page_address(msrpm_pages);
1070 svm_vcpu_init_msrpm(svm->msrpm);
1071
e6aa9abd 1072 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 1073 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 1074
a2fa3e9f
GH		 1075 svm->vmcb = page_address(page);
1076 clear_page(svm->vmcb);
1077 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1078 svm->asid_generation = 0;
e6101a96 1079 init_vmcb(svm);
99e3e30a 1080 kvm_write_tsc(&svm->vcpu, 0);
a2fa3e9f 1081
10ab25cd
JK		 1082 err = fx_init(&svm->vcpu);
1083 if (err)
1084 goto free_page4;
1085
ad312c7c 1086 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 1087 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 1088 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 1089
fb3f0f51 1090 return &svm->vcpu;
36241b8c 1091
10ab25cd
JK		 1092free_page4:
1093 __free_page(hsave_page);
b7af4043
TY		 1094free_page3:
1095 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1096free_page2:
1097 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1098free_page1:
1099 __free_page(page);
fb3f0f51
RR		 1100uninit:
1101 kvm_vcpu_uninit(&svm->vcpu);
1102free_svm:
a4770347 1103 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 1104out:
1105 return ERR_PTR(err);
6aa8b732
AK		 1106}
1107
1108static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1109{
a2fa3e9f
GH		 1110 struct vcpu_svm *svm = to_svm(vcpu);
1111
fb3f0f51 1112 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 1113 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 1114 __free_page(virt_to_page(svm->nested.hsave));
1115 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 1116 kvm_vcpu_uninit(vcpu);
a4770347 1117 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 1118}
1119
15ad7146 1120static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1121{
a2fa3e9f 1122 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 1123 int i;
0cc5064d 1124
0cc5064d 1125 if (unlikely(cpu != vcpu->cpu)) {
4b656b12 1126 svm->asid_generation = 0;
8d28fec4 1127 mark_all_dirty(svm->vmcb);
0cc5064d 1128 }
94dfbdb3 1129
82ca2d10
AK		 1130#ifdef CONFIG_X86_64
1131 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1132#endif
dacccfdd
AK		 1133 savesegment(fs, svm->host.fs);
1134 savesegment(gs, svm->host.gs);
1135 svm->host.ldt = kvm_read_ldt();
1136
94dfbdb3 1137 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1138 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 1139}
1140
1141static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1142{
a2fa3e9f 1143 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 1144 int i;
1145
e1beb1d3 1146 ++vcpu->stat.host_state_reload;
dacccfdd
AK		 1147 kvm_load_ldt(svm->host.ldt);
1148#ifdef CONFIG_X86_64
1149 loadsegment(fs, svm->host.fs);
1150 load_gs_index(svm->host.gs);
1151 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1152#else
1153 loadsegment(gs, svm->host.gs);
1154#endif
94dfbdb3 1155 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1156 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 1157}
1158
6aa8b732
AK		 1159static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1160{
a2fa3e9f 1161 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 1162}
1163
1164static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1165{
a2fa3e9f 1166 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 1167}
1168
6de4f3ad
AK		 1169static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1170{
1171 switch (reg) {
1172 case VCPU_EXREG_PDPTR:
1173 BUG_ON(!npt_enabled);
ff03a073 1174 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
6de4f3ad
AK		 1175 break;
1176 default:
1177 BUG();
1178 }
1179}
1180
f0b85051
AG		 1181static void svm_set_vintr(struct vcpu_svm *svm)
1182{
8a05a1b8 1183 set_intercept(svm, INTERCEPT_VINTR);
f0b85051
AG		 1184}
1185
1186static void svm_clear_vintr(struct vcpu_svm *svm)
1187{
8a05a1b8 1188 clr_intercept(svm, INTERCEPT_VINTR);
f0b85051
AG		 1189}
1190
6aa8b732
AK		 1191static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1192{
a2fa3e9f 1193 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 1194
1195 switch (seg) {
1196 case VCPU_SREG_CS: return &save->cs;
1197 case VCPU_SREG_DS: return &save->ds;
1198 case VCPU_SREG_ES: return &save->es;
1199 case VCPU_SREG_FS: return &save->fs;
1200 case VCPU_SREG_GS: return &save->gs;
1201 case VCPU_SREG_SS: return &save->ss;
1202 case VCPU_SREG_TR: return &save->tr;
1203 case VCPU_SREG_LDTR: return &save->ldtr;
1204 }
1205 BUG();
8b6d44c7 1206 return NULL;
6aa8b732
AK		 1207}
1208
1209static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1210{
1211 struct vmcb_seg *s = svm_seg(vcpu, seg);
1212
1213 return s->base;
1214}
1215
1216static void svm_get_segment(struct kvm_vcpu *vcpu,
1217 struct kvm_segment *var, int seg)
1218{
1219 struct vmcb_seg *s = svm_seg(vcpu, seg);
1220
1221 var->base = s->base;
1222 var->limit = s->limit;
1223 var->selector = s->selector;
1224 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1225 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1226 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1227 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1228 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1229 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1230 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1231 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 1232
e0231715
JR		 1233 /*
1234 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1235 * for cross vendor migration purposes by "not present"
1236 */
1237 var->unusable = !var->present || (var->type == 0);
1238
1fbdc7a5
AP		 1239 switch (seg) {
1240 case VCPU_SREG_CS:
1241 /*
1242 * SVM always stores 0 for the 'G' bit in the CS selector in
1243 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1244 * Intel's VMENTRY has a check on the 'G' bit.
1245 */
25022acc 1246 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 1247 break;
1248 case VCPU_SREG_TR:
1249 /*
1250 * Work around a bug where the busy flag in the tr selector
1251 * isn't exposed
1252 */
c0d09828 1253 var->type |= 0x2;
1fbdc7a5
AP		 1254 break;
1255 case VCPU_SREG_DS:
1256 case VCPU_SREG_ES:
1257 case VCPU_SREG_FS:
1258 case VCPU_SREG_GS:
1259 /*
1260 * The accessed bit must always be set in the segment
1261 * descriptor cache, although it can be cleared in the
1262 * descriptor, the cached bit always remains at 1. Since
1263 * Intel has a check on this, set it here to support
1264 * cross-vendor migration.
1265 */
1266 if (!var->unusable)
1267 var->type |= 0x1;
1268 break;
b586eb02 1269 case VCPU_SREG_SS:
e0231715
JR		 1270 /*
1271 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1272 * descriptor is left as 1, although the whole segment has
1273 * been made unusable. Clear it here to pass an Intel VMX
1274 * entry check when cross vendor migrating.
1275 */
1276 if (var->unusable)
1277 var->db = 0;
1278 break;
1fbdc7a5 1279 }
6aa8b732
AK		 1280}
1281
2e4d2653
IE		 1282static int svm_get_cpl(struct kvm_vcpu *vcpu)
1283{
1284 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1285
1286 return save->cpl;
1287}
1288
89a27f4d 1289static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1290{
a2fa3e9f
GH		 1291 struct vcpu_svm *svm = to_svm(vcpu);
1292
89a27f4d
GN		 1293 dt->size = svm->vmcb->save.idtr.limit;
1294 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1295}
1296
89a27f4d 1297static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1298{
a2fa3e9f
GH		 1299 struct vcpu_svm *svm = to_svm(vcpu);
1300
89a27f4d
GN		 1301 svm->vmcb->save.idtr.limit = dt->size;
1302 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 1303}
1304
89a27f4d 1305static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1306{
a2fa3e9f
GH		 1307 struct vcpu_svm *svm = to_svm(vcpu);
1308
89a27f4d
GN		 1309 dt->size = svm->vmcb->save.gdtr.limit;
1310 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1311}
1312
89a27f4d 1313static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1314{
a2fa3e9f
GH		 1315 struct vcpu_svm *svm = to_svm(vcpu);
1316
89a27f4d
GN		 1317 svm->vmcb->save.gdtr.limit = dt->size;
1318 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 1319}
1320
e8467fda
AK		 1321static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1322{
1323}
1324
25c4c276 1325static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1326{
1327}
1328
d225157b
AK		 1329static void update_cr0_intercept(struct vcpu_svm *svm)
1330{
1331 ulong gcr0 = svm->vcpu.arch.cr0;
1332 u64 *hcr0 = &svm->vmcb->save.cr0;
1333
1334 if (!svm->vcpu.fpu_active)
1335 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1336 else
1337 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1338 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1339
1340
1341 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
4ee546b4
RJ		 1342 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1343 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
d225157b 1344 } else {
4ee546b4
RJ		 1345 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1346 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
d225157b
AK		 1347 }
1348}
1349
6aa8b732
AK		 1350static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1351{
a2fa3e9f
GH		 1352 struct vcpu_svm *svm = to_svm(vcpu);
1353
2030753d 1354 if (is_guest_mode(vcpu)) {
7f5d8b56
JR		 1355 /*
1356 * We are here because we run in nested mode, the host kvm
1357 * intercepts cr0 writes but the l1 hypervisor does not.
1358 * But the L1 hypervisor may intercept selective cr0 writes.
1359 * This needs to be checked here.
1360 */
1361 unsigned long old, new;
1362
1363 /* Remove bits that would trigger a real cr0 write intercept */
1364 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1365 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1366
1367 if (old == new) {
1368 /* cr0 write with ts and mp unchanged */
1369 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
cda00082
JR		 1370 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1371 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1372 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1373 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7f5d8b56 1374 return;
cda00082 1375 }
7f5d8b56
JR		 1376 }
1377 }
1378
05b3e0c2 1379#ifdef CONFIG_X86_64
f6801dff 1380 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1381 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1382 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1383 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1384 }
1385
d77c26fc 1386 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1387 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1388 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1389 }
1390 }
1391#endif
ad312c7c 1392 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1393
1394 if (!npt_enabled)
1395 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1396
1397 if (!vcpu->fpu_active)
334df50a 1398 cr0 |= X86_CR0_TS;
709ddebf
JR		 1399 /*
1400 * re-enable caching here because the QEMU bios
1401 * does not do it - this results in some delay at
1402 * reboot
1403 */
1404 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1405 svm->vmcb->save.cr0 = cr0;
d225157b 1406 update_cr0_intercept(svm);
6aa8b732
AK		 1407}
1408
1409static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1410{
6394b649 1411 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1412 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1413
1414 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1415 force_new_asid(vcpu);
6394b649 1416
ec077263
JR		 1417 vcpu->arch.cr4 = cr4;
1418 if (!npt_enabled)
1419 cr4 |= X86_CR4_PAE;
6394b649 1420 cr4 |= host_cr4_mce;
ec077263 1421 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1422}
1423
1424static void svm_set_segment(struct kvm_vcpu *vcpu,
1425 struct kvm_segment *var, int seg)
1426{
a2fa3e9f 1427 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1428 struct vmcb_seg *s = svm_seg(vcpu, seg);
1429
1430 s->base = var->base;
1431 s->limit = var->limit;
1432 s->selector = var->selector;
1433 if (var->unusable)
1434 s->attrib = 0;
1435 else {
1436 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1437 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1438 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1439 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1440 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1441 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1442 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1443 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1444 }
1445 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1446 svm->vmcb->save.cpl
1447 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1448 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1449
1450}
1451
44c11430 1452static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1453{
d0bfb940
JK		 1454 struct vcpu_svm *svm = to_svm(vcpu);
1455
18c918c5
JR		 1456 clr_exception_intercept(svm, DB_VECTOR);
1457 clr_exception_intercept(svm, BP_VECTOR);
44c11430 1458
6be7d306 1459 if (svm->nmi_singlestep)
18c918c5 1460 set_exception_intercept(svm, DB_VECTOR);
44c11430 1461
d0bfb940
JK		 1462 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1463 if (vcpu->guest_debug &
1464 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
18c918c5 1465 set_exception_intercept(svm, DB_VECTOR);
d0bfb940 1466 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
18c918c5 1467 set_exception_intercept(svm, BP_VECTOR);
d0bfb940
JK		 1468 } else
1469 vcpu->guest_debug = 0;
44c11430
GN		 1470}
1471
355be0b9 1472static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1473{
44c11430
GN		 1474 struct vcpu_svm *svm = to_svm(vcpu);
1475
ae675ef0
JK		 1476 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1477 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1478 else
1479 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1480
355be0b9 1481 update_db_intercept(vcpu);
6aa8b732
AK		 1482}
1483
0fe1e009 1484static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1485{
0fe1e009
TH		 1486 if (sd->next_asid > sd->max_asid) {
1487 ++sd->asid_generation;
1488 sd->next_asid = 1;
a2fa3e9f 1489 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1490 }
1491
0fe1e009
TH		 1492 svm->asid_generation = sd->asid_generation;
1493 svm->vmcb->control.asid = sd->next_asid++;
d48086d1
JR		 1494
1495 mark_dirty(svm->vmcb, VMCB_ASID);
6aa8b732
AK		 1496}
1497
020df079 1498static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1499{
42dbaa5a 1500 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1501
020df079 1502 svm->vmcb->save.dr7 = value;
6aa8b732
AK		 1503}
1504
851ba692 1505static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1506{
631bc487 1507 u64 fault_address = svm->vmcb->control.exit_info_2;
6aa8b732 1508 u32 error_code;
631bc487 1509 int r = 1;
6aa8b732 1510
631bc487
GN		 1511 switch (svm->apf_reason) {
1512 default:
1513 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1514
631bc487
GN		 1515 trace_kvm_page_fault(fault_address, error_code);
1516 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1517 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1518 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1519 break;
1520 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1521 svm->apf_reason = 0;
1522 local_irq_disable();
1523 kvm_async_pf_task_wait(fault_address);
1524 local_irq_enable();
1525 break;
1526 case KVM_PV_REASON_PAGE_READY:
1527 svm->apf_reason = 0;
1528 local_irq_disable();
1529 kvm_async_pf_task_wake(fault_address);
1530 local_irq_enable();
1531 break;
1532 }
1533 return r;
6aa8b732
AK		 1534}
1535
851ba692 1536static int db_interception(struct vcpu_svm *svm)
d0bfb940 1537{
851ba692
AK		 1538 struct kvm_run *kvm_run = svm->vcpu.run;
1539
d0bfb940 1540 if (!(svm->vcpu.guest_debug &
44c11430 1541 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1542 !svm->nmi_singlestep) {
d0bfb940
JK		 1543 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1544 return 1;
1545 }
44c11430 1546
6be7d306
JK		 1547 if (svm->nmi_singlestep) {
1548 svm->nmi_singlestep = false;
44c11430
GN		 1549 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1550 svm->vmcb->save.rflags &=
1551 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1552 update_db_intercept(&svm->vcpu);
1553 }
1554
1555 if (svm->vcpu.guest_debug &
e0231715 1556 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1557 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1558 kvm_run->debug.arch.pc =
1559 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1560 kvm_run->debug.arch.exception = DB_VECTOR;
1561 return 0;
1562 }
1563
1564 return 1;
d0bfb940
JK		 1565}
1566
851ba692 1567static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1568{
851ba692
AK		 1569 struct kvm_run *kvm_run = svm->vcpu.run;
1570
d0bfb940
JK		 1571 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1572 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1573 kvm_run->debug.arch.exception = BP_VECTOR;
1574 return 0;
1575}
1576
851ba692 1577static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1578{
1579 int er;
1580
851ba692 1581 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1582 if (er != EMULATE_DONE)
7ee5d940 1583 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1584 return 1;
1585}
1586
6b52d186 1587static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1588{
6b52d186 1589 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7 1590
18c918c5 1591 clr_exception_intercept(svm, NM_VECTOR);
66a562f7 1592
e756fc62 1593 svm->vcpu.fpu_active = 1;
d225157b 1594 update_cr0_intercept(svm);
6b52d186 1595}
a2fa3e9f 1596
6b52d186
AK		 1597static int nm_interception(struct vcpu_svm *svm)
1598{
1599 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1600 return 1;
7807fa6c
AL		 1601}
1602
67ec6607
JR		 1603static bool is_erratum_383(void)
1604{
1605 int err, i;
1606 u64 value;
1607
1608 if (!erratum_383_found)
1609 return false;
1610
1611 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1612 if (err)
1613 return false;
1614
1615 /* Bit 62 may or may not be set for this mce */
1616 value &= ~(1ULL << 62);
1617
1618 if (value != 0xb600000000010015ULL)
1619 return false;
1620
1621 /* Clear MCi_STATUS registers */
1622 for (i = 0; i < 6; ++i)
1623 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1624
1625 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1626 if (!err) {
1627 u32 low, high;
1628
1629 value &= ~(1ULL << 2);
1630 low = lower_32_bits(value);
1631 high = upper_32_bits(value);
1632
1633 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1634 }
1635
1636 /* Flush tlb to evict multi-match entries */
1637 __flush_tlb_all();
1638
1639 return true;
1640}
1641
fe5913e4 1642static void svm_handle_mce(struct vcpu_svm *svm)
53371b50 1643{
67ec6607
JR		 1644 if (is_erratum_383()) {
1645 /*
1646 * Erratum 383 triggered. Guest state is corrupt so kill the
1647 * guest.
1648 */
1649 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1650
a8eeb04a 1651 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
67ec6607
JR		 1652
1653 return;
1654 }
1655
53371b50
JR		 1656 /*
1657 * On an #MC intercept the MCE handler is not called automatically in
1658 * the host. So do it by hand here.
1659 */
1660 asm volatile (
1661 "int $0x12\n");
1662 /* not sure if we ever come back to this point */
1663
fe5913e4
JR		 1664 return;
1665}
1666
1667static int mc_interception(struct vcpu_svm *svm)
1668{
53371b50
JR		 1669 return 1;
1670}
1671
851ba692 1672static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1673{
851ba692
AK		 1674 struct kvm_run *kvm_run = svm->vcpu.run;
1675
46fe4ddd
JR		 1676 /*
1677 * VMCB is undefined after a SHUTDOWN intercept
1678 * so reinitialize it.
1679 */
a2fa3e9f 1680 clear_page(svm->vmcb);
e6101a96 1681 init_vmcb(svm);
46fe4ddd
JR		 1682
1683 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1684 return 0;
1685}
1686
851ba692 1687static int io_interception(struct vcpu_svm *svm)
6aa8b732 1688{
cf8f70bf 1689 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1690 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1691 int size, in, string;
039576c0 1692 unsigned port;
6aa8b732 1693
e756fc62 1694 ++svm->vcpu.stat.io_exits;
e70669ab 1695 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1696 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
cf8f70bf 1697 if (string || in)
6d77dbfc 1698 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
cf8f70bf 1699
039576c0
AK		 1700 port = io_info >> 16;
1701 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1702 svm->next_rip = svm->vmcb->control.exit_info_2;
e93f36bc 1703 skip_emulated_instruction(&svm->vcpu);
cf8f70bf
GN		 1704
1705 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 1706}
1707
851ba692 1708static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1709{
1710 return 1;
1711}
1712
851ba692 1713static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1714{
1715 ++svm->vcpu.stat.irq_exits;
1716 return 1;
1717}
1718
851ba692 1719static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1720{
1721 return 1;
1722}
1723
851ba692 1724static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1725{
5fdbf976 1726 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1727 skip_emulated_instruction(&svm->vcpu);
1728 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1729}
1730
851ba692 1731static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1732{
5fdbf976 1733 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1734 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1735 kvm_emulate_hypercall(&svm->vcpu);
1736 return 1;
02e235bc
AK		 1737}
1738
5bd2edc3
JR		 1739static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1740{
1741 struct vcpu_svm *svm = to_svm(vcpu);
1742
1743 return svm->nested.nested_cr3;
1744}
1745
1746static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1747 unsigned long root)
1748{
1749 struct vcpu_svm *svm = to_svm(vcpu);
1750
1751 svm->vmcb->control.nested_cr3 = root;
1752 force_new_asid(vcpu);
1753}
1754
6389ee94
AK		 1755static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1756 struct x86_exception *fault)
5bd2edc3
JR		 1757{
1758 struct vcpu_svm *svm = to_svm(vcpu);
1759
1760 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1761 svm->vmcb->control.exit_code_hi = 0;
6389ee94
AK		 1762 svm->vmcb->control.exit_info_1 = fault->error_code;
1763 svm->vmcb->control.exit_info_2 = fault->address;
5bd2edc3
JR		 1764
1765 nested_svm_vmexit(svm);
1766}
1767
4b16184c
JR		 1768static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1769{
1770 int r;
1771
1772 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1773
1774 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1775 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1776 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1777 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1778 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1779
1780 return r;
1781}
1782
1783static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1784{
1785 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1786}
1787
c0725420
AG		 1788static int nested_svm_check_permissions(struct vcpu_svm *svm)
1789{
f6801dff 1790 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1791 || !is_paging(&svm->vcpu)) {
1792 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1793 return 1;
1794 }
1795
1796 if (svm->vmcb->save.cpl) {
1797 kvm_inject_gp(&svm->vcpu, 0);
1798 return 1;
1799 }
1800
1801 return 0;
1802}
1803
cf74a78b
AG		 1804static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1805 bool has_error_code, u32 error_code)
1806{
b8e88bc8
JR		 1807 int vmexit;
1808
2030753d 1809 if (!is_guest_mode(&svm->vcpu))
0295ad7d 1810 return 0;
cf74a78b 1811
0295ad7d
JR		 1812 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1813 svm->vmcb->control.exit_code_hi = 0;
1814 svm->vmcb->control.exit_info_1 = error_code;
1815 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1816
b8e88bc8
JR		 1817 vmexit = nested_svm_intercept(svm);
1818 if (vmexit == NESTED_EXIT_DONE)
1819 svm->nested.exit_required = true;
1820
1821 return vmexit;
cf74a78b
AG		 1822}
1823
8fe54654
JR		 1824/* This function returns true if it is save to enable the irq window */
1825static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1826{
2030753d 1827 if (!is_guest_mode(&svm->vcpu))
8fe54654 1828 return true;
cf74a78b 1829
26666957 1830 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1831 return true;
cf74a78b 1832
26666957 1833 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1834 return false;
cf74a78b 1835
a0a07cd2
GN		 1836 /*
1837 * if vmexit was already requested (by intercepted exception
1838 * for instance) do not overwrite it with "external interrupt"
1839 * vmexit.
1840 */
1841 if (svm->nested.exit_required)
1842 return false;
1843
197717d5
JR		 1844 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1845 svm->vmcb->control.exit_info_1 = 0;
1846 svm->vmcb->control.exit_info_2 = 0;
26666957 1847
cd3ff653
JR		 1848 if (svm->nested.intercept & 1ULL) {
1849 /*
1850 * The #vmexit can't be emulated here directly because this
1851 * code path runs with irqs and preemtion disabled. A
1852 * #vmexit emulation might sleep. Only signal request for
1853 * the #vmexit here.
1854 */
1855 svm->nested.exit_required = true;
236649de 1856 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1857 return false;
cf74a78b
AG		 1858 }
1859
8fe54654 1860 return true;
cf74a78b
AG		 1861}
1862
887f500c
JR		 1863/* This function returns true if it is save to enable the nmi window */
1864static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1865{
2030753d 1866 if (!is_guest_mode(&svm->vcpu))
887f500c
JR		 1867 return true;
1868
1869 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1870 return true;
1871
1872 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1873 svm->nested.exit_required = true;
1874
1875 return false;
cf74a78b
AG		 1876}
1877
7597f129 1878static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1879{
1880 struct page *page;
1881
6c3bd3d7
JR		 1882 might_sleep();
1883
34f80cfa 1884 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1885 if (is_error_page(page))
1886 goto error;
1887
7597f129
JR		 1888 *_page = page;
1889
1890 return kmap(page);
34f80cfa
JR		 1891
1892error:
1893 kvm_release_page_clean(page);
1894 kvm_inject_gp(&svm->vcpu, 0);
1895
1896 return NULL;
1897}
1898
7597f129 1899static void nested_svm_unmap(struct page *page)
34f80cfa 1900{
7597f129 1901 kunmap(page);
34f80cfa
JR		 1902 kvm_release_page_dirty(page);
1903}
34f80cfa 1904
ce2ac085
JR		 1905static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1906{
1907 unsigned port;
1908 u8 val, bit;
1909 u64 gpa;
34f80cfa 1910
ce2ac085
JR		 1911 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1912 return NESTED_EXIT_HOST;
34f80cfa 1913
ce2ac085
JR		 1914 port = svm->vmcb->control.exit_info_1 >> 16;
1915 gpa = svm->nested.vmcb_iopm + (port / 8);
1916 bit = port % 8;
1917 val = 0;
1918
1919 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1920 val &= (1 << bit);
1921
1922 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
34f80cfa
JR		 1923}
1924
d2477826 1925static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1926{
0d6b3537
JR		 1927 u32 offset, msr, value;
1928 int write, mask;
4c2161ae 1929
3d62d9aa 1930 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 1931 return NESTED_EXIT_HOST;
3d62d9aa 1932
0d6b3537
JR		 1933 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1934 offset = svm_msrpm_offset(msr);
1935 write = svm->vmcb->control.exit_info_1 & 1;
1936 mask = 1 << ((2 * (msr & 0xf)) + write);
3d62d9aa 1937
0d6b3537
JR		 1938 if (offset == MSR_INVALID)
1939 return NESTED_EXIT_DONE;
4c2161ae 1940
0d6b3537
JR		 1941 /* Offset is in 32 bit units but need in 8 bit units */
1942 offset *= 4;
4c2161ae 1943
0d6b3537
JR		 1944 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1945 return NESTED_EXIT_DONE;
3d62d9aa 1946
0d6b3537 1947 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
4c2161ae
JR		 1948}
1949
410e4d57 1950static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1951{
cf74a78b 1952 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1953
410e4d57
JR		 1954 switch (exit_code) {
1955 case SVM_EXIT_INTR:
1956 case SVM_EXIT_NMI:
ff47a49b 1957 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
410e4d57 1958 return NESTED_EXIT_HOST;
410e4d57 1959 case SVM_EXIT_NPF:
e0231715 1960 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1961 if (npt_enabled)
1962 return NESTED_EXIT_HOST;
1963 break;
410e4d57 1964 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
631bc487
GN		 1965 /* When we're shadowing, trap PFs, but not async PF */
1966 if (!npt_enabled && svm->apf_reason == 0)
410e4d57
JR		 1967 return NESTED_EXIT_HOST;
1968 break;
66a562f7
JR		 1969 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1970 nm_interception(svm);
1971 break;
410e4d57
JR		 1972 default:
1973 break;
cf74a78b
AG		 1974 }
1975
410e4d57
JR		 1976 return NESTED_EXIT_CONTINUE;
1977}
1978
1979/*
1980 * If this function returns true, this #vmexit was already handled
1981 */
b8e88bc8 1982static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1983{
1984 u32 exit_code = svm->vmcb->control.exit_code;
1985 int vmexit = NESTED_EXIT_HOST;
1986
cf74a78b 1987 switch (exit_code) {
9c4e40b9 1988 case SVM_EXIT_MSR:
3d62d9aa 1989 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1990 break;
ce2ac085
JR		 1991 case SVM_EXIT_IOIO:
1992 vmexit = nested_svm_intercept_ioio(svm);
1993 break;
4ee546b4
RJ		 1994 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
1995 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
1996 if (svm->nested.intercept_cr & bit)
410e4d57 1997 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1998 break;
1999 }
3aed041a
JR		 2000 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2001 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2002 if (svm->nested.intercept_dr & bit)
410e4d57 2003 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 2004 break;
2005 }
2006 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2007 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 2008 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 2009 vmexit = NESTED_EXIT_DONE;
631bc487
GN		 2010 /* async page fault always cause vmexit */
2011 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2012 svm->apf_reason != 0)
2013 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 2014 break;
2015 }
228070b1
JR		 2016 case SVM_EXIT_ERR: {
2017 vmexit = NESTED_EXIT_DONE;
2018 break;
2019 }
cf74a78b
AG		 2020 default: {
2021 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 2022 if (svm->nested.intercept & exit_bits)
410e4d57 2023 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 2024 }
2025 }
2026
b8e88bc8
JR		 2027 return vmexit;
2028}
2029
2030static int nested_svm_exit_handled(struct vcpu_svm *svm)
2031{
2032 int vmexit;
2033
2034 vmexit = nested_svm_intercept(svm);
2035
2036 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 2037 nested_svm_vmexit(svm);
9c4e40b9
JR		 2038
2039 return vmexit;
cf74a78b
AG		 2040}
2041
0460a979
JR		 2042static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2043{
2044 struct vmcb_control_area *dst = &dst_vmcb->control;
2045 struct vmcb_control_area *from = &from_vmcb->control;
2046
4ee546b4 2047 dst->intercept_cr = from->intercept_cr;
3aed041a 2048 dst->intercept_dr = from->intercept_dr;
0460a979
JR		 2049 dst->intercept_exceptions = from->intercept_exceptions;
2050 dst->intercept = from->intercept;
2051 dst->iopm_base_pa = from->iopm_base_pa;
2052 dst->msrpm_base_pa = from->msrpm_base_pa;
2053 dst->tsc_offset = from->tsc_offset;
2054 dst->asid = from->asid;
2055 dst->tlb_ctl = from->tlb_ctl;
2056 dst->int_ctl = from->int_ctl;
2057 dst->int_vector = from->int_vector;
2058 dst->int_state = from->int_state;
2059 dst->exit_code = from->exit_code;
2060 dst->exit_code_hi = from->exit_code_hi;
2061 dst->exit_info_1 = from->exit_info_1;
2062 dst->exit_info_2 = from->exit_info_2;
2063 dst->exit_int_info = from->exit_int_info;
2064 dst->exit_int_info_err = from->exit_int_info_err;
2065 dst->nested_ctl = from->nested_ctl;
2066 dst->event_inj = from->event_inj;
2067 dst->event_inj_err = from->event_inj_err;
2068 dst->nested_cr3 = from->nested_cr3;
2069 dst->lbr_ctl = from->lbr_ctl;
2070}
2071
34f80cfa 2072static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 2073{
34f80cfa 2074 struct vmcb *nested_vmcb;
e6aa9abd 2075 struct vmcb *hsave = svm->nested.hsave;
33740e40 2076 struct vmcb *vmcb = svm->vmcb;
7597f129 2077 struct page *page;
cf74a78b 2078
17897f36
JR		 2079 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2080 vmcb->control.exit_info_1,
2081 vmcb->control.exit_info_2,
2082 vmcb->control.exit_int_info,
2083 vmcb->control.exit_int_info_err);
2084
7597f129 2085 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 2086 if (!nested_vmcb)
2087 return 1;
2088
2030753d
JR		 2089 /* Exit Guest-Mode */
2090 leave_guest_mode(&svm->vcpu);
06fc7772
JR		 2091 svm->nested.vmcb = 0;
2092
cf74a78b 2093 /* Give the current vmcb to the guest */
33740e40
JR		 2094 disable_gif(svm);
2095
2096 nested_vmcb->save.es = vmcb->save.es;
2097 nested_vmcb->save.cs = vmcb->save.cs;
2098 nested_vmcb->save.ss = vmcb->save.ss;
2099 nested_vmcb->save.ds = vmcb->save.ds;
2100 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2101 nested_vmcb->save.idtr = vmcb->save.idtr;
3f6a9d16 2102 nested_vmcb->save.efer = svm->vcpu.arch.efer;
cdbbdc12 2103 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2be4fc7a 2104 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 2105 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 2106 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 2107 nested_vmcb->save.rflags = vmcb->save.rflags;
2108 nested_vmcb->save.rip = vmcb->save.rip;
2109 nested_vmcb->save.rsp = vmcb->save.rsp;
2110 nested_vmcb->save.rax = vmcb->save.rax;
2111 nested_vmcb->save.dr7 = vmcb->save.dr7;
2112 nested_vmcb->save.dr6 = vmcb->save.dr6;
2113 nested_vmcb->save.cpl = vmcb->save.cpl;
2114
2115 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2116 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2117 nested_vmcb->control.int_state = vmcb->control.int_state;
2118 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2119 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2120 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2121 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2122 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2123 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
7a190667 2124 nested_vmcb->control.next_rip = vmcb->control.next_rip;
8d23c466
AG		 2125
2126 /*
2127 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2128 * to make sure that we do not lose injected events. So check event_inj
2129 * here and copy it to exit_int_info if it is valid.
2130 * Exit_int_info and event_inj can't be both valid because the case
2131 * below only happens on a VMRUN instruction intercept which has
2132 * no valid exit_int_info set.
2133 */
2134 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2135 struct vmcb_control_area *nc = &nested_vmcb->control;
2136
2137 nc->exit_int_info = vmcb->control.event_inj;
2138 nc->exit_int_info_err = vmcb->control.event_inj_err;
2139 }
2140
33740e40
JR		 2141 nested_vmcb->control.tlb_ctl = 0;
2142 nested_vmcb->control.event_inj = 0;
2143 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 2144
2145 /* We always set V_INTR_MASKING and remember the old value in hflags */
2146 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2147 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2148
cf74a78b 2149 /* Restore the original control entries */
0460a979 2150 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 2151
219b65dc
AG		 2152 kvm_clear_exception_queue(&svm->vcpu);
2153 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b 2154
4b16184c
JR		 2155 svm->nested.nested_cr3 = 0;
2156
cf74a78b
AG		 2157 /* Restore selected save entries */
2158 svm->vmcb->save.es = hsave->save.es;
2159 svm->vmcb->save.cs = hsave->save.cs;
2160 svm->vmcb->save.ss = hsave->save.ss;
2161 svm->vmcb->save.ds = hsave->save.ds;
2162 svm->vmcb->save.gdtr = hsave->save.gdtr;
2163 svm->vmcb->save.idtr = hsave->save.idtr;
2164 svm->vmcb->save.rflags = hsave->save.rflags;
2165 svm_set_efer(&svm->vcpu, hsave->save.efer);
2166 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2167 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2168 if (npt_enabled) {
2169 svm->vmcb->save.cr3 = hsave->save.cr3;
2170 svm->vcpu.arch.cr3 = hsave->save.cr3;
2171 } else {
2390218b 2172 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
cf74a78b
AG		 2173 }
2174 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2175 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2176 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2177 svm->vmcb->save.dr7 = 0;
2178 svm->vmcb->save.cpl = 0;
2179 svm->vmcb->control.exit_int_info = 0;
2180
8d28fec4
RJ		 2181 mark_all_dirty(svm->vmcb);
2182
7597f129 2183 nested_svm_unmap(page);
cf74a78b 2184
4b16184c 2185 nested_svm_uninit_mmu_context(&svm->vcpu);
cf74a78b
AG		 2186 kvm_mmu_reset_context(&svm->vcpu);
2187 kvm_mmu_load(&svm->vcpu);
2188
2189 return 0;
2190}
3d6368ef 2191
9738b2c9 2192static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 2193{
323c3d80
JR		 2194 /*
2195 * This function merges the msr permission bitmaps of kvm and the
2196 * nested vmcb. It is omptimized in that it only merges the parts where
2197 * the kvm msr permission bitmap may contain zero bits
2198 */
3d6368ef 2199 int i;
9738b2c9 2200
323c3d80
JR		 2201 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2202 return true;
9738b2c9 2203
323c3d80
JR		 2204 for (i = 0; i < MSRPM_OFFSETS; i++) {
2205 u32 value, p;
2206 u64 offset;
9738b2c9 2207
323c3d80
JR		 2208 if (msrpm_offsets[i] == 0xffffffff)
2209 break;
3d6368ef 2210
0d6b3537
JR		 2211 p = msrpm_offsets[i];
2212 offset = svm->nested.vmcb_msrpm + (p * 4);
323c3d80
JR		 2213
2214 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2215 return false;
2216
2217 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2218 }
3d6368ef 2219
323c3d80 2220 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
9738b2c9
JR		 2221
2222 return true;
3d6368ef
AG		 2223}
2224
52c65a30
JR		 2225static bool nested_vmcb_checks(struct vmcb *vmcb)
2226{
2227 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2228 return false;
2229
dbe77584
JR		 2230 if (vmcb->control.asid == 0)
2231 return false;
2232
4b16184c
JR		 2233 if (vmcb->control.nested_ctl && !npt_enabled)
2234 return false;
2235
52c65a30
JR		 2236 return true;
2237}
2238
9738b2c9 2239static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 2240{
9738b2c9 2241 struct vmcb *nested_vmcb;
e6aa9abd 2242 struct vmcb *hsave = svm->nested.hsave;
defbba56 2243 struct vmcb *vmcb = svm->vmcb;
7597f129 2244 struct page *page;
06fc7772 2245 u64 vmcb_gpa;
3d6368ef 2246
06fc7772 2247 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 2248
7597f129 2249 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 2250 if (!nested_vmcb)
2251 return false;
2252
52c65a30
JR		 2253 if (!nested_vmcb_checks(nested_vmcb)) {
2254 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2255 nested_vmcb->control.exit_code_hi = 0;
2256 nested_vmcb->control.exit_info_1 = 0;
2257 nested_vmcb->control.exit_info_2 = 0;
2258
2259 nested_svm_unmap(page);
2260
2261 return false;
2262 }
2263
b75f4eb3 2264 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
0ac406de
JR		 2265 nested_vmcb->save.rip,
2266 nested_vmcb->control.int_ctl,
2267 nested_vmcb->control.event_inj,
2268 nested_vmcb->control.nested_ctl);
2269
4ee546b4
RJ		 2270 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2271 nested_vmcb->control.intercept_cr >> 16,
2e554e8d
JR		 2272 nested_vmcb->control.intercept_exceptions,
2273 nested_vmcb->control.intercept);
2274
3d6368ef 2275 /* Clear internal status */
219b65dc
AG		 2276 kvm_clear_exception_queue(&svm->vcpu);
2277 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 2278
e0231715
JR		 2279 /*
2280 * Save the old vmcb, so we don't need to pick what we save, but can
2281 * restore everything when a VMEXIT occurs
2282 */
defbba56
JR		 2283 hsave->save.es = vmcb->save.es;
2284 hsave->save.cs = vmcb->save.cs;
2285 hsave->save.ss = vmcb->save.ss;
2286 hsave->save.ds = vmcb->save.ds;
2287 hsave->save.gdtr = vmcb->save.gdtr;
2288 hsave->save.idtr = vmcb->save.idtr;
f6801dff 2289 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 2290 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 2291 hsave->save.cr4 = svm->vcpu.arch.cr4;
2292 hsave->save.rflags = vmcb->save.rflags;
b75f4eb3 2293 hsave->save.rip = kvm_rip_read(&svm->vcpu);
defbba56
JR		 2294 hsave->save.rsp = vmcb->save.rsp;
2295 hsave->save.rax = vmcb->save.rax;
2296 if (npt_enabled)
2297 hsave->save.cr3 = vmcb->save.cr3;
2298 else
2299 hsave->save.cr3 = svm->vcpu.arch.cr3;
2300
0460a979 2301 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 2302
2303 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2304 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2305 else
2306 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2307
4b16184c
JR		 2308 if (nested_vmcb->control.nested_ctl) {
2309 kvm_mmu_unload(&svm->vcpu);
2310 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2311 nested_svm_init_mmu_context(&svm->vcpu);
2312 }
2313
3d6368ef
AG		 2314 /* Load the nested guest state */
2315 svm->vmcb->save.es = nested_vmcb->save.es;
2316 svm->vmcb->save.cs = nested_vmcb->save.cs;
2317 svm->vmcb->save.ss = nested_vmcb->save.ss;
2318 svm->vmcb->save.ds = nested_vmcb->save.ds;
2319 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2320 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2321 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2322 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2323 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2324 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2325 if (npt_enabled) {
2326 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2327 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 2328 } else
2390218b 2329 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 2330
2331 /* Guest paging mode is active - reset mmu */
2332 kvm_mmu_reset_context(&svm->vcpu);
2333
defbba56 2334 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 2335 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2336 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2337 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 2338
3d6368ef
AG		 2339 /* In case we don't even reach vcpu_run, the fields are not updated */
2340 svm->vmcb->save.rax = nested_vmcb->save.rax;
2341 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2342 svm->vmcb->save.rip = nested_vmcb->save.rip;
2343 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2344 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2345 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2346
f7138538 2347 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
ce2ac085 2348 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3d6368ef 2349
aad42c64 2350 /* cache intercepts */
4ee546b4 2351 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
3aed041a 2352 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
aad42c64
JR		 2353 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2354 svm->nested.intercept = nested_vmcb->control.intercept;
2355
3d6368ef 2356 force_new_asid(&svm->vcpu);
3d6368ef 2357 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 2358 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2359 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2360 else
2361 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2362
88ab24ad
JR		 2363 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2364 /* We only want the cr8 intercept bits of the guest */
4ee546b4
RJ		 2365 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2366 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
88ab24ad
JR		 2367 }
2368
0d945bd9 2369 /* We don't want to see VMMCALLs from a nested guest */
8a05a1b8 2370 clr_intercept(svm, INTERCEPT_VMMCALL);
0d945bd9 2371
88ab24ad 2372 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2373 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2374 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2375 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2376 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2377 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2378
7597f129 2379 nested_svm_unmap(page);
9738b2c9 2380
2030753d
JR		 2381 /* Enter Guest-Mode */
2382 enter_guest_mode(&svm->vcpu);
2383
384c6368
JR		 2384 /*
2385 * Merge guest and host intercepts - must be called with vcpu in
2386 * guest-mode to take affect here
2387 */
2388 recalc_intercepts(svm);
2389
06fc7772 2390 svm->nested.vmcb = vmcb_gpa;
9738b2c9 2391
2af9194d 2392 enable_gif(svm);
3d6368ef 2393
8d28fec4
RJ		 2394 mark_all_dirty(svm->vmcb);
2395
9738b2c9 2396 return true;
3d6368ef
AG		 2397}
2398
9966bf68 2399static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2400{
2401 to_vmcb->save.fs = from_vmcb->save.fs;
2402 to_vmcb->save.gs = from_vmcb->save.gs;
2403 to_vmcb->save.tr = from_vmcb->save.tr;
2404 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2405 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2406 to_vmcb->save.star = from_vmcb->save.star;
2407 to_vmcb->save.lstar = from_vmcb->save.lstar;
2408 to_vmcb->save.cstar = from_vmcb->save.cstar;
2409 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2410 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2411 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2412 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2413}
2414
851ba692 2415static int vmload_interception(struct vcpu_svm *svm)
5542675b 2416{
9966bf68 2417 struct vmcb *nested_vmcb;
7597f129 2418 struct page *page;
9966bf68 2419
5542675b
AG		 2420 if (nested_svm_check_permissions(svm))
2421 return 1;
2422
2423 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2424 skip_emulated_instruction(&svm->vcpu);
2425
7597f129 2426 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2427 if (!nested_vmcb)
2428 return 1;
2429
2430 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2431 nested_svm_unmap(page);
5542675b
AG		 2432
2433 return 1;
2434}
2435
851ba692 2436static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2437{
9966bf68 2438 struct vmcb *nested_vmcb;
7597f129 2439 struct page *page;
9966bf68 2440
5542675b
AG		 2441 if (nested_svm_check_permissions(svm))
2442 return 1;
2443
2444 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2445 skip_emulated_instruction(&svm->vcpu);
2446
7597f129 2447 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2448 if (!nested_vmcb)
2449 return 1;
2450
2451 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2452 nested_svm_unmap(page);
5542675b
AG		 2453
2454 return 1;
2455}
2456
851ba692 2457static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2458{
3d6368ef
AG		 2459 if (nested_svm_check_permissions(svm))
2460 return 1;
2461
b75f4eb3
RJ		 2462 /* Save rip after vmrun instruction */
2463 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3d6368ef 2464
9738b2c9 2465 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2466 return 1;
2467
9738b2c9 2468 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2469 goto failed;
2470
2471 return 1;
2472
2473failed:
2474
2475 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2476 svm->vmcb->control.exit_code_hi = 0;
2477 svm->vmcb->control.exit_info_1 = 0;
2478 svm->vmcb->control.exit_info_2 = 0;
2479
2480 nested_svm_vmexit(svm);
3d6368ef
AG		 2481
2482 return 1;
2483}
2484
851ba692 2485static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2486{
2487 if (nested_svm_check_permissions(svm))
2488 return 1;
2489
2490 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2491 skip_emulated_instruction(&svm->vcpu);
3842d135 2492 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
1371d904 2493
2af9194d 2494 enable_gif(svm);
1371d904
AG		 2495
2496 return 1;
2497}
2498
851ba692 2499static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2500{
2501 if (nested_svm_check_permissions(svm))
2502 return 1;
2503
2504 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2505 skip_emulated_instruction(&svm->vcpu);
2506
2af9194d 2507 disable_gif(svm);
1371d904
AG		 2508
2509 /* After a CLGI no interrupts should come */
2510 svm_clear_vintr(svm);
2511 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2512
decdbf6a
JR		 2513 mark_dirty(svm->vmcb, VMCB_INTR);
2514
1371d904
AG		 2515 return 1;
2516}
2517
851ba692 2518static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2519{
2520 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2521
ec1ff790
JR		 2522 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2523 vcpu->arch.regs[VCPU_REGS_RAX]);
2524
ff092385
AG		 2525 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2526 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2527
2528 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2529 skip_emulated_instruction(&svm->vcpu);
2530 return 1;
2531}
2532
532a46b9
JR		 2533static int skinit_interception(struct vcpu_svm *svm)
2534{
2535 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2536
2537 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2538 return 1;
2539}
2540
851ba692 2541static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2542{
7ee5d940 2543 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2544 return 1;
2545}
2546
851ba692 2547static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2548{
37817f29 2549 u16 tss_selector;
64a7ec06
GN		 2550 int reason;
2551 int int_type = svm->vmcb->control.exit_int_info &
2552 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2553 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2554 uint32_t type =
2555 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2556 uint32_t idt_v =
2557 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2558 bool has_error_code = false;
2559 u32 error_code = 0;
37817f29
IE		 2560
2561 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2562
37817f29
IE		 2563 if (svm->vmcb->control.exit_info_2 &
2564 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2565 reason = TASK_SWITCH_IRET;
2566 else if (svm->vmcb->control.exit_info_2 &
2567 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2568 reason = TASK_SWITCH_JMP;
fe8e7f83 2569 else if (idt_v)
64a7ec06
GN		 2570 reason = TASK_SWITCH_GATE;
2571 else
2572 reason = TASK_SWITCH_CALL;
2573
fe8e7f83
GN		 2574 if (reason == TASK_SWITCH_GATE) {
2575 switch (type) {
2576 case SVM_EXITINTINFO_TYPE_NMI:
2577 svm->vcpu.arch.nmi_injected = false;
2578 break;
2579 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2580 if (svm->vmcb->control.exit_info_2 &
2581 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2582 has_error_code = true;
2583 error_code =
2584 (u32)svm->vmcb->control.exit_info_2;
2585 }
fe8e7f83
GN		 2586 kvm_clear_exception_queue(&svm->vcpu);
2587 break;
2588 case SVM_EXITINTINFO_TYPE_INTR:
2589 kvm_clear_interrupt_queue(&svm->vcpu);
2590 break;
2591 default:
2592 break;
2593 }
2594 }
64a7ec06 2595
8317c298
GN		 2596 if (reason != TASK_SWITCH_GATE ||
2597 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2598 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2599 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2600 skip_emulated_instruction(&svm->vcpu);
64a7ec06 2601
acb54517
GN		 2602 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2603 has_error_code, error_code) == EMULATE_FAIL) {
2604 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2605 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2606 svm->vcpu.run->internal.ndata = 0;
2607 return 0;
2608 }
2609 return 1;
6aa8b732
AK		 2610}
2611
851ba692 2612static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2613{
5fdbf976 2614 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2615 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2616 return 1;
6aa8b732
AK		 2617}
2618
851ba692 2619static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2620{
2621 ++svm->vcpu.stat.nmi_window_exits;
8a05a1b8 2622 clr_intercept(svm, INTERCEPT_IRET);
44c11430 2623 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2624 return 1;
2625}
2626
851ba692 2627static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2628{
6d77dbfc 2629 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
a7052897
MT		 2630}
2631
851ba692 2632static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2633{
6d77dbfc 2634 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
6aa8b732
AK		 2635}
2636
cda00082
JR		 2637static int cr0_write_interception(struct vcpu_svm *svm)
2638{
2639 struct kvm_vcpu *vcpu = &svm->vcpu;
2640 int r;
2641
2642 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2643
2644 if (svm->nested.vmexit_rip) {
2645 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2646 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2647 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2648 svm->nested.vmexit_rip = 0;
2649 }
2650
2651 return r == EMULATE_DONE;
2652}
2653
851ba692 2654static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2655{
851ba692
AK		 2656 struct kvm_run *kvm_run = svm->vcpu.run;
2657
0a5fff19
GN		 2658 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2659 /* instruction emulation calls kvm_set_cr8() */
851ba692 2660 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273 2661 if (irqchip_in_kernel(svm->vcpu.kvm)) {
4ee546b4 2662 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1d075434 2663 return 1;
95ba8273 2664 }
0a5fff19
GN		 2665 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2666 return 1;
1d075434
JR		 2667 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2668 return 0;
2669}
2670
6aa8b732
AK		 2671static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2672{
a2fa3e9f
GH		 2673 struct vcpu_svm *svm = to_svm(vcpu);
2674
6aa8b732 2675 switch (ecx) {
af24a4e4 2676 case MSR_IA32_TSC: {
4cc70310 2677 struct vmcb *vmcb = get_host_vmcb(svm);
6aa8b732 2678
4cc70310 2679 *data = vmcb->control.tsc_offset + native_read_tsc();
6aa8b732
AK		 2680 break;
2681 }
8c06585d 2682 case MSR_STAR:
a2fa3e9f 2683 *data = svm->vmcb->save.star;
6aa8b732 2684 break;
0e859cac 2685#ifdef CONFIG_X86_64
6aa8b732 2686 case MSR_LSTAR:
a2fa3e9f 2687 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2688 break;
2689 case MSR_CSTAR:
a2fa3e9f 2690 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2691 break;
2692 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2693 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2694 break;
2695 case MSR_SYSCALL_MASK:
a2fa3e9f 2696 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2697 break;
2698#endif
2699 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2700 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2701 break;
2702 case MSR_IA32_SYSENTER_EIP:
017cb99e 2703 *data = svm->sysenter_eip;
6aa8b732
AK		 2704 break;
2705 case MSR_IA32_SYSENTER_ESP:
017cb99e 2706 *data = svm->sysenter_esp;
6aa8b732 2707 break;
e0231715
JR		 2708 /*
2709 * Nobody will change the following 5 values in the VMCB so we can
2710 * safely return them on rdmsr. They will always be 0 until LBRV is
2711 * implemented.
2712 */
a2938c80
JR		 2713 case MSR_IA32_DEBUGCTLMSR:
2714 *data = svm->vmcb->save.dbgctl;
2715 break;
2716 case MSR_IA32_LASTBRANCHFROMIP:
2717 *data = svm->vmcb->save.br_from;
2718 break;
2719 case MSR_IA32_LASTBRANCHTOIP:
2720 *data = svm->vmcb->save.br_to;
2721 break;
2722 case MSR_IA32_LASTINTFROMIP:
2723 *data = svm->vmcb->save.last_excp_from;
2724 break;
2725 case MSR_IA32_LASTINTTOIP:
2726 *data = svm->vmcb->save.last_excp_to;
2727 break;
b286d5d8 2728 case MSR_VM_HSAVE_PA:
e6aa9abd 2729 *data = svm->nested.hsave_msr;
b286d5d8 2730 break;
eb6f302e 2731 case MSR_VM_CR:
4a810181 2732 *data = svm->nested.vm_cr_msr;
eb6f302e 2733 break;
c8a73f18
AG		 2734 case MSR_IA32_UCODE_REV:
2735 *data = 0x01000065;
2736 break;
6aa8b732 2737 default:
3bab1f5d 2738 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2739 }
2740 return 0;
2741}
2742
851ba692 2743static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2744{
ad312c7c 2745 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2746 u64 data;
2747
59200273
AK		 2748 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2749 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2750 kvm_inject_gp(&svm->vcpu, 0);
59200273 2751 } else {
229456fc 2752 trace_kvm_msr_read(ecx, data);
af9ca2d7 2753
5fdbf976 2754 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2755 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2756 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2757 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2758 }
2759 return 1;
2760}
2761
4a810181
JR		 2762static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2763{
2764 struct vcpu_svm *svm = to_svm(vcpu);
2765 int svm_dis, chg_mask;
2766
2767 if (data & ~SVM_VM_CR_VALID_MASK)
2768 return 1;
2769
2770 chg_mask = SVM_VM_CR_VALID_MASK;
2771
2772 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2773 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2774
2775 svm->nested.vm_cr_msr &= ~chg_mask;
2776 svm->nested.vm_cr_msr |= (data & chg_mask);
2777
2778 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2779
2780 /* check for svm_disable while efer.svme is set */
2781 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2782 return 1;
2783
2784 return 0;
2785}
2786
6aa8b732
AK		 2787static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2788{
a2fa3e9f
GH		 2789 struct vcpu_svm *svm = to_svm(vcpu);
2790
6aa8b732 2791 switch (ecx) {
f4e1b3c8 2792 case MSR_IA32_TSC:
99e3e30a 2793 kvm_write_tsc(vcpu, data);
6aa8b732 2794 break;
8c06585d 2795 case MSR_STAR:
a2fa3e9f 2796 svm->vmcb->save.star = data;
6aa8b732 2797 break;
49b14f24 2798#ifdef CONFIG_X86_64
6aa8b732 2799 case MSR_LSTAR:
a2fa3e9f 2800 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2801 break;
2802 case MSR_CSTAR:
a2fa3e9f 2803 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2804 break;
2805 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2806 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2807 break;
2808 case MSR_SYSCALL_MASK:
a2fa3e9f 2809 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2810 break;
2811#endif
2812 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2813 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2814 break;
2815 case MSR_IA32_SYSENTER_EIP:
017cb99e 2816 svm->sysenter_eip = data;
a2fa3e9f 2817 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2818 break;
2819 case MSR_IA32_SYSENTER_ESP:
017cb99e 2820 svm->sysenter_esp = data;
a2fa3e9f 2821 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2822 break;
a2938c80 2823 case MSR_IA32_DEBUGCTLMSR:
2a6b20b8 2824 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
24e09cbf 2825 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2826 __func__, data);
24e09cbf
JR		 2827 break;
2828 }
2829 if (data & DEBUGCTL_RESERVED_BITS)
2830 return 1;
2831
2832 svm->vmcb->save.dbgctl = data;
2833 if (data & (1ULL<<0))
2834 svm_enable_lbrv(svm);
2835 else
2836 svm_disable_lbrv(svm);
a2938c80 2837 break;
b286d5d8 2838 case MSR_VM_HSAVE_PA:
e6aa9abd 2839 svm->nested.hsave_msr = data;
62b9abaa 2840 break;
3c5d0a44 2841 case MSR_VM_CR:
4a810181 2842 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2843 case MSR_VM_IGNNE:
3c5d0a44
AG		 2844 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2845 break;
6aa8b732 2846 default:
3bab1f5d 2847 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2848 }
2849 return 0;
2850}
2851
851ba692 2852static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2853{
ad312c7c 2854 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2855 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2856 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2857
af9ca2d7 2858
5fdbf976 2859 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2860 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2861 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2862 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2863 } else {
2864 trace_kvm_msr_write(ecx, data);
e756fc62 2865 skip_emulated_instruction(&svm->vcpu);
59200273 2866 }
6aa8b732
AK		 2867 return 1;
2868}
2869
851ba692 2870static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2871{
e756fc62 2872 if (svm->vmcb->control.exit_info_1)
851ba692 2873 return wrmsr_interception(svm);
6aa8b732 2874 else
851ba692 2875 return rdmsr_interception(svm);
6aa8b732
AK		 2876}
2877
851ba692 2878static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2879{
851ba692
AK		 2880 struct kvm_run *kvm_run = svm->vcpu.run;
2881
3842d135 2882 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
f0b85051 2883 svm_clear_vintr(svm);
85f455f7 2884 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
decdbf6a 2885 mark_dirty(svm->vmcb, VMCB_INTR);
c1150d8c
DL		 2886 /*
2887 * If the user space waits to inject interrupts, exit as soon as
2888 * possible
2889 */
8061823a
GN		 2890 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2891 kvm_run->request_interrupt_window &&
2892 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2893 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2894 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2895 return 0;
2896 }
2897
2898 return 1;
2899}
2900
565d0998
ML		 2901static int pause_interception(struct vcpu_svm *svm)
2902{
2903 kvm_vcpu_on_spin(&(svm->vcpu));
2904 return 1;
2905}
2906
851ba692 2907static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2908 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2909 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2910 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2911 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2912 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
cda00082 2913 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
e0231715
JR		 2914 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2915 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2916 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2917 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2918 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2919 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2920 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2921 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2922 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2923 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2924 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2925 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2926 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2927 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2928 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2929 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2930 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2931 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2932 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2933 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2934 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2935 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2936 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2937 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2938 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2939 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2940 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2941 [SVM_EXIT_SMI] = nop_on_interception,
2942 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2943 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2944 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2945 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2946 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2947 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2948 [SVM_EXIT_HLT] = halt_interception,
a7052897 2949 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2950 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2951 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2952 [SVM_EXIT_MSR] = msr_interception,
2953 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2954 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2955 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2956 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2957 [SVM_EXIT_VMLOAD] = vmload_interception,
2958 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2959 [SVM_EXIT_STGI] = stgi_interception,
2960 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2961 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2962 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2963 [SVM_EXIT_MONITOR] = invalid_op_interception,
2964 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2965 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2966};
2967
3f10c846
JR		 2968void dump_vmcb(struct kvm_vcpu *vcpu)
2969{
2970 struct vcpu_svm *svm = to_svm(vcpu);
2971 struct vmcb_control_area *control = &svm->vmcb->control;
2972 struct vmcb_save_area *save = &svm->vmcb->save;
2973
2974 pr_err("VMCB Control Area:\n");
4ee546b4
RJ		 2975 pr_err("cr_read: %04x\n", control->intercept_cr & 0xffff);
2976 pr_err("cr_write: %04x\n", control->intercept_cr >> 16);
3aed041a
JR		 2977 pr_err("dr_read: %04x\n", control->intercept_dr & 0xffff);
2978 pr_err("dr_write: %04x\n", control->intercept_dr >> 16);
3f10c846
JR		 2979 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2980 pr_err("intercepts: %016llx\n", control->intercept);
2981 pr_err("pause filter count: %d\n", control->pause_filter_count);
2982 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2983 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2984 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2985 pr_err("asid: %d\n", control->asid);
2986 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2987 pr_err("int_ctl: %08x\n", control->int_ctl);
2988 pr_err("int_vector: %08x\n", control->int_vector);
2989 pr_err("int_state: %08x\n", control->int_state);
2990 pr_err("exit_code: %08x\n", control->exit_code);
2991 pr_err("exit_info1: %016llx\n", control->exit_info_1);
2992 pr_err("exit_info2: %016llx\n", control->exit_info_2);
2993 pr_err("exit_int_info: %08x\n", control->exit_int_info);
2994 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
2995 pr_err("nested_ctl: %lld\n", control->nested_ctl);
2996 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
2997 pr_err("event_inj: %08x\n", control->event_inj);
2998 pr_err("event_inj_err: %08x\n", control->event_inj_err);
2999 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
3000 pr_err("next_rip: %016llx\n", control->next_rip);
3001 pr_err("VMCB State Save Area:\n");
3002 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
3003 save->es.selector, save->es.attrib,
3004 save->es.limit, save->es.base);
3005 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
3006 save->cs.selector, save->cs.attrib,
3007 save->cs.limit, save->cs.base);
3008 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
3009 save->ss.selector, save->ss.attrib,
3010 save->ss.limit, save->ss.base);
3011 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
3012 save->ds.selector, save->ds.attrib,
3013 save->ds.limit, save->ds.base);
3014 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
3015 save->fs.selector, save->fs.attrib,
3016 save->fs.limit, save->fs.base);
3017 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
3018 save->gs.selector, save->gs.attrib,
3019 save->gs.limit, save->gs.base);
3020 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
3021 save->gdtr.selector, save->gdtr.attrib,
3022 save->gdtr.limit, save->gdtr.base);
3023 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
3024 save->ldtr.selector, save->ldtr.attrib,
3025 save->ldtr.limit, save->ldtr.base);
3026 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
3027 save->idtr.selector, save->idtr.attrib,
3028 save->idtr.limit, save->idtr.base);
3029 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
3030 save->tr.selector, save->tr.attrib,
3031 save->tr.limit, save->tr.base);
3032 pr_err("cpl: %d efer: %016llx\n",
3033 save->cpl, save->efer);
3034 pr_err("cr0: %016llx cr2: %016llx\n",
3035 save->cr0, save->cr2);
3036 pr_err("cr3: %016llx cr4: %016llx\n",
3037 save->cr3, save->cr4);
3038 pr_err("dr6: %016llx dr7: %016llx\n",
3039 save->dr6, save->dr7);
3040 pr_err("rip: %016llx rflags: %016llx\n",
3041 save->rip, save->rflags);
3042 pr_err("rsp: %016llx rax: %016llx\n",
3043 save->rsp, save->rax);
3044 pr_err("star: %016llx lstar: %016llx\n",
3045 save->star, save->lstar);
3046 pr_err("cstar: %016llx sfmask: %016llx\n",
3047 save->cstar, save->sfmask);
3048 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
3049 save->kernel_gs_base, save->sysenter_cs);
3050 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
3051 save->sysenter_esp, save->sysenter_eip);
3052 pr_err("gpat: %016llx dbgctl: %016llx\n",
3053 save->g_pat, save->dbgctl);
3054 pr_err("br_from: %016llx br_to: %016llx\n",
3055 save->br_from, save->br_to);
3056 pr_err("excp_from: %016llx excp_to: %016llx\n",
3057 save->last_excp_from, save->last_excp_to);
3058
3059}
3060
586f9607
AK		 3061static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3062{
3063 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3064
3065 *info1 = control->exit_info_1;
3066 *info2 = control->exit_info_2;
3067}
3068
851ba692 3069static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3070{
04d2cc77 3071 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 3072 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 3073 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 3074
aa17911e 3075 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
af9ca2d7 3076
4ee546b4 3077 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
2be4fc7a
JR		 3078 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3079 if (npt_enabled)
3080 vcpu->arch.cr3 = svm->vmcb->save.cr3;
af9ca2d7 3081
cd3ff653
JR		 3082 if (unlikely(svm->nested.exit_required)) {
3083 nested_svm_vmexit(svm);
3084 svm->nested.exit_required = false;
3085
3086 return 1;
3087 }
3088
2030753d 3089 if (is_guest_mode(vcpu)) {
410e4d57
JR		 3090 int vmexit;
3091
d8cabddf
JR		 3092 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3093 svm->vmcb->control.exit_info_1,
3094 svm->vmcb->control.exit_info_2,
3095 svm->vmcb->control.exit_int_info,
3096 svm->vmcb->control.exit_int_info_err);
3097
410e4d57
JR		 3098 vmexit = nested_svm_exit_special(svm);
3099
3100 if (vmexit == NESTED_EXIT_CONTINUE)
3101 vmexit = nested_svm_exit_handled(svm);
3102
3103 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 3104 return 1;
cf74a78b
AG		 3105 }
3106
a5c3832d
JR		 3107 svm_complete_interrupts(svm);
3108
04d2cc77
AK		 3109 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3110 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3111 kvm_run->fail_entry.hardware_entry_failure_reason
3112 = svm->vmcb->control.exit_code;
3f10c846
JR		 3113 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3114 dump_vmcb(vcpu);
04d2cc77
AK		 3115 return 0;
3116 }
3117
a2fa3e9f 3118 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 3119 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
55c5e464
JR		 3120 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3121 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
6aa8b732
AK		 3122 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3123 "exit_code 0x%x\n",
b8688d51 3124 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 3125 exit_code);
3126
9d8f549d 3127 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 3128 || !svm_exit_handlers[exit_code]) {
6aa8b732 3129 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 3130 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 3131 return 0;
3132 }
3133
851ba692 3134 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 3135}
3136
3137static void reload_tss(struct kvm_vcpu *vcpu)
3138{
3139 int cpu = raw_smp_processor_id();
3140
0fe1e009
TH		 3141 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3142 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 3143 load_TR_desc();
3144}
3145
e756fc62 3146static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 3147{
3148 int cpu = raw_smp_processor_id();
3149
0fe1e009 3150 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 3151
a2fa3e9f 3152 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 3153 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 3154 if (svm->asid_generation != sd->asid_generation)
3155 new_asid(svm, sd);
6aa8b732
AK		 3156}
3157
95ba8273
GN		 3158static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3159{
3160 struct vcpu_svm *svm = to_svm(vcpu);
3161
3162 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3163 vcpu->arch.hflags |= HF_NMI_MASK;
8a05a1b8 3164 set_intercept(svm, INTERCEPT_IRET);
95ba8273
GN		 3165 ++vcpu->stat.nmi_injections;
3166}
6aa8b732 3167
85f455f7 3168static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 3169{
3170 struct vmcb_control_area *control;
3171
e756fc62 3172 control = &svm->vmcb->control;
85f455f7 3173 control->int_vector = irq;
6aa8b732
AK		 3174 control->int_ctl &= ~V_INTR_PRIO_MASK;
3175 control->int_ctl |= V_IRQ_MASK |
3176 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
decdbf6a 3177 mark_dirty(svm->vmcb, VMCB_INTR);
6aa8b732
AK		 3178}
3179
66fd3f7f 3180static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 3181{
3182 struct vcpu_svm *svm = to_svm(vcpu);
3183
2af9194d 3184 BUG_ON(!(gif_set(svm)));
cf74a78b 3185
9fb2d2b4
GN		 3186 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3187 ++vcpu->stat.irq_injections;
3188
219b65dc
AG		 3189 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3190 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 3191}
3192
95ba8273 3193static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 3194{
3195 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 3196
2030753d 3197 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
88ab24ad
JR		 3198 return;
3199
95ba8273 3200 if (irr == -1)
aaacfc9a
JR		 3201 return;
3202
95ba8273 3203 if (tpr >= irr)
4ee546b4 3204 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
95ba8273 3205}
aaacfc9a 3206
95ba8273
GN		 3207static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3208{
3209 struct vcpu_svm *svm = to_svm(vcpu);
3210 struct vmcb *vmcb = svm->vmcb;
924584cc
JR		 3211 int ret;
3212 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3213 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3214 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3215
3216 return ret;
aaacfc9a
JR		 3217}
3218
3cfc3092
JK		 3219static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3220{
3221 struct vcpu_svm *svm = to_svm(vcpu);
3222
3223 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3224}
3225
3226static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3227{
3228 struct vcpu_svm *svm = to_svm(vcpu);
3229
3230 if (masked) {
3231 svm->vcpu.arch.hflags |= HF_NMI_MASK;
8a05a1b8 3232 set_intercept(svm, INTERCEPT_IRET);
3cfc3092
JK		 3233 } else {
3234 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
8a05a1b8 3235 clr_intercept(svm, INTERCEPT_IRET);
3cfc3092
JK		 3236 }
3237}
3238
78646121
GN		 3239static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3240{
3241 struct vcpu_svm *svm = to_svm(vcpu);
3242 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 3243 int ret;
3244
3245 if (!gif_set(svm) ||
3246 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3247 return 0;
3248
3249 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3250
2030753d 3251 if (is_guest_mode(vcpu))
7fcdb510
JR		 3252 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3253
3254 return ret;
78646121
GN		 3255}
3256
9222be18 3257static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 3258{
219b65dc 3259 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 3260
e0231715
JR		 3261 /*
3262 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3263 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3264 * get that intercept, this function will be called again though and
3265 * we'll get the vintr intercept.
3266 */
8fe54654 3267 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 3268 svm_set_vintr(svm);
3269 svm_inject_irq(svm, 0x0);
3270 }
85f455f7
ED		 3271}
3272
95ba8273 3273static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 3274{
04d2cc77 3275 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 3276
44c11430
GN		 3277 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3278 == HF_NMI_MASK)
3279 return; /* IRET will cause a vm exit */
3280
e0231715
JR		 3281 /*
3282 * Something prevents NMI from been injected. Single step over possible
3283 * problem (IRET or exception injection or interrupt shadow)
3284 */
6be7d306 3285 svm->nmi_singlestep = true;
44c11430
GN		 3286 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3287 update_db_intercept(vcpu);
c1150d8c
DL		 3288}
3289
cbc94022
IE		 3290static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3291{
3292 return 0;
3293}
3294
d9e368d6
AK		 3295static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3296{
3297 force_new_asid(vcpu);
3298}
3299
04d2cc77
AK		 3300static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3301{
3302}
3303
d7bf8221
JR		 3304static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3305{
3306 struct vcpu_svm *svm = to_svm(vcpu);
3307
2030753d 3308 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
88ab24ad
JR		 3309 return;
3310
4ee546b4 3311 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
d7bf8221 3312 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 3313 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 3314 }
3315}
3316
649d6864
JR		 3317static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3318{
3319 struct vcpu_svm *svm = to_svm(vcpu);
3320 u64 cr8;
3321
2030753d 3322 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
88ab24ad
JR		 3323 return;
3324
649d6864
JR		 3325 cr8 = kvm_get_cr8(vcpu);
3326 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3327 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3328}
3329
9222be18
GN		 3330static void svm_complete_interrupts(struct vcpu_svm *svm)
3331{
3332 u8 vector;
3333 int type;
3334 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 3335 unsigned int3_injected = svm->int3_injected;
3336
3337 svm->int3_injected = 0;
9222be18 3338
3842d135 3339 if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
44c11430 3340 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3842d135
AK		 3341 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3342 }
44c11430 3343
9222be18
GN		 3344 svm->vcpu.arch.nmi_injected = false;
3345 kvm_clear_exception_queue(&svm->vcpu);
3346 kvm_clear_interrupt_queue(&svm->vcpu);
3347
3348 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3349 return;
3350
3842d135
AK		 3351 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3352
9222be18
GN		 3353 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3354 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3355
3356 switch (type) {
3357 case SVM_EXITINTINFO_TYPE_NMI:
3358 svm->vcpu.arch.nmi_injected = true;
3359 break;
3360 case SVM_EXITINTINFO_TYPE_EXEPT:
66b7138f
JK		 3361 /*
3362 * In case of software exceptions, do not reinject the vector,
3363 * but re-execute the instruction instead. Rewind RIP first
3364 * if we emulated INT3 before.
3365 */
3366 if (kvm_exception_is_soft(vector)) {
3367 if (vector == BP_VECTOR && int3_injected &&
3368 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3369 kvm_rip_write(&svm->vcpu,
3370 kvm_rip_read(&svm->vcpu) -
3371 int3_injected);
9222be18 3372 break;
66b7138f 3373 }
9222be18
GN		 3374 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3375 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 3376 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 3377
3378 } else
ce7ddec4 3379 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 3380 break;
3381 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 3382 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 3383 break;
3384 default:
3385 break;
3386 }
3387}
3388
b463a6f7
AK		 3389static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3390{
3391 struct vcpu_svm *svm = to_svm(vcpu);
3392 struct vmcb_control_area *control = &svm->vmcb->control;
3393
3394 control->exit_int_info = control->event_inj;
3395 control->exit_int_info_err = control->event_inj_err;
3396 control->event_inj = 0;
3397 svm_complete_interrupts(svm);
3398}
3399
80e31d4f
AK		 3400#ifdef CONFIG_X86_64
3401#define R "r"
3402#else
3403#define R "e"
3404#endif
3405
851ba692 3406static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3407{
a2fa3e9f 3408 struct vcpu_svm *svm = to_svm(vcpu);
d9e368d6 3409
2041a06a
JR		 3410 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3411 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3412 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3413
cd3ff653
JR		 3414 /*
3415 * A vmexit emulation is required before the vcpu can be executed
3416 * again.
3417 */
3418 if (unlikely(svm->nested.exit_required))
3419 return;
3420
e756fc62 3421 pre_svm_run(svm);
6aa8b732 3422
649d6864
JR		 3423 sync_lapic_to_cr8(vcpu);
3424
cda0ffdd 3425 svm->vmcb->save.cr2 = vcpu->arch.cr2;
6aa8b732 3426
04d2cc77
AK		 3427 clgi();
3428
3429 local_irq_enable();
36241b8c 3430
6aa8b732 3431 asm volatile (
80e31d4f
AK		 3432 "push %%"R"bp; \n\t"
3433 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3434 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3435 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3436 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3437 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3438 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 3439#ifdef CONFIG_X86_64
fb3f0f51
RR		 3440 "mov %c[r8](%[svm]), %%r8 \n\t"
3441 "mov %c[r9](%[svm]), %%r9 \n\t"
3442 "mov %c[r10](%[svm]), %%r10 \n\t"
3443 "mov %c[r11](%[svm]), %%r11 \n\t"
3444 "mov %c[r12](%[svm]), %%r12 \n\t"
3445 "mov %c[r13](%[svm]), %%r13 \n\t"
3446 "mov %c[r14](%[svm]), %%r14 \n\t"
3447 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 3448#endif
3449
6aa8b732 3450 /* Enter guest mode */
80e31d4f
AK		 3451 "push %%"R"ax \n\t"
3452 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 3453 __ex(SVM_VMLOAD) "\n\t"
3454 __ex(SVM_VMRUN) "\n\t"
3455 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 3456 "pop %%"R"ax \n\t"
6aa8b732
AK		 3457
3458 /* Save guest registers, load host registers */
80e31d4f
AK		 3459 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3460 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3461 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3462 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3463 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3464 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 3465#ifdef CONFIG_X86_64
fb3f0f51
RR		 3466 "mov %%r8, %c[r8](%[svm]) \n\t"
3467 "mov %%r9, %c[r9](%[svm]) \n\t"
3468 "mov %%r10, %c[r10](%[svm]) \n\t"
3469 "mov %%r11, %c[r11](%[svm]) \n\t"
3470 "mov %%r12, %c[r12](%[svm]) \n\t"
3471 "mov %%r13, %c[r13](%[svm]) \n\t"
3472 "mov %%r14, %c[r14](%[svm]) \n\t"
3473 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 3474#endif
80e31d4f 3475 "pop %%"R"bp"
6aa8b732 3476 :
fb3f0f51 3477 : [svm]"a"(svm),
6aa8b732 3478 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 3479 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3480 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3481 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3482 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3483 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3484 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 3485#ifdef CONFIG_X86_64
ad312c7c
ZX		 3486 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3487 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3488 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3489 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3490 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3491 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3492 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3493 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 3494#endif
54a08c04 3495 : "cc", "memory"
80e31d4f 3496 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 3497#ifdef CONFIG_X86_64
54a08c04
LV		 3498 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3499#endif
3500 );
6aa8b732 3501
82ca2d10
AK		 3502#ifdef CONFIG_X86_64
3503 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3504#else
dacccfdd 3505 loadsegment(fs, svm->host.fs);
9581d442 3506#endif
6aa8b732
AK		 3507
3508 reload_tss(vcpu);
3509
56ba47dd
AK		 3510 local_irq_disable();
3511
3512 stgi();
3513
13c34e07
AK		 3514 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3515 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3516 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3517 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3518
d7bf8221
JR		 3519 sync_cr8_to_lapic(vcpu);
3520
a2fa3e9f 3521 svm->next_rip = 0;
9222be18 3522
631bc487
GN		 3523 /* if exit due to PF check for async PF */
3524 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3525 svm->apf_reason = kvm_read_and_reset_pf_reason();
3526
6de4f3ad
AK		 3527 if (npt_enabled) {
3528 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3529 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3530 }
fe5913e4
JR		 3531
3532 /*
3533 * We need to handle MC intercepts here before the vcpu has a chance to
3534 * change the physical cpu
3535 */
3536 if (unlikely(svm->vmcb->control.exit_code ==
3537 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3538 svm_handle_mce(svm);
8d28fec4
RJ		 3539
3540 mark_all_clean(svm->vmcb);
6aa8b732
AK		 3541}
3542
80e31d4f
AK		 3543#undef R
3544
6aa8b732
AK		 3545static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3546{
a2fa3e9f
GH		 3547 struct vcpu_svm *svm = to_svm(vcpu);
3548
3549 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 3550 force_new_asid(vcpu);
3551}
3552
1c97f0a0
JR		 3553static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3554{
3555 struct vcpu_svm *svm = to_svm(vcpu);
3556
3557 svm->vmcb->control.nested_cr3 = root;
3558
3559 /* Also sync guest cr3 here in case we live migrate */
3560 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3561
3562 force_new_asid(vcpu);
3563}
3564
6aa8b732
AK		 3565static int is_disabled(void)
3566{
6031a61c
JR		 3567 u64 vm_cr;
3568
3569 rdmsrl(MSR_VM_CR, vm_cr);
3570 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3571 return 1;
3572
6aa8b732
AK		 3573 return 0;
3574}
3575
102d8325
IM		 3576static void
3577svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3578{
3579 /*
3580 * Patch in the VMMCALL instruction:
3581 */
3582 hypercall[0] = 0x0f;
3583 hypercall[1] = 0x01;
3584 hypercall[2] = 0xd9;
102d8325
IM		 3585}
3586
002c7f7c
YS		 3587static void svm_check_processor_compat(void *rtn)
3588{
3589 *(int *)rtn = 0;
3590}
3591
774ead3a
AK		 3592static bool svm_cpu_has_accelerated_tpr(void)
3593{
3594 return false;
3595}
3596
4b12f0de 3597static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3598{
3599 return 0;
3600}
3601
0e851880
SY		 3602static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3603{
3604}
3605
d4330ef2
JR		 3606static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3607{
c2c63a49 3608 switch (func) {
24d1b15f
JR		 3609 case 0x00000001:
3610 /* Mask out xsave bit as long as it is not supported by SVM */
3611 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3612 break;
4c62a2dc
JR		 3613 case 0x80000001:
3614 if (nested)
3615 entry->ecx |= (1 << 2); /* Set SVM bit */
3616 break;
c2c63a49
JR		 3617 case 0x8000000A:
3618 entry->eax = 1; /* SVM revision 1 */
3619 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3620 ASID emulation to nested SVM */
3621 entry->ecx = 0; /* Reserved */
7a190667
JR		 3622 entry->edx = 0; /* Per default do not support any
3623 additional features */
3624
3625 /* Support next_rip if host supports it */
2a6b20b8 3626 if (boot_cpu_has(X86_FEATURE_NRIPS))
7a190667 3627 entry->edx |= SVM_FEATURE_NRIP;
c2c63a49 3628
3d4aeaad
JR		 3629 /* Support NPT for the guest if enabled */
3630 if (npt_enabled)
3631 entry->edx |= SVM_FEATURE_NPT;
3632
c2c63a49
JR		 3633 break;
3634 }
d4330ef2
JR		 3635}
3636
229456fc 3637static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 3638 { SVM_EXIT_READ_CR0, "read_cr0" },
3639 { SVM_EXIT_READ_CR3, "read_cr3" },
3640 { SVM_EXIT_READ_CR4, "read_cr4" },
3641 { SVM_EXIT_READ_CR8, "read_cr8" },
3642 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3643 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3644 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3645 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3646 { SVM_EXIT_READ_DR0, "read_dr0" },
3647 { SVM_EXIT_READ_DR1, "read_dr1" },
3648 { SVM_EXIT_READ_DR2, "read_dr2" },
3649 { SVM_EXIT_READ_DR3, "read_dr3" },
3650 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3651 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3652 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3653 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3654 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3655 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3656 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3657 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3658 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3659 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3660 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3661 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3662 { SVM_EXIT_INTR, "interrupt" },
3663 { SVM_EXIT_NMI, "nmi" },
3664 { SVM_EXIT_SMI, "smi" },
3665 { SVM_EXIT_INIT, "init" },
3666 { SVM_EXIT_VINTR, "vintr" },
3667 { SVM_EXIT_CPUID, "cpuid" },
3668 { SVM_EXIT_INVD, "invd" },
3669 { SVM_EXIT_HLT, "hlt" },
3670 { SVM_EXIT_INVLPG, "invlpg" },
3671 { SVM_EXIT_INVLPGA, "invlpga" },
3672 { SVM_EXIT_IOIO, "io" },
3673 { SVM_EXIT_MSR, "msr" },
3674 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3675 { SVM_EXIT_SHUTDOWN, "shutdown" },
3676 { SVM_EXIT_VMRUN, "vmrun" },
3677 { SVM_EXIT_VMMCALL, "hypercall" },
3678 { SVM_EXIT_VMLOAD, "vmload" },
3679 { SVM_EXIT_VMSAVE, "vmsave" },
3680 { SVM_EXIT_STGI, "stgi" },
3681 { SVM_EXIT_CLGI, "clgi" },
3682 { SVM_EXIT_SKINIT, "skinit" },
3683 { SVM_EXIT_WBINVD, "wbinvd" },
3684 { SVM_EXIT_MONITOR, "monitor" },
3685 { SVM_EXIT_MWAIT, "mwait" },
3686 { SVM_EXIT_NPF, "npf" },
3687 { -1, NULL }
3688};
3689
17cc3935 3690static int svm_get_lpage_level(void)
344f414f 3691{
17cc3935 3692 return PT_PDPE_LEVEL;
344f414f
JR		 3693}
3694
4e47c7a6
SY		 3695static bool svm_rdtscp_supported(void)
3696{
3697 return false;
3698}
3699
f5f48ee1
SY		 3700static bool svm_has_wbinvd_exit(void)
3701{
3702 return true;
3703}
3704
02daab21
AK		 3705static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3706{
3707 struct vcpu_svm *svm = to_svm(vcpu);
3708
18c918c5 3709 set_exception_intercept(svm, NM_VECTOR);
66a562f7 3710 update_cr0_intercept(svm);
02daab21
AK		 3711}
3712
cbdd1bea 3713static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3714 .cpu_has_kvm_support = has_svm,
3715 .disabled_by_bios = is_disabled,
3716 .hardware_setup = svm_hardware_setup,
3717 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3718 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3719 .hardware_enable = svm_hardware_enable,
3720 .hardware_disable = svm_hardware_disable,
774ead3a 3721 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3722
3723 .vcpu_create = svm_create_vcpu,
3724 .vcpu_free = svm_free_vcpu,
04d2cc77 3725 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3726
04d2cc77 3727 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3728 .vcpu_load = svm_vcpu_load,
3729 .vcpu_put = svm_vcpu_put,
3730
3731 .set_guest_debug = svm_guest_debug,
3732 .get_msr = svm_get_msr,
3733 .set_msr = svm_set_msr,
3734 .get_segment_base = svm_get_segment_base,
3735 .get_segment = svm_get_segment,
3736 .set_segment = svm_set_segment,
2e4d2653 3737 .get_cpl = svm_get_cpl,
1747fb71 3738 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3739 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3740 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3741 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3742 .set_cr3 = svm_set_cr3,
3743 .set_cr4 = svm_set_cr4,
3744 .set_efer = svm_set_efer,
3745 .get_idt = svm_get_idt,
3746 .set_idt = svm_set_idt,
3747 .get_gdt = svm_get_gdt,
3748 .set_gdt = svm_set_gdt,
020df079 3749 .set_dr7 = svm_set_dr7,
6de4f3ad 3750 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3751 .get_rflags = svm_get_rflags,
3752 .set_rflags = svm_set_rflags,
6b52d186 3753 .fpu_activate = svm_fpu_activate,
02daab21 3754 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3755
6aa8b732 3756 .tlb_flush = svm_flush_tlb,
6aa8b732 3757
6aa8b732 3758 .run = svm_vcpu_run,
04d2cc77 3759 .handle_exit = handle_exit,
6aa8b732 3760 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3761 .set_interrupt_shadow = svm_set_interrupt_shadow,
3762 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3763 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3764 .set_irq = svm_set_irq,
95ba8273 3765 .set_nmi = svm_inject_nmi,
298101da 3766 .queue_exception = svm_queue_exception,
b463a6f7 3767 .cancel_injection = svm_cancel_injection,
78646121 3768 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3769 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3770 .get_nmi_mask = svm_get_nmi_mask,
3771 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3772 .enable_nmi_window = enable_nmi_window,
3773 .enable_irq_window = enable_irq_window,
3774 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3775
3776 .set_tss_addr = svm_set_tss_addr,
67253af5 3777 .get_tdp_level = get_npt_level,
4b12f0de 3778 .get_mt_mask = svm_get_mt_mask,
229456fc 3779
586f9607 3780 .get_exit_info = svm_get_exit_info,
229456fc 3781 .exit_reasons_str = svm_exit_reasons_str,
586f9607 3782
17cc3935 3783 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3784
3785 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3786
3787 .rdtscp_supported = svm_rdtscp_supported,
d4330ef2
JR		 3788
3789 .set_supported_cpuid = svm_set_supported_cpuid,
f5f48ee1
SY		 3790
3791 .has_wbinvd_exit = svm_has_wbinvd_exit,
99e3e30a
ZA		 3792
3793 .write_tsc_offset = svm_write_tsc_offset,
e48672fa 3794 .adjust_tsc_offset = svm_adjust_tsc_offset,
1c97f0a0
JR		 3795
3796 .set_tdp_cr3 = set_tdp_cr3,
6aa8b732
AK		 3797};
3798
3799static int __init svm_init(void)
3800{
cb498ea2 3801 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
0ee75bea 3802 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 3803}
3804
3805static void __exit svm_exit(void)
3806{
cb498ea2 3807 kvm_exit();
6aa8b732
AK		 3808}
3809
3810module_init(svm_init)
3811module_exit(svm_exit)
kernel source for telekom puls (alcatel/mediatek)