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percpu: make percpu symbols in xen unique
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
6aa8b732 29
e495606d 30#include <asm/desc.h>
6aa8b732 31
63d1142f 32#include <asm/virtext.h>
229456fc 33#include "trace.h"
63d1142f 34
4ecac3fd
AK		 35#define __ex(x) __kvm_handle_fault_on_reboot(x)
36
6aa8b732
AK		 37MODULE_AUTHOR("Qumranet");
38MODULE_LICENSE("GPL");
39
40#define IOPM_ALLOC_ORDER 2
41#define MSRPM_ALLOC_ORDER 1
42
6aa8b732
AK		 43#define SEG_TYPE_LDT 2
44#define SEG_TYPE_BUSY_TSS16 3
45
80b7706e
JR		 46#define SVM_FEATURE_NPT (1 << 0)
47#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 48#define SVM_FEATURE_SVML (1 << 2)
80b7706e 49
410e4d57
JR		 50#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
51#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
52#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
53
24e09cbf
JR		 54#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
55
c0725420
AG		 56/* Turn on to get debugging output*/
57/* #define NESTED_DEBUG */
58
59#ifdef NESTED_DEBUG
60#define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
61#else
62#define nsvm_printk(fmt, args...) do {} while(0)
63#endif
64
6c8166a7
AK		 65static const u32 host_save_user_msrs[] = {
66#ifdef CONFIG_X86_64
67 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
68 MSR_FS_BASE,
69#endif
70 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
71};
72
73#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
74
75struct kvm_vcpu;
76
e6aa9abd
JR		 77struct nested_state {
78 struct vmcb *hsave;
79 u64 hsave_msr;
80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
aad42c64
JR		 87
88 /* cache for intercepts of the guest */
89 u16 intercept_cr_read;
90 u16 intercept_cr_write;
91 u16 intercept_dr_read;
92 u16 intercept_dr_write;
93 u32 intercept_exceptions;
94 u64 intercept;
95
e6aa9abd
JR		 96};
97
6c8166a7
AK		 98struct vcpu_svm {
99 struct kvm_vcpu vcpu;
100 struct vmcb *vmcb;
101 unsigned long vmcb_pa;
102 struct svm_cpu_data *svm_data;
103 uint64_t asid_generation;
104 uint64_t sysenter_esp;
105 uint64_t sysenter_eip;
106
107 u64 next_rip;
108
109 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
110 u64 host_gs_base;
6c8166a7
AK		 111
112 u32 *msrpm;
6c8166a7 113
e6aa9abd 114 struct nested_state nested;
6c8166a7
AK		 115};
116
709ddebf
JR		 117/* enable NPT for AMD64 and X86 with PAE */
118#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
119static bool npt_enabled = true;
120#else
e3da3acd 121static bool npt_enabled = false;
709ddebf 122#endif
6c7dac72
JR		 123static int npt = 1;
124
125module_param(npt, int, S_IRUGO);
e3da3acd 126
4b6e4dca 127static int nested = 1;
236de055
AG		 128module_param(nested, int, S_IRUGO);
129
44874f84 130static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 131static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 132
410e4d57 133static int nested_svm_exit_handled(struct vcpu_svm *svm);
cf74a78b 134static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 135static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
136 bool has_error_code, u32 error_code);
137
a2fa3e9f
GH		 138static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
139{
fb3f0f51 140 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 141}
142
3d6368ef
AG		 143static inline bool is_nested(struct vcpu_svm *svm)
144{
e6aa9abd 145 return svm->nested.vmcb;
3d6368ef
AG		 146}
147
2af9194d
JR		 148static inline void enable_gif(struct vcpu_svm *svm)
149{
150 svm->vcpu.arch.hflags |= HF_GIF_MASK;
151}
152
153static inline void disable_gif(struct vcpu_svm *svm)
154{
155 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
156}
157
158static inline bool gif_set(struct vcpu_svm *svm)
159{
160 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
161}
162
4866d5e3 163static unsigned long iopm_base;
6aa8b732
AK		 164
165struct kvm_ldttss_desc {
166 u16 limit0;
167 u16 base0;
168 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
169 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
170 u32 base3;
171 u32 zero1;
172} __attribute__((packed));
173
174struct svm_cpu_data {
175 int cpu;
176
5008fdf5
AK		 177 u64 asid_generation;
178 u32 max_asid;
179 u32 next_asid;
6aa8b732
AK		 180 struct kvm_ldttss_desc *tss_desc;
181
182 struct page *save_area;
183};
184
185static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 186static uint32_t svm_features;
6aa8b732
AK		 187
188struct svm_init_data {
189 int cpu;
190 int r;
191};
192
193static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
194
9d8f549d 195#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 196#define MSRS_RANGE_SIZE 2048
197#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
198
199#define MAX_INST_SIZE 15
200
80b7706e
JR		 201static inline u32 svm_has(u32 feat)
202{
203 return svm_features & feat;
204}
205
6aa8b732
AK		 206static inline void clgi(void)
207{
4ecac3fd 208 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 209}
210
211static inline void stgi(void)
212{
4ecac3fd 213 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 214}
215
216static inline void invlpga(unsigned long addr, u32 asid)
217{
4ecac3fd 218 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 219}
220
6aa8b732
AK		 221static inline void force_new_asid(struct kvm_vcpu *vcpu)
222{
a2fa3e9f 223 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 224}
225
226static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
227{
228 force_new_asid(vcpu);
229}
230
231static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
232{
709ddebf 233 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 234 efer &= ~EFER_LME;
6aa8b732 235
9962d032 236 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
ad312c7c 237 vcpu->arch.shadow_efer = efer;
6aa8b732
AK		 238}
239
298101da
AK		 240static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
241 bool has_error_code, u32 error_code)
242{
243 struct vcpu_svm *svm = to_svm(vcpu);
244
cf74a78b
AG		 245 /* If we are within a nested VM we'd better #VMEXIT and let the
246 guest handle the exception */
247 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
248 return;
249
298101da
AK		 250 svm->vmcb->control.event_inj = nr
251 | SVM_EVTINJ_VALID
252 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
253 | SVM_EVTINJ_TYPE_EXEPT;
254 svm->vmcb->control.event_inj_err = error_code;
255}
256
6aa8b732
AK		 257static int is_external_interrupt(u32 info)
258{
259 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
260 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
261}
262
2809f5d2
GC		 263static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
264{
265 struct vcpu_svm *svm = to_svm(vcpu);
266 u32 ret = 0;
267
268 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
269 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
270 return ret & mask;
271}
272
273static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
274{
275 struct vcpu_svm *svm = to_svm(vcpu);
276
277 if (mask == 0)
278 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
279 else
280 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
281
282}
283
6aa8b732
AK		 284static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
285{
a2fa3e9f
GH		 286 struct vcpu_svm *svm = to_svm(vcpu);
287
288 if (!svm->next_rip) {
f629cf84
GN		 289 if (emulate_instruction(vcpu, vcpu->run, 0, 0, EMULTYPE_SKIP) !=
290 EMULATE_DONE)
291 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 292 return;
293 }
5fdbf976
MT		 294 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
295 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
296 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 297
5fdbf976 298 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 299 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 300}
301
302static int has_svm(void)
303{
63d1142f 304 const char *msg;
6aa8b732 305
63d1142f 306 if (!cpu_has_svm(&msg)) {
ff81ff10 307 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 308 return 0;
309 }
310
6aa8b732
AK		 311 return 1;
312}
313
314static void svm_hardware_disable(void *garbage)
315{
2c8dceeb 316 cpu_svm_disable();
6aa8b732
AK		 317}
318
319static void svm_hardware_enable(void *garbage)
320{
321
322 struct svm_cpu_data *svm_data;
323 uint64_t efer;
b792c344 324 struct descriptor_table gdt_descr;
6aa8b732
AK		 325 struct desc_struct *gdt;
326 int me = raw_smp_processor_id();
327
328 if (!has_svm()) {
329 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
330 return;
331 }
332 svm_data = per_cpu(svm_data, me);
333
334 if (!svm_data) {
335 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
336 me);
337 return;
338 }
339
340 svm_data->asid_generation = 1;
341 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
342 svm_data->next_asid = svm_data->max_asid + 1;
343
b792c344
AM		 344 kvm_get_gdt(&gdt_descr);
345 gdt = (struct desc_struct *)gdt_descr.base;
6aa8b732
AK		 346 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
347
348 rdmsrl(MSR_EFER, efer);
9962d032 349 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732
AK		 350
351 wrmsrl(MSR_VM_HSAVE_PA,
352 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
353}
354
0da1db75
JR		 355static void svm_cpu_uninit(int cpu)
356{
357 struct svm_cpu_data *svm_data
358 = per_cpu(svm_data, raw_smp_processor_id());
359
360 if (!svm_data)
361 return;
362
363 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
364 __free_page(svm_data->save_area);
365 kfree(svm_data);
366}
367
6aa8b732
AK		 368static int svm_cpu_init(int cpu)
369{
370 struct svm_cpu_data *svm_data;
371 int r;
372
373 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
374 if (!svm_data)
375 return -ENOMEM;
376 svm_data->cpu = cpu;
377 svm_data->save_area = alloc_page(GFP_KERNEL);
378 r = -ENOMEM;
379 if (!svm_data->save_area)
380 goto err_1;
381
382 per_cpu(svm_data, cpu) = svm_data;
383
384 return 0;
385
386err_1:
387 kfree(svm_data);
388 return r;
389
390}
391
bfc733a7
RR		 392static void set_msr_interception(u32 *msrpm, unsigned msr,
393 int read, int write)
6aa8b732
AK		 394{
395 int i;
396
397 for (i = 0; i < NUM_MSR_MAPS; i++) {
398 if (msr >= msrpm_ranges[i] &&
399 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
400 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
401 msrpm_ranges[i]) * 2;
402
403 u32 *base = msrpm + (msr_offset / 32);
404 u32 msr_shift = msr_offset % 32;
405 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
406 *base = (*base & ~(0x3 << msr_shift)) |
407 (mask << msr_shift);
bfc733a7 408 return;
6aa8b732
AK		 409 }
410 }
bfc733a7 411 BUG();
6aa8b732
AK		 412}
413
f65c229c
JR		 414static void svm_vcpu_init_msrpm(u32 *msrpm)
415{
416 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
417
418#ifdef CONFIG_X86_64
419 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
420 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
421 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
422 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
423 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
424 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
425#endif
426 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
427 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
f65c229c
JR		 428}
429
24e09cbf
JR		 430static void svm_enable_lbrv(struct vcpu_svm *svm)
431{
432 u32 *msrpm = svm->msrpm;
433
434 svm->vmcb->control.lbr_ctl = 1;
435 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
436 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
437 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
438 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
439}
440
441static void svm_disable_lbrv(struct vcpu_svm *svm)
442{
443 u32 *msrpm = svm->msrpm;
444
445 svm->vmcb->control.lbr_ctl = 0;
446 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
447 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
448 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
449 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
450}
451
6aa8b732
AK		 452static __init int svm_hardware_setup(void)
453{
454 int cpu;
455 struct page *iopm_pages;
f65c229c 456 void *iopm_va;
6aa8b732
AK		 457 int r;
458
6aa8b732
AK		 459 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
460
461 if (!iopm_pages)
462 return -ENOMEM;
c8681339
AL		 463
464 iopm_va = page_address(iopm_pages);
465 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 466 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
467
50a37eb4
JR		 468 if (boot_cpu_has(X86_FEATURE_NX))
469 kvm_enable_efer_bits(EFER_NX);
470
1b2fd70c
AG		 471 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
472 kvm_enable_efer_bits(EFER_FFXSR);
473
236de055
AG		 474 if (nested) {
475 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
476 kvm_enable_efer_bits(EFER_SVME);
477 }
478
6aa8b732
AK		 479 for_each_online_cpu(cpu) {
480 r = svm_cpu_init(cpu);
481 if (r)
f65c229c 482 goto err;
6aa8b732 483 }
33bd6a0b
JR		 484
485 svm_features = cpuid_edx(SVM_CPUID_FUNC);
486
e3da3acd
JR		 487 if (!svm_has(SVM_FEATURE_NPT))
488 npt_enabled = false;
489
6c7dac72
JR		 490 if (npt_enabled && !npt) {
491 printk(KERN_INFO "kvm: Nested Paging disabled\n");
492 npt_enabled = false;
493 }
494
18552672 495 if (npt_enabled) {
e3da3acd 496 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 497 kvm_enable_tdp();
5f4cb662
JR		 498 } else
499 kvm_disable_tdp();
e3da3acd 500
6aa8b732
AK		 501 return 0;
502
f65c229c 503err:
6aa8b732
AK		 504 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
505 iopm_base = 0;
506 return r;
507}
508
509static __exit void svm_hardware_unsetup(void)
510{
0da1db75
JR		 511 int cpu;
512
513 for_each_online_cpu(cpu)
514 svm_cpu_uninit(cpu);
515
6aa8b732 516 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 517 iopm_base = 0;
6aa8b732
AK		 518}
519
520static void init_seg(struct vmcb_seg *seg)
521{
522 seg->selector = 0;
523 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
524 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
525 seg->limit = 0xffff;
526 seg->base = 0;
527}
528
529static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
530{
531 seg->selector = 0;
532 seg->attrib = SVM_SELECTOR_P_MASK | type;
533 seg->limit = 0xffff;
534 seg->base = 0;
535}
536
e6101a96 537static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 538{
e6101a96
JR		 539 struct vmcb_control_area *control = &svm->vmcb->control;
540 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732
AK		 541
542 control->intercept_cr_read = INTERCEPT_CR0_MASK |
543 INTERCEPT_CR3_MASK |
649d6864 544 INTERCEPT_CR4_MASK;
6aa8b732
AK		 545
546 control->intercept_cr_write = INTERCEPT_CR0_MASK |
547 INTERCEPT_CR3_MASK |
80a8119c
AK		 548 INTERCEPT_CR4_MASK |
549 INTERCEPT_CR8_MASK;
6aa8b732
AK		 550
551 control->intercept_dr_read = INTERCEPT_DR0_MASK |
552 INTERCEPT_DR1_MASK |
553 INTERCEPT_DR2_MASK |
554 INTERCEPT_DR3_MASK;
555
556 control->intercept_dr_write = INTERCEPT_DR0_MASK |
557 INTERCEPT_DR1_MASK |
558 INTERCEPT_DR2_MASK |
559 INTERCEPT_DR3_MASK |
560 INTERCEPT_DR5_MASK |
561 INTERCEPT_DR7_MASK;
562
7aa81cc0 563 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 564 (1 << UD_VECTOR) |
565 (1 << MC_VECTOR);
6aa8b732
AK		 566
567
568 control->intercept = (1ULL << INTERCEPT_INTR) |
569 (1ULL << INTERCEPT_NMI) |
0152527b 570 (1ULL << INTERCEPT_SMI) |
6aa8b732 571 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 572 (1ULL << INTERCEPT_INVD) |
6aa8b732 573 (1ULL << INTERCEPT_HLT) |
a7052897 574 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 575 (1ULL << INTERCEPT_INVLPGA) |
576 (1ULL << INTERCEPT_IOIO_PROT) |
577 (1ULL << INTERCEPT_MSR_PROT) |
578 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 579 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 580 (1ULL << INTERCEPT_VMRUN) |
581 (1ULL << INTERCEPT_VMMCALL) |
582 (1ULL << INTERCEPT_VMLOAD) |
583 (1ULL << INTERCEPT_VMSAVE) |
584 (1ULL << INTERCEPT_STGI) |
585 (1ULL << INTERCEPT_CLGI) |
916ce236 586 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 587 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 588 (1ULL << INTERCEPT_MONITOR) |
589 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 590
591 control->iopm_base_pa = iopm_base;
f65c229c 592 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 593 control->tsc_offset = 0;
6aa8b732
AK		 594 control->int_ctl = V_INTR_MASKING_MASK;
595
596 init_seg(&save->es);
597 init_seg(&save->ss);
598 init_seg(&save->ds);
599 init_seg(&save->fs);
600 init_seg(&save->gs);
601
602 save->cs.selector = 0xf000;
603 /* Executable/Readable Code Segment */
604 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
605 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
606 save->cs.limit = 0xffff;
d92899a0
AK		 607 /*
608 * cs.base should really be 0xffff0000, but vmx can't handle that, so
609 * be consistent with it.
610 *
611 * Replace when we have real mode working for vmx.
612 */
613 save->cs.base = 0xf0000;
6aa8b732
AK		 614
615 save->gdtr.limit = 0xffff;
616 save->idtr.limit = 0xffff;
617
618 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
619 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
620
9962d032 621 save->efer = EFER_SVME;
d77c26fc 622 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 623 save->dr7 = 0x400;
624 save->rflags = 2;
625 save->rip = 0x0000fff0;
5fdbf976 626 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732
AK		 627
628 /*
629 * cr0 val on cpu init should be 0x60000010, we enable cpu
630 * cache by default. the orderly way is to enable cache in bios.
631 */
707d92fa 632 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
66aee91a 633 save->cr4 = X86_CR4_PAE;
6aa8b732 634 /* rdx = ?? */
709ddebf
JR		 635
636 if (npt_enabled) {
637 /* Setup VMCB for Nested Paging */
638 control->nested_ctl = 1;
a7052897
MT		 639 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
640 (1ULL << INTERCEPT_INVLPG));
709ddebf
JR		 641 control->intercept_exceptions &= ~(1 << PF_VECTOR);
642 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
643 INTERCEPT_CR3_MASK);
644 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
645 INTERCEPT_CR3_MASK);
646 save->g_pat = 0x0007040600070406ULL;
647 /* enable caching because the QEMU Bios doesn't enable it */
648 save->cr0 = X86_CR0_ET;
649 save->cr3 = 0;
650 save->cr4 = 0;
651 }
a79d2f18 652 force_new_asid(&svm->vcpu);
1371d904 653
e6aa9abd 654 svm->nested.vmcb = 0;
2af9194d
JR		 655 svm->vcpu.arch.hflags = 0;
656
657 enable_gif(svm);
6aa8b732
AK		 658}
659
e00c8cf2 660static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 661{
662 struct vcpu_svm *svm = to_svm(vcpu);
663
e6101a96 664 init_vmcb(svm);
70433389 665
c5af89b6 666 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 667 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 668 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
669 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 670 }
5fdbf976
MT		 671 vcpu->arch.regs_avail = ~0;
672 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 673
674 return 0;
04d2cc77
AK		 675}
676
fb3f0f51 677static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 678{
a2fa3e9f 679 struct vcpu_svm *svm;
6aa8b732 680 struct page *page;
f65c229c 681 struct page *msrpm_pages;
b286d5d8 682 struct page *hsave_page;
3d6368ef 683 struct page *nested_msrpm_pages;
fb3f0f51 684 int err;
6aa8b732 685
c16f862d 686 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 687 if (!svm) {
688 err = -ENOMEM;
689 goto out;
690 }
691
692 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
693 if (err)
694 goto free_svm;
695
6aa8b732 696 page = alloc_page(GFP_KERNEL);
fb3f0f51
RR		 697 if (!page) {
698 err = -ENOMEM;
699 goto uninit;
700 }
6aa8b732 701
f65c229c
JR		 702 err = -ENOMEM;
703 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
704 if (!msrpm_pages)
705 goto uninit;
3d6368ef
AG		 706
707 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
708 if (!nested_msrpm_pages)
709 goto uninit;
710
f65c229c
JR		 711 svm->msrpm = page_address(msrpm_pages);
712 svm_vcpu_init_msrpm(svm->msrpm);
713
b286d5d8
AG		 714 hsave_page = alloc_page(GFP_KERNEL);
715 if (!hsave_page)
716 goto uninit;
e6aa9abd 717 svm->nested.hsave = page_address(hsave_page);
b286d5d8 718
e6aa9abd 719 svm->nested.msrpm = page_address(nested_msrpm_pages);
3d6368ef 720
a2fa3e9f
GH		 721 svm->vmcb = page_address(page);
722 clear_page(svm->vmcb);
723 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
724 svm->asid_generation = 0;
e6101a96 725 init_vmcb(svm);
a2fa3e9f 726
fb3f0f51
RR		 727 fx_init(&svm->vcpu);
728 svm->vcpu.fpu_active = 1;
ad312c7c 729 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 730 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 731 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 732
fb3f0f51 733 return &svm->vcpu;
36241b8c 734
fb3f0f51
RR		 735uninit:
736 kvm_vcpu_uninit(&svm->vcpu);
737free_svm:
a4770347 738 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 739out:
740 return ERR_PTR(err);
6aa8b732
AK		 741}
742
743static void svm_free_vcpu(struct kvm_vcpu *vcpu)
744{
a2fa3e9f
GH		 745 struct vcpu_svm *svm = to_svm(vcpu);
746
fb3f0f51 747 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 748 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 749 __free_page(virt_to_page(svm->nested.hsave));
750 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 751 kvm_vcpu_uninit(vcpu);
a4770347 752 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 753}
754
15ad7146 755static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 756{
a2fa3e9f 757 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 758 int i;
0cc5064d 759
0cc5064d
AK		 760 if (unlikely(cpu != vcpu->cpu)) {
761 u64 tsc_this, delta;
762
763 /*
764 * Make sure that the guest sees a monotonically
765 * increasing TSC.
766 */
767 rdtscll(tsc_this);
ad312c7c 768 delta = vcpu->arch.host_tsc - tsc_this;
a2fa3e9f 769 svm->vmcb->control.tsc_offset += delta;
0cc5064d 770 vcpu->cpu = cpu;
2f599714 771 kvm_migrate_timers(vcpu);
4b656b12 772 svm->asid_generation = 0;
0cc5064d 773 }
94dfbdb3
AL		 774
775 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 776 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 777}
778
779static void svm_vcpu_put(struct kvm_vcpu *vcpu)
780{
a2fa3e9f 781 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 782 int i;
783
e1beb1d3 784 ++vcpu->stat.host_state_reload;
94dfbdb3 785 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 786 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 787
ad312c7c 788 rdtscll(vcpu->arch.host_tsc);
6aa8b732
AK		 789}
790
6aa8b732
AK		 791static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
792{
a2fa3e9f 793 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 794}
795
796static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
797{
a2fa3e9f 798 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 799}
800
6de4f3ad
AK		 801static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
802{
803 switch (reg) {
804 case VCPU_EXREG_PDPTR:
805 BUG_ON(!npt_enabled);
806 load_pdptrs(vcpu, vcpu->arch.cr3);
807 break;
808 default:
809 BUG();
810 }
811}
812
f0b85051
AG		 813static void svm_set_vintr(struct vcpu_svm *svm)
814{
815 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
816}
817
818static void svm_clear_vintr(struct vcpu_svm *svm)
819{
820 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
821}
822
6aa8b732
AK		 823static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
824{
a2fa3e9f 825 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 826
827 switch (seg) {
828 case VCPU_SREG_CS: return &save->cs;
829 case VCPU_SREG_DS: return &save->ds;
830 case VCPU_SREG_ES: return &save->es;
831 case VCPU_SREG_FS: return &save->fs;
832 case VCPU_SREG_GS: return &save->gs;
833 case VCPU_SREG_SS: return &save->ss;
834 case VCPU_SREG_TR: return &save->tr;
835 case VCPU_SREG_LDTR: return &save->ldtr;
836 }
837 BUG();
8b6d44c7 838 return NULL;
6aa8b732
AK		 839}
840
841static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
842{
843 struct vmcb_seg *s = svm_seg(vcpu, seg);
844
845 return s->base;
846}
847
848static void svm_get_segment(struct kvm_vcpu *vcpu,
849 struct kvm_segment *var, int seg)
850{
851 struct vmcb_seg *s = svm_seg(vcpu, seg);
852
853 var->base = s->base;
854 var->limit = s->limit;
855 var->selector = s->selector;
856 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
857 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
858 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
859 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
860 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
861 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
862 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
863 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 864
19bca6ab
AP		 865 /* AMD's VMCB does not have an explicit unusable field, so emulate it
866 * for cross vendor migration purposes by "not present"
867 */
868 var->unusable = !var->present || (var->type == 0);
869
1fbdc7a5
AP		 870 switch (seg) {
871 case VCPU_SREG_CS:
872 /*
873 * SVM always stores 0 for the 'G' bit in the CS selector in
874 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
875 * Intel's VMENTRY has a check on the 'G' bit.
876 */
25022acc 877 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 878 break;
879 case VCPU_SREG_TR:
880 /*
881 * Work around a bug where the busy flag in the tr selector
882 * isn't exposed
883 */
c0d09828 884 var->type |= 0x2;
1fbdc7a5
AP		 885 break;
886 case VCPU_SREG_DS:
887 case VCPU_SREG_ES:
888 case VCPU_SREG_FS:
889 case VCPU_SREG_GS:
890 /*
891 * The accessed bit must always be set in the segment
892 * descriptor cache, although it can be cleared in the
893 * descriptor, the cached bit always remains at 1. Since
894 * Intel has a check on this, set it here to support
895 * cross-vendor migration.
896 */
897 if (!var->unusable)
898 var->type |= 0x1;
899 break;
b586eb02
AP		 900 case VCPU_SREG_SS:
901 /* On AMD CPUs sometimes the DB bit in the segment
902 * descriptor is left as 1, although the whole segment has
903 * been made unusable. Clear it here to pass an Intel VMX
904 * entry check when cross vendor migrating.
905 */
906 if (var->unusable)
907 var->db = 0;
908 break;
1fbdc7a5 909 }
6aa8b732
AK		 910}
911
2e4d2653
IE		 912static int svm_get_cpl(struct kvm_vcpu *vcpu)
913{
914 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
915
916 return save->cpl;
917}
918
6aa8b732
AK		 919static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
920{
a2fa3e9f
GH		 921 struct vcpu_svm *svm = to_svm(vcpu);
922
923 dt->limit = svm->vmcb->save.idtr.limit;
924 dt->base = svm->vmcb->save.idtr.base;
6aa8b732
AK		 925}
926
927static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
928{
a2fa3e9f
GH		 929 struct vcpu_svm *svm = to_svm(vcpu);
930
931 svm->vmcb->save.idtr.limit = dt->limit;
932 svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 933}
934
935static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
936{
a2fa3e9f
GH		 937 struct vcpu_svm *svm = to_svm(vcpu);
938
939 dt->limit = svm->vmcb->save.gdtr.limit;
940 dt->base = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 941}
942
943static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
944{
a2fa3e9f
GH		 945 struct vcpu_svm *svm = to_svm(vcpu);
946
947 svm->vmcb->save.gdtr.limit = dt->limit;
948 svm->vmcb->save.gdtr.base = dt->base ;
6aa8b732
AK		 949}
950
25c4c276 951static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 952{
953}
954
6aa8b732
AK		 955static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
956{
a2fa3e9f
GH		 957 struct vcpu_svm *svm = to_svm(vcpu);
958
05b3e0c2 959#ifdef CONFIG_X86_64
ad312c7c 960 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 961 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
ad312c7c 962 vcpu->arch.shadow_efer |= EFER_LMA;
2b5203ee 963 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 964 }
965
d77c26fc 966 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
ad312c7c 967 vcpu->arch.shadow_efer &= ~EFER_LMA;
2b5203ee 968 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 969 }
970 }
971#endif
709ddebf
JR		 972 if (npt_enabled)
973 goto set;
974
ad312c7c 975 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
a2fa3e9f 976 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
7807fa6c
AL		 977 vcpu->fpu_active = 1;
978 }
979
ad312c7c 980 vcpu->arch.cr0 = cr0;
707d92fa 981 cr0 |= X86_CR0_PG | X86_CR0_WP;
6b390b63
JR		 982 if (!vcpu->fpu_active) {
983 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
334df50a 984 cr0 |= X86_CR0_TS;
6b390b63 985 }
709ddebf
JR		 986set:
987 /*
988 * re-enable caching here because the QEMU bios
989 * does not do it - this results in some delay at
990 * reboot
991 */
992 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 993 svm->vmcb->save.cr0 = cr0;
6aa8b732
AK		 994}
995
996static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
997{
6394b649 998 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 999 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1000
1001 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1002 force_new_asid(vcpu);
6394b649 1003
ec077263
JR		 1004 vcpu->arch.cr4 = cr4;
1005 if (!npt_enabled)
1006 cr4 |= X86_CR4_PAE;
6394b649 1007 cr4 |= host_cr4_mce;
ec077263 1008 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1009}
1010
1011static void svm_set_segment(struct kvm_vcpu *vcpu,
1012 struct kvm_segment *var, int seg)
1013{
a2fa3e9f 1014 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1015 struct vmcb_seg *s = svm_seg(vcpu, seg);
1016
1017 s->base = var->base;
1018 s->limit = var->limit;
1019 s->selector = var->selector;
1020 if (var->unusable)
1021 s->attrib = 0;
1022 else {
1023 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1024 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1025 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1026 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1027 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1028 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1029 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1030 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1031 }
1032 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1033 svm->vmcb->save.cpl
1034 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1035 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1036
1037}
1038
44c11430 1039static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1040{
d0bfb940
JK		 1041 struct vcpu_svm *svm = to_svm(vcpu);
1042
d0bfb940
JK		 1043 svm->vmcb->control.intercept_exceptions &=
1044 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430
GN		 1045
1046 if (vcpu->arch.singlestep)
1047 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1048
d0bfb940
JK		 1049 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1050 if (vcpu->guest_debug &
1051 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1052 svm->vmcb->control.intercept_exceptions |=
1053 1 << DB_VECTOR;
1054 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1055 svm->vmcb->control.intercept_exceptions |=
1056 1 << BP_VECTOR;
1057 } else
1058 vcpu->guest_debug = 0;
44c11430
GN		 1059}
1060
1061static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1062{
1063 int old_debug = vcpu->guest_debug;
1064 struct vcpu_svm *svm = to_svm(vcpu);
1065
1066 vcpu->guest_debug = dbg->control;
1067
1068 update_db_intercept(vcpu);
d0bfb940 1069
ae675ef0
JK		 1070 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1071 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1072 else
1073 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1074
d0bfb940
JK		 1075 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1076 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1077 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1078 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1079
1080 return 0;
6aa8b732
AK		 1081}
1082
1083static void load_host_msrs(struct kvm_vcpu *vcpu)
1084{
94dfbdb3 1085#ifdef CONFIG_X86_64
a2fa3e9f 1086 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1087#endif
6aa8b732
AK		 1088}
1089
1090static void save_host_msrs(struct kvm_vcpu *vcpu)
1091{
94dfbdb3 1092#ifdef CONFIG_X86_64
a2fa3e9f 1093 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1094#endif
6aa8b732
AK		 1095}
1096
e756fc62 1097static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
6aa8b732
AK		 1098{
1099 if (svm_data->next_asid > svm_data->max_asid) {
1100 ++svm_data->asid_generation;
1101 svm_data->next_asid = 1;
a2fa3e9f 1102 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1103 }
1104
a2fa3e9f
GH		 1105 svm->asid_generation = svm_data->asid_generation;
1106 svm->vmcb->control.asid = svm_data->next_asid++;
6aa8b732
AK		 1107}
1108
6aa8b732
AK		 1109static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1110{
42dbaa5a
JK		 1111 struct vcpu_svm *svm = to_svm(vcpu);
1112 unsigned long val;
1113
1114 switch (dr) {
1115 case 0 ... 3:
1116 val = vcpu->arch.db[dr];
1117 break;
1118 case 6:
1119 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1120 val = vcpu->arch.dr6;
1121 else
1122 val = svm->vmcb->save.dr6;
1123 break;
1124 case 7:
1125 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1126 val = vcpu->arch.dr7;
1127 else
1128 val = svm->vmcb->save.dr7;
1129 break;
1130 default:
1131 val = 0;
1132 }
1133
af9ca2d7 1134 return val;
6aa8b732
AK		 1135}
1136
1137static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1138 int *exception)
1139{
a2fa3e9f
GH		 1140 struct vcpu_svm *svm = to_svm(vcpu);
1141
42dbaa5a 1142 *exception = 0;
6aa8b732
AK		 1143
1144 switch (dr) {
1145 case 0 ... 3:
42dbaa5a
JK		 1146 vcpu->arch.db[dr] = value;
1147 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1148 vcpu->arch.eff_db[dr] = value;
6aa8b732
AK		 1149 return;
1150 case 4 ... 5:
42dbaa5a 1151 if (vcpu->arch.cr4 & X86_CR4_DE)
6aa8b732 1152 *exception = UD_VECTOR;
42dbaa5a
JK		 1153 return;
1154 case 6:
1155 if (value & 0xffffffff00000000ULL) {
1156 *exception = GP_VECTOR;
6aa8b732
AK		 1157 return;
1158 }
42dbaa5a
JK		 1159 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1160 return;
1161 case 7:
1162 if (value & 0xffffffff00000000ULL) {
6aa8b732
AK		 1163 *exception = GP_VECTOR;
1164 return;
1165 }
42dbaa5a
JK		 1166 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1167 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1168 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1169 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1170 }
6aa8b732 1171 return;
6aa8b732 1172 default:
42dbaa5a 1173 /* FIXME: Possible case? */
6aa8b732 1174 printk(KERN_DEBUG "%s: unexpected dr %u\n",
b8688d51 1175 __func__, dr);
6aa8b732
AK		 1176 *exception = UD_VECTOR;
1177 return;
1178 }
1179}
1180
e756fc62 1181static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1182{
6aa8b732
AK		 1183 u64 fault_address;
1184 u32 error_code;
6aa8b732 1185
a2fa3e9f
GH		 1186 fault_address = svm->vmcb->control.exit_info_2;
1187 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1188
229456fc 1189 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1190 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1191 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1192 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1193}
1194
d0bfb940
JK		 1195static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1196{
1197 if (!(svm->vcpu.guest_debug &
44c11430
GN		 1198 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1199 !svm->vcpu.arch.singlestep) {
d0bfb940
JK		 1200 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1201 return 1;
1202 }
44c11430
GN		 1203
1204 if (svm->vcpu.arch.singlestep) {
1205 svm->vcpu.arch.singlestep = false;
1206 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1207 svm->vmcb->save.rflags &=
1208 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1209 update_db_intercept(&svm->vcpu);
1210 }
1211
1212 if (svm->vcpu.guest_debug &
1213 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1214 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1215 kvm_run->debug.arch.pc =
1216 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1217 kvm_run->debug.arch.exception = DB_VECTOR;
1218 return 0;
1219 }
1220
1221 return 1;
d0bfb940
JK		 1222}
1223
1224static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1225{
1226 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1227 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1228 kvm_run->debug.arch.exception = BP_VECTOR;
1229 return 0;
1230}
1231
7aa81cc0
AL		 1232static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1233{
1234 int er;
1235
571008da 1236 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1237 if (er != EMULATE_DONE)
7ee5d940 1238 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1239 return 1;
1240}
1241
e756fc62 1242static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
7807fa6c 1243{
a2fa3e9f 1244 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
ad312c7c 1245 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
a2fa3e9f 1246 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
e756fc62 1247 svm->vcpu.fpu_active = 1;
a2fa3e9f
GH		 1248
1249 return 1;
7807fa6c
AL		 1250}
1251
53371b50
JR		 1252static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1253{
1254 /*
1255 * On an #MC intercept the MCE handler is not called automatically in
1256 * the host. So do it by hand here.
1257 */
1258 asm volatile (
1259 "int $0x12\n");
1260 /* not sure if we ever come back to this point */
1261
1262 return 1;
1263}
1264
e756fc62 1265static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
46fe4ddd
JR		 1266{
1267 /*
1268 * VMCB is undefined after a SHUTDOWN intercept
1269 * so reinitialize it.
1270 */
a2fa3e9f 1271 clear_page(svm->vmcb);
e6101a96 1272 init_vmcb(svm);
46fe4ddd
JR		 1273
1274 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1275 return 0;
1276}
1277
e756fc62 1278static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1279{
d77c26fc 1280 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1281 int size, in, string;
039576c0 1282 unsigned port;
6aa8b732 1283
e756fc62 1284 ++svm->vcpu.stat.io_exits;
6aa8b732 1285
a2fa3e9f 1286 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1287
e70669ab
LV		 1288 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1289
1290 if (string) {
3427318f
LV		 1291 if (emulate_instruction(&svm->vcpu,
1292 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1293 return 0;
1294 return 1;
1295 }
1296
039576c0
AK		 1297 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1298 port = io_info >> 16;
1299 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1300
e93f36bc 1301 skip_emulated_instruction(&svm->vcpu);
3090dd73 1302 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
6aa8b732
AK		 1303}
1304
c47f098d
JR		 1305static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1306{
1307 return 1;
1308}
1309
a0698055
JR		 1310static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1311{
1312 ++svm->vcpu.stat.irq_exits;
1313 return 1;
1314}
1315
e756fc62 1316static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732
AK		 1317{
1318 return 1;
1319}
1320
e756fc62 1321static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1322{
5fdbf976 1323 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1324 skip_emulated_instruction(&svm->vcpu);
1325 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1326}
1327
e756fc62 1328static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
02e235bc 1329{
5fdbf976 1330 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1331 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1332 kvm_emulate_hypercall(&svm->vcpu);
1333 return 1;
02e235bc
AK		 1334}
1335
c0725420
AG		 1336static int nested_svm_check_permissions(struct vcpu_svm *svm)
1337{
1338 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1339 || !is_paging(&svm->vcpu)) {
1340 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1341 return 1;
1342 }
1343
1344 if (svm->vmcb->save.cpl) {
1345 kvm_inject_gp(&svm->vcpu, 0);
1346 return 1;
1347 }
1348
1349 return 0;
1350}
1351
cf74a78b
AG		 1352static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1353 bool has_error_code, u32 error_code)
1354{
0295ad7d
JR		 1355 if (!is_nested(svm))
1356 return 0;
cf74a78b 1357
0295ad7d
JR		 1358 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1359 svm->vmcb->control.exit_code_hi = 0;
1360 svm->vmcb->control.exit_info_1 = error_code;
1361 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1362
410e4d57 1363 return nested_svm_exit_handled(svm);
cf74a78b
AG		 1364}
1365
1366static inline int nested_svm_intr(struct vcpu_svm *svm)
1367{
26666957
JR		 1368 if (!is_nested(svm))
1369 return 0;
cf74a78b 1370
26666957
JR		 1371 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1372 return 0;
cf74a78b 1373
26666957
JR		 1374 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1375 return 0;
cf74a78b 1376
26666957
JR		 1377 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1378
1379 if (nested_svm_exit_handled(svm)) {
1380 nsvm_printk("VMexit -> INTR\n");
1381 return 1;
cf74a78b
AG		 1382 }
1383
1384 return 0;
1385}
1386
34f80cfa
JR		 1387static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1388{
1389 struct page *page;
1390
1391 down_read(&current->mm->mmap_sem);
1392 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1393 up_read(&current->mm->mmap_sem);
1394
1395 if (is_error_page(page))
1396 goto error;
1397
1398 return kmap_atomic(page, idx);
1399
1400error:
1401 kvm_release_page_clean(page);
1402 kvm_inject_gp(&svm->vcpu, 0);
1403
1404 return NULL;
1405}
1406
1407static void nested_svm_unmap(void *addr, enum km_type idx)
1408{
1409 struct page *page;
1410
1411 if (!addr)
1412 return;
1413
1414 page = kmap_atomic_to_page(addr);
1415
1416 kunmap_atomic(addr, idx);
1417 kvm_release_page_dirty(page);
1418}
1419
3d62d9aa 1420static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1421{
4c2161ae 1422 u32 param = svm->vmcb->control.exit_info_1 & 1;
3d62d9aa
JR		 1423 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1424 bool ret = false;
1425 u32 t0, t1;
1426 u8 *msrpm;
4c2161ae 1427
3d62d9aa
JR		 1428 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1429 return false;
1430
1431 msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1432
1433 if (!msrpm)
1434 goto out;
4c2161ae
JR		 1435
1436 switch (msr) {
1437 case 0 ... 0x1fff:
1438 t0 = (msr * 2) % 8;
1439 t1 = msr / 8;
1440 break;
1441 case 0xc0000000 ... 0xc0001fff:
1442 t0 = (8192 + msr - 0xc0000000) * 2;
1443 t1 = (t0 / 8);
1444 t0 %= 8;
1445 break;
1446 case 0xc0010000 ... 0xc0011fff:
1447 t0 = (16384 + msr - 0xc0010000) * 2;
1448 t1 = (t0 / 8);
1449 t0 %= 8;
1450 break;
1451 default:
3d62d9aa
JR		 1452 ret = true;
1453 goto out;
4c2161ae 1454 }
4c2161ae 1455
3d62d9aa
JR		 1456 ret = msrpm[t1] & ((1 << param) << t0);
1457
1458out:
1459 nested_svm_unmap(msrpm, KM_USER0);
1460
1461 return ret;
4c2161ae
JR		 1462}
1463
410e4d57 1464static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1465{
cf74a78b 1466 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1467
410e4d57
JR		 1468 switch (exit_code) {
1469 case SVM_EXIT_INTR:
1470 case SVM_EXIT_NMI:
1471 return NESTED_EXIT_HOST;
cf74a78b 1472 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1473 case SVM_EXIT_NPF:
1474 if (npt_enabled)
1475 return NESTED_EXIT_HOST;
1476 break;
1477 /* When we're shadowing, trap PFs */
1478 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1479 if (!npt_enabled)
1480 return NESTED_EXIT_HOST;
1481 break;
1482 default:
1483 break;
cf74a78b
AG		 1484 }
1485
410e4d57
JR		 1486 return NESTED_EXIT_CONTINUE;
1487}
1488
1489/*
1490 * If this function returns true, this #vmexit was already handled
1491 */
1492static int nested_svm_exit_handled(struct vcpu_svm *svm)
1493{
1494 u32 exit_code = svm->vmcb->control.exit_code;
1495 int vmexit = NESTED_EXIT_HOST;
1496
cf74a78b 1497 switch (exit_code) {
9c4e40b9 1498 case SVM_EXIT_MSR:
3d62d9aa 1499 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1500 break;
cf74a78b
AG		 1501 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1502 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1503 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1504 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1505 break;
1506 }
1507 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1508 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1509 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1510 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1511 break;
1512 }
1513 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1514 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1515 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1516 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1517 break;
1518 }
1519 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1520 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1521 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1522 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1523 break;
1524 }
1525 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1526 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1527 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1528 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1529 break;
1530 }
1531 default: {
1532 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1533 nsvm_printk("exit code: 0x%x\n", exit_code);
aad42c64 1534 if (svm->nested.intercept & exit_bits)
410e4d57 1535 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1536 }
1537 }
1538
410e4d57 1539 if (vmexit == NESTED_EXIT_DONE) {
9c4e40b9
JR		 1540 nsvm_printk("#VMEXIT reason=%04x\n", exit_code);
1541 nested_svm_vmexit(svm);
1542 }
1543
1544 return vmexit;
cf74a78b
AG		 1545}
1546
0460a979
JR		 1547static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1548{
1549 struct vmcb_control_area *dst = &dst_vmcb->control;
1550 struct vmcb_control_area *from = &from_vmcb->control;
1551
1552 dst->intercept_cr_read = from->intercept_cr_read;
1553 dst->intercept_cr_write = from->intercept_cr_write;
1554 dst->intercept_dr_read = from->intercept_dr_read;
1555 dst->intercept_dr_write = from->intercept_dr_write;
1556 dst->intercept_exceptions = from->intercept_exceptions;
1557 dst->intercept = from->intercept;
1558 dst->iopm_base_pa = from->iopm_base_pa;
1559 dst->msrpm_base_pa = from->msrpm_base_pa;
1560 dst->tsc_offset = from->tsc_offset;
1561 dst->asid = from->asid;
1562 dst->tlb_ctl = from->tlb_ctl;
1563 dst->int_ctl = from->int_ctl;
1564 dst->int_vector = from->int_vector;
1565 dst->int_state = from->int_state;
1566 dst->exit_code = from->exit_code;
1567 dst->exit_code_hi = from->exit_code_hi;
1568 dst->exit_info_1 = from->exit_info_1;
1569 dst->exit_info_2 = from->exit_info_2;
1570 dst->exit_int_info = from->exit_int_info;
1571 dst->exit_int_info_err = from->exit_int_info_err;
1572 dst->nested_ctl = from->nested_ctl;
1573 dst->event_inj = from->event_inj;
1574 dst->event_inj_err = from->event_inj_err;
1575 dst->nested_cr3 = from->nested_cr3;
1576 dst->lbr_ctl = from->lbr_ctl;
1577}
1578
34f80cfa 1579static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1580{
34f80cfa 1581 struct vmcb *nested_vmcb;
e6aa9abd 1582 struct vmcb *hsave = svm->nested.hsave;
33740e40 1583 struct vmcb *vmcb = svm->vmcb;
cf74a78b 1584
34f80cfa
JR		 1585 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1586 if (!nested_vmcb)
1587 return 1;
1588
cf74a78b 1589 /* Give the current vmcb to the guest */
33740e40
JR		 1590 disable_gif(svm);
1591
1592 nested_vmcb->save.es = vmcb->save.es;
1593 nested_vmcb->save.cs = vmcb->save.cs;
1594 nested_vmcb->save.ss = vmcb->save.ss;
1595 nested_vmcb->save.ds = vmcb->save.ds;
1596 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1597 nested_vmcb->save.idtr = vmcb->save.idtr;
1598 if (npt_enabled)
1599 nested_vmcb->save.cr3 = vmcb->save.cr3;
1600 nested_vmcb->save.cr2 = vmcb->save.cr2;
1601 nested_vmcb->save.rflags = vmcb->save.rflags;
1602 nested_vmcb->save.rip = vmcb->save.rip;
1603 nested_vmcb->save.rsp = vmcb->save.rsp;
1604 nested_vmcb->save.rax = vmcb->save.rax;
1605 nested_vmcb->save.dr7 = vmcb->save.dr7;
1606 nested_vmcb->save.dr6 = vmcb->save.dr6;
1607 nested_vmcb->save.cpl = vmcb->save.cpl;
1608
1609 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1610 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1611 nested_vmcb->control.int_state = vmcb->control.int_state;
1612 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1613 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1614 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1615 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1616 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1617 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1618 nested_vmcb->control.tlb_ctl = 0;
1619 nested_vmcb->control.event_inj = 0;
1620 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1621
1622 /* We always set V_INTR_MASKING and remember the old value in hflags */
1623 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1624 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1625
cf74a78b 1626 /* Restore the original control entries */
0460a979 1627 copy_vmcb_control_area(vmcb, hsave);
cf74a78b
AG		 1628
1629 /* Kill any pending exceptions */
1630 if (svm->vcpu.arch.exception.pending == true)
1631 nsvm_printk("WARNING: Pending Exception\n");
33740e40 1632
219b65dc
AG		 1633 kvm_clear_exception_queue(&svm->vcpu);
1634 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1635
1636 /* Restore selected save entries */
1637 svm->vmcb->save.es = hsave->save.es;
1638 svm->vmcb->save.cs = hsave->save.cs;
1639 svm->vmcb->save.ss = hsave->save.ss;
1640 svm->vmcb->save.ds = hsave->save.ds;
1641 svm->vmcb->save.gdtr = hsave->save.gdtr;
1642 svm->vmcb->save.idtr = hsave->save.idtr;
1643 svm->vmcb->save.rflags = hsave->save.rflags;
1644 svm_set_efer(&svm->vcpu, hsave->save.efer);
1645 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1646 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1647 if (npt_enabled) {
1648 svm->vmcb->save.cr3 = hsave->save.cr3;
1649 svm->vcpu.arch.cr3 = hsave->save.cr3;
1650 } else {
1651 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1652 }
1653 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1654 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1655 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1656 svm->vmcb->save.dr7 = 0;
1657 svm->vmcb->save.cpl = 0;
1658 svm->vmcb->control.exit_int_info = 0;
1659
cf74a78b 1660 /* Exit nested SVM mode */
e6aa9abd 1661 svm->nested.vmcb = 0;
cf74a78b 1662
34f80cfa 1663 nested_svm_unmap(nested_vmcb, KM_USER0);
cf74a78b
AG		 1664
1665 kvm_mmu_reset_context(&svm->vcpu);
1666 kvm_mmu_load(&svm->vcpu);
1667
1668 return 0;
1669}
3d6368ef 1670
9738b2c9 1671static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1672{
9738b2c9 1673 u32 *nested_msrpm;
3d6368ef 1674 int i;
9738b2c9
JR		 1675
1676 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1677 if (!nested_msrpm)
1678 return false;
1679
3d6368ef 1680 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
e6aa9abd 1681 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
9738b2c9 1682
e6aa9abd 1683 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
3d6368ef 1684
9738b2c9
JR		 1685 nested_svm_unmap(nested_msrpm, KM_USER0);
1686
1687 return true;
3d6368ef
AG		 1688}
1689
9738b2c9 1690static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 1691{
9738b2c9 1692 struct vmcb *nested_vmcb;
e6aa9abd 1693 struct vmcb *hsave = svm->nested.hsave;
defbba56 1694 struct vmcb *vmcb = svm->vmcb;
3d6368ef 1695
9738b2c9
JR		 1696 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1697 if (!nested_vmcb)
1698 return false;
1699
3d6368ef 1700 /* nested_vmcb is our indicator if nested SVM is activated */
e6aa9abd 1701 svm->nested.vmcb = svm->vmcb->save.rax;
3d6368ef
AG		 1702
1703 /* Clear internal status */
219b65dc
AG		 1704 kvm_clear_exception_queue(&svm->vcpu);
1705 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef
AG		 1706
1707 /* Save the old vmcb, so we don't need to pick what we save, but
1708 can restore everything when a VMEXIT occurs */
defbba56
JR		 1709 hsave->save.es = vmcb->save.es;
1710 hsave->save.cs = vmcb->save.cs;
1711 hsave->save.ss = vmcb->save.ss;
1712 hsave->save.ds = vmcb->save.ds;
1713 hsave->save.gdtr = vmcb->save.gdtr;
1714 hsave->save.idtr = vmcb->save.idtr;
1715 hsave->save.efer = svm->vcpu.arch.shadow_efer;
1716 hsave->save.cr0 = svm->vcpu.arch.cr0;
1717 hsave->save.cr4 = svm->vcpu.arch.cr4;
1718 hsave->save.rflags = vmcb->save.rflags;
1719 hsave->save.rip = svm->next_rip;
1720 hsave->save.rsp = vmcb->save.rsp;
1721 hsave->save.rax = vmcb->save.rax;
1722 if (npt_enabled)
1723 hsave->save.cr3 = vmcb->save.cr3;
1724 else
1725 hsave->save.cr3 = svm->vcpu.arch.cr3;
1726
0460a979 1727 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 1728
1729 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1730 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1731 else
1732 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1733
1734 /* Load the nested guest state */
1735 svm->vmcb->save.es = nested_vmcb->save.es;
1736 svm->vmcb->save.cs = nested_vmcb->save.cs;
1737 svm->vmcb->save.ss = nested_vmcb->save.ss;
1738 svm->vmcb->save.ds = nested_vmcb->save.ds;
1739 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1740 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1741 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1742 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1743 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1744 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1745 if (npt_enabled) {
1746 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1747 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1748 } else {
1749 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1750 kvm_mmu_reset_context(&svm->vcpu);
1751 }
defbba56 1752 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 1753 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1754 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1755 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1756 /* In case we don't even reach vcpu_run, the fields are not updated */
1757 svm->vmcb->save.rax = nested_vmcb->save.rax;
1758 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1759 svm->vmcb->save.rip = nested_vmcb->save.rip;
1760 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1761 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1762 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1763
1764 /* We don't want a nested guest to be more powerful than the guest,
1765 so all intercepts are ORed */
1766 svm->vmcb->control.intercept_cr_read |=
1767 nested_vmcb->control.intercept_cr_read;
1768 svm->vmcb->control.intercept_cr_write |=
1769 nested_vmcb->control.intercept_cr_write;
1770 svm->vmcb->control.intercept_dr_read |=
1771 nested_vmcb->control.intercept_dr_read;
1772 svm->vmcb->control.intercept_dr_write |=
1773 nested_vmcb->control.intercept_dr_write;
1774 svm->vmcb->control.intercept_exceptions |=
1775 nested_vmcb->control.intercept_exceptions;
1776
1777 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1778
e6aa9abd 1779 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
3d6368ef 1780
aad42c64
JR		 1781 /* cache intercepts */
1782 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1783 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1784 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1785 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1786 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1787 svm->nested.intercept = nested_vmcb->control.intercept;
1788
3d6368ef
AG		 1789 force_new_asid(&svm->vcpu);
1790 svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1791 svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1792 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1793 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1794 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1795 nested_vmcb->control.int_ctl);
1796 }
1797 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1798 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1799 else
1800 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1801
1802 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1803 nested_vmcb->control.exit_int_info,
1804 nested_vmcb->control.int_state);
1805
1806 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1807 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1808 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1809 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1810 nsvm_printk("Injecting Event: 0x%x\n",
1811 nested_vmcb->control.event_inj);
1812 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1813 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1814
9738b2c9
JR		 1815 nested_svm_unmap(nested_vmcb, KM_USER0);
1816
2af9194d 1817 enable_gif(svm);
3d6368ef 1818
9738b2c9 1819 return true;
3d6368ef
AG		 1820}
1821
9966bf68 1822static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 1823{
1824 to_vmcb->save.fs = from_vmcb->save.fs;
1825 to_vmcb->save.gs = from_vmcb->save.gs;
1826 to_vmcb->save.tr = from_vmcb->save.tr;
1827 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1828 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1829 to_vmcb->save.star = from_vmcb->save.star;
1830 to_vmcb->save.lstar = from_vmcb->save.lstar;
1831 to_vmcb->save.cstar = from_vmcb->save.cstar;
1832 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1833 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1834 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1835 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 1836}
1837
1838static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1839{
9966bf68
JR		 1840 struct vmcb *nested_vmcb;
1841
5542675b
AG		 1842 if (nested_svm_check_permissions(svm))
1843 return 1;
1844
1845 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1846 skip_emulated_instruction(&svm->vcpu);
1847
9966bf68
JR		 1848 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1849 if (!nested_vmcb)
1850 return 1;
1851
1852 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1853 nested_svm_unmap(nested_vmcb, KM_USER0);
5542675b
AG		 1854
1855 return 1;
1856}
1857
1858static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1859{
9966bf68
JR		 1860 struct vmcb *nested_vmcb;
1861
5542675b
AG		 1862 if (nested_svm_check_permissions(svm))
1863 return 1;
1864
1865 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1866 skip_emulated_instruction(&svm->vcpu);
1867
9966bf68
JR		 1868 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1869 if (!nested_vmcb)
1870 return 1;
1871
1872 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1873 nested_svm_unmap(nested_vmcb, KM_USER0);
5542675b
AG		 1874
1875 return 1;
1876}
1877
3d6368ef
AG		 1878static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1879{
1880 nsvm_printk("VMrun\n");
1f8da478 1881
3d6368ef
AG		 1882 if (nested_svm_check_permissions(svm))
1883 return 1;
1884
1885 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1886 skip_emulated_instruction(&svm->vcpu);
1887
9738b2c9 1888 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 1889 return 1;
1890
9738b2c9 1891 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 1892 goto failed;
1893
1894 return 1;
1895
1896failed:
1897
1898 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
1899 svm->vmcb->control.exit_code_hi = 0;
1900 svm->vmcb->control.exit_info_1 = 0;
1901 svm->vmcb->control.exit_info_2 = 0;
1902
1903 nested_svm_vmexit(svm);
3d6368ef
AG		 1904
1905 return 1;
1906}
1907
1371d904
AG		 1908static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1909{
1910 if (nested_svm_check_permissions(svm))
1911 return 1;
1912
1913 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1914 skip_emulated_instruction(&svm->vcpu);
1915
2af9194d 1916 enable_gif(svm);
1371d904
AG		 1917
1918 return 1;
1919}
1920
1921static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1922{
1923 if (nested_svm_check_permissions(svm))
1924 return 1;
1925
1926 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1927 skip_emulated_instruction(&svm->vcpu);
1928
2af9194d 1929 disable_gif(svm);
1371d904
AG		 1930
1931 /* After a CLGI no interrupts should come */
1932 svm_clear_vintr(svm);
1933 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1934
1935 return 1;
1936}
1937
ff092385
AG		 1938static int invlpga_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1939{
1940 struct kvm_vcpu *vcpu = &svm->vcpu;
1941 nsvm_printk("INVLPGA\n");
1942
1943 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1944 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1945
1946 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1947 skip_emulated_instruction(&svm->vcpu);
1948 return 1;
1949}
1950
e756fc62
RR		 1951static int invalid_op_interception(struct vcpu_svm *svm,
1952 struct kvm_run *kvm_run)
6aa8b732 1953{
7ee5d940 1954 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 1955 return 1;
1956}
1957
e756fc62
RR		 1958static int task_switch_interception(struct vcpu_svm *svm,
1959 struct kvm_run *kvm_run)
6aa8b732 1960{
37817f29 1961 u16 tss_selector;
64a7ec06
GN		 1962 int reason;
1963 int int_type = svm->vmcb->control.exit_int_info &
1964 SVM_EXITINTINFO_TYPE_MASK;
8317c298 1965 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 1966 uint32_t type =
1967 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1968 uint32_t idt_v =
1969 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 1970
1971 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 1972
37817f29
IE		 1973 if (svm->vmcb->control.exit_info_2 &
1974 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 1975 reason = TASK_SWITCH_IRET;
1976 else if (svm->vmcb->control.exit_info_2 &
1977 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1978 reason = TASK_SWITCH_JMP;
fe8e7f83 1979 else if (idt_v)
64a7ec06
GN		 1980 reason = TASK_SWITCH_GATE;
1981 else
1982 reason = TASK_SWITCH_CALL;
1983
fe8e7f83
GN		 1984 if (reason == TASK_SWITCH_GATE) {
1985 switch (type) {
1986 case SVM_EXITINTINFO_TYPE_NMI:
1987 svm->vcpu.arch.nmi_injected = false;
1988 break;
1989 case SVM_EXITINTINFO_TYPE_EXEPT:
1990 kvm_clear_exception_queue(&svm->vcpu);
1991 break;
1992 case SVM_EXITINTINFO_TYPE_INTR:
1993 kvm_clear_interrupt_queue(&svm->vcpu);
1994 break;
1995 default:
1996 break;
1997 }
1998 }
64a7ec06 1999
8317c298
GN		 2000 if (reason != TASK_SWITCH_GATE ||
2001 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2002 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2003 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2004 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2005
2006 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2007}
2008
e756fc62 2009static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2010{
5fdbf976 2011 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2012 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2013 return 1;
6aa8b732
AK		 2014}
2015
95ba8273
GN		 2016static int iret_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2017{
2018 ++svm->vcpu.stat.nmi_window_exits;
2019 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2020 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2021 return 1;
2022}
2023
a7052897
MT		 2024static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2025{
2026 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
2027 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2028 return 1;
2029}
2030
e756fc62
RR		 2031static int emulate_on_interception(struct vcpu_svm *svm,
2032 struct kvm_run *kvm_run)
6aa8b732 2033{
3427318f 2034 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
b8688d51 2035 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2036 return 1;
2037}
2038
1d075434
JR		 2039static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2040{
0a5fff19
GN		 2041 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2042 /* instruction emulation calls kvm_set_cr8() */
1d075434 2043 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
95ba8273
GN		 2044 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2045 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2046 return 1;
95ba8273 2047 }
0a5fff19
GN		 2048 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2049 return 1;
1d075434
JR		 2050 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2051 return 0;
2052}
2053
6aa8b732
AK		 2054static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2055{
a2fa3e9f
GH		 2056 struct vcpu_svm *svm = to_svm(vcpu);
2057
6aa8b732 2058 switch (ecx) {
af24a4e4 2059 case MSR_IA32_TSC: {
6aa8b732
AK		 2060 u64 tsc;
2061
2062 rdtscll(tsc);
a2fa3e9f 2063 *data = svm->vmcb->control.tsc_offset + tsc;
6aa8b732
AK		 2064 break;
2065 }
0e859cac 2066 case MSR_K6_STAR:
a2fa3e9f 2067 *data = svm->vmcb->save.star;
6aa8b732 2068 break;
0e859cac 2069#ifdef CONFIG_X86_64
6aa8b732 2070 case MSR_LSTAR:
a2fa3e9f 2071 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2072 break;
2073 case MSR_CSTAR:
a2fa3e9f 2074 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2075 break;
2076 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2077 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2078 break;
2079 case MSR_SYSCALL_MASK:
a2fa3e9f 2080 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2081 break;
2082#endif
2083 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2084 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2085 break;
2086 case MSR_IA32_SYSENTER_EIP:
017cb99e 2087 *data = svm->sysenter_eip;
6aa8b732
AK		 2088 break;
2089 case MSR_IA32_SYSENTER_ESP:
017cb99e 2090 *data = svm->sysenter_esp;
6aa8b732 2091 break;
a2938c80
JR		 2092 /* Nobody will change the following 5 values in the VMCB so
2093 we can safely return them on rdmsr. They will always be 0
2094 until LBRV is implemented. */
2095 case MSR_IA32_DEBUGCTLMSR:
2096 *data = svm->vmcb->save.dbgctl;
2097 break;
2098 case MSR_IA32_LASTBRANCHFROMIP:
2099 *data = svm->vmcb->save.br_from;
2100 break;
2101 case MSR_IA32_LASTBRANCHTOIP:
2102 *data = svm->vmcb->save.br_to;
2103 break;
2104 case MSR_IA32_LASTINTFROMIP:
2105 *data = svm->vmcb->save.last_excp_from;
2106 break;
2107 case MSR_IA32_LASTINTTOIP:
2108 *data = svm->vmcb->save.last_excp_to;
2109 break;
b286d5d8 2110 case MSR_VM_HSAVE_PA:
e6aa9abd 2111 *data = svm->nested.hsave_msr;
b286d5d8 2112 break;
eb6f302e
JR		 2113 case MSR_VM_CR:
2114 *data = 0;
2115 break;
c8a73f18
AG		 2116 case MSR_IA32_UCODE_REV:
2117 *data = 0x01000065;
2118 break;
6aa8b732 2119 default:
3bab1f5d 2120 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2121 }
2122 return 0;
2123}
2124
e756fc62 2125static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2126{
ad312c7c 2127 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2128 u64 data;
2129
e756fc62 2130 if (svm_get_msr(&svm->vcpu, ecx, &data))
c1a5d4f9 2131 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2132 else {
229456fc 2133 trace_kvm_msr_read(ecx, data);
af9ca2d7 2134
5fdbf976 2135 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2136 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2137 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2138 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2139 }
2140 return 1;
2141}
2142
2143static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2144{
a2fa3e9f
GH		 2145 struct vcpu_svm *svm = to_svm(vcpu);
2146
6aa8b732 2147 switch (ecx) {
af24a4e4 2148 case MSR_IA32_TSC: {
6aa8b732
AK		 2149 u64 tsc;
2150
2151 rdtscll(tsc);
a2fa3e9f 2152 svm->vmcb->control.tsc_offset = data - tsc;
6aa8b732
AK		 2153 break;
2154 }
0e859cac 2155 case MSR_K6_STAR:
a2fa3e9f 2156 svm->vmcb->save.star = data;
6aa8b732 2157 break;
49b14f24 2158#ifdef CONFIG_X86_64
6aa8b732 2159 case MSR_LSTAR:
a2fa3e9f 2160 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2161 break;
2162 case MSR_CSTAR:
a2fa3e9f 2163 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2164 break;
2165 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2166 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2167 break;
2168 case MSR_SYSCALL_MASK:
a2fa3e9f 2169 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2170 break;
2171#endif
2172 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2173 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2174 break;
2175 case MSR_IA32_SYSENTER_EIP:
017cb99e 2176 svm->sysenter_eip = data;
a2fa3e9f 2177 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2178 break;
2179 case MSR_IA32_SYSENTER_ESP:
017cb99e 2180 svm->sysenter_esp = data;
a2fa3e9f 2181 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2182 break;
a2938c80 2183 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2184 if (!svm_has(SVM_FEATURE_LBRV)) {
2185 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2186 __func__, data);
24e09cbf
JR		 2187 break;
2188 }
2189 if (data & DEBUGCTL_RESERVED_BITS)
2190 return 1;
2191
2192 svm->vmcb->save.dbgctl = data;
2193 if (data & (1ULL<<0))
2194 svm_enable_lbrv(svm);
2195 else
2196 svm_disable_lbrv(svm);
a2938c80 2197 break;
b286d5d8 2198 case MSR_VM_HSAVE_PA:
e6aa9abd 2199 svm->nested.hsave_msr = data;
62b9abaa 2200 break;
3c5d0a44
AG		 2201 case MSR_VM_CR:
2202 case MSR_VM_IGNNE:
3c5d0a44
AG		 2203 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2204 break;
6aa8b732 2205 default:
3bab1f5d 2206 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2207 }
2208 return 0;
2209}
2210
e756fc62 2211static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2212{
ad312c7c 2213 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2214 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2215 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2216
229456fc 2217 trace_kvm_msr_write(ecx, data);
af9ca2d7 2218
5fdbf976 2219 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2220 if (svm_set_msr(&svm->vcpu, ecx, data))
c1a5d4f9 2221 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2222 else
e756fc62 2223 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2224 return 1;
2225}
2226
e756fc62 2227static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2228{
e756fc62
RR		 2229 if (svm->vmcb->control.exit_info_1)
2230 return wrmsr_interception(svm, kvm_run);
6aa8b732 2231 else
e756fc62 2232 return rdmsr_interception(svm, kvm_run);
6aa8b732
AK		 2233}
2234
e756fc62 2235static int interrupt_window_interception(struct vcpu_svm *svm,
c1150d8c
DL		 2236 struct kvm_run *kvm_run)
2237{
f0b85051 2238 svm_clear_vintr(svm);
85f455f7 2239 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2240 /*
2241 * If the user space waits to inject interrupts, exit as soon as
2242 * possible
2243 */
8061823a
GN		 2244 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2245 kvm_run->request_interrupt_window &&
2246 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2247 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2248 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2249 return 0;
2250 }
2251
2252 return 1;
2253}
2254
e756fc62 2255static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
6aa8b732
AK		 2256 struct kvm_run *kvm_run) = {
2257 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2258 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2259 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2260 [SVM_EXIT_READ_CR8] = emulate_on_interception,
6aa8b732
AK		 2261 /* for now: */
2262 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2263 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2264 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2265 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2266 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2267 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2268 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2269 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2270 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2271 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2272 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2273 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2274 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2275 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2276 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2277 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2278 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2279 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2280 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2281 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2282 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2283 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2284 [SVM_EXIT_SMI] = nop_on_interception,
2285 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2286 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2287 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2288 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2289 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2290 [SVM_EXIT_INVD] = emulate_on_interception,
6aa8b732 2291 [SVM_EXIT_HLT] = halt_interception,
a7052897 2292 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2293 [SVM_EXIT_INVLPGA] = invlpga_interception,
6aa8b732
AK		 2294 [SVM_EXIT_IOIO] = io_interception,
2295 [SVM_EXIT_MSR] = msr_interception,
2296 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2297 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2298 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2299 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2300 [SVM_EXIT_VMLOAD] = vmload_interception,
2301 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2302 [SVM_EXIT_STGI] = stgi_interception,
2303 [SVM_EXIT_CLGI] = clgi_interception,
6aa8b732 2304 [SVM_EXIT_SKINIT] = invalid_op_interception,
cf5a94d1 2305 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2306 [SVM_EXIT_MONITOR] = invalid_op_interception,
2307 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2308 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2309};
2310
04d2cc77 2311static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
6aa8b732 2312{
04d2cc77 2313 struct vcpu_svm *svm = to_svm(vcpu);
a2fa3e9f 2314 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2315
229456fc 2316 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
af9ca2d7 2317
cf74a78b 2318 if (is_nested(svm)) {
410e4d57
JR		 2319 int vmexit;
2320
cf74a78b
AG		 2321 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2322 exit_code, svm->vmcb->control.exit_info_1,
2323 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
410e4d57
JR		 2324
2325 vmexit = nested_svm_exit_special(svm);
2326
2327 if (vmexit == NESTED_EXIT_CONTINUE)
2328 vmexit = nested_svm_exit_handled(svm);
2329
2330 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2331 return 1;
cf74a78b
AG		 2332 }
2333
a5c3832d
JR		 2334 svm_complete_interrupts(svm);
2335
709ddebf
JR		 2336 if (npt_enabled) {
2337 int mmu_reload = 0;
2338 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2339 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2340 mmu_reload = 1;
2341 }
2342 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2343 vcpu->arch.cr3 = svm->vmcb->save.cr3;
709ddebf
JR		 2344 if (mmu_reload) {
2345 kvm_mmu_reset_context(vcpu);
2346 kvm_mmu_load(vcpu);
2347 }
2348 }
2349
04d2cc77
AK		 2350
2351 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2352 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2353 kvm_run->fail_entry.hardware_entry_failure_reason
2354 = svm->vmcb->control.exit_code;
2355 return 0;
2356 }
2357
a2fa3e9f 2358 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2359 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2360 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2361 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2362 "exit_code 0x%x\n",
b8688d51 2363 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2364 exit_code);
2365
9d8f549d 2366 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2367 || !svm_exit_handlers[exit_code]) {
6aa8b732 2368 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2369 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2370 return 0;
2371 }
2372
e756fc62 2373 return svm_exit_handlers[exit_code](svm, kvm_run);
6aa8b732
AK		 2374}
2375
2376static void reload_tss(struct kvm_vcpu *vcpu)
2377{
2378 int cpu = raw_smp_processor_id();
2379
2380 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
d77c26fc 2381 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2382 load_TR_desc();
2383}
2384
e756fc62 2385static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2386{
2387 int cpu = raw_smp_processor_id();
2388
2389 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2390
a2fa3e9f 2391 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12
MT		 2392 /* FIXME: handle wraparound of asid_generation */
2393 if (svm->asid_generation != svm_data->asid_generation)
e756fc62 2394 new_asid(svm, svm_data);
6aa8b732
AK		 2395}
2396
95ba8273
GN		 2397static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2398{
2399 struct vcpu_svm *svm = to_svm(vcpu);
2400
2401 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2402 vcpu->arch.hflags |= HF_NMI_MASK;
2403 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2404 ++vcpu->stat.nmi_injections;
2405}
6aa8b732 2406
85f455f7 2407static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2408{
2409 struct vmcb_control_area *control;
2410
229456fc 2411 trace_kvm_inj_virq(irq);
af9ca2d7 2412
fa89a817 2413 ++svm->vcpu.stat.irq_injections;
e756fc62 2414 control = &svm->vmcb->control;
85f455f7 2415 control->int_vector = irq;
6aa8b732
AK		 2416 control->int_ctl &= ~V_INTR_PRIO_MASK;
2417 control->int_ctl |= V_IRQ_MASK |
2418 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2419}
2420
66fd3f7f 2421static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2422{
2423 struct vcpu_svm *svm = to_svm(vcpu);
2424
2af9194d 2425 BUG_ON(!(gif_set(svm)));
cf74a78b 2426
219b65dc
AG		 2427 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2428 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2429}
2430
95ba8273 2431static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2432{
2433 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2434
95ba8273 2435 if (irr == -1)
aaacfc9a
JR		 2436 return;
2437
95ba8273
GN		 2438 if (tpr >= irr)
2439 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2440}
aaacfc9a 2441
95ba8273
GN		 2442static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2443{
2444 struct vcpu_svm *svm = to_svm(vcpu);
2445 struct vmcb *vmcb = svm->vmcb;
2446 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2447 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2448}
2449
78646121
GN		 2450static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2451{
2452 struct vcpu_svm *svm = to_svm(vcpu);
2453 struct vmcb *vmcb = svm->vmcb;
2454 return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2455 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2af9194d 2456 gif_set(svm) &&
108768de 2457 !(is_nested(svm) && (svm->vcpu.arch.hflags & HF_VINTR_MASK));
78646121
GN		 2458}
2459
9222be18 2460static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2461{
219b65dc
AG		 2462 struct vcpu_svm *svm = to_svm(vcpu);
2463 nsvm_printk("Trying to open IRQ window\n");
2464
2465 nested_svm_intr(svm);
2466
2467 /* In case GIF=0 we can't rely on the CPU to tell us when
2468 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2469 * The next time we get that intercept, this function will be
2470 * called again though and we'll get the vintr intercept. */
2af9194d 2471 if (gif_set(svm)) {
219b65dc
AG		 2472 svm_set_vintr(svm);
2473 svm_inject_irq(svm, 0x0);
2474 }
85f455f7
ED		 2475}
2476
95ba8273 2477static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2478{
04d2cc77 2479 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2480
44c11430
GN		 2481 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2482 == HF_NMI_MASK)
2483 return; /* IRET will cause a vm exit */
2484
2485 /* Something prevents NMI from been injected. Single step over
2486 possible problem (IRET or exception injection or interrupt
2487 shadow) */
2488 vcpu->arch.singlestep = true;
2489 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2490 update_db_intercept(vcpu);
c1150d8c
DL		 2491}
2492
cbc94022
IE		 2493static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2494{
2495 return 0;
2496}
2497
d9e368d6
AK		 2498static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2499{
2500 force_new_asid(vcpu);
2501}
2502
04d2cc77
AK		 2503static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2504{
2505}
2506
d7bf8221
JR		 2507static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2508{
2509 struct vcpu_svm *svm = to_svm(vcpu);
2510
2511 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2512 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2513 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2514 }
2515}
2516
649d6864
JR		 2517static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2518{
2519 struct vcpu_svm *svm = to_svm(vcpu);
2520 u64 cr8;
2521
649d6864
JR		 2522 cr8 = kvm_get_cr8(vcpu);
2523 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2524 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2525}
2526
9222be18
GN		 2527static void svm_complete_interrupts(struct vcpu_svm *svm)
2528{
2529 u8 vector;
2530 int type;
2531 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2532
44c11430
GN		 2533 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2534 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2535
9222be18
GN		 2536 svm->vcpu.arch.nmi_injected = false;
2537 kvm_clear_exception_queue(&svm->vcpu);
2538 kvm_clear_interrupt_queue(&svm->vcpu);
2539
2540 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2541 return;
2542
2543 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2544 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2545
2546 switch (type) {
2547 case SVM_EXITINTINFO_TYPE_NMI:
2548 svm->vcpu.arch.nmi_injected = true;
2549 break;
2550 case SVM_EXITINTINFO_TYPE_EXEPT:
2551 /* In case of software exception do not reinject an exception
2552 vector, but re-execute and instruction instead */
219b65dc
AG		 2553 if (is_nested(svm))
2554 break;
66fd3f7f 2555 if (kvm_exception_is_soft(vector))
9222be18
GN		 2556 break;
2557 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2558 u32 err = svm->vmcb->control.exit_int_info_err;
2559 kvm_queue_exception_e(&svm->vcpu, vector, err);
2560
2561 } else
2562 kvm_queue_exception(&svm->vcpu, vector);
2563 break;
2564 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2565 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2566 break;
2567 default:
2568 break;
2569 }
2570}
2571
80e31d4f
AK		 2572#ifdef CONFIG_X86_64
2573#define R "r"
2574#else
2575#define R "e"
2576#endif
2577
04d2cc77 2578static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2579{
a2fa3e9f 2580 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2581 u16 fs_selector;
2582 u16 gs_selector;
2583 u16 ldt_selector;
d9e368d6 2584
5fdbf976
MT		 2585 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2586 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2587 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2588
e756fc62 2589 pre_svm_run(svm);
6aa8b732 2590
649d6864
JR		 2591 sync_lapic_to_cr8(vcpu);
2592
6aa8b732 2593 save_host_msrs(vcpu);
d6e88aec
AK		 2594 fs_selector = kvm_read_fs();
2595 gs_selector = kvm_read_gs();
2596 ldt_selector = kvm_read_ldt();
cda0ffdd 2597 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2598 /* required for live migration with NPT */
2599 if (npt_enabled)
2600 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2601
04d2cc77
AK		 2602 clgi();
2603
2604 local_irq_enable();
36241b8c 2605
6aa8b732 2606 asm volatile (
80e31d4f
AK		 2607 "push %%"R"bp; \n\t"
2608 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2609 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2610 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2611 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2612 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2613 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2614#ifdef CONFIG_X86_64
fb3f0f51
RR		 2615 "mov %c[r8](%[svm]), %%r8 \n\t"
2616 "mov %c[r9](%[svm]), %%r9 \n\t"
2617 "mov %c[r10](%[svm]), %%r10 \n\t"
2618 "mov %c[r11](%[svm]), %%r11 \n\t"
2619 "mov %c[r12](%[svm]), %%r12 \n\t"
2620 "mov %c[r13](%[svm]), %%r13 \n\t"
2621 "mov %c[r14](%[svm]), %%r14 \n\t"
2622 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2623#endif
2624
6aa8b732 2625 /* Enter guest mode */
80e31d4f
AK		 2626 "push %%"R"ax \n\t"
2627 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2628 __ex(SVM_VMLOAD) "\n\t"
2629 __ex(SVM_VMRUN) "\n\t"
2630 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2631 "pop %%"R"ax \n\t"
6aa8b732
AK		 2632
2633 /* Save guest registers, load host registers */
80e31d4f
AK		 2634 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2635 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2636 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2637 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2638 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2639 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2640#ifdef CONFIG_X86_64
fb3f0f51
RR		 2641 "mov %%r8, %c[r8](%[svm]) \n\t"
2642 "mov %%r9, %c[r9](%[svm]) \n\t"
2643 "mov %%r10, %c[r10](%[svm]) \n\t"
2644 "mov %%r11, %c[r11](%[svm]) \n\t"
2645 "mov %%r12, %c[r12](%[svm]) \n\t"
2646 "mov %%r13, %c[r13](%[svm]) \n\t"
2647 "mov %%r14, %c[r14](%[svm]) \n\t"
2648 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2649#endif
80e31d4f 2650 "pop %%"R"bp"
6aa8b732 2651 :
fb3f0f51 2652 : [svm]"a"(svm),
6aa8b732 2653 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2654 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2655 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2656 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2657 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2658 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2659 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2660#ifdef CONFIG_X86_64
ad312c7c
ZX		 2661 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2662 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2663 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2664 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2665 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2666 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2667 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2668 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2669#endif
54a08c04 2670 : "cc", "memory"
80e31d4f 2671 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2672#ifdef CONFIG_X86_64
54a08c04
LV		 2673 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2674#endif
2675 );
6aa8b732 2676
ad312c7c 2677 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2678 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2679 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2680 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2681
d6e88aec
AK		 2682 kvm_load_fs(fs_selector);
2683 kvm_load_gs(gs_selector);
2684 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2685 load_host_msrs(vcpu);
2686
2687 reload_tss(vcpu);
2688
56ba47dd
AK		 2689 local_irq_disable();
2690
2691 stgi();
2692
d7bf8221
JR		 2693 sync_cr8_to_lapic(vcpu);
2694
a2fa3e9f 2695 svm->next_rip = 0;
9222be18 2696
6de4f3ad
AK		 2697 if (npt_enabled) {
2698 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2699 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2700 }
6aa8b732
AK		 2701}
2702
80e31d4f
AK		 2703#undef R
2704
6aa8b732
AK		 2705static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2706{
a2fa3e9f
GH		 2707 struct vcpu_svm *svm = to_svm(vcpu);
2708
709ddebf
JR		 2709 if (npt_enabled) {
2710 svm->vmcb->control.nested_cr3 = root;
2711 force_new_asid(vcpu);
2712 return;
2713 }
2714
a2fa3e9f 2715 svm->vmcb->save.cr3 = root;
6aa8b732 2716 force_new_asid(vcpu);
7807fa6c
AL		 2717
2718 if (vcpu->fpu_active) {
a2fa3e9f
GH		 2719 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2720 svm->vmcb->save.cr0 |= X86_CR0_TS;
7807fa6c
AL		 2721 vcpu->fpu_active = 0;
2722 }
6aa8b732
AK		 2723}
2724
6aa8b732
AK		 2725static int is_disabled(void)
2726{
6031a61c
JR		 2727 u64 vm_cr;
2728
2729 rdmsrl(MSR_VM_CR, vm_cr);
2730 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2731 return 1;
2732
6aa8b732
AK		 2733 return 0;
2734}
2735
102d8325
IM		 2736static void
2737svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2738{
2739 /*
2740 * Patch in the VMMCALL instruction:
2741 */
2742 hypercall[0] = 0x0f;
2743 hypercall[1] = 0x01;
2744 hypercall[2] = 0xd9;
102d8325
IM		 2745}
2746
002c7f7c
YS		 2747static void svm_check_processor_compat(void *rtn)
2748{
2749 *(int *)rtn = 0;
2750}
2751
774ead3a
AK		 2752static bool svm_cpu_has_accelerated_tpr(void)
2753{
2754 return false;
2755}
2756
67253af5
SY		 2757static int get_npt_level(void)
2758{
2759#ifdef CONFIG_X86_64
2760 return PT64_ROOT_LEVEL;
2761#else
2762 return PT32E_ROOT_LEVEL;
2763#endif
2764}
2765
4b12f0de 2766static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 2767{
2768 return 0;
2769}
2770
229456fc
MT		 2771static const struct trace_print_flags svm_exit_reasons_str[] = {
2772 { SVM_EXIT_READ_CR0, "read_cr0" },
2773 { SVM_EXIT_READ_CR3, "read_cr3" },
2774 { SVM_EXIT_READ_CR4, "read_cr4" },
2775 { SVM_EXIT_READ_CR8, "read_cr8" },
2776 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2777 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2778 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2779 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2780 { SVM_EXIT_READ_DR0, "read_dr0" },
2781 { SVM_EXIT_READ_DR1, "read_dr1" },
2782 { SVM_EXIT_READ_DR2, "read_dr2" },
2783 { SVM_EXIT_READ_DR3, "read_dr3" },
2784 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2785 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2786 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2787 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2788 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2789 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2790 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2791 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2792 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2793 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2794 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2795 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2796 { SVM_EXIT_INTR, "interrupt" },
2797 { SVM_EXIT_NMI, "nmi" },
2798 { SVM_EXIT_SMI, "smi" },
2799 { SVM_EXIT_INIT, "init" },
2800 { SVM_EXIT_VINTR, "vintr" },
2801 { SVM_EXIT_CPUID, "cpuid" },
2802 { SVM_EXIT_INVD, "invd" },
2803 { SVM_EXIT_HLT, "hlt" },
2804 { SVM_EXIT_INVLPG, "invlpg" },
2805 { SVM_EXIT_INVLPGA, "invlpga" },
2806 { SVM_EXIT_IOIO, "io" },
2807 { SVM_EXIT_MSR, "msr" },
2808 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2809 { SVM_EXIT_SHUTDOWN, "shutdown" },
2810 { SVM_EXIT_VMRUN, "vmrun" },
2811 { SVM_EXIT_VMMCALL, "hypercall" },
2812 { SVM_EXIT_VMLOAD, "vmload" },
2813 { SVM_EXIT_VMSAVE, "vmsave" },
2814 { SVM_EXIT_STGI, "stgi" },
2815 { SVM_EXIT_CLGI, "clgi" },
2816 { SVM_EXIT_SKINIT, "skinit" },
2817 { SVM_EXIT_WBINVD, "wbinvd" },
2818 { SVM_EXIT_MONITOR, "monitor" },
2819 { SVM_EXIT_MWAIT, "mwait" },
2820 { SVM_EXIT_NPF, "npf" },
2821 { -1, NULL }
2822};
2823
344f414f
JR		 2824static bool svm_gb_page_enable(void)
2825{
2826 return true;
2827}
2828
cbdd1bea 2829static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 2830 .cpu_has_kvm_support = has_svm,
2831 .disabled_by_bios = is_disabled,
2832 .hardware_setup = svm_hardware_setup,
2833 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 2834 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 2835 .hardware_enable = svm_hardware_enable,
2836 .hardware_disable = svm_hardware_disable,
774ead3a 2837 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 2838
2839 .vcpu_create = svm_create_vcpu,
2840 .vcpu_free = svm_free_vcpu,
04d2cc77 2841 .vcpu_reset = svm_vcpu_reset,
6aa8b732 2842
04d2cc77 2843 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 2844 .vcpu_load = svm_vcpu_load,
2845 .vcpu_put = svm_vcpu_put,
2846
2847 .set_guest_debug = svm_guest_debug,
2848 .get_msr = svm_get_msr,
2849 .set_msr = svm_set_msr,
2850 .get_segment_base = svm_get_segment_base,
2851 .get_segment = svm_get_segment,
2852 .set_segment = svm_set_segment,
2e4d2653 2853 .get_cpl = svm_get_cpl,
1747fb71 2854 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
25c4c276 2855 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 2856 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 2857 .set_cr3 = svm_set_cr3,
2858 .set_cr4 = svm_set_cr4,
2859 .set_efer = svm_set_efer,
2860 .get_idt = svm_get_idt,
2861 .set_idt = svm_set_idt,
2862 .get_gdt = svm_get_gdt,
2863 .set_gdt = svm_set_gdt,
2864 .get_dr = svm_get_dr,
2865 .set_dr = svm_set_dr,
6de4f3ad 2866 .cache_reg = svm_cache_reg,
6aa8b732
AK		 2867 .get_rflags = svm_get_rflags,
2868 .set_rflags = svm_set_rflags,
2869
6aa8b732 2870 .tlb_flush = svm_flush_tlb,
6aa8b732 2871
6aa8b732 2872 .run = svm_vcpu_run,
04d2cc77 2873 .handle_exit = handle_exit,
6aa8b732 2874 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 2875 .set_interrupt_shadow = svm_set_interrupt_shadow,
2876 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 2877 .patch_hypercall = svm_patch_hypercall,
2a8067f1 2878 .set_irq = svm_set_irq,
95ba8273 2879 .set_nmi = svm_inject_nmi,
298101da 2880 .queue_exception = svm_queue_exception,
78646121 2881 .interrupt_allowed = svm_interrupt_allowed,
95ba8273
GN		 2882 .nmi_allowed = svm_nmi_allowed,
2883 .enable_nmi_window = enable_nmi_window,
2884 .enable_irq_window = enable_irq_window,
2885 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 2886
2887 .set_tss_addr = svm_set_tss_addr,
67253af5 2888 .get_tdp_level = get_npt_level,
4b12f0de 2889 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 2890
2891 .exit_reasons_str = svm_exit_reasons_str,
344f414f 2892 .gb_page_enable = svm_gb_page_enable,
6aa8b732
AK		 2893};
2894
2895static int __init svm_init(void)
2896{
cb498ea2 2897 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 2898 THIS_MODULE);
6aa8b732
AK		 2899}
2900
2901static void __exit svm_exit(void)
2902{
cb498ea2 2903 kvm_exit();
6aa8b732
AK		 2904}
2905
2906module_init(svm_init)
2907module_exit(svm_exit)
kernel source for telekom puls (alcatel/mediatek)