projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: VMX: Simplify pdptr and cr3 management
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
6aa8b732 28
e495606d 29#include <asm/desc.h>
6aa8b732 30
63d1142f
EH		 31#include <asm/virtext.h>
32
4ecac3fd
AK		 33#define __ex(x) __kvm_handle_fault_on_reboot(x)
34
6aa8b732
AK		 35MODULE_AUTHOR("Qumranet");
36MODULE_LICENSE("GPL");
37
38#define IOPM_ALLOC_ORDER 2
39#define MSRPM_ALLOC_ORDER 1
40
6aa8b732
AK		 41#define SEG_TYPE_LDT 2
42#define SEG_TYPE_BUSY_TSS16 3
43
80b7706e
JR		 44#define SVM_FEATURE_NPT (1 << 0)
45#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 46#define SVM_FEATURE_SVML (1 << 2)
80b7706e 47
24e09cbf
JR		 48#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
49
c0725420
AG		 50/* Turn on to get debugging output*/
51/* #define NESTED_DEBUG */
52
53#ifdef NESTED_DEBUG
54#define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
55#else
56#define nsvm_printk(fmt, args...) do {} while(0)
57#endif
58
6c8166a7
AK		 59static const u32 host_save_user_msrs[] = {
60#ifdef CONFIG_X86_64
61 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
62 MSR_FS_BASE,
63#endif
64 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
65};
66
67#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
68
69struct kvm_vcpu;
70
71struct vcpu_svm {
72 struct kvm_vcpu vcpu;
73 struct vmcb *vmcb;
74 unsigned long vmcb_pa;
75 struct svm_cpu_data *svm_data;
76 uint64_t asid_generation;
77 uint64_t sysenter_esp;
78 uint64_t sysenter_eip;
79
80 u64 next_rip;
81
82 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
83 u64 host_gs_base;
84 unsigned long host_cr2;
85
86 u32 *msrpm;
87 struct vmcb *hsave;
88 u64 hsave_msr;
89
90 u64 nested_vmcb;
91
92 /* These are the merged vectors */
93 u32 *nested_msrpm;
94
95 /* gpa pointers to the real vectors */
96 u64 nested_vmcb_msrpm;
97};
98
709ddebf
JR		 99/* enable NPT for AMD64 and X86 with PAE */
100#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
101static bool npt_enabled = true;
102#else
e3da3acd 103static bool npt_enabled = false;
709ddebf 104#endif
6c7dac72
JR		 105static int npt = 1;
106
107module_param(npt, int, S_IRUGO);
e3da3acd 108
236de055
AG		 109static int nested = 0;
110module_param(nested, int, S_IRUGO);
111
44874f84 112static void svm_flush_tlb(struct kvm_vcpu *vcpu);
04d2cc77 113
cf74a78b
AG		 114static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
115static int nested_svm_vmexit(struct vcpu_svm *svm);
116static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
117 void *arg2, void *opaque);
118static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
119 bool has_error_code, u32 error_code);
120
a2fa3e9f
GH		 121static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
122{
fb3f0f51 123 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 124}
125
3d6368ef
AG		 126static inline bool is_nested(struct vcpu_svm *svm)
127{
128 return svm->nested_vmcb;
129}
130
4866d5e3 131static unsigned long iopm_base;
6aa8b732
AK		 132
133struct kvm_ldttss_desc {
134 u16 limit0;
135 u16 base0;
136 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
137 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
138 u32 base3;
139 u32 zero1;
140} __attribute__((packed));
141
142struct svm_cpu_data {
143 int cpu;
144
5008fdf5
AK		 145 u64 asid_generation;
146 u32 max_asid;
147 u32 next_asid;
6aa8b732
AK		 148 struct kvm_ldttss_desc *tss_desc;
149
150 struct page *save_area;
151};
152
153static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 154static uint32_t svm_features;
6aa8b732
AK		 155
156struct svm_init_data {
157 int cpu;
158 int r;
159};
160
161static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
162
9d8f549d 163#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 164#define MSRS_RANGE_SIZE 2048
165#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
166
167#define MAX_INST_SIZE 15
168
80b7706e
JR		 169static inline u32 svm_has(u32 feat)
170{
171 return svm_features & feat;
172}
173
6aa8b732
AK		 174static inline void clgi(void)
175{
4ecac3fd 176 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 177}
178
179static inline void stgi(void)
180{
4ecac3fd 181 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 182}
183
184static inline void invlpga(unsigned long addr, u32 asid)
185{
4ecac3fd 186 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 187}
188
189static inline unsigned long kvm_read_cr2(void)
190{
191 unsigned long cr2;
192
193 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
194 return cr2;
195}
196
197static inline void kvm_write_cr2(unsigned long val)
198{
199 asm volatile ("mov %0, %%cr2" :: "r" (val));
200}
201
6aa8b732
AK		 202static inline void force_new_asid(struct kvm_vcpu *vcpu)
203{
a2fa3e9f 204 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 205}
206
207static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
208{
209 force_new_asid(vcpu);
210}
211
212static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
213{
709ddebf 214 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 215 efer &= ~EFER_LME;
6aa8b732 216
9962d032 217 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
ad312c7c 218 vcpu->arch.shadow_efer = efer;
6aa8b732
AK		 219}
220
298101da
AK		 221static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
222 bool has_error_code, u32 error_code)
223{
224 struct vcpu_svm *svm = to_svm(vcpu);
225
cf74a78b
AG		 226 /* If we are within a nested VM we'd better #VMEXIT and let the
227 guest handle the exception */
228 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
229 return;
230
298101da
AK		 231 svm->vmcb->control.event_inj = nr
232 | SVM_EVTINJ_VALID
233 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
234 | SVM_EVTINJ_TYPE_EXEPT;
235 svm->vmcb->control.event_inj_err = error_code;
236}
237
6aa8b732
AK		 238static int is_external_interrupt(u32 info)
239{
240 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
241 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
242}
243
2809f5d2
GC		 244static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
245{
246 struct vcpu_svm *svm = to_svm(vcpu);
247 u32 ret = 0;
248
249 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
250 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
251 return ret & mask;
252}
253
254static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
255{
256 struct vcpu_svm *svm = to_svm(vcpu);
257
258 if (mask == 0)
259 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
260 else
261 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
262
263}
264
6aa8b732
AK		 265static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
266{
a2fa3e9f
GH		 267 struct vcpu_svm *svm = to_svm(vcpu);
268
269 if (!svm->next_rip) {
f629cf84
GN		 270 if (emulate_instruction(vcpu, vcpu->run, 0, 0, EMULTYPE_SKIP) !=
271 EMULATE_DONE)
272 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 273 return;
274 }
5fdbf976
MT		 275 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
276 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
277 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 278
5fdbf976 279 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 280 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 281}
282
283static int has_svm(void)
284{
63d1142f 285 const char *msg;
6aa8b732 286
63d1142f 287 if (!cpu_has_svm(&msg)) {
ff81ff10 288 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 289 return 0;
290 }
291
6aa8b732
AK		 292 return 1;
293}
294
295static void svm_hardware_disable(void *garbage)
296{
2c8dceeb 297 cpu_svm_disable();
6aa8b732
AK		 298}
299
300static void svm_hardware_enable(void *garbage)
301{
302
303 struct svm_cpu_data *svm_data;
304 uint64_t efer;
6aa8b732 305 struct desc_ptr gdt_descr;
6aa8b732
AK		 306 struct desc_struct *gdt;
307 int me = raw_smp_processor_id();
308
309 if (!has_svm()) {
310 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
311 return;
312 }
313 svm_data = per_cpu(svm_data, me);
314
315 if (!svm_data) {
316 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
317 me);
318 return;
319 }
320
321 svm_data->asid_generation = 1;
322 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
323 svm_data->next_asid = svm_data->max_asid + 1;
324
d77c26fc 325 asm volatile ("sgdt %0" : "=m"(gdt_descr));
6aa8b732
AK		 326 gdt = (struct desc_struct *)gdt_descr.address;
327 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
328
329 rdmsrl(MSR_EFER, efer);
9962d032 330 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732
AK		 331
332 wrmsrl(MSR_VM_HSAVE_PA,
333 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
334}
335
0da1db75
JR		 336static void svm_cpu_uninit(int cpu)
337{
338 struct svm_cpu_data *svm_data
339 = per_cpu(svm_data, raw_smp_processor_id());
340
341 if (!svm_data)
342 return;
343
344 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
345 __free_page(svm_data->save_area);
346 kfree(svm_data);
347}
348
6aa8b732
AK		 349static int svm_cpu_init(int cpu)
350{
351 struct svm_cpu_data *svm_data;
352 int r;
353
354 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
355 if (!svm_data)
356 return -ENOMEM;
357 svm_data->cpu = cpu;
358 svm_data->save_area = alloc_page(GFP_KERNEL);
359 r = -ENOMEM;
360 if (!svm_data->save_area)
361 goto err_1;
362
363 per_cpu(svm_data, cpu) = svm_data;
364
365 return 0;
366
367err_1:
368 kfree(svm_data);
369 return r;
370
371}
372
bfc733a7
RR		 373static void set_msr_interception(u32 *msrpm, unsigned msr,
374 int read, int write)
6aa8b732
AK		 375{
376 int i;
377
378 for (i = 0; i < NUM_MSR_MAPS; i++) {
379 if (msr >= msrpm_ranges[i] &&
380 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
381 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
382 msrpm_ranges[i]) * 2;
383
384 u32 *base = msrpm + (msr_offset / 32);
385 u32 msr_shift = msr_offset % 32;
386 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
387 *base = (*base & ~(0x3 << msr_shift)) |
388 (mask << msr_shift);
bfc733a7 389 return;
6aa8b732
AK		 390 }
391 }
bfc733a7 392 BUG();
6aa8b732
AK		 393}
394
f65c229c
JR		 395static void svm_vcpu_init_msrpm(u32 *msrpm)
396{
397 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
398
399#ifdef CONFIG_X86_64
400 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
401 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
402 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
403 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
404 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
405 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
406#endif
407 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
408 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
f65c229c
JR		 409}
410
24e09cbf
JR		 411static void svm_enable_lbrv(struct vcpu_svm *svm)
412{
413 u32 *msrpm = svm->msrpm;
414
415 svm->vmcb->control.lbr_ctl = 1;
416 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
417 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
418 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
419 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
420}
421
422static void svm_disable_lbrv(struct vcpu_svm *svm)
423{
424 u32 *msrpm = svm->msrpm;
425
426 svm->vmcb->control.lbr_ctl = 0;
427 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
428 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
429 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
430 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
431}
432
6aa8b732
AK		 433static __init int svm_hardware_setup(void)
434{
435 int cpu;
436 struct page *iopm_pages;
f65c229c 437 void *iopm_va;
6aa8b732
AK		 438 int r;
439
6aa8b732
AK		 440 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
441
442 if (!iopm_pages)
443 return -ENOMEM;
c8681339
AL		 444
445 iopm_va = page_address(iopm_pages);
446 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 447 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
448
50a37eb4
JR		 449 if (boot_cpu_has(X86_FEATURE_NX))
450 kvm_enable_efer_bits(EFER_NX);
451
1b2fd70c
AG		 452 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
453 kvm_enable_efer_bits(EFER_FFXSR);
454
236de055
AG		 455 if (nested) {
456 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
457 kvm_enable_efer_bits(EFER_SVME);
458 }
459
6aa8b732
AK		 460 for_each_online_cpu(cpu) {
461 r = svm_cpu_init(cpu);
462 if (r)
f65c229c 463 goto err;
6aa8b732 464 }
33bd6a0b
JR		 465
466 svm_features = cpuid_edx(SVM_CPUID_FUNC);
467
e3da3acd
JR		 468 if (!svm_has(SVM_FEATURE_NPT))
469 npt_enabled = false;
470
6c7dac72
JR		 471 if (npt_enabled && !npt) {
472 printk(KERN_INFO "kvm: Nested Paging disabled\n");
473 npt_enabled = false;
474 }
475
18552672 476 if (npt_enabled) {
e3da3acd 477 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 478 kvm_enable_tdp();
5f4cb662
JR		 479 } else
480 kvm_disable_tdp();
e3da3acd 481
6aa8b732
AK		 482 return 0;
483
f65c229c 484err:
6aa8b732
AK		 485 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
486 iopm_base = 0;
487 return r;
488}
489
490static __exit void svm_hardware_unsetup(void)
491{
0da1db75
JR		 492 int cpu;
493
494 for_each_online_cpu(cpu)
495 svm_cpu_uninit(cpu);
496
6aa8b732 497 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 498 iopm_base = 0;
6aa8b732
AK		 499}
500
501static void init_seg(struct vmcb_seg *seg)
502{
503 seg->selector = 0;
504 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
505 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
506 seg->limit = 0xffff;
507 seg->base = 0;
508}
509
510static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
511{
512 seg->selector = 0;
513 seg->attrib = SVM_SELECTOR_P_MASK | type;
514 seg->limit = 0xffff;
515 seg->base = 0;
516}
517
e6101a96 518static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 519{
e6101a96
JR		 520 struct vmcb_control_area *control = &svm->vmcb->control;
521 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732
AK		 522
523 control->intercept_cr_read = INTERCEPT_CR0_MASK |
524 INTERCEPT_CR3_MASK |
649d6864 525 INTERCEPT_CR4_MASK;
6aa8b732
AK		 526
527 control->intercept_cr_write = INTERCEPT_CR0_MASK |
528 INTERCEPT_CR3_MASK |
80a8119c
AK		 529 INTERCEPT_CR4_MASK |
530 INTERCEPT_CR8_MASK;
6aa8b732
AK		 531
532 control->intercept_dr_read = INTERCEPT_DR0_MASK |
533 INTERCEPT_DR1_MASK |
534 INTERCEPT_DR2_MASK |
535 INTERCEPT_DR3_MASK;
536
537 control->intercept_dr_write = INTERCEPT_DR0_MASK |
538 INTERCEPT_DR1_MASK |
539 INTERCEPT_DR2_MASK |
540 INTERCEPT_DR3_MASK |
541 INTERCEPT_DR5_MASK |
542 INTERCEPT_DR7_MASK;
543
7aa81cc0 544 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 545 (1 << UD_VECTOR) |
546 (1 << MC_VECTOR);
6aa8b732
AK		 547
548
549 control->intercept = (1ULL << INTERCEPT_INTR) |
550 (1ULL << INTERCEPT_NMI) |
0152527b 551 (1ULL << INTERCEPT_SMI) |
6aa8b732 552 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 553 (1ULL << INTERCEPT_INVD) |
6aa8b732 554 (1ULL << INTERCEPT_HLT) |
a7052897 555 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 556 (1ULL << INTERCEPT_INVLPGA) |
557 (1ULL << INTERCEPT_IOIO_PROT) |
558 (1ULL << INTERCEPT_MSR_PROT) |
559 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 560 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 561 (1ULL << INTERCEPT_VMRUN) |
562 (1ULL << INTERCEPT_VMMCALL) |
563 (1ULL << INTERCEPT_VMLOAD) |
564 (1ULL << INTERCEPT_VMSAVE) |
565 (1ULL << INTERCEPT_STGI) |
566 (1ULL << INTERCEPT_CLGI) |
916ce236 567 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 568 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 569 (1ULL << INTERCEPT_MONITOR) |
570 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 571
572 control->iopm_base_pa = iopm_base;
f65c229c 573 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 574 control->tsc_offset = 0;
6aa8b732
AK		 575 control->int_ctl = V_INTR_MASKING_MASK;
576
577 init_seg(&save->es);
578 init_seg(&save->ss);
579 init_seg(&save->ds);
580 init_seg(&save->fs);
581 init_seg(&save->gs);
582
583 save->cs.selector = 0xf000;
584 /* Executable/Readable Code Segment */
585 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
586 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
587 save->cs.limit = 0xffff;
d92899a0
AK		 588 /*
589 * cs.base should really be 0xffff0000, but vmx can't handle that, so
590 * be consistent with it.
591 *
592 * Replace when we have real mode working for vmx.
593 */
594 save->cs.base = 0xf0000;
6aa8b732
AK		 595
596 save->gdtr.limit = 0xffff;
597 save->idtr.limit = 0xffff;
598
599 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
600 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
601
9962d032 602 save->efer = EFER_SVME;
d77c26fc 603 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 604 save->dr7 = 0x400;
605 save->rflags = 2;
606 save->rip = 0x0000fff0;
5fdbf976 607 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732
AK		 608
609 /*
610 * cr0 val on cpu init should be 0x60000010, we enable cpu
611 * cache by default. the orderly way is to enable cache in bios.
612 */
707d92fa 613 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
66aee91a 614 save->cr4 = X86_CR4_PAE;
6aa8b732 615 /* rdx = ?? */
709ddebf
JR		 616
617 if (npt_enabled) {
618 /* Setup VMCB for Nested Paging */
619 control->nested_ctl = 1;
a7052897
MT		 620 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
621 (1ULL << INTERCEPT_INVLPG));
709ddebf
JR		 622 control->intercept_exceptions &= ~(1 << PF_VECTOR);
623 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
624 INTERCEPT_CR3_MASK);
625 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
626 INTERCEPT_CR3_MASK);
627 save->g_pat = 0x0007040600070406ULL;
628 /* enable caching because the QEMU Bios doesn't enable it */
629 save->cr0 = X86_CR0_ET;
630 save->cr3 = 0;
631 save->cr4 = 0;
632 }
a79d2f18 633 force_new_asid(&svm->vcpu);
1371d904 634
3d6368ef 635 svm->nested_vmcb = 0;
1371d904 636 svm->vcpu.arch.hflags = HF_GIF_MASK;
6aa8b732
AK		 637}
638
e00c8cf2 639static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 640{
641 struct vcpu_svm *svm = to_svm(vcpu);
642
e6101a96 643 init_vmcb(svm);
70433389
AK		 644
645 if (vcpu->vcpu_id != 0) {
5fdbf976 646 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 647 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
648 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 649 }
5fdbf976
MT		 650 vcpu->arch.regs_avail = ~0;
651 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 652
653 return 0;
04d2cc77
AK		 654}
655
fb3f0f51 656static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 657{
a2fa3e9f 658 struct vcpu_svm *svm;
6aa8b732 659 struct page *page;
f65c229c 660 struct page *msrpm_pages;
b286d5d8 661 struct page *hsave_page;
3d6368ef 662 struct page *nested_msrpm_pages;
fb3f0f51 663 int err;
6aa8b732 664
c16f862d 665 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 666 if (!svm) {
667 err = -ENOMEM;
668 goto out;
669 }
670
671 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
672 if (err)
673 goto free_svm;
674
6aa8b732 675 page = alloc_page(GFP_KERNEL);
fb3f0f51
RR		 676 if (!page) {
677 err = -ENOMEM;
678 goto uninit;
679 }
6aa8b732 680
f65c229c
JR		 681 err = -ENOMEM;
682 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
683 if (!msrpm_pages)
684 goto uninit;
3d6368ef
AG		 685
686 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
687 if (!nested_msrpm_pages)
688 goto uninit;
689
f65c229c
JR		 690 svm->msrpm = page_address(msrpm_pages);
691 svm_vcpu_init_msrpm(svm->msrpm);
692
b286d5d8
AG		 693 hsave_page = alloc_page(GFP_KERNEL);
694 if (!hsave_page)
695 goto uninit;
696 svm->hsave = page_address(hsave_page);
697
3d6368ef
AG		 698 svm->nested_msrpm = page_address(nested_msrpm_pages);
699
a2fa3e9f
GH		 700 svm->vmcb = page_address(page);
701 clear_page(svm->vmcb);
702 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
703 svm->asid_generation = 0;
e6101a96 704 init_vmcb(svm);
a2fa3e9f 705
fb3f0f51
RR		 706 fx_init(&svm->vcpu);
707 svm->vcpu.fpu_active = 1;
ad312c7c 708 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
fb3f0f51 709 if (svm->vcpu.vcpu_id == 0)
ad312c7c 710 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 711
fb3f0f51 712 return &svm->vcpu;
36241b8c 713
fb3f0f51
RR		 714uninit:
715 kvm_vcpu_uninit(&svm->vcpu);
716free_svm:
a4770347 717 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 718out:
719 return ERR_PTR(err);
6aa8b732
AK		 720}
721
722static void svm_free_vcpu(struct kvm_vcpu *vcpu)
723{
a2fa3e9f
GH		 724 struct vcpu_svm *svm = to_svm(vcpu);
725
fb3f0f51 726 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 727 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
b286d5d8 728 __free_page(virt_to_page(svm->hsave));
3d6368ef 729 __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 730 kvm_vcpu_uninit(vcpu);
a4770347 731 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 732}
733
15ad7146 734static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 735{
a2fa3e9f 736 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 737 int i;
0cc5064d 738
0cc5064d
AK		 739 if (unlikely(cpu != vcpu->cpu)) {
740 u64 tsc_this, delta;
741
742 /*
743 * Make sure that the guest sees a monotonically
744 * increasing TSC.
745 */
746 rdtscll(tsc_this);
ad312c7c 747 delta = vcpu->arch.host_tsc - tsc_this;
a2fa3e9f 748 svm->vmcb->control.tsc_offset += delta;
0cc5064d 749 vcpu->cpu = cpu;
2f599714 750 kvm_migrate_timers(vcpu);
4b656b12 751 svm->asid_generation = 0;
0cc5064d 752 }
94dfbdb3
AL		 753
754 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 755 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 756}
757
758static void svm_vcpu_put(struct kvm_vcpu *vcpu)
759{
a2fa3e9f 760 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 761 int i;
762
e1beb1d3 763 ++vcpu->stat.host_state_reload;
94dfbdb3 764 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 765 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 766
ad312c7c 767 rdtscll(vcpu->arch.host_tsc);
6aa8b732
AK		 768}
769
6aa8b732
AK		 770static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
771{
a2fa3e9f 772 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 773}
774
775static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
776{
a2fa3e9f 777 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 778}
779
f0b85051
AG		 780static void svm_set_vintr(struct vcpu_svm *svm)
781{
782 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
783}
784
785static void svm_clear_vintr(struct vcpu_svm *svm)
786{
787 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
788}
789
6aa8b732
AK		 790static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
791{
a2fa3e9f 792 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 793
794 switch (seg) {
795 case VCPU_SREG_CS: return &save->cs;
796 case VCPU_SREG_DS: return &save->ds;
797 case VCPU_SREG_ES: return &save->es;
798 case VCPU_SREG_FS: return &save->fs;
799 case VCPU_SREG_GS: return &save->gs;
800 case VCPU_SREG_SS: return &save->ss;
801 case VCPU_SREG_TR: return &save->tr;
802 case VCPU_SREG_LDTR: return &save->ldtr;
803 }
804 BUG();
8b6d44c7 805 return NULL;
6aa8b732
AK		 806}
807
808static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
809{
810 struct vmcb_seg *s = svm_seg(vcpu, seg);
811
812 return s->base;
813}
814
815static void svm_get_segment(struct kvm_vcpu *vcpu,
816 struct kvm_segment *var, int seg)
817{
818 struct vmcb_seg *s = svm_seg(vcpu, seg);
819
820 var->base = s->base;
821 var->limit = s->limit;
822 var->selector = s->selector;
823 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
824 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
825 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
826 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
827 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
828 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
829 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
830 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 831
19bca6ab
AP		 832 /* AMD's VMCB does not have an explicit unusable field, so emulate it
833 * for cross vendor migration purposes by "not present"
834 */
835 var->unusable = !var->present || (var->type == 0);
836
1fbdc7a5
AP		 837 switch (seg) {
838 case VCPU_SREG_CS:
839 /*
840 * SVM always stores 0 for the 'G' bit in the CS selector in
841 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
842 * Intel's VMENTRY has a check on the 'G' bit.
843 */
25022acc 844 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 845 break;
846 case VCPU_SREG_TR:
847 /*
848 * Work around a bug where the busy flag in the tr selector
849 * isn't exposed
850 */
c0d09828 851 var->type |= 0x2;
1fbdc7a5
AP		 852 break;
853 case VCPU_SREG_DS:
854 case VCPU_SREG_ES:
855 case VCPU_SREG_FS:
856 case VCPU_SREG_GS:
857 /*
858 * The accessed bit must always be set in the segment
859 * descriptor cache, although it can be cleared in the
860 * descriptor, the cached bit always remains at 1. Since
861 * Intel has a check on this, set it here to support
862 * cross-vendor migration.
863 */
864 if (!var->unusable)
865 var->type |= 0x1;
866 break;
b586eb02
AP		 867 case VCPU_SREG_SS:
868 /* On AMD CPUs sometimes the DB bit in the segment
869 * descriptor is left as 1, although the whole segment has
870 * been made unusable. Clear it here to pass an Intel VMX
871 * entry check when cross vendor migrating.
872 */
873 if (var->unusable)
874 var->db = 0;
875 break;
1fbdc7a5 876 }
6aa8b732
AK		 877}
878
2e4d2653
IE		 879static int svm_get_cpl(struct kvm_vcpu *vcpu)
880{
881 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
882
883 return save->cpl;
884}
885
6aa8b732
AK		 886static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
887{
a2fa3e9f
GH		 888 struct vcpu_svm *svm = to_svm(vcpu);
889
890 dt->limit = svm->vmcb->save.idtr.limit;
891 dt->base = svm->vmcb->save.idtr.base;
6aa8b732
AK		 892}
893
894static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
895{
a2fa3e9f
GH		 896 struct vcpu_svm *svm = to_svm(vcpu);
897
898 svm->vmcb->save.idtr.limit = dt->limit;
899 svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 900}
901
902static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
903{
a2fa3e9f
GH		 904 struct vcpu_svm *svm = to_svm(vcpu);
905
906 dt->limit = svm->vmcb->save.gdtr.limit;
907 dt->base = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 908}
909
910static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
911{
a2fa3e9f
GH		 912 struct vcpu_svm *svm = to_svm(vcpu);
913
914 svm->vmcb->save.gdtr.limit = dt->limit;
915 svm->vmcb->save.gdtr.base = dt->base ;
6aa8b732
AK		 916}
917
25c4c276 918static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 919{
920}
921
6aa8b732
AK		 922static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
923{
a2fa3e9f
GH		 924 struct vcpu_svm *svm = to_svm(vcpu);
925
05b3e0c2 926#ifdef CONFIG_X86_64
ad312c7c 927 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 928 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
ad312c7c 929 vcpu->arch.shadow_efer |= EFER_LMA;
2b5203ee 930 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 931 }
932
d77c26fc 933 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
ad312c7c 934 vcpu->arch.shadow_efer &= ~EFER_LMA;
2b5203ee 935 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 936 }
937 }
938#endif
709ddebf
JR		 939 if (npt_enabled)
940 goto set;
941
ad312c7c 942 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
a2fa3e9f 943 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
7807fa6c
AL		 944 vcpu->fpu_active = 1;
945 }
946
ad312c7c 947 vcpu->arch.cr0 = cr0;
707d92fa 948 cr0 |= X86_CR0_PG | X86_CR0_WP;
6b390b63
JR		 949 if (!vcpu->fpu_active) {
950 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
334df50a 951 cr0 |= X86_CR0_TS;
6b390b63 952 }
709ddebf
JR		 953set:
954 /*
955 * re-enable caching here because the QEMU bios
956 * does not do it - this results in some delay at
957 * reboot
958 */
959 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 960 svm->vmcb->save.cr0 = cr0;
6aa8b732
AK		 961}
962
963static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
964{
6394b649 965 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 966 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
967
968 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
969 force_new_asid(vcpu);
6394b649 970
ec077263
JR		 971 vcpu->arch.cr4 = cr4;
972 if (!npt_enabled)
973 cr4 |= X86_CR4_PAE;
6394b649 974 cr4 |= host_cr4_mce;
ec077263 975 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 976}
977
978static void svm_set_segment(struct kvm_vcpu *vcpu,
979 struct kvm_segment *var, int seg)
980{
a2fa3e9f 981 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 982 struct vmcb_seg *s = svm_seg(vcpu, seg);
983
984 s->base = var->base;
985 s->limit = var->limit;
986 s->selector = var->selector;
987 if (var->unusable)
988 s->attrib = 0;
989 else {
990 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
991 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
992 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
993 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
994 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
995 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
996 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
997 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
998 }
999 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1000 svm->vmcb->save.cpl
1001 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1002 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1003
1004}
1005
44c11430 1006static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1007{
d0bfb940
JK		 1008 struct vcpu_svm *svm = to_svm(vcpu);
1009
d0bfb940
JK		 1010 svm->vmcb->control.intercept_exceptions &=
1011 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430
GN		 1012
1013 if (vcpu->arch.singlestep)
1014 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1015
d0bfb940
JK		 1016 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1017 if (vcpu->guest_debug &
1018 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1019 svm->vmcb->control.intercept_exceptions |=
1020 1 << DB_VECTOR;
1021 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1022 svm->vmcb->control.intercept_exceptions |=
1023 1 << BP_VECTOR;
1024 } else
1025 vcpu->guest_debug = 0;
44c11430
GN		 1026}
1027
1028static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1029{
1030 int old_debug = vcpu->guest_debug;
1031 struct vcpu_svm *svm = to_svm(vcpu);
1032
1033 vcpu->guest_debug = dbg->control;
1034
1035 update_db_intercept(vcpu);
d0bfb940 1036
ae675ef0
JK		 1037 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1038 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1039 else
1040 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1041
d0bfb940
JK		 1042 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1043 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1044 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1045 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1046
1047 return 0;
6aa8b732
AK		 1048}
1049
1050static void load_host_msrs(struct kvm_vcpu *vcpu)
1051{
94dfbdb3 1052#ifdef CONFIG_X86_64
a2fa3e9f 1053 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1054#endif
6aa8b732
AK		 1055}
1056
1057static void save_host_msrs(struct kvm_vcpu *vcpu)
1058{
94dfbdb3 1059#ifdef CONFIG_X86_64
a2fa3e9f 1060 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1061#endif
6aa8b732
AK		 1062}
1063
e756fc62 1064static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
6aa8b732
AK		 1065{
1066 if (svm_data->next_asid > svm_data->max_asid) {
1067 ++svm_data->asid_generation;
1068 svm_data->next_asid = 1;
a2fa3e9f 1069 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1070 }
1071
a2fa3e9f
GH		 1072 svm->asid_generation = svm_data->asid_generation;
1073 svm->vmcb->control.asid = svm_data->next_asid++;
6aa8b732
AK		 1074}
1075
6aa8b732
AK		 1076static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1077{
42dbaa5a
JK		 1078 struct vcpu_svm *svm = to_svm(vcpu);
1079 unsigned long val;
1080
1081 switch (dr) {
1082 case 0 ... 3:
1083 val = vcpu->arch.db[dr];
1084 break;
1085 case 6:
1086 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1087 val = vcpu->arch.dr6;
1088 else
1089 val = svm->vmcb->save.dr6;
1090 break;
1091 case 7:
1092 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1093 val = vcpu->arch.dr7;
1094 else
1095 val = svm->vmcb->save.dr7;
1096 break;
1097 default:
1098 val = 0;
1099 }
1100
af9ca2d7
JR		 1101 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
1102 return val;
6aa8b732
AK		 1103}
1104
1105static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1106 int *exception)
1107{
a2fa3e9f
GH		 1108 struct vcpu_svm *svm = to_svm(vcpu);
1109
42dbaa5a 1110 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)value, handler);
6aa8b732 1111
42dbaa5a 1112 *exception = 0;
6aa8b732
AK		 1113
1114 switch (dr) {
1115 case 0 ... 3:
42dbaa5a
JK		 1116 vcpu->arch.db[dr] = value;
1117 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1118 vcpu->arch.eff_db[dr] = value;
6aa8b732
AK		 1119 return;
1120 case 4 ... 5:
42dbaa5a 1121 if (vcpu->arch.cr4 & X86_CR4_DE)
6aa8b732 1122 *exception = UD_VECTOR;
42dbaa5a
JK		 1123 return;
1124 case 6:
1125 if (value & 0xffffffff00000000ULL) {
1126 *exception = GP_VECTOR;
6aa8b732
AK		 1127 return;
1128 }
42dbaa5a
JK		 1129 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1130 return;
1131 case 7:
1132 if (value & 0xffffffff00000000ULL) {
6aa8b732
AK		 1133 *exception = GP_VECTOR;
1134 return;
1135 }
42dbaa5a
JK		 1136 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1137 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1138 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1139 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1140 }
6aa8b732 1141 return;
6aa8b732 1142 default:
42dbaa5a 1143 /* FIXME: Possible case? */
6aa8b732 1144 printk(KERN_DEBUG "%s: unexpected dr %u\n",
b8688d51 1145 __func__, dr);
6aa8b732
AK		 1146 *exception = UD_VECTOR;
1147 return;
1148 }
1149}
1150
e756fc62 1151static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1152{
6aa8b732
AK		 1153 u64 fault_address;
1154 u32 error_code;
6aa8b732 1155
a2fa3e9f
GH		 1156 fault_address = svm->vmcb->control.exit_info_2;
1157 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7
JR		 1158
1159 if (!npt_enabled)
1160 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1161 (u32)fault_address, (u32)(fault_address >> 32),
1162 handler);
d2ebb410
JR		 1163 else
1164 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1165 (u32)fault_address, (u32)(fault_address >> 32),
1166 handler);
44874f84
JR		 1167 /*
1168 * FIXME: Tis shouldn't be necessary here, but there is a flush
1169 * missing in the MMU code. Until we find this bug, flush the
1170 * complete TLB here on an NPF
1171 */
1172 if (npt_enabled)
1173 svm_flush_tlb(&svm->vcpu);
9222be18 1174 else {
3298b75c 1175 if (kvm_event_needs_reinjection(&svm->vcpu))
9222be18
GN		 1176 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1177 }
3067714c 1178 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1179}
1180
d0bfb940
JK		 1181static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1182{
1183 if (!(svm->vcpu.guest_debug &
44c11430
GN		 1184 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1185 !svm->vcpu.arch.singlestep) {
d0bfb940
JK		 1186 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1187 return 1;
1188 }
44c11430
GN		 1189
1190 if (svm->vcpu.arch.singlestep) {
1191 svm->vcpu.arch.singlestep = false;
1192 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1193 svm->vmcb->save.rflags &=
1194 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1195 update_db_intercept(&svm->vcpu);
1196 }
1197
1198 if (svm->vcpu.guest_debug &
1199 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1200 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1201 kvm_run->debug.arch.pc =
1202 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1203 kvm_run->debug.arch.exception = DB_VECTOR;
1204 return 0;
1205 }
1206
1207 return 1;
d0bfb940
JK		 1208}
1209
1210static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1211{
1212 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1213 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1214 kvm_run->debug.arch.exception = BP_VECTOR;
1215 return 0;
1216}
1217
7aa81cc0
AL		 1218static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1219{
1220 int er;
1221
571008da 1222 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1223 if (er != EMULATE_DONE)
7ee5d940 1224 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1225 return 1;
1226}
1227
e756fc62 1228static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
7807fa6c 1229{
a2fa3e9f 1230 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
ad312c7c 1231 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
a2fa3e9f 1232 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
e756fc62 1233 svm->vcpu.fpu_active = 1;
a2fa3e9f
GH		 1234
1235 return 1;
7807fa6c
AL		 1236}
1237
53371b50
JR		 1238static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1239{
1240 /*
1241 * On an #MC intercept the MCE handler is not called automatically in
1242 * the host. So do it by hand here.
1243 */
1244 asm volatile (
1245 "int $0x12\n");
1246 /* not sure if we ever come back to this point */
1247
1248 return 1;
1249}
1250
e756fc62 1251static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
46fe4ddd
JR		 1252{
1253 /*
1254 * VMCB is undefined after a SHUTDOWN intercept
1255 * so reinitialize it.
1256 */
a2fa3e9f 1257 clear_page(svm->vmcb);
e6101a96 1258 init_vmcb(svm);
46fe4ddd
JR		 1259
1260 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1261 return 0;
1262}
1263
e756fc62 1264static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1265{
d77c26fc 1266 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1267 int size, in, string;
039576c0 1268 unsigned port;
6aa8b732 1269
e756fc62 1270 ++svm->vcpu.stat.io_exits;
6aa8b732 1271
a2fa3e9f 1272 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1273
e70669ab
LV		 1274 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1275
1276 if (string) {
3427318f
LV		 1277 if (emulate_instruction(&svm->vcpu,
1278 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1279 return 0;
1280 return 1;
1281 }
1282
039576c0
AK		 1283 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1284 port = io_info >> 16;
1285 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1286
e93f36bc 1287 skip_emulated_instruction(&svm->vcpu);
3090dd73 1288 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
6aa8b732
AK		 1289}
1290
c47f098d
JR		 1291static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1292{
af9ca2d7 1293 KVMTRACE_0D(NMI, &svm->vcpu, handler);
c47f098d
JR		 1294 return 1;
1295}
1296
a0698055
JR		 1297static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1298{
1299 ++svm->vcpu.stat.irq_exits;
af9ca2d7 1300 KVMTRACE_0D(INTR, &svm->vcpu, handler);
a0698055
JR		 1301 return 1;
1302}
1303
e756fc62 1304static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732
AK		 1305{
1306 return 1;
1307}
1308
e756fc62 1309static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1310{
5fdbf976 1311 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1312 skip_emulated_instruction(&svm->vcpu);
1313 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1314}
1315
e756fc62 1316static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
02e235bc 1317{
5fdbf976 1318 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1319 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1320 kvm_emulate_hypercall(&svm->vcpu);
1321 return 1;
02e235bc
AK		 1322}
1323
c0725420
AG		 1324static int nested_svm_check_permissions(struct vcpu_svm *svm)
1325{
1326 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1327 || !is_paging(&svm->vcpu)) {
1328 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1329 return 1;
1330 }
1331
1332 if (svm->vmcb->save.cpl) {
1333 kvm_inject_gp(&svm->vcpu, 0);
1334 return 1;
1335 }
1336
1337 return 0;
1338}
1339
cf74a78b
AG		 1340static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1341 bool has_error_code, u32 error_code)
1342{
1343 if (is_nested(svm)) {
1344 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1345 svm->vmcb->control.exit_code_hi = 0;
1346 svm->vmcb->control.exit_info_1 = error_code;
1347 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1348 if (nested_svm_exit_handled(svm, false)) {
1349 nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1350
1351 nested_svm_vmexit(svm);
1352 return 1;
1353 }
1354 }
1355
1356 return 0;
1357}
1358
1359static inline int nested_svm_intr(struct vcpu_svm *svm)
1360{
1361 if (is_nested(svm)) {
1362 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1363 return 0;
1364
1365 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1366 return 0;
1367
1368 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1369
1370 if (nested_svm_exit_handled(svm, false)) {
1371 nsvm_printk("VMexit -> INTR\n");
1372 nested_svm_vmexit(svm);
1373 return 1;
1374 }
1375 }
1376
1377 return 0;
1378}
1379
c0725420
AG		 1380static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1381{
1382 struct page *page;
1383
1384 down_read(&current->mm->mmap_sem);
1385 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1386 up_read(&current->mm->mmap_sem);
1387
1388 if (is_error_page(page)) {
1389 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1390 __func__, gpa);
1391 kvm_release_page_clean(page);
1392 kvm_inject_gp(&svm->vcpu, 0);
1393 return NULL;
1394 }
1395 return page;
1396}
1397
1398static int nested_svm_do(struct vcpu_svm *svm,
1399 u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1400 int (*handler)(struct vcpu_svm *svm,
1401 void *arg1,
1402 void *arg2,
1403 void *opaque))
1404{
1405 struct page *arg1_page;
1406 struct page *arg2_page = NULL;
1407 void *arg1;
1408 void *arg2 = NULL;
1409 int retval;
1410
1411 arg1_page = nested_svm_get_page(svm, arg1_gpa);
1412 if(arg1_page == NULL)
1413 return 1;
1414
1415 if (arg2_gpa) {
1416 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1417 if(arg2_page == NULL) {
1418 kvm_release_page_clean(arg1_page);
1419 return 1;
1420 }
1421 }
1422
1423 arg1 = kmap_atomic(arg1_page, KM_USER0);
1424 if (arg2_gpa)
1425 arg2 = kmap_atomic(arg2_page, KM_USER1);
1426
1427 retval = handler(svm, arg1, arg2, opaque);
1428
1429 kunmap_atomic(arg1, KM_USER0);
1430 if (arg2_gpa)
1431 kunmap_atomic(arg2, KM_USER1);
1432
1433 kvm_release_page_dirty(arg1_page);
1434 if (arg2_gpa)
1435 kvm_release_page_dirty(arg2_page);
1436
1437 return retval;
1438}
1439
cf74a78b
AG		 1440static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1441 void *arg1,
1442 void *arg2,
1443 void *opaque)
1444{
1445 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1446 bool kvm_overrides = *(bool *)opaque;
1447 u32 exit_code = svm->vmcb->control.exit_code;
1448
1449 if (kvm_overrides) {
1450 switch (exit_code) {
1451 case SVM_EXIT_INTR:
1452 case SVM_EXIT_NMI:
1453 return 0;
1454 /* For now we are always handling NPFs when using them */
1455 case SVM_EXIT_NPF:
1456 if (npt_enabled)
1457 return 0;
1458 break;
1459 /* When we're shadowing, trap PFs */
1460 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1461 if (!npt_enabled)
1462 return 0;
1463 break;
1464 default:
1465 break;
1466 }
1467 }
1468
1469 switch (exit_code) {
1470 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1471 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1472 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1473 return 1;
1474 break;
1475 }
1476 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1477 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1478 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1479 return 1;
1480 break;
1481 }
1482 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1483 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1484 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1485 return 1;
1486 break;
1487 }
1488 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1489 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1490 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1491 return 1;
1492 break;
1493 }
1494 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1495 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1496 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1497 return 1;
1498 break;
1499 }
1500 default: {
1501 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1502 nsvm_printk("exit code: 0x%x\n", exit_code);
1503 if (nested_vmcb->control.intercept & exit_bits)
1504 return 1;
1505 }
1506 }
1507
1508 return 0;
1509}
1510
1511static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1512 void *arg1, void *arg2,
1513 void *opaque)
1514{
1515 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1516 u8 *msrpm = (u8 *)arg2;
1517 u32 t0, t1;
1518 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1519 u32 param = svm->vmcb->control.exit_info_1 & 1;
1520
1521 if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1522 return 0;
1523
1524 switch(msr) {
1525 case 0 ... 0x1fff:
1526 t0 = (msr * 2) % 8;
1527 t1 = msr / 8;
1528 break;
1529 case 0xc0000000 ... 0xc0001fff:
1530 t0 = (8192 + msr - 0xc0000000) * 2;
1531 t1 = (t0 / 8);
1532 t0 %= 8;
1533 break;
1534 case 0xc0010000 ... 0xc0011fff:
1535 t0 = (16384 + msr - 0xc0010000) * 2;
1536 t1 = (t0 / 8);
1537 t0 %= 8;
1538 break;
1539 default:
1540 return 1;
1541 break;
1542 }
1543 if (msrpm[t1] & ((1 << param) << t0))
1544 return 1;
1545
1546 return 0;
1547}
1548
1549static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1550{
1551 bool k = kvm_override;
1552
1553 switch (svm->vmcb->control.exit_code) {
1554 case SVM_EXIT_MSR:
1555 return nested_svm_do(svm, svm->nested_vmcb,
1556 svm->nested_vmcb_msrpm, NULL,
1557 nested_svm_exit_handled_msr);
1558 default: break;
1559 }
1560
1561 return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
1562 nested_svm_exit_handled_real);
1563}
1564
1565static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1566 void *arg2, void *opaque)
1567{
1568 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1569 struct vmcb *hsave = svm->hsave;
1570 u64 nested_save[] = { nested_vmcb->save.cr0,
1571 nested_vmcb->save.cr3,
1572 nested_vmcb->save.cr4,
1573 nested_vmcb->save.efer,
1574 nested_vmcb->control.intercept_cr_read,
1575 nested_vmcb->control.intercept_cr_write,
1576 nested_vmcb->control.intercept_dr_read,
1577 nested_vmcb->control.intercept_dr_write,
1578 nested_vmcb->control.intercept_exceptions,
1579 nested_vmcb->control.intercept,
1580 nested_vmcb->control.msrpm_base_pa,
1581 nested_vmcb->control.iopm_base_pa,
1582 nested_vmcb->control.tsc_offset };
1583
1584 /* Give the current vmcb to the guest */
1585 memcpy(nested_vmcb, svm->vmcb, sizeof(struct vmcb));
1586 nested_vmcb->save.cr0 = nested_save[0];
1587 if (!npt_enabled)
1588 nested_vmcb->save.cr3 = nested_save[1];
1589 nested_vmcb->save.cr4 = nested_save[2];
1590 nested_vmcb->save.efer = nested_save[3];
1591 nested_vmcb->control.intercept_cr_read = nested_save[4];
1592 nested_vmcb->control.intercept_cr_write = nested_save[5];
1593 nested_vmcb->control.intercept_dr_read = nested_save[6];
1594 nested_vmcb->control.intercept_dr_write = nested_save[7];
1595 nested_vmcb->control.intercept_exceptions = nested_save[8];
1596 nested_vmcb->control.intercept = nested_save[9];
1597 nested_vmcb->control.msrpm_base_pa = nested_save[10];
1598 nested_vmcb->control.iopm_base_pa = nested_save[11];
1599 nested_vmcb->control.tsc_offset = nested_save[12];
1600
1601 /* We always set V_INTR_MASKING and remember the old value in hflags */
1602 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1603 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1604
1605 if ((nested_vmcb->control.int_ctl & V_IRQ_MASK) &&
1606 (nested_vmcb->control.int_vector)) {
1607 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1608 nested_vmcb->control.int_vector);
1609 }
1610
1611 /* Restore the original control entries */
1612 svm->vmcb->control = hsave->control;
1613
1614 /* Kill any pending exceptions */
1615 if (svm->vcpu.arch.exception.pending == true)
1616 nsvm_printk("WARNING: Pending Exception\n");
1617 svm->vcpu.arch.exception.pending = false;
1618
1619 /* Restore selected save entries */
1620 svm->vmcb->save.es = hsave->save.es;
1621 svm->vmcb->save.cs = hsave->save.cs;
1622 svm->vmcb->save.ss = hsave->save.ss;
1623 svm->vmcb->save.ds = hsave->save.ds;
1624 svm->vmcb->save.gdtr = hsave->save.gdtr;
1625 svm->vmcb->save.idtr = hsave->save.idtr;
1626 svm->vmcb->save.rflags = hsave->save.rflags;
1627 svm_set_efer(&svm->vcpu, hsave->save.efer);
1628 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1629 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1630 if (npt_enabled) {
1631 svm->vmcb->save.cr3 = hsave->save.cr3;
1632 svm->vcpu.arch.cr3 = hsave->save.cr3;
1633 } else {
1634 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1635 }
1636 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1637 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1638 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1639 svm->vmcb->save.dr7 = 0;
1640 svm->vmcb->save.cpl = 0;
1641 svm->vmcb->control.exit_int_info = 0;
1642
1643 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1644 /* Exit nested SVM mode */
1645 svm->nested_vmcb = 0;
1646
1647 return 0;
1648}
1649
1650static int nested_svm_vmexit(struct vcpu_svm *svm)
1651{
1652 nsvm_printk("VMexit\n");
1653 if (nested_svm_do(svm, svm->nested_vmcb, 0,
1654 NULL, nested_svm_vmexit_real))
1655 return 1;
1656
1657 kvm_mmu_reset_context(&svm->vcpu);
1658 kvm_mmu_load(&svm->vcpu);
1659
1660 return 0;
1661}
3d6368ef
AG		 1662
1663static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1664 void *arg2, void *opaque)
1665{
1666 int i;
1667 u32 *nested_msrpm = (u32*)arg1;
1668 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1669 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1670 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1671
1672 return 0;
1673}
1674
1675static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1676 void *arg2, void *opaque)
1677{
1678 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1679 struct vmcb *hsave = svm->hsave;
1680
1681 /* nested_vmcb is our indicator if nested SVM is activated */
1682 svm->nested_vmcb = svm->vmcb->save.rax;
1683
1684 /* Clear internal status */
1685 svm->vcpu.arch.exception.pending = false;
1686
1687 /* Save the old vmcb, so we don't need to pick what we save, but
1688 can restore everything when a VMEXIT occurs */
1689 memcpy(hsave, svm->vmcb, sizeof(struct vmcb));
1690 /* We need to remember the original CR3 in the SPT case */
1691 if (!npt_enabled)
1692 hsave->save.cr3 = svm->vcpu.arch.cr3;
1693 hsave->save.cr4 = svm->vcpu.arch.cr4;
1694 hsave->save.rip = svm->next_rip;
1695
1696 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1697 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1698 else
1699 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1700
1701 /* Load the nested guest state */
1702 svm->vmcb->save.es = nested_vmcb->save.es;
1703 svm->vmcb->save.cs = nested_vmcb->save.cs;
1704 svm->vmcb->save.ss = nested_vmcb->save.ss;
1705 svm->vmcb->save.ds = nested_vmcb->save.ds;
1706 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1707 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1708 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1709 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1710 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1711 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1712 if (npt_enabled) {
1713 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1714 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1715 } else {
1716 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1717 kvm_mmu_reset_context(&svm->vcpu);
1718 }
1719 svm->vmcb->save.cr2 = nested_vmcb->save.cr2;
1720 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1721 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1722 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1723 /* In case we don't even reach vcpu_run, the fields are not updated */
1724 svm->vmcb->save.rax = nested_vmcb->save.rax;
1725 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1726 svm->vmcb->save.rip = nested_vmcb->save.rip;
1727 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1728 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1729 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1730
1731 /* We don't want a nested guest to be more powerful than the guest,
1732 so all intercepts are ORed */
1733 svm->vmcb->control.intercept_cr_read |=
1734 nested_vmcb->control.intercept_cr_read;
1735 svm->vmcb->control.intercept_cr_write |=
1736 nested_vmcb->control.intercept_cr_write;
1737 svm->vmcb->control.intercept_dr_read |=
1738 nested_vmcb->control.intercept_dr_read;
1739 svm->vmcb->control.intercept_dr_write |=
1740 nested_vmcb->control.intercept_dr_write;
1741 svm->vmcb->control.intercept_exceptions |=
1742 nested_vmcb->control.intercept_exceptions;
1743
1744 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1745
1746 svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1747
1748 force_new_asid(&svm->vcpu);
1749 svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1750 svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1751 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1752 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1753 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1754 nested_vmcb->control.int_ctl);
1755 }
1756 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1757 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1758 else
1759 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1760
1761 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1762 nested_vmcb->control.exit_int_info,
1763 nested_vmcb->control.int_state);
1764
1765 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1766 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1767 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1768 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1769 nsvm_printk("Injecting Event: 0x%x\n",
1770 nested_vmcb->control.event_inj);
1771 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1772 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1773
1774 svm->vcpu.arch.hflags |= HF_GIF_MASK;
1775
1776 return 0;
1777}
1778
5542675b
AG		 1779static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1780{
1781 to_vmcb->save.fs = from_vmcb->save.fs;
1782 to_vmcb->save.gs = from_vmcb->save.gs;
1783 to_vmcb->save.tr = from_vmcb->save.tr;
1784 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1785 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1786 to_vmcb->save.star = from_vmcb->save.star;
1787 to_vmcb->save.lstar = from_vmcb->save.lstar;
1788 to_vmcb->save.cstar = from_vmcb->save.cstar;
1789 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1790 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1791 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1792 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1793
1794 return 1;
1795}
1796
1797static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1798 void *arg2, void *opaque)
1799{
1800 return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1801}
1802
1803static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1804 void *arg2, void *opaque)
1805{
1806 return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1807}
1808
1809static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1810{
1811 if (nested_svm_check_permissions(svm))
1812 return 1;
1813
1814 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1815 skip_emulated_instruction(&svm->vcpu);
1816
1817 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1818
1819 return 1;
1820}
1821
1822static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1823{
1824 if (nested_svm_check_permissions(svm))
1825 return 1;
1826
1827 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1828 skip_emulated_instruction(&svm->vcpu);
1829
1830 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1831
1832 return 1;
1833}
1834
3d6368ef
AG		 1835static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1836{
1837 nsvm_printk("VMrun\n");
1838 if (nested_svm_check_permissions(svm))
1839 return 1;
1840
1841 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1842 skip_emulated_instruction(&svm->vcpu);
1843
1844 if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1845 NULL, nested_svm_vmrun))
1846 return 1;
1847
1848 if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1849 NULL, nested_svm_vmrun_msrpm))
1850 return 1;
1851
1852 return 1;
1853}
1854
1371d904
AG		 1855static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1856{
1857 if (nested_svm_check_permissions(svm))
1858 return 1;
1859
1860 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1861 skip_emulated_instruction(&svm->vcpu);
1862
1863 svm->vcpu.arch.hflags |= HF_GIF_MASK;
1864
1865 return 1;
1866}
1867
1868static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1869{
1870 if (nested_svm_check_permissions(svm))
1871 return 1;
1872
1873 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1874 skip_emulated_instruction(&svm->vcpu);
1875
1876 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1877
1878 /* After a CLGI no interrupts should come */
1879 svm_clear_vintr(svm);
1880 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1881
1882 return 1;
1883}
1884
e756fc62
RR		 1885static int invalid_op_interception(struct vcpu_svm *svm,
1886 struct kvm_run *kvm_run)
6aa8b732 1887{
7ee5d940 1888 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 1889 return 1;
1890}
1891
e756fc62
RR		 1892static int task_switch_interception(struct vcpu_svm *svm,
1893 struct kvm_run *kvm_run)
6aa8b732 1894{
37817f29 1895 u16 tss_selector;
64a7ec06
GN		 1896 int reason;
1897 int int_type = svm->vmcb->control.exit_int_info &
1898 SVM_EXITINTINFO_TYPE_MASK;
8317c298 1899 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 1900 uint32_t type =
1901 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1902 uint32_t idt_v =
1903 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 1904
1905 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 1906
37817f29
IE		 1907 if (svm->vmcb->control.exit_info_2 &
1908 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 1909 reason = TASK_SWITCH_IRET;
1910 else if (svm->vmcb->control.exit_info_2 &
1911 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1912 reason = TASK_SWITCH_JMP;
fe8e7f83 1913 else if (idt_v)
64a7ec06
GN		 1914 reason = TASK_SWITCH_GATE;
1915 else
1916 reason = TASK_SWITCH_CALL;
1917
fe8e7f83
GN		 1918 if (reason == TASK_SWITCH_GATE) {
1919 switch (type) {
1920 case SVM_EXITINTINFO_TYPE_NMI:
1921 svm->vcpu.arch.nmi_injected = false;
1922 break;
1923 case SVM_EXITINTINFO_TYPE_EXEPT:
1924 kvm_clear_exception_queue(&svm->vcpu);
1925 break;
1926 case SVM_EXITINTINFO_TYPE_INTR:
1927 kvm_clear_interrupt_queue(&svm->vcpu);
1928 break;
1929 default:
1930 break;
1931 }
1932 }
64a7ec06 1933
8317c298
GN		 1934 if (reason != TASK_SWITCH_GATE ||
1935 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
1936 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 1937 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
1938 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 1939
1940 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 1941}
1942
e756fc62 1943static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1944{
5fdbf976 1945 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 1946 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 1947 return 1;
6aa8b732
AK		 1948}
1949
95ba8273
GN		 1950static int iret_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1951{
1952 ++svm->vcpu.stat.nmi_window_exits;
1953 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 1954 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 1955 return 1;
1956}
1957
a7052897
MT		 1958static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1959{
1960 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1961 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1962 return 1;
1963}
1964
e756fc62
RR		 1965static int emulate_on_interception(struct vcpu_svm *svm,
1966 struct kvm_run *kvm_run)
6aa8b732 1967{
3427318f 1968 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
b8688d51 1969 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 1970 return 1;
1971}
1972
1d075434
JR		 1973static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1974{
0a5fff19
GN		 1975 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
1976 /* instruction emulation calls kvm_set_cr8() */
1d075434 1977 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
95ba8273
GN		 1978 if (irqchip_in_kernel(svm->vcpu.kvm)) {
1979 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 1980 return 1;
95ba8273 1981 }
0a5fff19
GN		 1982 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
1983 return 1;
1d075434
JR		 1984 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1985 return 0;
1986}
1987
6aa8b732
AK		 1988static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1989{
a2fa3e9f
GH		 1990 struct vcpu_svm *svm = to_svm(vcpu);
1991
6aa8b732 1992 switch (ecx) {
af24a4e4 1993 case MSR_IA32_TSC: {
6aa8b732
AK		 1994 u64 tsc;
1995
1996 rdtscll(tsc);
a2fa3e9f 1997 *data = svm->vmcb->control.tsc_offset + tsc;
6aa8b732
AK		 1998 break;
1999 }
0e859cac 2000 case MSR_K6_STAR:
a2fa3e9f 2001 *data = svm->vmcb->save.star;
6aa8b732 2002 break;
0e859cac 2003#ifdef CONFIG_X86_64
6aa8b732 2004 case MSR_LSTAR:
a2fa3e9f 2005 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2006 break;
2007 case MSR_CSTAR:
a2fa3e9f 2008 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2009 break;
2010 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2011 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2012 break;
2013 case MSR_SYSCALL_MASK:
a2fa3e9f 2014 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2015 break;
2016#endif
2017 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2018 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2019 break;
2020 case MSR_IA32_SYSENTER_EIP:
017cb99e 2021 *data = svm->sysenter_eip;
6aa8b732
AK		 2022 break;
2023 case MSR_IA32_SYSENTER_ESP:
017cb99e 2024 *data = svm->sysenter_esp;
6aa8b732 2025 break;
a2938c80
JR		 2026 /* Nobody will change the following 5 values in the VMCB so
2027 we can safely return them on rdmsr. They will always be 0
2028 until LBRV is implemented. */
2029 case MSR_IA32_DEBUGCTLMSR:
2030 *data = svm->vmcb->save.dbgctl;
2031 break;
2032 case MSR_IA32_LASTBRANCHFROMIP:
2033 *data = svm->vmcb->save.br_from;
2034 break;
2035 case MSR_IA32_LASTBRANCHTOIP:
2036 *data = svm->vmcb->save.br_to;
2037 break;
2038 case MSR_IA32_LASTINTFROMIP:
2039 *data = svm->vmcb->save.last_excp_from;
2040 break;
2041 case MSR_IA32_LASTINTTOIP:
2042 *data = svm->vmcb->save.last_excp_to;
2043 break;
b286d5d8
AG		 2044 case MSR_VM_HSAVE_PA:
2045 *data = svm->hsave_msr;
2046 break;
eb6f302e
JR		 2047 case MSR_VM_CR:
2048 *data = 0;
2049 break;
c8a73f18
AG		 2050 case MSR_IA32_UCODE_REV:
2051 *data = 0x01000065;
2052 break;
6aa8b732 2053 default:
3bab1f5d 2054 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2055 }
2056 return 0;
2057}
2058
e756fc62 2059static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2060{
ad312c7c 2061 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2062 u64 data;
2063
e756fc62 2064 if (svm_get_msr(&svm->vcpu, ecx, &data))
c1a5d4f9 2065 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2066 else {
af9ca2d7
JR		 2067 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
2068 (u32)(data >> 32), handler);
2069
5fdbf976 2070 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2071 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2072 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2073 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2074 }
2075 return 1;
2076}
2077
2078static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2079{
a2fa3e9f
GH		 2080 struct vcpu_svm *svm = to_svm(vcpu);
2081
6aa8b732 2082 switch (ecx) {
af24a4e4 2083 case MSR_IA32_TSC: {
6aa8b732
AK		 2084 u64 tsc;
2085
2086 rdtscll(tsc);
a2fa3e9f 2087 svm->vmcb->control.tsc_offset = data - tsc;
6aa8b732
AK		 2088 break;
2089 }
0e859cac 2090 case MSR_K6_STAR:
a2fa3e9f 2091 svm->vmcb->save.star = data;
6aa8b732 2092 break;
49b14f24 2093#ifdef CONFIG_X86_64
6aa8b732 2094 case MSR_LSTAR:
a2fa3e9f 2095 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2096 break;
2097 case MSR_CSTAR:
a2fa3e9f 2098 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2099 break;
2100 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2101 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2102 break;
2103 case MSR_SYSCALL_MASK:
a2fa3e9f 2104 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2105 break;
2106#endif
2107 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2108 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2109 break;
2110 case MSR_IA32_SYSENTER_EIP:
017cb99e 2111 svm->sysenter_eip = data;
a2fa3e9f 2112 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2113 break;
2114 case MSR_IA32_SYSENTER_ESP:
017cb99e 2115 svm->sysenter_esp = data;
a2fa3e9f 2116 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2117 break;
a2938c80 2118 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2119 if (!svm_has(SVM_FEATURE_LBRV)) {
2120 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2121 __func__, data);
24e09cbf
JR		 2122 break;
2123 }
2124 if (data & DEBUGCTL_RESERVED_BITS)
2125 return 1;
2126
2127 svm->vmcb->save.dbgctl = data;
2128 if (data & (1ULL<<0))
2129 svm_enable_lbrv(svm);
2130 else
2131 svm_disable_lbrv(svm);
a2938c80 2132 break;
62b9abaa
JR		 2133 case MSR_K7_EVNTSEL0:
2134 case MSR_K7_EVNTSEL1:
2135 case MSR_K7_EVNTSEL2:
2136 case MSR_K7_EVNTSEL3:
14ae51b6
CL		 2137 case MSR_K7_PERFCTR0:
2138 case MSR_K7_PERFCTR1:
2139 case MSR_K7_PERFCTR2:
2140 case MSR_K7_PERFCTR3:
62b9abaa 2141 /*
14ae51b6
CL		 2142 * Just discard all writes to the performance counters; this
2143 * should keep both older linux and windows 64-bit guests
2144 * happy
62b9abaa 2145 */
14ae51b6
CL		 2146 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
2147
b286d5d8
AG		 2148 break;
2149 case MSR_VM_HSAVE_PA:
2150 svm->hsave_msr = data;
62b9abaa 2151 break;
6aa8b732 2152 default:
3bab1f5d 2153 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2154 }
2155 return 0;
2156}
2157
e756fc62 2158static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2159{
ad312c7c 2160 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2161 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2162 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7
JR		 2163
2164 KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
2165 handler);
2166
5fdbf976 2167 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2168 if (svm_set_msr(&svm->vcpu, ecx, data))
c1a5d4f9 2169 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2170 else
e756fc62 2171 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2172 return 1;
2173}
2174
e756fc62 2175static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2176{
e756fc62
RR		 2177 if (svm->vmcb->control.exit_info_1)
2178 return wrmsr_interception(svm, kvm_run);
6aa8b732 2179 else
e756fc62 2180 return rdmsr_interception(svm, kvm_run);
6aa8b732
AK		 2181}
2182
e756fc62 2183static int interrupt_window_interception(struct vcpu_svm *svm,
c1150d8c
DL		 2184 struct kvm_run *kvm_run)
2185{
af9ca2d7
JR		 2186 KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
2187
f0b85051 2188 svm_clear_vintr(svm);
85f455f7 2189 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2190 /*
2191 * If the user space waits to inject interrupts, exit as soon as
2192 * possible
2193 */
8061823a
GN		 2194 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2195 kvm_run->request_interrupt_window &&
2196 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2197 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2198 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2199 return 0;
2200 }
2201
2202 return 1;
2203}
2204
e756fc62 2205static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
6aa8b732
AK		 2206 struct kvm_run *kvm_run) = {
2207 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2208 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2209 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2210 [SVM_EXIT_READ_CR8] = emulate_on_interception,
6aa8b732
AK		 2211 /* for now: */
2212 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2213 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2214 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2215 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2216 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2217 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2218 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2219 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2220 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2221 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2222 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2223 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2224 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2225 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2226 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2227 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2228 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2229 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2230 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2231 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2232 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2233 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2234 [SVM_EXIT_SMI] = nop_on_interception,
2235 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2236 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2237 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2238 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2239 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2240 [SVM_EXIT_INVD] = emulate_on_interception,
6aa8b732 2241 [SVM_EXIT_HLT] = halt_interception,
a7052897 2242 [SVM_EXIT_INVLPG] = invlpg_interception,
6aa8b732
AK		 2243 [SVM_EXIT_INVLPGA] = invalid_op_interception,
2244 [SVM_EXIT_IOIO] = io_interception,
2245 [SVM_EXIT_MSR] = msr_interception,
2246 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2247 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2248 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2249 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2250 [SVM_EXIT_VMLOAD] = vmload_interception,
2251 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2252 [SVM_EXIT_STGI] = stgi_interception,
2253 [SVM_EXIT_CLGI] = clgi_interception,
6aa8b732 2254 [SVM_EXIT_SKINIT] = invalid_op_interception,
cf5a94d1 2255 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2256 [SVM_EXIT_MONITOR] = invalid_op_interception,
2257 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2258 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2259};
2260
04d2cc77 2261static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
6aa8b732 2262{
04d2cc77 2263 struct vcpu_svm *svm = to_svm(vcpu);
a2fa3e9f 2264 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2265
af9ca2d7
JR		 2266 KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
2267 (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
2268
cf74a78b
AG		 2269 if (is_nested(svm)) {
2270 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2271 exit_code, svm->vmcb->control.exit_info_1,
2272 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2273 if (nested_svm_exit_handled(svm, true)) {
2274 nested_svm_vmexit(svm);
2275 nsvm_printk("-> #VMEXIT\n");
2276 return 1;
2277 }
2278 }
2279
709ddebf
JR		 2280 if (npt_enabled) {
2281 int mmu_reload = 0;
2282 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2283 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2284 mmu_reload = 1;
2285 }
2286 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2287 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2288 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2289 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
2290 kvm_inject_gp(vcpu, 0);
2291 return 1;
2292 }
2293 }
2294 if (mmu_reload) {
2295 kvm_mmu_reset_context(vcpu);
2296 kvm_mmu_load(vcpu);
2297 }
2298 }
2299
04d2cc77
AK		 2300
2301 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2302 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2303 kvm_run->fail_entry.hardware_entry_failure_reason
2304 = svm->vmcb->control.exit_code;
2305 return 0;
2306 }
2307
a2fa3e9f 2308 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2309 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2310 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2311 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2312 "exit_code 0x%x\n",
b8688d51 2313 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2314 exit_code);
2315
9d8f549d 2316 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2317 || !svm_exit_handlers[exit_code]) {
6aa8b732 2318 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2319 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2320 return 0;
2321 }
2322
e756fc62 2323 return svm_exit_handlers[exit_code](svm, kvm_run);
6aa8b732
AK		 2324}
2325
2326static void reload_tss(struct kvm_vcpu *vcpu)
2327{
2328 int cpu = raw_smp_processor_id();
2329
2330 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
d77c26fc 2331 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2332 load_TR_desc();
2333}
2334
e756fc62 2335static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2336{
2337 int cpu = raw_smp_processor_id();
2338
2339 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2340
a2fa3e9f 2341 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12
MT		 2342 /* FIXME: handle wraparound of asid_generation */
2343 if (svm->asid_generation != svm_data->asid_generation)
e756fc62 2344 new_asid(svm, svm_data);
6aa8b732
AK		 2345}
2346
95ba8273
GN		 2347static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2348{
2349 struct vcpu_svm *svm = to_svm(vcpu);
2350
2351 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2352 vcpu->arch.hflags |= HF_NMI_MASK;
2353 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2354 ++vcpu->stat.nmi_injections;
2355}
6aa8b732 2356
85f455f7 2357static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2358{
2359 struct vmcb_control_area *control;
2360
af9ca2d7
JR		 2361 KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
2362
fa89a817 2363 ++svm->vcpu.stat.irq_injections;
e756fc62 2364 control = &svm->vmcb->control;
85f455f7 2365 control->int_vector = irq;
6aa8b732
AK		 2366 control->int_ctl &= ~V_INTR_PRIO_MASK;
2367 control->int_ctl |= V_IRQ_MASK |
2368 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2369}
2370
95ba8273 2371static void svm_queue_irq(struct kvm_vcpu *vcpu, unsigned nr)
9222be18 2372{
95ba8273
GN		 2373 struct vcpu_svm *svm = to_svm(vcpu);
2374
9222be18
GN		 2375 svm->vmcb->control.event_inj = nr |
2376 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2377}
2378
66fd3f7f 2379static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2380{
2381 struct vcpu_svm *svm = to_svm(vcpu);
2382
cf74a78b
AG		 2383 nested_svm_intr(svm);
2384
66fd3f7f 2385 svm_queue_irq(vcpu, vcpu->arch.interrupt.nr);
2a8067f1
ED		 2386}
2387
95ba8273 2388static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2389{
2390 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2391
95ba8273 2392 if (irr == -1)
aaacfc9a
JR		 2393 return;
2394
95ba8273
GN		 2395 if (tpr >= irr)
2396 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2397}
aaacfc9a 2398
95ba8273
GN		 2399static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2400{
2401 struct vcpu_svm *svm = to_svm(vcpu);
2402 struct vmcb *vmcb = svm->vmcb;
2403 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2404 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2405}
2406
78646121
GN		 2407static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2408{
2409 struct vcpu_svm *svm = to_svm(vcpu);
2410 struct vmcb *vmcb = svm->vmcb;
2411 return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2412 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2413 (svm->vcpu.arch.hflags & HF_GIF_MASK);
2414}
2415
9222be18 2416static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2417{
9222be18
GN		 2418 svm_set_vintr(to_svm(vcpu));
2419 svm_inject_irq(to_svm(vcpu), 0x0);
85f455f7
ED		 2420}
2421
95ba8273 2422static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2423{
04d2cc77 2424 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2425
44c11430
GN		 2426 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2427 == HF_NMI_MASK)
2428 return; /* IRET will cause a vm exit */
2429
2430 /* Something prevents NMI from been injected. Single step over
2431 possible problem (IRET or exception injection or interrupt
2432 shadow) */
2433 vcpu->arch.singlestep = true;
2434 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2435 update_db_intercept(vcpu);
c1150d8c
DL		 2436}
2437
cbc94022
IE		 2438static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2439{
2440 return 0;
2441}
2442
d9e368d6
AK		 2443static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2444{
2445 force_new_asid(vcpu);
2446}
2447
04d2cc77
AK		 2448static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2449{
2450}
2451
d7bf8221
JR		 2452static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2453{
2454 struct vcpu_svm *svm = to_svm(vcpu);
2455
2456 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2457 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2458 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2459 }
2460}
2461
649d6864
JR		 2462static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2463{
2464 struct vcpu_svm *svm = to_svm(vcpu);
2465 u64 cr8;
2466
649d6864
JR		 2467 cr8 = kvm_get_cr8(vcpu);
2468 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2469 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2470}
2471
9222be18
GN		 2472static void svm_complete_interrupts(struct vcpu_svm *svm)
2473{
2474 u8 vector;
2475 int type;
2476 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2477
44c11430
GN		 2478 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2479 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2480
9222be18
GN		 2481 svm->vcpu.arch.nmi_injected = false;
2482 kvm_clear_exception_queue(&svm->vcpu);
2483 kvm_clear_interrupt_queue(&svm->vcpu);
2484
2485 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2486 return;
2487
2488 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2489 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2490
2491 switch (type) {
2492 case SVM_EXITINTINFO_TYPE_NMI:
2493 svm->vcpu.arch.nmi_injected = true;
2494 break;
2495 case SVM_EXITINTINFO_TYPE_EXEPT:
2496 /* In case of software exception do not reinject an exception
2497 vector, but re-execute and instruction instead */
66fd3f7f 2498 if (kvm_exception_is_soft(vector))
9222be18
GN		 2499 break;
2500 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2501 u32 err = svm->vmcb->control.exit_int_info_err;
2502 kvm_queue_exception_e(&svm->vcpu, vector, err);
2503
2504 } else
2505 kvm_queue_exception(&svm->vcpu, vector);
2506 break;
2507 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2508 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2509 break;
2510 default:
2511 break;
2512 }
2513}
2514
80e31d4f
AK		 2515#ifdef CONFIG_X86_64
2516#define R "r"
2517#else
2518#define R "e"
2519#endif
2520
04d2cc77 2521static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2522{
a2fa3e9f 2523 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2524 u16 fs_selector;
2525 u16 gs_selector;
2526 u16 ldt_selector;
d9e368d6 2527
5fdbf976
MT		 2528 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2529 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2530 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2531
e756fc62 2532 pre_svm_run(svm);
6aa8b732 2533
649d6864
JR		 2534 sync_lapic_to_cr8(vcpu);
2535
6aa8b732 2536 save_host_msrs(vcpu);
d6e88aec
AK		 2537 fs_selector = kvm_read_fs();
2538 gs_selector = kvm_read_gs();
2539 ldt_selector = kvm_read_ldt();
a2fa3e9f 2540 svm->host_cr2 = kvm_read_cr2();
3d6368ef
AG		 2541 if (!is_nested(svm))
2542 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2543 /* required for live migration with NPT */
2544 if (npt_enabled)
2545 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2546
04d2cc77
AK		 2547 clgi();
2548
2549 local_irq_enable();
36241b8c 2550
6aa8b732 2551 asm volatile (
80e31d4f
AK		 2552 "push %%"R"bp; \n\t"
2553 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2554 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2555 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2556 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2557 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2558 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2559#ifdef CONFIG_X86_64
fb3f0f51
RR		 2560 "mov %c[r8](%[svm]), %%r8 \n\t"
2561 "mov %c[r9](%[svm]), %%r9 \n\t"
2562 "mov %c[r10](%[svm]), %%r10 \n\t"
2563 "mov %c[r11](%[svm]), %%r11 \n\t"
2564 "mov %c[r12](%[svm]), %%r12 \n\t"
2565 "mov %c[r13](%[svm]), %%r13 \n\t"
2566 "mov %c[r14](%[svm]), %%r14 \n\t"
2567 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2568#endif
2569
6aa8b732 2570 /* Enter guest mode */
80e31d4f
AK		 2571 "push %%"R"ax \n\t"
2572 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2573 __ex(SVM_VMLOAD) "\n\t"
2574 __ex(SVM_VMRUN) "\n\t"
2575 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2576 "pop %%"R"ax \n\t"
6aa8b732
AK		 2577
2578 /* Save guest registers, load host registers */
80e31d4f
AK		 2579 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2580 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2581 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2582 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2583 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2584 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2585#ifdef CONFIG_X86_64
fb3f0f51
RR		 2586 "mov %%r8, %c[r8](%[svm]) \n\t"
2587 "mov %%r9, %c[r9](%[svm]) \n\t"
2588 "mov %%r10, %c[r10](%[svm]) \n\t"
2589 "mov %%r11, %c[r11](%[svm]) \n\t"
2590 "mov %%r12, %c[r12](%[svm]) \n\t"
2591 "mov %%r13, %c[r13](%[svm]) \n\t"
2592 "mov %%r14, %c[r14](%[svm]) \n\t"
2593 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2594#endif
80e31d4f 2595 "pop %%"R"bp"
6aa8b732 2596 :
fb3f0f51 2597 : [svm]"a"(svm),
6aa8b732 2598 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2599 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2600 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2601 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2602 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2603 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2604 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2605#ifdef CONFIG_X86_64
ad312c7c
ZX		 2606 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2607 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2608 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2609 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2610 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2611 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2612 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2613 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2614#endif
54a08c04 2615 : "cc", "memory"
80e31d4f 2616 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2617#ifdef CONFIG_X86_64
54a08c04
LV		 2618 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2619#endif
2620 );
6aa8b732 2621
ad312c7c 2622 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2623 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2624 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2625 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2626
a2fa3e9f 2627 kvm_write_cr2(svm->host_cr2);
6aa8b732 2628
d6e88aec
AK		 2629 kvm_load_fs(fs_selector);
2630 kvm_load_gs(gs_selector);
2631 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2632 load_host_msrs(vcpu);
2633
2634 reload_tss(vcpu);
2635
56ba47dd
AK		 2636 local_irq_disable();
2637
2638 stgi();
2639
d7bf8221
JR		 2640 sync_cr8_to_lapic(vcpu);
2641
a2fa3e9f 2642 svm->next_rip = 0;
9222be18
GN		 2643
2644 svm_complete_interrupts(svm);
6aa8b732
AK		 2645}
2646
80e31d4f
AK		 2647#undef R
2648
6aa8b732
AK		 2649static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2650{
a2fa3e9f
GH		 2651 struct vcpu_svm *svm = to_svm(vcpu);
2652
709ddebf
JR		 2653 if (npt_enabled) {
2654 svm->vmcb->control.nested_cr3 = root;
2655 force_new_asid(vcpu);
2656 return;
2657 }
2658
a2fa3e9f 2659 svm->vmcb->save.cr3 = root;
6aa8b732 2660 force_new_asid(vcpu);
7807fa6c
AL		 2661
2662 if (vcpu->fpu_active) {
a2fa3e9f
GH		 2663 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2664 svm->vmcb->save.cr0 |= X86_CR0_TS;
7807fa6c
AL		 2665 vcpu->fpu_active = 0;
2666 }
6aa8b732
AK		 2667}
2668
6aa8b732
AK		 2669static int is_disabled(void)
2670{
6031a61c
JR		 2671 u64 vm_cr;
2672
2673 rdmsrl(MSR_VM_CR, vm_cr);
2674 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2675 return 1;
2676
6aa8b732
AK		 2677 return 0;
2678}
2679
102d8325
IM		 2680static void
2681svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2682{
2683 /*
2684 * Patch in the VMMCALL instruction:
2685 */
2686 hypercall[0] = 0x0f;
2687 hypercall[1] = 0x01;
2688 hypercall[2] = 0xd9;
102d8325
IM		 2689}
2690
002c7f7c
YS		 2691static void svm_check_processor_compat(void *rtn)
2692{
2693 *(int *)rtn = 0;
2694}
2695
774ead3a
AK		 2696static bool svm_cpu_has_accelerated_tpr(void)
2697{
2698 return false;
2699}
2700
67253af5
SY		 2701static int get_npt_level(void)
2702{
2703#ifdef CONFIG_X86_64
2704 return PT64_ROOT_LEVEL;
2705#else
2706 return PT32E_ROOT_LEVEL;
2707#endif
2708}
2709
4b12f0de 2710static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 2711{
2712 return 0;
2713}
2714
cbdd1bea 2715static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 2716 .cpu_has_kvm_support = has_svm,
2717 .disabled_by_bios = is_disabled,
2718 .hardware_setup = svm_hardware_setup,
2719 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 2720 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 2721 .hardware_enable = svm_hardware_enable,
2722 .hardware_disable = svm_hardware_disable,
774ead3a 2723 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 2724
2725 .vcpu_create = svm_create_vcpu,
2726 .vcpu_free = svm_free_vcpu,
04d2cc77 2727 .vcpu_reset = svm_vcpu_reset,
6aa8b732 2728
04d2cc77 2729 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 2730 .vcpu_load = svm_vcpu_load,
2731 .vcpu_put = svm_vcpu_put,
2732
2733 .set_guest_debug = svm_guest_debug,
2734 .get_msr = svm_get_msr,
2735 .set_msr = svm_set_msr,
2736 .get_segment_base = svm_get_segment_base,
2737 .get_segment = svm_get_segment,
2738 .set_segment = svm_set_segment,
2e4d2653 2739 .get_cpl = svm_get_cpl,
1747fb71 2740 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
25c4c276 2741 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 2742 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 2743 .set_cr3 = svm_set_cr3,
2744 .set_cr4 = svm_set_cr4,
2745 .set_efer = svm_set_efer,
2746 .get_idt = svm_get_idt,
2747 .set_idt = svm_set_idt,
2748 .get_gdt = svm_get_gdt,
2749 .set_gdt = svm_set_gdt,
2750 .get_dr = svm_get_dr,
2751 .set_dr = svm_set_dr,
6aa8b732
AK		 2752 .get_rflags = svm_get_rflags,
2753 .set_rflags = svm_set_rflags,
2754
6aa8b732 2755 .tlb_flush = svm_flush_tlb,
6aa8b732 2756
6aa8b732 2757 .run = svm_vcpu_run,
04d2cc77 2758 .handle_exit = handle_exit,
6aa8b732 2759 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 2760 .set_interrupt_shadow = svm_set_interrupt_shadow,
2761 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 2762 .patch_hypercall = svm_patch_hypercall,
2a8067f1 2763 .set_irq = svm_set_irq,
95ba8273 2764 .set_nmi = svm_inject_nmi,
298101da 2765 .queue_exception = svm_queue_exception,
78646121 2766 .interrupt_allowed = svm_interrupt_allowed,
95ba8273
GN		 2767 .nmi_allowed = svm_nmi_allowed,
2768 .enable_nmi_window = enable_nmi_window,
2769 .enable_irq_window = enable_irq_window,
2770 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 2771
2772 .set_tss_addr = svm_set_tss_addr,
67253af5 2773 .get_tdp_level = get_npt_level,
4b12f0de 2774 .get_mt_mask = svm_get_mt_mask,
6aa8b732
AK		 2775};
2776
2777static int __init svm_init(void)
2778{
cb498ea2 2779 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 2780 THIS_MODULE);
6aa8b732
AK		 2781}
2782
2783static void __exit svm_exit(void)
2784{
cb498ea2 2785 kvm_exit();
6aa8b732
AK		 2786}
2787
2788module_init(svm_init)
2789module_exit(svm_exit)
kernel source for telekom puls (alcatel/mediatek)