Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
edf88417 AK |
16 | #include <linux/kvm_host.h> |
17 | ||
e495606d | 18 | #include "kvm_svm.h" |
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
e495606d | 21 | |
6aa8b732 | 22 | #include <linux/module.h> |
9d8f549d | 23 | #include <linux/kernel.h> |
6aa8b732 AK |
24 | #include <linux/vmalloc.h> |
25 | #include <linux/highmem.h> | |
e8edc6e0 | 26 | #include <linux/sched.h> |
6aa8b732 | 27 | |
e495606d | 28 | #include <asm/desc.h> |
6aa8b732 AK |
29 | |
30 | MODULE_AUTHOR("Qumranet"); | |
31 | MODULE_LICENSE("GPL"); | |
32 | ||
33 | #define IOPM_ALLOC_ORDER 2 | |
34 | #define MSRPM_ALLOC_ORDER 1 | |
35 | ||
36 | #define DB_VECTOR 1 | |
37 | #define UD_VECTOR 6 | |
38 | #define GP_VECTOR 13 | |
39 | ||
40 | #define DR7_GD_MASK (1 << 13) | |
41 | #define DR6_BD_MASK (1 << 13) | |
6aa8b732 AK |
42 | |
43 | #define SEG_TYPE_LDT 2 | |
44 | #define SEG_TYPE_BUSY_TSS16 3 | |
45 | ||
80b7706e JR |
46 | #define SVM_FEATURE_NPT (1 << 0) |
47 | #define SVM_FEATURE_LBRV (1 << 1) | |
48 | #define SVM_DEATURE_SVML (1 << 2) | |
49 | ||
e3da3acd | 50 | static bool npt_enabled = false; |
6c7dac72 JR |
51 | static int npt = 1; |
52 | ||
53 | module_param(npt, int, S_IRUGO); | |
e3da3acd | 54 | |
04d2cc77 AK |
55 | static void kvm_reput_irq(struct vcpu_svm *svm); |
56 | ||
a2fa3e9f GH |
57 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
58 | { | |
fb3f0f51 | 59 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
60 | } |
61 | ||
6aa8b732 AK |
62 | unsigned long iopm_base; |
63 | unsigned long msrpm_base; | |
64 | ||
65 | struct kvm_ldttss_desc { | |
66 | u16 limit0; | |
67 | u16 base0; | |
68 | unsigned base1 : 8, type : 5, dpl : 2, p : 1; | |
69 | unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; | |
70 | u32 base3; | |
71 | u32 zero1; | |
72 | } __attribute__((packed)); | |
73 | ||
74 | struct svm_cpu_data { | |
75 | int cpu; | |
76 | ||
5008fdf5 AK |
77 | u64 asid_generation; |
78 | u32 max_asid; | |
79 | u32 next_asid; | |
6aa8b732 AK |
80 | struct kvm_ldttss_desc *tss_desc; |
81 | ||
82 | struct page *save_area; | |
83 | }; | |
84 | ||
85 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 86 | static uint32_t svm_features; |
6aa8b732 AK |
87 | |
88 | struct svm_init_data { | |
89 | int cpu; | |
90 | int r; | |
91 | }; | |
92 | ||
93 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
94 | ||
9d8f549d | 95 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
96 | #define MSRS_RANGE_SIZE 2048 |
97 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
98 | ||
99 | #define MAX_INST_SIZE 15 | |
100 | ||
80b7706e JR |
101 | static inline u32 svm_has(u32 feat) |
102 | { | |
103 | return svm_features & feat; | |
104 | } | |
105 | ||
6aa8b732 AK |
106 | static inline u8 pop_irq(struct kvm_vcpu *vcpu) |
107 | { | |
ad312c7c ZX |
108 | int word_index = __ffs(vcpu->arch.irq_summary); |
109 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
6aa8b732 AK |
110 | int irq = word_index * BITS_PER_LONG + bit_index; |
111 | ||
ad312c7c ZX |
112 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
113 | if (!vcpu->arch.irq_pending[word_index]) | |
114 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
115 | return irq; |
116 | } | |
117 | ||
118 | static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq) | |
119 | { | |
ad312c7c ZX |
120 | set_bit(irq, vcpu->arch.irq_pending); |
121 | set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
122 | } |
123 | ||
124 | static inline void clgi(void) | |
125 | { | |
126 | asm volatile (SVM_CLGI); | |
127 | } | |
128 | ||
129 | static inline void stgi(void) | |
130 | { | |
131 | asm volatile (SVM_STGI); | |
132 | } | |
133 | ||
134 | static inline void invlpga(unsigned long addr, u32 asid) | |
135 | { | |
136 | asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid)); | |
137 | } | |
138 | ||
139 | static inline unsigned long kvm_read_cr2(void) | |
140 | { | |
141 | unsigned long cr2; | |
142 | ||
143 | asm volatile ("mov %%cr2, %0" : "=r" (cr2)); | |
144 | return cr2; | |
145 | } | |
146 | ||
147 | static inline void kvm_write_cr2(unsigned long val) | |
148 | { | |
149 | asm volatile ("mov %0, %%cr2" :: "r" (val)); | |
150 | } | |
151 | ||
152 | static inline unsigned long read_dr6(void) | |
153 | { | |
154 | unsigned long dr6; | |
155 | ||
156 | asm volatile ("mov %%dr6, %0" : "=r" (dr6)); | |
157 | return dr6; | |
158 | } | |
159 | ||
160 | static inline void write_dr6(unsigned long val) | |
161 | { | |
162 | asm volatile ("mov %0, %%dr6" :: "r" (val)); | |
163 | } | |
164 | ||
165 | static inline unsigned long read_dr7(void) | |
166 | { | |
167 | unsigned long dr7; | |
168 | ||
169 | asm volatile ("mov %%dr7, %0" : "=r" (dr7)); | |
170 | return dr7; | |
171 | } | |
172 | ||
173 | static inline void write_dr7(unsigned long val) | |
174 | { | |
175 | asm volatile ("mov %0, %%dr7" :: "r" (val)); | |
176 | } | |
177 | ||
6aa8b732 AK |
178 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
179 | { | |
a2fa3e9f | 180 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
181 | } |
182 | ||
183 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
184 | { | |
185 | force_new_asid(vcpu); | |
186 | } | |
187 | ||
188 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
189 | { | |
2b5203ee CMAB |
190 | if (!(efer & EFER_LMA)) |
191 | efer &= ~EFER_LME; | |
6aa8b732 | 192 | |
a2fa3e9f | 193 | to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK; |
ad312c7c | 194 | vcpu->arch.shadow_efer = efer; |
6aa8b732 AK |
195 | } |
196 | ||
298101da AK |
197 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
198 | bool has_error_code, u32 error_code) | |
199 | { | |
200 | struct vcpu_svm *svm = to_svm(vcpu); | |
201 | ||
202 | svm->vmcb->control.event_inj = nr | |
203 | | SVM_EVTINJ_VALID | |
204 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
205 | | SVM_EVTINJ_TYPE_EXEPT; | |
206 | svm->vmcb->control.event_inj_err = error_code; | |
207 | } | |
208 | ||
209 | static bool svm_exception_injected(struct kvm_vcpu *vcpu) | |
210 | { | |
211 | struct vcpu_svm *svm = to_svm(vcpu); | |
212 | ||
213 | return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID); | |
214 | } | |
215 | ||
6aa8b732 AK |
216 | static int is_external_interrupt(u32 info) |
217 | { | |
218 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
219 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
220 | } | |
221 | ||
222 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
223 | { | |
a2fa3e9f GH |
224 | struct vcpu_svm *svm = to_svm(vcpu); |
225 | ||
226 | if (!svm->next_rip) { | |
6aa8b732 AK |
227 | printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__); |
228 | return; | |
229 | } | |
d77c26fc | 230 | if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE) |
6aa8b732 AK |
231 | printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n", |
232 | __FUNCTION__, | |
a2fa3e9f GH |
233 | svm->vmcb->save.rip, |
234 | svm->next_rip); | |
6aa8b732 | 235 | |
ad312c7c | 236 | vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip; |
a2fa3e9f | 237 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; |
c1150d8c | 238 | |
ad312c7c | 239 | vcpu->arch.interrupt_window_open = 1; |
6aa8b732 AK |
240 | } |
241 | ||
242 | static int has_svm(void) | |
243 | { | |
244 | uint32_t eax, ebx, ecx, edx; | |
245 | ||
1e885461 | 246 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { |
6aa8b732 AK |
247 | printk(KERN_INFO "has_svm: not amd\n"); |
248 | return 0; | |
249 | } | |
250 | ||
251 | cpuid(0x80000000, &eax, &ebx, &ecx, &edx); | |
252 | if (eax < SVM_CPUID_FUNC) { | |
253 | printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n"); | |
254 | return 0; | |
255 | } | |
256 | ||
257 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
258 | if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) { | |
259 | printk(KERN_DEBUG "has_svm: svm not available\n"); | |
260 | return 0; | |
261 | } | |
262 | return 1; | |
263 | } | |
264 | ||
265 | static void svm_hardware_disable(void *garbage) | |
266 | { | |
267 | struct svm_cpu_data *svm_data | |
268 | = per_cpu(svm_data, raw_smp_processor_id()); | |
269 | ||
270 | if (svm_data) { | |
271 | uint64_t efer; | |
272 | ||
273 | wrmsrl(MSR_VM_HSAVE_PA, 0); | |
274 | rdmsrl(MSR_EFER, efer); | |
275 | wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK); | |
8b6d44c7 | 276 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; |
6aa8b732 AK |
277 | __free_page(svm_data->save_area); |
278 | kfree(svm_data); | |
279 | } | |
280 | } | |
281 | ||
282 | static void svm_hardware_enable(void *garbage) | |
283 | { | |
284 | ||
285 | struct svm_cpu_data *svm_data; | |
286 | uint64_t efer; | |
05b3e0c2 | 287 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
288 | struct desc_ptr gdt_descr; |
289 | #else | |
6b68f01b | 290 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
291 | #endif |
292 | struct desc_struct *gdt; | |
293 | int me = raw_smp_processor_id(); | |
294 | ||
295 | if (!has_svm()) { | |
296 | printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me); | |
297 | return; | |
298 | } | |
299 | svm_data = per_cpu(svm_data, me); | |
300 | ||
301 | if (!svm_data) { | |
302 | printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n", | |
303 | me); | |
304 | return; | |
305 | } | |
306 | ||
307 | svm_data->asid_generation = 1; | |
308 | svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
309 | svm_data->next_asid = svm_data->max_asid + 1; | |
310 | ||
d77c26fc | 311 | asm volatile ("sgdt %0" : "=m"(gdt_descr)); |
6aa8b732 AK |
312 | gdt = (struct desc_struct *)gdt_descr.address; |
313 | svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); | |
314 | ||
315 | rdmsrl(MSR_EFER, efer); | |
316 | wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK); | |
317 | ||
318 | wrmsrl(MSR_VM_HSAVE_PA, | |
319 | page_to_pfn(svm_data->save_area) << PAGE_SHIFT); | |
320 | } | |
321 | ||
322 | static int svm_cpu_init(int cpu) | |
323 | { | |
324 | struct svm_cpu_data *svm_data; | |
325 | int r; | |
326 | ||
327 | svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); | |
328 | if (!svm_data) | |
329 | return -ENOMEM; | |
330 | svm_data->cpu = cpu; | |
331 | svm_data->save_area = alloc_page(GFP_KERNEL); | |
332 | r = -ENOMEM; | |
333 | if (!svm_data->save_area) | |
334 | goto err_1; | |
335 | ||
336 | per_cpu(svm_data, cpu) = svm_data; | |
337 | ||
338 | return 0; | |
339 | ||
340 | err_1: | |
341 | kfree(svm_data); | |
342 | return r; | |
343 | ||
344 | } | |
345 | ||
bfc733a7 RR |
346 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
347 | int read, int write) | |
6aa8b732 AK |
348 | { |
349 | int i; | |
350 | ||
351 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
352 | if (msr >= msrpm_ranges[i] && | |
353 | msr < msrpm_ranges[i] + MSRS_IN_RANGE) { | |
354 | u32 msr_offset = (i * MSRS_IN_RANGE + msr - | |
355 | msrpm_ranges[i]) * 2; | |
356 | ||
357 | u32 *base = msrpm + (msr_offset / 32); | |
358 | u32 msr_shift = msr_offset % 32; | |
359 | u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); | |
360 | *base = (*base & ~(0x3 << msr_shift)) | | |
361 | (mask << msr_shift); | |
bfc733a7 | 362 | return; |
6aa8b732 AK |
363 | } |
364 | } | |
bfc733a7 | 365 | BUG(); |
6aa8b732 AK |
366 | } |
367 | ||
368 | static __init int svm_hardware_setup(void) | |
369 | { | |
370 | int cpu; | |
371 | struct page *iopm_pages; | |
372 | struct page *msrpm_pages; | |
c8681339 | 373 | void *iopm_va, *msrpm_va; |
6aa8b732 AK |
374 | int r; |
375 | ||
6aa8b732 AK |
376 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
377 | ||
378 | if (!iopm_pages) | |
379 | return -ENOMEM; | |
c8681339 AL |
380 | |
381 | iopm_va = page_address(iopm_pages); | |
382 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
383 | clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */ | |
6aa8b732 AK |
384 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
385 | ||
386 | ||
387 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
388 | ||
389 | r = -ENOMEM; | |
390 | if (!msrpm_pages) | |
391 | goto err_1; | |
392 | ||
393 | msrpm_va = page_address(msrpm_pages); | |
394 | memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
395 | msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT; | |
396 | ||
05b3e0c2 | 397 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
398 | set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1); |
399 | set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1); | |
400 | set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1); | |
6aa8b732 AK |
401 | set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1); |
402 | set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1); | |
403 | set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1); | |
404 | #endif | |
0e859cac | 405 | set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1); |
6aa8b732 AK |
406 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1); |
407 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1); | |
408 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1); | |
409 | ||
50a37eb4 JR |
410 | if (boot_cpu_has(X86_FEATURE_NX)) |
411 | kvm_enable_efer_bits(EFER_NX); | |
412 | ||
6aa8b732 AK |
413 | for_each_online_cpu(cpu) { |
414 | r = svm_cpu_init(cpu); | |
415 | if (r) | |
416 | goto err_2; | |
417 | } | |
33bd6a0b JR |
418 | |
419 | svm_features = cpuid_edx(SVM_CPUID_FUNC); | |
420 | ||
e3da3acd JR |
421 | if (!svm_has(SVM_FEATURE_NPT)) |
422 | npt_enabled = false; | |
423 | ||
6c7dac72 JR |
424 | if (npt_enabled && !npt) { |
425 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
426 | npt_enabled = false; | |
427 | } | |
428 | ||
e3da3acd JR |
429 | if (npt_enabled) |
430 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); | |
431 | ||
6aa8b732 AK |
432 | return 0; |
433 | ||
434 | err_2: | |
435 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
436 | msrpm_base = 0; | |
437 | err_1: | |
438 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); | |
439 | iopm_base = 0; | |
440 | return r; | |
441 | } | |
442 | ||
443 | static __exit void svm_hardware_unsetup(void) | |
444 | { | |
445 | __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER); | |
446 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); | |
447 | iopm_base = msrpm_base = 0; | |
448 | } | |
449 | ||
450 | static void init_seg(struct vmcb_seg *seg) | |
451 | { | |
452 | seg->selector = 0; | |
453 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
454 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
455 | seg->limit = 0xffff; | |
456 | seg->base = 0; | |
457 | } | |
458 | ||
459 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
460 | { | |
461 | seg->selector = 0; | |
462 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
463 | seg->limit = 0xffff; | |
464 | seg->base = 0; | |
465 | } | |
466 | ||
6aa8b732 AK |
467 | static void init_vmcb(struct vmcb *vmcb) |
468 | { | |
469 | struct vmcb_control_area *control = &vmcb->control; | |
470 | struct vmcb_save_area *save = &vmcb->save; | |
6aa8b732 AK |
471 | |
472 | control->intercept_cr_read = INTERCEPT_CR0_MASK | | |
473 | INTERCEPT_CR3_MASK | | |
80a8119c AK |
474 | INTERCEPT_CR4_MASK | |
475 | INTERCEPT_CR8_MASK; | |
6aa8b732 AK |
476 | |
477 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
478 | INTERCEPT_CR3_MASK | | |
80a8119c AK |
479 | INTERCEPT_CR4_MASK | |
480 | INTERCEPT_CR8_MASK; | |
6aa8b732 AK |
481 | |
482 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
483 | INTERCEPT_DR1_MASK | | |
484 | INTERCEPT_DR2_MASK | | |
485 | INTERCEPT_DR3_MASK; | |
486 | ||
487 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
488 | INTERCEPT_DR1_MASK | | |
489 | INTERCEPT_DR2_MASK | | |
490 | INTERCEPT_DR3_MASK | | |
491 | INTERCEPT_DR5_MASK | | |
492 | INTERCEPT_DR7_MASK; | |
493 | ||
7aa81cc0 AL |
494 | control->intercept_exceptions = (1 << PF_VECTOR) | |
495 | (1 << UD_VECTOR); | |
6aa8b732 AK |
496 | |
497 | ||
498 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
499 | (1ULL << INTERCEPT_NMI) | | |
0152527b | 500 | (1ULL << INTERCEPT_SMI) | |
6aa8b732 AK |
501 | /* |
502 | * selective cr0 intercept bug? | |
503 | * 0: 0f 22 d8 mov %eax,%cr3 | |
504 | * 3: 0f 20 c0 mov %cr0,%eax | |
505 | * 6: 0d 00 00 00 80 or $0x80000000,%eax | |
506 | * b: 0f 22 c0 mov %eax,%cr0 | |
507 | * set cr3 ->interception | |
508 | * get cr0 ->interception | |
509 | * set cr0 -> no interception | |
510 | */ | |
511 | /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */ | |
512 | (1ULL << INTERCEPT_CPUID) | | |
cf5a94d1 | 513 | (1ULL << INTERCEPT_INVD) | |
6aa8b732 | 514 | (1ULL << INTERCEPT_HLT) | |
6aa8b732 AK |
515 | (1ULL << INTERCEPT_INVLPGA) | |
516 | (1ULL << INTERCEPT_IOIO_PROT) | | |
517 | (1ULL << INTERCEPT_MSR_PROT) | | |
518 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 519 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
520 | (1ULL << INTERCEPT_VMRUN) | |
521 | (1ULL << INTERCEPT_VMMCALL) | | |
522 | (1ULL << INTERCEPT_VMLOAD) | | |
523 | (1ULL << INTERCEPT_VMSAVE) | | |
524 | (1ULL << INTERCEPT_STGI) | | |
525 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 | 526 | (1ULL << INTERCEPT_SKINIT) | |
cf5a94d1 | 527 | (1ULL << INTERCEPT_WBINVD) | |
916ce236 JR |
528 | (1ULL << INTERCEPT_MONITOR) | |
529 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
530 | |
531 | control->iopm_base_pa = iopm_base; | |
532 | control->msrpm_base_pa = msrpm_base; | |
0cc5064d | 533 | control->tsc_offset = 0; |
6aa8b732 AK |
534 | control->int_ctl = V_INTR_MASKING_MASK; |
535 | ||
536 | init_seg(&save->es); | |
537 | init_seg(&save->ss); | |
538 | init_seg(&save->ds); | |
539 | init_seg(&save->fs); | |
540 | init_seg(&save->gs); | |
541 | ||
542 | save->cs.selector = 0xf000; | |
543 | /* Executable/Readable Code Segment */ | |
544 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
545 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
546 | save->cs.limit = 0xffff; | |
d92899a0 AK |
547 | /* |
548 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
549 | * be consistent with it. | |
550 | * | |
551 | * Replace when we have real mode working for vmx. | |
552 | */ | |
553 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
554 | |
555 | save->gdtr.limit = 0xffff; | |
556 | save->idtr.limit = 0xffff; | |
557 | ||
558 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
559 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
560 | ||
561 | save->efer = MSR_EFER_SVME_MASK; | |
d77c26fc | 562 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
563 | save->dr7 = 0x400; |
564 | save->rflags = 2; | |
565 | save->rip = 0x0000fff0; | |
566 | ||
567 | /* | |
568 | * cr0 val on cpu init should be 0x60000010, we enable cpu | |
569 | * cache by default. the orderly way is to enable cache in bios. | |
570 | */ | |
707d92fa | 571 | save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP; |
66aee91a | 572 | save->cr4 = X86_CR4_PAE; |
6aa8b732 AK |
573 | /* rdx = ?? */ |
574 | } | |
575 | ||
e00c8cf2 | 576 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
577 | { |
578 | struct vcpu_svm *svm = to_svm(vcpu); | |
579 | ||
580 | init_vmcb(svm->vmcb); | |
70433389 AK |
581 | |
582 | if (vcpu->vcpu_id != 0) { | |
583 | svm->vmcb->save.rip = 0; | |
ad312c7c ZX |
584 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
585 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 586 | } |
e00c8cf2 AK |
587 | |
588 | return 0; | |
04d2cc77 AK |
589 | } |
590 | ||
fb3f0f51 | 591 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 592 | { |
a2fa3e9f | 593 | struct vcpu_svm *svm; |
6aa8b732 | 594 | struct page *page; |
fb3f0f51 | 595 | int err; |
6aa8b732 | 596 | |
c16f862d | 597 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
598 | if (!svm) { |
599 | err = -ENOMEM; | |
600 | goto out; | |
601 | } | |
602 | ||
603 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
604 | if (err) | |
605 | goto free_svm; | |
606 | ||
6aa8b732 | 607 | page = alloc_page(GFP_KERNEL); |
fb3f0f51 RR |
608 | if (!page) { |
609 | err = -ENOMEM; | |
610 | goto uninit; | |
611 | } | |
6aa8b732 | 612 | |
a2fa3e9f GH |
613 | svm->vmcb = page_address(page); |
614 | clear_page(svm->vmcb); | |
615 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
616 | svm->asid_generation = 0; | |
617 | memset(svm->db_regs, 0, sizeof(svm->db_regs)); | |
618 | init_vmcb(svm->vmcb); | |
619 | ||
fb3f0f51 RR |
620 | fx_init(&svm->vcpu); |
621 | svm->vcpu.fpu_active = 1; | |
ad312c7c | 622 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
fb3f0f51 | 623 | if (svm->vcpu.vcpu_id == 0) |
ad312c7c | 624 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 625 | |
fb3f0f51 | 626 | return &svm->vcpu; |
36241b8c | 627 | |
fb3f0f51 RR |
628 | uninit: |
629 | kvm_vcpu_uninit(&svm->vcpu); | |
630 | free_svm: | |
a4770347 | 631 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
632 | out: |
633 | return ERR_PTR(err); | |
6aa8b732 AK |
634 | } |
635 | ||
636 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
637 | { | |
a2fa3e9f GH |
638 | struct vcpu_svm *svm = to_svm(vcpu); |
639 | ||
fb3f0f51 RR |
640 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
641 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 642 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
643 | } |
644 | ||
15ad7146 | 645 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 646 | { |
a2fa3e9f | 647 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 648 | int i; |
0cc5064d | 649 | |
0cc5064d AK |
650 | if (unlikely(cpu != vcpu->cpu)) { |
651 | u64 tsc_this, delta; | |
652 | ||
653 | /* | |
654 | * Make sure that the guest sees a monotonically | |
655 | * increasing TSC. | |
656 | */ | |
657 | rdtscll(tsc_this); | |
ad312c7c | 658 | delta = vcpu->arch.host_tsc - tsc_this; |
a2fa3e9f | 659 | svm->vmcb->control.tsc_offset += delta; |
0cc5064d | 660 | vcpu->cpu = cpu; |
a3d7f85f | 661 | kvm_migrate_apic_timer(vcpu); |
0cc5064d | 662 | } |
94dfbdb3 AL |
663 | |
664 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 665 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
666 | } |
667 | ||
668 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
669 | { | |
a2fa3e9f | 670 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
671 | int i; |
672 | ||
e1beb1d3 | 673 | ++vcpu->stat.host_state_reload; |
94dfbdb3 | 674 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 675 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
94dfbdb3 | 676 | |
ad312c7c | 677 | rdtscll(vcpu->arch.host_tsc); |
6aa8b732 AK |
678 | } |
679 | ||
774c47f1 AK |
680 | static void svm_vcpu_decache(struct kvm_vcpu *vcpu) |
681 | { | |
682 | } | |
683 | ||
6aa8b732 AK |
684 | static void svm_cache_regs(struct kvm_vcpu *vcpu) |
685 | { | |
a2fa3e9f GH |
686 | struct vcpu_svm *svm = to_svm(vcpu); |
687 | ||
ad312c7c ZX |
688 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; |
689 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
690 | vcpu->arch.rip = svm->vmcb->save.rip; | |
6aa8b732 AK |
691 | } |
692 | ||
693 | static void svm_decache_regs(struct kvm_vcpu *vcpu) | |
694 | { | |
a2fa3e9f | 695 | struct vcpu_svm *svm = to_svm(vcpu); |
ad312c7c ZX |
696 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
697 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
698 | svm->vmcb->save.rip = vcpu->arch.rip; | |
6aa8b732 AK |
699 | } |
700 | ||
701 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) | |
702 | { | |
a2fa3e9f | 703 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
704 | } |
705 | ||
706 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
707 | { | |
a2fa3e9f | 708 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
709 | } |
710 | ||
711 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) | |
712 | { | |
a2fa3e9f | 713 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
714 | |
715 | switch (seg) { | |
716 | case VCPU_SREG_CS: return &save->cs; | |
717 | case VCPU_SREG_DS: return &save->ds; | |
718 | case VCPU_SREG_ES: return &save->es; | |
719 | case VCPU_SREG_FS: return &save->fs; | |
720 | case VCPU_SREG_GS: return &save->gs; | |
721 | case VCPU_SREG_SS: return &save->ss; | |
722 | case VCPU_SREG_TR: return &save->tr; | |
723 | case VCPU_SREG_LDTR: return &save->ldtr; | |
724 | } | |
725 | BUG(); | |
8b6d44c7 | 726 | return NULL; |
6aa8b732 AK |
727 | } |
728 | ||
729 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
730 | { | |
731 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
732 | ||
733 | return s->base; | |
734 | } | |
735 | ||
736 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
737 | struct kvm_segment *var, int seg) | |
738 | { | |
739 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
740 | ||
741 | var->base = s->base; | |
742 | var->limit = s->limit; | |
743 | var->selector = s->selector; | |
744 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
745 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
746 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
747 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
748 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
749 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
750 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
751 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
752 | var->unusable = !var->present; | |
753 | } | |
754 | ||
6aa8b732 AK |
755 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) |
756 | { | |
a2fa3e9f GH |
757 | struct vcpu_svm *svm = to_svm(vcpu); |
758 | ||
759 | dt->limit = svm->vmcb->save.idtr.limit; | |
760 | dt->base = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
761 | } |
762 | ||
763 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
764 | { | |
a2fa3e9f GH |
765 | struct vcpu_svm *svm = to_svm(vcpu); |
766 | ||
767 | svm->vmcb->save.idtr.limit = dt->limit; | |
768 | svm->vmcb->save.idtr.base = dt->base ; | |
6aa8b732 AK |
769 | } |
770 | ||
771 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
772 | { | |
a2fa3e9f GH |
773 | struct vcpu_svm *svm = to_svm(vcpu); |
774 | ||
775 | dt->limit = svm->vmcb->save.gdtr.limit; | |
776 | dt->base = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
777 | } |
778 | ||
779 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
780 | { | |
a2fa3e9f GH |
781 | struct vcpu_svm *svm = to_svm(vcpu); |
782 | ||
783 | svm->vmcb->save.gdtr.limit = dt->limit; | |
784 | svm->vmcb->save.gdtr.base = dt->base ; | |
6aa8b732 AK |
785 | } |
786 | ||
25c4c276 | 787 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
788 | { |
789 | } | |
790 | ||
6aa8b732 AK |
791 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
792 | { | |
a2fa3e9f GH |
793 | struct vcpu_svm *svm = to_svm(vcpu); |
794 | ||
05b3e0c2 | 795 | #ifdef CONFIG_X86_64 |
ad312c7c | 796 | if (vcpu->arch.shadow_efer & EFER_LME) { |
707d92fa | 797 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
ad312c7c | 798 | vcpu->arch.shadow_efer |= EFER_LMA; |
2b5203ee | 799 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
800 | } |
801 | ||
d77c26fc | 802 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
ad312c7c | 803 | vcpu->arch.shadow_efer &= ~EFER_LMA; |
2b5203ee | 804 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
805 | } |
806 | } | |
807 | #endif | |
ad312c7c | 808 | if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) { |
a2fa3e9f | 809 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
7807fa6c AL |
810 | vcpu->fpu_active = 1; |
811 | } | |
812 | ||
ad312c7c | 813 | vcpu->arch.cr0 = cr0; |
707d92fa RR |
814 | cr0 |= X86_CR0_PG | X86_CR0_WP; |
815 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
6b390b63 JR |
816 | if (!vcpu->fpu_active) { |
817 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); | |
334df50a | 818 | cr0 |= X86_CR0_TS; |
6b390b63 | 819 | } |
a2fa3e9f | 820 | svm->vmcb->save.cr0 = cr0; |
6aa8b732 AK |
821 | } |
822 | ||
823 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
824 | { | |
ad312c7c | 825 | vcpu->arch.cr4 = cr4; |
a2fa3e9f | 826 | to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE; |
6aa8b732 AK |
827 | } |
828 | ||
829 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
830 | struct kvm_segment *var, int seg) | |
831 | { | |
a2fa3e9f | 832 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
833 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
834 | ||
835 | s->base = var->base; | |
836 | s->limit = var->limit; | |
837 | s->selector = var->selector; | |
838 | if (var->unusable) | |
839 | s->attrib = 0; | |
840 | else { | |
841 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
842 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
843 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
844 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
845 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
846 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
847 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
848 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
849 | } | |
850 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
851 | svm->vmcb->save.cpl |
852 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
853 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
854 | ||
855 | } | |
856 | ||
857 | /* FIXME: | |
858 | ||
a2fa3e9f GH |
859 | svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK; |
860 | svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK); | |
6aa8b732 AK |
861 | |
862 | */ | |
863 | ||
864 | static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
865 | { | |
866 | return -EOPNOTSUPP; | |
867 | } | |
868 | ||
2a8067f1 ED |
869 | static int svm_get_irq(struct kvm_vcpu *vcpu) |
870 | { | |
871 | struct vcpu_svm *svm = to_svm(vcpu); | |
872 | u32 exit_int_info = svm->vmcb->control.exit_int_info; | |
873 | ||
874 | if (is_external_interrupt(exit_int_info)) | |
875 | return exit_int_info & SVM_EVTINJ_VEC_MASK; | |
876 | return -1; | |
877 | } | |
878 | ||
6aa8b732 AK |
879 | static void load_host_msrs(struct kvm_vcpu *vcpu) |
880 | { | |
94dfbdb3 | 881 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 882 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 883 | #endif |
6aa8b732 AK |
884 | } |
885 | ||
886 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
887 | { | |
94dfbdb3 | 888 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 889 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 890 | #endif |
6aa8b732 AK |
891 | } |
892 | ||
e756fc62 | 893 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data) |
6aa8b732 AK |
894 | { |
895 | if (svm_data->next_asid > svm_data->max_asid) { | |
896 | ++svm_data->asid_generation; | |
897 | svm_data->next_asid = 1; | |
a2fa3e9f | 898 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
899 | } |
900 | ||
e756fc62 | 901 | svm->vcpu.cpu = svm_data->cpu; |
a2fa3e9f GH |
902 | svm->asid_generation = svm_data->asid_generation; |
903 | svm->vmcb->control.asid = svm_data->next_asid++; | |
6aa8b732 AK |
904 | } |
905 | ||
6aa8b732 AK |
906 | static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr) |
907 | { | |
a2fa3e9f | 908 | return to_svm(vcpu)->db_regs[dr]; |
6aa8b732 AK |
909 | } |
910 | ||
911 | static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value, | |
912 | int *exception) | |
913 | { | |
a2fa3e9f GH |
914 | struct vcpu_svm *svm = to_svm(vcpu); |
915 | ||
6aa8b732 AK |
916 | *exception = 0; |
917 | ||
a2fa3e9f GH |
918 | if (svm->vmcb->save.dr7 & DR7_GD_MASK) { |
919 | svm->vmcb->save.dr7 &= ~DR7_GD_MASK; | |
920 | svm->vmcb->save.dr6 |= DR6_BD_MASK; | |
6aa8b732 AK |
921 | *exception = DB_VECTOR; |
922 | return; | |
923 | } | |
924 | ||
925 | switch (dr) { | |
926 | case 0 ... 3: | |
a2fa3e9f | 927 | svm->db_regs[dr] = value; |
6aa8b732 AK |
928 | return; |
929 | case 4 ... 5: | |
ad312c7c | 930 | if (vcpu->arch.cr4 & X86_CR4_DE) { |
6aa8b732 AK |
931 | *exception = UD_VECTOR; |
932 | return; | |
933 | } | |
934 | case 7: { | |
935 | if (value & ~((1ULL << 32) - 1)) { | |
936 | *exception = GP_VECTOR; | |
937 | return; | |
938 | } | |
a2fa3e9f | 939 | svm->vmcb->save.dr7 = value; |
6aa8b732 AK |
940 | return; |
941 | } | |
942 | default: | |
943 | printk(KERN_DEBUG "%s: unexpected dr %u\n", | |
944 | __FUNCTION__, dr); | |
945 | *exception = UD_VECTOR; | |
946 | return; | |
947 | } | |
948 | } | |
949 | ||
e756fc62 | 950 | static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 951 | { |
a2fa3e9f | 952 | u32 exit_int_info = svm->vmcb->control.exit_int_info; |
e756fc62 | 953 | struct kvm *kvm = svm->vcpu.kvm; |
6aa8b732 AK |
954 | u64 fault_address; |
955 | u32 error_code; | |
6aa8b732 | 956 | |
85f455f7 ED |
957 | if (!irqchip_in_kernel(kvm) && |
958 | is_external_interrupt(exit_int_info)) | |
e756fc62 | 959 | push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK); |
6aa8b732 | 960 | |
a2fa3e9f GH |
961 | fault_address = svm->vmcb->control.exit_info_2; |
962 | error_code = svm->vmcb->control.exit_info_1; | |
3067714c | 963 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); |
6aa8b732 AK |
964 | } |
965 | ||
7aa81cc0 AL |
966 | static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
967 | { | |
968 | int er; | |
969 | ||
571008da | 970 | er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 971 | if (er != EMULATE_DONE) |
7ee5d940 | 972 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
973 | return 1; |
974 | } | |
975 | ||
e756fc62 | 976 | static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
7807fa6c | 977 | { |
a2fa3e9f | 978 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
ad312c7c | 979 | if (!(svm->vcpu.arch.cr0 & X86_CR0_TS)) |
a2fa3e9f | 980 | svm->vmcb->save.cr0 &= ~X86_CR0_TS; |
e756fc62 | 981 | svm->vcpu.fpu_active = 1; |
a2fa3e9f GH |
982 | |
983 | return 1; | |
7807fa6c AL |
984 | } |
985 | ||
e756fc62 | 986 | static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
46fe4ddd JR |
987 | { |
988 | /* | |
989 | * VMCB is undefined after a SHUTDOWN intercept | |
990 | * so reinitialize it. | |
991 | */ | |
a2fa3e9f GH |
992 | clear_page(svm->vmcb); |
993 | init_vmcb(svm->vmcb); | |
46fe4ddd JR |
994 | |
995 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
996 | return 0; | |
997 | } | |
998 | ||
e756fc62 | 999 | static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1000 | { |
d77c26fc | 1001 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
039576c0 AK |
1002 | int size, down, in, string, rep; |
1003 | unsigned port; | |
6aa8b732 | 1004 | |
e756fc62 | 1005 | ++svm->vcpu.stat.io_exits; |
6aa8b732 | 1006 | |
a2fa3e9f | 1007 | svm->next_rip = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1008 | |
e70669ab LV |
1009 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
1010 | ||
1011 | if (string) { | |
3427318f LV |
1012 | if (emulate_instruction(&svm->vcpu, |
1013 | kvm_run, 0, 0, 0) == EMULATE_DO_MMIO) | |
e70669ab LV |
1014 | return 0; |
1015 | return 1; | |
1016 | } | |
1017 | ||
039576c0 AK |
1018 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
1019 | port = io_info >> 16; | |
1020 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
039576c0 | 1021 | rep = (io_info & SVM_IOIO_REP_MASK) != 0; |
a2fa3e9f | 1022 | down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0; |
6aa8b732 | 1023 | |
3090dd73 | 1024 | return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
1025 | } |
1026 | ||
e756fc62 | 1027 | static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 AK |
1028 | { |
1029 | return 1; | |
1030 | } | |
1031 | ||
e756fc62 | 1032 | static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1033 | { |
a2fa3e9f | 1034 | svm->next_rip = svm->vmcb->save.rip + 1; |
e756fc62 RR |
1035 | skip_emulated_instruction(&svm->vcpu); |
1036 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1037 | } |
1038 | ||
e756fc62 | 1039 | static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
02e235bc | 1040 | { |
a2fa3e9f | 1041 | svm->next_rip = svm->vmcb->save.rip + 3; |
e756fc62 | 1042 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1043 | kvm_emulate_hypercall(&svm->vcpu); |
1044 | return 1; | |
02e235bc AK |
1045 | } |
1046 | ||
e756fc62 RR |
1047 | static int invalid_op_interception(struct vcpu_svm *svm, |
1048 | struct kvm_run *kvm_run) | |
6aa8b732 | 1049 | { |
7ee5d940 | 1050 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
1051 | return 1; |
1052 | } | |
1053 | ||
e756fc62 RR |
1054 | static int task_switch_interception(struct vcpu_svm *svm, |
1055 | struct kvm_run *kvm_run) | |
6aa8b732 | 1056 | { |
f0242478 | 1057 | pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __FUNCTION__); |
6aa8b732 AK |
1058 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
1059 | return 0; | |
1060 | } | |
1061 | ||
e756fc62 | 1062 | static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1063 | { |
a2fa3e9f | 1064 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1065 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 1066 | return 1; |
6aa8b732 AK |
1067 | } |
1068 | ||
e756fc62 RR |
1069 | static int emulate_on_interception(struct vcpu_svm *svm, |
1070 | struct kvm_run *kvm_run) | |
6aa8b732 | 1071 | { |
3427318f | 1072 | if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE) |
f0242478 | 1073 | pr_unimpl(&svm->vcpu, "%s: failed\n", __FUNCTION__); |
6aa8b732 AK |
1074 | return 1; |
1075 | } | |
1076 | ||
1d075434 JR |
1077 | static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1078 | { | |
1079 | emulate_instruction(&svm->vcpu, NULL, 0, 0, 0); | |
1080 | if (irqchip_in_kernel(svm->vcpu.kvm)) | |
1081 | return 1; | |
1082 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; | |
1083 | return 0; | |
1084 | } | |
1085 | ||
6aa8b732 AK |
1086 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
1087 | { | |
a2fa3e9f GH |
1088 | struct vcpu_svm *svm = to_svm(vcpu); |
1089 | ||
6aa8b732 | 1090 | switch (ecx) { |
6aa8b732 AK |
1091 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1092 | u64 tsc; | |
1093 | ||
1094 | rdtscll(tsc); | |
a2fa3e9f | 1095 | *data = svm->vmcb->control.tsc_offset + tsc; |
6aa8b732 AK |
1096 | break; |
1097 | } | |
0e859cac | 1098 | case MSR_K6_STAR: |
a2fa3e9f | 1099 | *data = svm->vmcb->save.star; |
6aa8b732 | 1100 | break; |
0e859cac | 1101 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1102 | case MSR_LSTAR: |
a2fa3e9f | 1103 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
1104 | break; |
1105 | case MSR_CSTAR: | |
a2fa3e9f | 1106 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
1107 | break; |
1108 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1109 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
1110 | break; |
1111 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1112 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
1113 | break; |
1114 | #endif | |
1115 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1116 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
1117 | break; |
1118 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1119 | *data = svm->vmcb->save.sysenter_eip; |
6aa8b732 AK |
1120 | break; |
1121 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1122 | *data = svm->vmcb->save.sysenter_esp; |
6aa8b732 | 1123 | break; |
a2938c80 JR |
1124 | /* Nobody will change the following 5 values in the VMCB so |
1125 | we can safely return them on rdmsr. They will always be 0 | |
1126 | until LBRV is implemented. */ | |
1127 | case MSR_IA32_DEBUGCTLMSR: | |
1128 | *data = svm->vmcb->save.dbgctl; | |
1129 | break; | |
1130 | case MSR_IA32_LASTBRANCHFROMIP: | |
1131 | *data = svm->vmcb->save.br_from; | |
1132 | break; | |
1133 | case MSR_IA32_LASTBRANCHTOIP: | |
1134 | *data = svm->vmcb->save.br_to; | |
1135 | break; | |
1136 | case MSR_IA32_LASTINTFROMIP: | |
1137 | *data = svm->vmcb->save.last_excp_from; | |
1138 | break; | |
1139 | case MSR_IA32_LASTINTTOIP: | |
1140 | *data = svm->vmcb->save.last_excp_to; | |
1141 | break; | |
6aa8b732 | 1142 | default: |
3bab1f5d | 1143 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1144 | } |
1145 | return 0; | |
1146 | } | |
1147 | ||
e756fc62 | 1148 | static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1149 | { |
ad312c7c | 1150 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
1151 | u64 data; |
1152 | ||
e756fc62 | 1153 | if (svm_get_msr(&svm->vcpu, ecx, &data)) |
c1a5d4f9 | 1154 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1155 | else { |
a2fa3e9f | 1156 | svm->vmcb->save.rax = data & 0xffffffff; |
ad312c7c | 1157 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
a2fa3e9f | 1158 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1159 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1160 | } |
1161 | return 1; | |
1162 | } | |
1163 | ||
1164 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
1165 | { | |
a2fa3e9f GH |
1166 | struct vcpu_svm *svm = to_svm(vcpu); |
1167 | ||
6aa8b732 | 1168 | switch (ecx) { |
6aa8b732 AK |
1169 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1170 | u64 tsc; | |
1171 | ||
1172 | rdtscll(tsc); | |
a2fa3e9f | 1173 | svm->vmcb->control.tsc_offset = data - tsc; |
6aa8b732 AK |
1174 | break; |
1175 | } | |
0e859cac | 1176 | case MSR_K6_STAR: |
a2fa3e9f | 1177 | svm->vmcb->save.star = data; |
6aa8b732 | 1178 | break; |
49b14f24 | 1179 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1180 | case MSR_LSTAR: |
a2fa3e9f | 1181 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
1182 | break; |
1183 | case MSR_CSTAR: | |
a2fa3e9f | 1184 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
1185 | break; |
1186 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1187 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
1188 | break; |
1189 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1190 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
1191 | break; |
1192 | #endif | |
1193 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1194 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
1195 | break; |
1196 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1197 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
1198 | break; |
1199 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1200 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 1201 | break; |
a2938c80 JR |
1202 | case MSR_IA32_DEBUGCTLMSR: |
1203 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", | |
1204 | __FUNCTION__, data); | |
1205 | break; | |
62b9abaa JR |
1206 | case MSR_K7_EVNTSEL0: |
1207 | case MSR_K7_EVNTSEL1: | |
1208 | case MSR_K7_EVNTSEL2: | |
1209 | case MSR_K7_EVNTSEL3: | |
1210 | /* | |
1211 | * only support writing 0 to the performance counters for now | |
1212 | * to make Windows happy. Should be replaced by a real | |
1213 | * performance counter emulation later. | |
1214 | */ | |
1215 | if (data != 0) | |
1216 | goto unhandled; | |
1217 | break; | |
6aa8b732 | 1218 | default: |
62b9abaa | 1219 | unhandled: |
3bab1f5d | 1220 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1221 | } |
1222 | return 0; | |
1223 | } | |
1224 | ||
e756fc62 | 1225 | static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1226 | { |
ad312c7c | 1227 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
a2fa3e9f | 1228 | u64 data = (svm->vmcb->save.rax & -1u) |
ad312c7c | 1229 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
a2fa3e9f | 1230 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1231 | if (svm_set_msr(&svm->vcpu, ecx, data)) |
c1a5d4f9 | 1232 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1233 | else |
e756fc62 | 1234 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1235 | return 1; |
1236 | } | |
1237 | ||
e756fc62 | 1238 | static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1239 | { |
e756fc62 RR |
1240 | if (svm->vmcb->control.exit_info_1) |
1241 | return wrmsr_interception(svm, kvm_run); | |
6aa8b732 | 1242 | else |
e756fc62 | 1243 | return rdmsr_interception(svm, kvm_run); |
6aa8b732 AK |
1244 | } |
1245 | ||
e756fc62 | 1246 | static int interrupt_window_interception(struct vcpu_svm *svm, |
c1150d8c DL |
1247 | struct kvm_run *kvm_run) |
1248 | { | |
85f455f7 ED |
1249 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); |
1250 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
c1150d8c DL |
1251 | /* |
1252 | * If the user space waits to inject interrupts, exit as soon as | |
1253 | * possible | |
1254 | */ | |
1255 | if (kvm_run->request_interrupt_window && | |
ad312c7c | 1256 | !svm->vcpu.arch.irq_summary) { |
e756fc62 | 1257 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
1258 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1259 | return 0; | |
1260 | } | |
1261 | ||
1262 | return 1; | |
1263 | } | |
1264 | ||
e756fc62 | 1265 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm, |
6aa8b732 AK |
1266 | struct kvm_run *kvm_run) = { |
1267 | [SVM_EXIT_READ_CR0] = emulate_on_interception, | |
1268 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
1269 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
80a8119c | 1270 | [SVM_EXIT_READ_CR8] = emulate_on_interception, |
6aa8b732 AK |
1271 | /* for now: */ |
1272 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, | |
1273 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
1274 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
1d075434 | 1275 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
6aa8b732 AK |
1276 | [SVM_EXIT_READ_DR0] = emulate_on_interception, |
1277 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
1278 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
1279 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
1280 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, | |
1281 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
1282 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
1283 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
1284 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, | |
1285 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, | |
7aa81cc0 | 1286 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
6aa8b732 | 1287 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
7807fa6c | 1288 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, |
6aa8b732 AK |
1289 | [SVM_EXIT_INTR] = nop_on_interception, |
1290 | [SVM_EXIT_NMI] = nop_on_interception, | |
1291 | [SVM_EXIT_SMI] = nop_on_interception, | |
1292 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 1293 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 AK |
1294 | /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ |
1295 | [SVM_EXIT_CPUID] = cpuid_interception, | |
cf5a94d1 | 1296 | [SVM_EXIT_INVD] = emulate_on_interception, |
6aa8b732 AK |
1297 | [SVM_EXIT_HLT] = halt_interception, |
1298 | [SVM_EXIT_INVLPG] = emulate_on_interception, | |
1299 | [SVM_EXIT_INVLPGA] = invalid_op_interception, | |
1300 | [SVM_EXIT_IOIO] = io_interception, | |
1301 | [SVM_EXIT_MSR] = msr_interception, | |
1302 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 1303 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
6aa8b732 | 1304 | [SVM_EXIT_VMRUN] = invalid_op_interception, |
02e235bc | 1305 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
6aa8b732 AK |
1306 | [SVM_EXIT_VMLOAD] = invalid_op_interception, |
1307 | [SVM_EXIT_VMSAVE] = invalid_op_interception, | |
1308 | [SVM_EXIT_STGI] = invalid_op_interception, | |
1309 | [SVM_EXIT_CLGI] = invalid_op_interception, | |
1310 | [SVM_EXIT_SKINIT] = invalid_op_interception, | |
cf5a94d1 | 1311 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
1312 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
1313 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
6aa8b732 AK |
1314 | }; |
1315 | ||
1316 | ||
04d2cc77 | 1317 | static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) |
6aa8b732 | 1318 | { |
04d2cc77 | 1319 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1320 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 1321 | |
04d2cc77 AK |
1322 | kvm_reput_irq(svm); |
1323 | ||
1324 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { | |
1325 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
1326 | kvm_run->fail_entry.hardware_entry_failure_reason | |
1327 | = svm->vmcb->control.exit_code; | |
1328 | return 0; | |
1329 | } | |
1330 | ||
a2fa3e9f | 1331 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
6aa8b732 AK |
1332 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR) |
1333 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " | |
1334 | "exit_code 0x%x\n", | |
a2fa3e9f | 1335 | __FUNCTION__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
1336 | exit_code); |
1337 | ||
9d8f549d | 1338 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 1339 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 1340 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 1341 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
1342 | return 0; |
1343 | } | |
1344 | ||
e756fc62 | 1345 | return svm_exit_handlers[exit_code](svm, kvm_run); |
6aa8b732 AK |
1346 | } |
1347 | ||
1348 | static void reload_tss(struct kvm_vcpu *vcpu) | |
1349 | { | |
1350 | int cpu = raw_smp_processor_id(); | |
1351 | ||
1352 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
d77c26fc | 1353 | svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */ |
6aa8b732 AK |
1354 | load_TR_desc(); |
1355 | } | |
1356 | ||
e756fc62 | 1357 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
1358 | { |
1359 | int cpu = raw_smp_processor_id(); | |
1360 | ||
1361 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
1362 | ||
a2fa3e9f | 1363 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
e756fc62 | 1364 | if (svm->vcpu.cpu != cpu || |
a2fa3e9f | 1365 | svm->asid_generation != svm_data->asid_generation) |
e756fc62 | 1366 | new_asid(svm, svm_data); |
6aa8b732 AK |
1367 | } |
1368 | ||
1369 | ||
85f455f7 | 1370 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
1371 | { |
1372 | struct vmcb_control_area *control; | |
1373 | ||
e756fc62 | 1374 | control = &svm->vmcb->control; |
85f455f7 | 1375 | control->int_vector = irq; |
6aa8b732 AK |
1376 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
1377 | control->int_ctl |= V_IRQ_MASK | | |
1378 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
1379 | } | |
1380 | ||
2a8067f1 ED |
1381 | static void svm_set_irq(struct kvm_vcpu *vcpu, int irq) |
1382 | { | |
1383 | struct vcpu_svm *svm = to_svm(vcpu); | |
1384 | ||
1385 | svm_inject_irq(svm, irq); | |
1386 | } | |
1387 | ||
04d2cc77 | 1388 | static void svm_intr_assist(struct kvm_vcpu *vcpu) |
6aa8b732 | 1389 | { |
04d2cc77 | 1390 | struct vcpu_svm *svm = to_svm(vcpu); |
85f455f7 ED |
1391 | struct vmcb *vmcb = svm->vmcb; |
1392 | int intr_vector = -1; | |
1393 | ||
1394 | if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) && | |
1395 | ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) { | |
1396 | intr_vector = vmcb->control.exit_int_info & | |
1397 | SVM_EVTINJ_VEC_MASK; | |
1398 | vmcb->control.exit_int_info = 0; | |
1399 | svm_inject_irq(svm, intr_vector); | |
1400 | return; | |
1401 | } | |
1402 | ||
1403 | if (vmcb->control.int_ctl & V_IRQ_MASK) | |
1404 | return; | |
1405 | ||
1b9778da | 1406 | if (!kvm_cpu_has_interrupt(vcpu)) |
85f455f7 ED |
1407 | return; |
1408 | ||
1409 | if (!(vmcb->save.rflags & X86_EFLAGS_IF) || | |
1410 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) || | |
1411 | (vmcb->control.event_inj & SVM_EVTINJ_VALID)) { | |
1412 | /* unable to deliver irq, set pending irq */ | |
1413 | vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR); | |
1414 | svm_inject_irq(svm, 0x0); | |
1415 | return; | |
1416 | } | |
1417 | /* Okay, we can deliver the interrupt: grab it and update PIC state. */ | |
1b9778da | 1418 | intr_vector = kvm_cpu_get_interrupt(vcpu); |
85f455f7 | 1419 | svm_inject_irq(svm, intr_vector); |
1b9778da | 1420 | kvm_timer_intr_post(vcpu, intr_vector); |
85f455f7 ED |
1421 | } |
1422 | ||
1423 | static void kvm_reput_irq(struct vcpu_svm *svm) | |
1424 | { | |
e756fc62 | 1425 | struct vmcb_control_area *control = &svm->vmcb->control; |
6aa8b732 | 1426 | |
7017fc3d ED |
1427 | if ((control->int_ctl & V_IRQ_MASK) |
1428 | && !irqchip_in_kernel(svm->vcpu.kvm)) { | |
6aa8b732 | 1429 | control->int_ctl &= ~V_IRQ_MASK; |
e756fc62 | 1430 | push_irq(&svm->vcpu, control->int_vector); |
6aa8b732 | 1431 | } |
c1150d8c | 1432 | |
ad312c7c | 1433 | svm->vcpu.arch.interrupt_window_open = |
c1150d8c DL |
1434 | !(control->int_state & SVM_INTERRUPT_SHADOW_MASK); |
1435 | } | |
1436 | ||
85f455f7 ED |
1437 | static void svm_do_inject_vector(struct vcpu_svm *svm) |
1438 | { | |
1439 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ad312c7c ZX |
1440 | int word_index = __ffs(vcpu->arch.irq_summary); |
1441 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
85f455f7 ED |
1442 | int irq = word_index * BITS_PER_LONG + bit_index; |
1443 | ||
ad312c7c ZX |
1444 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
1445 | if (!vcpu->arch.irq_pending[word_index]) | |
1446 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
85f455f7 ED |
1447 | svm_inject_irq(svm, irq); |
1448 | } | |
1449 | ||
04d2cc77 | 1450 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, |
c1150d8c DL |
1451 | struct kvm_run *kvm_run) |
1452 | { | |
04d2cc77 | 1453 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1454 | struct vmcb_control_area *control = &svm->vmcb->control; |
c1150d8c | 1455 | |
ad312c7c | 1456 | svm->vcpu.arch.interrupt_window_open = |
c1150d8c | 1457 | (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) && |
a2fa3e9f | 1458 | (svm->vmcb->save.rflags & X86_EFLAGS_IF)); |
c1150d8c | 1459 | |
ad312c7c | 1460 | if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary) |
c1150d8c DL |
1461 | /* |
1462 | * If interrupts enabled, and not blocked by sti or mov ss. Good. | |
1463 | */ | |
85f455f7 | 1464 | svm_do_inject_vector(svm); |
c1150d8c DL |
1465 | |
1466 | /* | |
1467 | * Interrupts blocked. Wait for unblock. | |
1468 | */ | |
ad312c7c ZX |
1469 | if (!svm->vcpu.arch.interrupt_window_open && |
1470 | (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window)) | |
c1150d8c | 1471 | control->intercept |= 1ULL << INTERCEPT_VINTR; |
d77c26fc | 1472 | else |
c1150d8c DL |
1473 | control->intercept &= ~(1ULL << INTERCEPT_VINTR); |
1474 | } | |
1475 | ||
cbc94022 IE |
1476 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
1477 | { | |
1478 | return 0; | |
1479 | } | |
1480 | ||
6aa8b732 AK |
1481 | static void save_db_regs(unsigned long *db_regs) |
1482 | { | |
5aff458e AK |
1483 | asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0])); |
1484 | asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1])); | |
1485 | asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2])); | |
1486 | asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3])); | |
6aa8b732 AK |
1487 | } |
1488 | ||
1489 | static void load_db_regs(unsigned long *db_regs) | |
1490 | { | |
5aff458e AK |
1491 | asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0])); |
1492 | asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1])); | |
1493 | asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2])); | |
1494 | asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3])); | |
6aa8b732 AK |
1495 | } |
1496 | ||
d9e368d6 AK |
1497 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
1498 | { | |
1499 | force_new_asid(vcpu); | |
1500 | } | |
1501 | ||
04d2cc77 AK |
1502 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
1503 | { | |
1504 | } | |
1505 | ||
1506 | static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
6aa8b732 | 1507 | { |
a2fa3e9f | 1508 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1509 | u16 fs_selector; |
1510 | u16 gs_selector; | |
1511 | u16 ldt_selector; | |
d9e368d6 | 1512 | |
e756fc62 | 1513 | pre_svm_run(svm); |
6aa8b732 AK |
1514 | |
1515 | save_host_msrs(vcpu); | |
1516 | fs_selector = read_fs(); | |
1517 | gs_selector = read_gs(); | |
1518 | ldt_selector = read_ldt(); | |
a2fa3e9f GH |
1519 | svm->host_cr2 = kvm_read_cr2(); |
1520 | svm->host_dr6 = read_dr6(); | |
1521 | svm->host_dr7 = read_dr7(); | |
ad312c7c | 1522 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 1523 | |
a2fa3e9f | 1524 | if (svm->vmcb->save.dr7 & 0xff) { |
6aa8b732 | 1525 | write_dr7(0); |
a2fa3e9f GH |
1526 | save_db_regs(svm->host_db_regs); |
1527 | load_db_regs(svm->db_regs); | |
6aa8b732 | 1528 | } |
36241b8c | 1529 | |
04d2cc77 AK |
1530 | clgi(); |
1531 | ||
1532 | local_irq_enable(); | |
36241b8c | 1533 | |
6aa8b732 | 1534 | asm volatile ( |
05b3e0c2 | 1535 | #ifdef CONFIG_X86_64 |
54a08c04 | 1536 | "push %%rbp; \n\t" |
6aa8b732 | 1537 | #else |
fe7935d4 | 1538 | "push %%ebp; \n\t" |
6aa8b732 AK |
1539 | #endif |
1540 | ||
05b3e0c2 | 1541 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1542 | "mov %c[rbx](%[svm]), %%rbx \n\t" |
1543 | "mov %c[rcx](%[svm]), %%rcx \n\t" | |
1544 | "mov %c[rdx](%[svm]), %%rdx \n\t" | |
1545 | "mov %c[rsi](%[svm]), %%rsi \n\t" | |
1546 | "mov %c[rdi](%[svm]), %%rdi \n\t" | |
1547 | "mov %c[rbp](%[svm]), %%rbp \n\t" | |
1548 | "mov %c[r8](%[svm]), %%r8 \n\t" | |
1549 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
1550 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
1551 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
1552 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
1553 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
1554 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
1555 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 | 1556 | #else |
fb3f0f51 RR |
1557 | "mov %c[rbx](%[svm]), %%ebx \n\t" |
1558 | "mov %c[rcx](%[svm]), %%ecx \n\t" | |
1559 | "mov %c[rdx](%[svm]), %%edx \n\t" | |
1560 | "mov %c[rsi](%[svm]), %%esi \n\t" | |
1561 | "mov %c[rdi](%[svm]), %%edi \n\t" | |
1562 | "mov %c[rbp](%[svm]), %%ebp \n\t" | |
6aa8b732 AK |
1563 | #endif |
1564 | ||
05b3e0c2 | 1565 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1566 | /* Enter guest mode */ |
1567 | "push %%rax \n\t" | |
fb3f0f51 | 1568 | "mov %c[vmcb](%[svm]), %%rax \n\t" |
6aa8b732 AK |
1569 | SVM_VMLOAD "\n\t" |
1570 | SVM_VMRUN "\n\t" | |
1571 | SVM_VMSAVE "\n\t" | |
1572 | "pop %%rax \n\t" | |
1573 | #else | |
1574 | /* Enter guest mode */ | |
1575 | "push %%eax \n\t" | |
fb3f0f51 | 1576 | "mov %c[vmcb](%[svm]), %%eax \n\t" |
6aa8b732 AK |
1577 | SVM_VMLOAD "\n\t" |
1578 | SVM_VMRUN "\n\t" | |
1579 | SVM_VMSAVE "\n\t" | |
1580 | "pop %%eax \n\t" | |
1581 | #endif | |
1582 | ||
1583 | /* Save guest registers, load host registers */ | |
05b3e0c2 | 1584 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1585 | "mov %%rbx, %c[rbx](%[svm]) \n\t" |
1586 | "mov %%rcx, %c[rcx](%[svm]) \n\t" | |
1587 | "mov %%rdx, %c[rdx](%[svm]) \n\t" | |
1588 | "mov %%rsi, %c[rsi](%[svm]) \n\t" | |
1589 | "mov %%rdi, %c[rdi](%[svm]) \n\t" | |
1590 | "mov %%rbp, %c[rbp](%[svm]) \n\t" | |
1591 | "mov %%r8, %c[r8](%[svm]) \n\t" | |
1592 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
1593 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
1594 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
1595 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
1596 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
1597 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
1598 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 1599 | |
54a08c04 | 1600 | "pop %%rbp; \n\t" |
6aa8b732 | 1601 | #else |
fb3f0f51 RR |
1602 | "mov %%ebx, %c[rbx](%[svm]) \n\t" |
1603 | "mov %%ecx, %c[rcx](%[svm]) \n\t" | |
1604 | "mov %%edx, %c[rdx](%[svm]) \n\t" | |
1605 | "mov %%esi, %c[rsi](%[svm]) \n\t" | |
1606 | "mov %%edi, %c[rdi](%[svm]) \n\t" | |
1607 | "mov %%ebp, %c[rbp](%[svm]) \n\t" | |
6aa8b732 | 1608 | |
fe7935d4 | 1609 | "pop %%ebp; \n\t" |
6aa8b732 AK |
1610 | #endif |
1611 | : | |
fb3f0f51 | 1612 | : [svm]"a"(svm), |
6aa8b732 | 1613 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
1614 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
1615 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
1616 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
1617 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
1618 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
1619 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 1620 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
1621 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
1622 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
1623 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
1624 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
1625 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
1626 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
1627 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
1628 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 1629 | #endif |
54a08c04 LV |
1630 | : "cc", "memory" |
1631 | #ifdef CONFIG_X86_64 | |
1632 | , "rbx", "rcx", "rdx", "rsi", "rdi" | |
1633 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" | |
fe7935d4 LV |
1634 | #else |
1635 | , "ebx", "ecx", "edx" , "esi", "edi" | |
54a08c04 LV |
1636 | #endif |
1637 | ); | |
6aa8b732 | 1638 | |
a2fa3e9f GH |
1639 | if ((svm->vmcb->save.dr7 & 0xff)) |
1640 | load_db_regs(svm->host_db_regs); | |
6aa8b732 | 1641 | |
ad312c7c | 1642 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
6aa8b732 | 1643 | |
a2fa3e9f GH |
1644 | write_dr6(svm->host_dr6); |
1645 | write_dr7(svm->host_dr7); | |
1646 | kvm_write_cr2(svm->host_cr2); | |
6aa8b732 AK |
1647 | |
1648 | load_fs(fs_selector); | |
1649 | load_gs(gs_selector); | |
1650 | load_ldt(ldt_selector); | |
1651 | load_host_msrs(vcpu); | |
1652 | ||
1653 | reload_tss(vcpu); | |
1654 | ||
56ba47dd AK |
1655 | local_irq_disable(); |
1656 | ||
1657 | stgi(); | |
1658 | ||
a2fa3e9f | 1659 | svm->next_rip = 0; |
6aa8b732 AK |
1660 | } |
1661 | ||
6aa8b732 AK |
1662 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
1663 | { | |
a2fa3e9f GH |
1664 | struct vcpu_svm *svm = to_svm(vcpu); |
1665 | ||
1666 | svm->vmcb->save.cr3 = root; | |
6aa8b732 | 1667 | force_new_asid(vcpu); |
7807fa6c AL |
1668 | |
1669 | if (vcpu->fpu_active) { | |
a2fa3e9f GH |
1670 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); |
1671 | svm->vmcb->save.cr0 |= X86_CR0_TS; | |
7807fa6c AL |
1672 | vcpu->fpu_active = 0; |
1673 | } | |
6aa8b732 AK |
1674 | } |
1675 | ||
6aa8b732 AK |
1676 | static int is_disabled(void) |
1677 | { | |
6031a61c JR |
1678 | u64 vm_cr; |
1679 | ||
1680 | rdmsrl(MSR_VM_CR, vm_cr); | |
1681 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
1682 | return 1; | |
1683 | ||
6aa8b732 AK |
1684 | return 0; |
1685 | } | |
1686 | ||
102d8325 IM |
1687 | static void |
1688 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
1689 | { | |
1690 | /* | |
1691 | * Patch in the VMMCALL instruction: | |
1692 | */ | |
1693 | hypercall[0] = 0x0f; | |
1694 | hypercall[1] = 0x01; | |
1695 | hypercall[2] = 0xd9; | |
102d8325 IM |
1696 | } |
1697 | ||
002c7f7c YS |
1698 | static void svm_check_processor_compat(void *rtn) |
1699 | { | |
1700 | *(int *)rtn = 0; | |
1701 | } | |
1702 | ||
774ead3a AK |
1703 | static bool svm_cpu_has_accelerated_tpr(void) |
1704 | { | |
1705 | return false; | |
1706 | } | |
1707 | ||
cbdd1bea | 1708 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
1709 | .cpu_has_kvm_support = has_svm, |
1710 | .disabled_by_bios = is_disabled, | |
1711 | .hardware_setup = svm_hardware_setup, | |
1712 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 1713 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
1714 | .hardware_enable = svm_hardware_enable, |
1715 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 1716 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
1717 | |
1718 | .vcpu_create = svm_create_vcpu, | |
1719 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 1720 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 1721 | |
04d2cc77 | 1722 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
1723 | .vcpu_load = svm_vcpu_load, |
1724 | .vcpu_put = svm_vcpu_put, | |
774c47f1 | 1725 | .vcpu_decache = svm_vcpu_decache, |
6aa8b732 AK |
1726 | |
1727 | .set_guest_debug = svm_guest_debug, | |
1728 | .get_msr = svm_get_msr, | |
1729 | .set_msr = svm_set_msr, | |
1730 | .get_segment_base = svm_get_segment_base, | |
1731 | .get_segment = svm_get_segment, | |
1732 | .set_segment = svm_set_segment, | |
1747fb71 | 1733 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
25c4c276 | 1734 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 1735 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
1736 | .set_cr3 = svm_set_cr3, |
1737 | .set_cr4 = svm_set_cr4, | |
1738 | .set_efer = svm_set_efer, | |
1739 | .get_idt = svm_get_idt, | |
1740 | .set_idt = svm_set_idt, | |
1741 | .get_gdt = svm_get_gdt, | |
1742 | .set_gdt = svm_set_gdt, | |
1743 | .get_dr = svm_get_dr, | |
1744 | .set_dr = svm_set_dr, | |
1745 | .cache_regs = svm_cache_regs, | |
1746 | .decache_regs = svm_decache_regs, | |
1747 | .get_rflags = svm_get_rflags, | |
1748 | .set_rflags = svm_set_rflags, | |
1749 | ||
6aa8b732 | 1750 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 1751 | |
6aa8b732 | 1752 | .run = svm_vcpu_run, |
04d2cc77 | 1753 | .handle_exit = handle_exit, |
6aa8b732 | 1754 | .skip_emulated_instruction = skip_emulated_instruction, |
102d8325 | 1755 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 ED |
1756 | .get_irq = svm_get_irq, |
1757 | .set_irq = svm_set_irq, | |
298101da AK |
1758 | .queue_exception = svm_queue_exception, |
1759 | .exception_injected = svm_exception_injected, | |
04d2cc77 AK |
1760 | .inject_pending_irq = svm_intr_assist, |
1761 | .inject_pending_vectors = do_interrupt_requests, | |
cbc94022 IE |
1762 | |
1763 | .set_tss_addr = svm_set_tss_addr, | |
6aa8b732 AK |
1764 | }; |
1765 | ||
1766 | static int __init svm_init(void) | |
1767 | { | |
cb498ea2 | 1768 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
c16f862d | 1769 | THIS_MODULE); |
6aa8b732 AK |
1770 | } |
1771 | ||
1772 | static void __exit svm_exit(void) | |
1773 | { | |
cb498ea2 | 1774 | kvm_exit(); |
6aa8b732 AK |
1775 | } |
1776 | ||
1777 | module_init(svm_init) | |
1778 | module_exit(svm_exit) |