Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 7 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
8 | * |
9 | * Authors: | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
edf88417 AK |
17 | #include <linux/kvm_host.h> |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
5fdbf976 | 21 | #include "kvm_cache_regs.h" |
fe4c7b19 | 22 | #include "x86.h" |
66f7b72e | 23 | #include "cpuid.h" |
e495606d | 24 | |
6aa8b732 | 25 | #include <linux/module.h> |
ae759544 | 26 | #include <linux/mod_devicetable.h> |
9d8f549d | 27 | #include <linux/kernel.h> |
6aa8b732 AK |
28 | #include <linux/vmalloc.h> |
29 | #include <linux/highmem.h> | |
e8edc6e0 | 30 | #include <linux/sched.h> |
229456fc | 31 | #include <linux/ftrace_event.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
6aa8b732 | 33 | |
1018faa6 | 34 | #include <asm/perf_event.h> |
67ec6607 | 35 | #include <asm/tlbflush.h> |
e495606d | 36 | #include <asm/desc.h> |
631bc487 | 37 | #include <asm/kvm_para.h> |
6aa8b732 | 38 | |
63d1142f | 39 | #include <asm/virtext.h> |
229456fc | 40 | #include "trace.h" |
63d1142f | 41 | |
4ecac3fd AK |
42 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
43 | ||
6aa8b732 AK |
44 | MODULE_AUTHOR("Qumranet"); |
45 | MODULE_LICENSE("GPL"); | |
46 | ||
ae759544 JT |
47 | static const struct x86_cpu_id svm_cpu_id[] = { |
48 | X86_FEATURE_MATCH(X86_FEATURE_SVM), | |
49 | {} | |
50 | }; | |
51 | MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id); | |
52 | ||
6aa8b732 AK |
53 | #define IOPM_ALLOC_ORDER 2 |
54 | #define MSRPM_ALLOC_ORDER 1 | |
55 | ||
6aa8b732 AK |
56 | #define SEG_TYPE_LDT 2 |
57 | #define SEG_TYPE_BUSY_TSS16 3 | |
58 | ||
6bc31bdc AP |
59 | #define SVM_FEATURE_NPT (1 << 0) |
60 | #define SVM_FEATURE_LBRV (1 << 1) | |
61 | #define SVM_FEATURE_SVML (1 << 2) | |
62 | #define SVM_FEATURE_NRIP (1 << 3) | |
ddce97aa AP |
63 | #define SVM_FEATURE_TSC_RATE (1 << 4) |
64 | #define SVM_FEATURE_VMCB_CLEAN (1 << 5) | |
65 | #define SVM_FEATURE_FLUSH_ASID (1 << 6) | |
66 | #define SVM_FEATURE_DECODE_ASSIST (1 << 7) | |
6bc31bdc | 67 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) |
80b7706e | 68 | |
410e4d57 JR |
69 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
70 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
71 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
72 | ||
24e09cbf JR |
73 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
74 | ||
fbc0db76 | 75 | #define TSC_RATIO_RSVD 0xffffff0000000000ULL |
92a1f12d JR |
76 | #define TSC_RATIO_MIN 0x0000000000000001ULL |
77 | #define TSC_RATIO_MAX 0x000000ffffffffffULL | |
fbc0db76 | 78 | |
67ec6607 JR |
79 | static bool erratum_383_found __read_mostly; |
80 | ||
6c8166a7 AK |
81 | static const u32 host_save_user_msrs[] = { |
82 | #ifdef CONFIG_X86_64 | |
83 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
84 | MSR_FS_BASE, | |
85 | #endif | |
86 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
87 | }; | |
88 | ||
89 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
90 | ||
91 | struct kvm_vcpu; | |
92 | ||
e6aa9abd JR |
93 | struct nested_state { |
94 | struct vmcb *hsave; | |
95 | u64 hsave_msr; | |
4a810181 | 96 | u64 vm_cr_msr; |
e6aa9abd JR |
97 | u64 vmcb; |
98 | ||
99 | /* These are the merged vectors */ | |
100 | u32 *msrpm; | |
101 | ||
102 | /* gpa pointers to the real vectors */ | |
103 | u64 vmcb_msrpm; | |
ce2ac085 | 104 | u64 vmcb_iopm; |
aad42c64 | 105 | |
cd3ff653 JR |
106 | /* A VMEXIT is required but not yet emulated */ |
107 | bool exit_required; | |
108 | ||
aad42c64 | 109 | /* cache for intercepts of the guest */ |
4ee546b4 | 110 | u32 intercept_cr; |
3aed041a | 111 | u32 intercept_dr; |
aad42c64 JR |
112 | u32 intercept_exceptions; |
113 | u64 intercept; | |
114 | ||
5bd2edc3 JR |
115 | /* Nested Paging related state */ |
116 | u64 nested_cr3; | |
e6aa9abd JR |
117 | }; |
118 | ||
323c3d80 JR |
119 | #define MSRPM_OFFSETS 16 |
120 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
121 | ||
2b036c6b BO |
122 | /* |
123 | * Set osvw_len to higher value when updated Revision Guides | |
124 | * are published and we know what the new status bits are | |
125 | */ | |
126 | static uint64_t osvw_len = 4, osvw_status; | |
127 | ||
6c8166a7 AK |
128 | struct vcpu_svm { |
129 | struct kvm_vcpu vcpu; | |
130 | struct vmcb *vmcb; | |
131 | unsigned long vmcb_pa; | |
132 | struct svm_cpu_data *svm_data; | |
133 | uint64_t asid_generation; | |
134 | uint64_t sysenter_esp; | |
135 | uint64_t sysenter_eip; | |
136 | ||
137 | u64 next_rip; | |
138 | ||
139 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
afe9e66f | 140 | struct { |
dacccfdd AK |
141 | u16 fs; |
142 | u16 gs; | |
143 | u16 ldt; | |
afe9e66f AK |
144 | u64 gs_base; |
145 | } host; | |
6c8166a7 AK |
146 | |
147 | u32 *msrpm; | |
6c8166a7 | 148 | |
bd3d1ec3 AK |
149 | ulong nmi_iret_rip; |
150 | ||
e6aa9abd | 151 | struct nested_state nested; |
6be7d306 JK |
152 | |
153 | bool nmi_singlestep; | |
66b7138f JK |
154 | |
155 | unsigned int3_injected; | |
156 | unsigned long int3_rip; | |
631bc487 | 157 | u32 apf_reason; |
fbc0db76 JR |
158 | |
159 | u64 tsc_ratio; | |
6c8166a7 AK |
160 | }; |
161 | ||
fbc0db76 JR |
162 | static DEFINE_PER_CPU(u64, current_tsc_ratio); |
163 | #define TSC_RATIO_DEFAULT 0x0100000000ULL | |
164 | ||
455716fa JR |
165 | #define MSR_INVALID 0xffffffffU |
166 | ||
09941fbb | 167 | static const struct svm_direct_access_msrs { |
ac72a9b7 JR |
168 | u32 index; /* Index of the MSR */ |
169 | bool always; /* True if intercept is always on */ | |
170 | } direct_access_msrs[] = { | |
8c06585d | 171 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
172 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
173 | #ifdef CONFIG_X86_64 | |
174 | { .index = MSR_GS_BASE, .always = true }, | |
175 | { .index = MSR_FS_BASE, .always = true }, | |
176 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
177 | { .index = MSR_LSTAR, .always = true }, | |
178 | { .index = MSR_CSTAR, .always = true }, | |
179 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
180 | #endif | |
181 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, | |
182 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
183 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
184 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
185 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
186 | }; |
187 | ||
709ddebf JR |
188 | /* enable NPT for AMD64 and X86 with PAE */ |
189 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
190 | static bool npt_enabled = true; | |
191 | #else | |
e0231715 | 192 | static bool npt_enabled; |
709ddebf | 193 | #endif |
6c7dac72 | 194 | |
e2358851 DB |
195 | /* allow nested paging (virtualized MMU) for all guests */ |
196 | static int npt = true; | |
6c7dac72 | 197 | module_param(npt, int, S_IRUGO); |
e3da3acd | 198 | |
e2358851 DB |
199 | /* allow nested virtualization in KVM/SVM */ |
200 | static int nested = true; | |
236de055 AG |
201 | module_param(nested, int, S_IRUGO); |
202 | ||
44874f84 | 203 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 204 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 205 | |
410e4d57 | 206 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 207 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 208 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
209 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
210 | bool has_error_code, u32 error_code); | |
92a1f12d | 211 | static u64 __scale_tsc(u64 ratio, u64 tsc); |
cf74a78b | 212 | |
8d28fec4 | 213 | enum { |
116a0a23 JR |
214 | VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, |
215 | pause filter count */ | |
f56838e4 | 216 | VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ |
d48086d1 | 217 | VMCB_ASID, /* ASID */ |
decdbf6a | 218 | VMCB_INTR, /* int_ctl, int_vector */ |
b2747166 | 219 | VMCB_NPT, /* npt_en, nCR3, gPAT */ |
dcca1a65 | 220 | VMCB_CR, /* CR0, CR3, CR4, EFER */ |
72214b96 | 221 | VMCB_DR, /* DR6, DR7 */ |
17a703cb | 222 | VMCB_DT, /* GDT, IDT */ |
060d0c9a | 223 | VMCB_SEG, /* CS, DS, SS, ES, CPL */ |
0574dec0 | 224 | VMCB_CR2, /* CR2 only */ |
b53ba3f9 | 225 | VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ |
8d28fec4 RJ |
226 | VMCB_DIRTY_MAX, |
227 | }; | |
228 | ||
0574dec0 JR |
229 | /* TPR and CR2 are always written before VMRUN */ |
230 | #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) | |
8d28fec4 RJ |
231 | |
232 | static inline void mark_all_dirty(struct vmcb *vmcb) | |
233 | { | |
234 | vmcb->control.clean = 0; | |
235 | } | |
236 | ||
237 | static inline void mark_all_clean(struct vmcb *vmcb) | |
238 | { | |
239 | vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) | |
240 | & ~VMCB_ALWAYS_DIRTY_MASK; | |
241 | } | |
242 | ||
243 | static inline void mark_dirty(struct vmcb *vmcb, int bit) | |
244 | { | |
245 | vmcb->control.clean &= ~(1 << bit); | |
246 | } | |
247 | ||
a2fa3e9f GH |
248 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
249 | { | |
fb3f0f51 | 250 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
251 | } |
252 | ||
384c6368 JR |
253 | static void recalc_intercepts(struct vcpu_svm *svm) |
254 | { | |
255 | struct vmcb_control_area *c, *h; | |
256 | struct nested_state *g; | |
257 | ||
116a0a23 JR |
258 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
259 | ||
384c6368 JR |
260 | if (!is_guest_mode(&svm->vcpu)) |
261 | return; | |
262 | ||
263 | c = &svm->vmcb->control; | |
264 | h = &svm->nested.hsave->control; | |
265 | g = &svm->nested; | |
266 | ||
4ee546b4 | 267 | c->intercept_cr = h->intercept_cr | g->intercept_cr; |
3aed041a | 268 | c->intercept_dr = h->intercept_dr | g->intercept_dr; |
384c6368 JR |
269 | c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions; |
270 | c->intercept = h->intercept | g->intercept; | |
271 | } | |
272 | ||
4ee546b4 RJ |
273 | static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) |
274 | { | |
275 | if (is_guest_mode(&svm->vcpu)) | |
276 | return svm->nested.hsave; | |
277 | else | |
278 | return svm->vmcb; | |
279 | } | |
280 | ||
281 | static inline void set_cr_intercept(struct vcpu_svm *svm, int bit) | |
282 | { | |
283 | struct vmcb *vmcb = get_host_vmcb(svm); | |
284 | ||
285 | vmcb->control.intercept_cr |= (1U << bit); | |
286 | ||
287 | recalc_intercepts(svm); | |
288 | } | |
289 | ||
290 | static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit) | |
291 | { | |
292 | struct vmcb *vmcb = get_host_vmcb(svm); | |
293 | ||
294 | vmcb->control.intercept_cr &= ~(1U << bit); | |
295 | ||
296 | recalc_intercepts(svm); | |
297 | } | |
298 | ||
299 | static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit) | |
300 | { | |
301 | struct vmcb *vmcb = get_host_vmcb(svm); | |
302 | ||
303 | return vmcb->control.intercept_cr & (1U << bit); | |
304 | } | |
305 | ||
3aed041a JR |
306 | static inline void set_dr_intercept(struct vcpu_svm *svm, int bit) |
307 | { | |
308 | struct vmcb *vmcb = get_host_vmcb(svm); | |
309 | ||
310 | vmcb->control.intercept_dr |= (1U << bit); | |
311 | ||
312 | recalc_intercepts(svm); | |
313 | } | |
314 | ||
315 | static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit) | |
316 | { | |
317 | struct vmcb *vmcb = get_host_vmcb(svm); | |
318 | ||
319 | vmcb->control.intercept_dr &= ~(1U << bit); | |
320 | ||
321 | recalc_intercepts(svm); | |
322 | } | |
323 | ||
18c918c5 JR |
324 | static inline void set_exception_intercept(struct vcpu_svm *svm, int bit) |
325 | { | |
326 | struct vmcb *vmcb = get_host_vmcb(svm); | |
327 | ||
328 | vmcb->control.intercept_exceptions |= (1U << bit); | |
329 | ||
330 | recalc_intercepts(svm); | |
331 | } | |
332 | ||
333 | static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit) | |
334 | { | |
335 | struct vmcb *vmcb = get_host_vmcb(svm); | |
336 | ||
337 | vmcb->control.intercept_exceptions &= ~(1U << bit); | |
338 | ||
339 | recalc_intercepts(svm); | |
340 | } | |
341 | ||
8a05a1b8 JR |
342 | static inline void set_intercept(struct vcpu_svm *svm, int bit) |
343 | { | |
344 | struct vmcb *vmcb = get_host_vmcb(svm); | |
345 | ||
346 | vmcb->control.intercept |= (1ULL << bit); | |
347 | ||
348 | recalc_intercepts(svm); | |
349 | } | |
350 | ||
351 | static inline void clr_intercept(struct vcpu_svm *svm, int bit) | |
352 | { | |
353 | struct vmcb *vmcb = get_host_vmcb(svm); | |
354 | ||
355 | vmcb->control.intercept &= ~(1ULL << bit); | |
356 | ||
357 | recalc_intercepts(svm); | |
358 | } | |
359 | ||
2af9194d JR |
360 | static inline void enable_gif(struct vcpu_svm *svm) |
361 | { | |
362 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
363 | } | |
364 | ||
365 | static inline void disable_gif(struct vcpu_svm *svm) | |
366 | { | |
367 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
368 | } | |
369 | ||
370 | static inline bool gif_set(struct vcpu_svm *svm) | |
371 | { | |
372 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
373 | } | |
374 | ||
4866d5e3 | 375 | static unsigned long iopm_base; |
6aa8b732 AK |
376 | |
377 | struct kvm_ldttss_desc { | |
378 | u16 limit0; | |
379 | u16 base0; | |
e0231715 JR |
380 | unsigned base1:8, type:5, dpl:2, p:1; |
381 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
382 | u32 base3; |
383 | u32 zero1; | |
384 | } __attribute__((packed)); | |
385 | ||
386 | struct svm_cpu_data { | |
387 | int cpu; | |
388 | ||
5008fdf5 AK |
389 | u64 asid_generation; |
390 | u32 max_asid; | |
391 | u32 next_asid; | |
6aa8b732 AK |
392 | struct kvm_ldttss_desc *tss_desc; |
393 | ||
394 | struct page *save_area; | |
395 | }; | |
396 | ||
397 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
398 | ||
399 | struct svm_init_data { | |
400 | int cpu; | |
401 | int r; | |
402 | }; | |
403 | ||
09941fbb | 404 | static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; |
6aa8b732 | 405 | |
9d8f549d | 406 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
407 | #define MSRS_RANGE_SIZE 2048 |
408 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
409 | ||
455716fa JR |
410 | static u32 svm_msrpm_offset(u32 msr) |
411 | { | |
412 | u32 offset; | |
413 | int i; | |
414 | ||
415 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
416 | if (msr < msrpm_ranges[i] || | |
417 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
418 | continue; | |
419 | ||
420 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
421 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
422 | ||
423 | /* Now we have the u8 offset - but need the u32 offset */ | |
424 | return offset / 4; | |
425 | } | |
426 | ||
427 | /* MSR not in any range */ | |
428 | return MSR_INVALID; | |
429 | } | |
430 | ||
6aa8b732 AK |
431 | #define MAX_INST_SIZE 15 |
432 | ||
6aa8b732 AK |
433 | static inline void clgi(void) |
434 | { | |
4ecac3fd | 435 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
436 | } |
437 | ||
438 | static inline void stgi(void) | |
439 | { | |
4ecac3fd | 440 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
441 | } |
442 | ||
443 | static inline void invlpga(unsigned long addr, u32 asid) | |
444 | { | |
e0231715 | 445 | asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); |
6aa8b732 AK |
446 | } |
447 | ||
4b16184c JR |
448 | static int get_npt_level(void) |
449 | { | |
450 | #ifdef CONFIG_X86_64 | |
451 | return PT64_ROOT_LEVEL; | |
452 | #else | |
453 | return PT32E_ROOT_LEVEL; | |
454 | #endif | |
455 | } | |
456 | ||
6aa8b732 AK |
457 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
458 | { | |
6dc696d4 | 459 | vcpu->arch.efer = efer; |
709ddebf | 460 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 461 | efer &= ~EFER_LME; |
6aa8b732 | 462 | |
9962d032 | 463 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
dcca1a65 | 464 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
6aa8b732 AK |
465 | } |
466 | ||
6aa8b732 AK |
467 | static int is_external_interrupt(u32 info) |
468 | { | |
469 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
470 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
471 | } | |
472 | ||
2809f5d2 GC |
473 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
474 | { | |
475 | struct vcpu_svm *svm = to_svm(vcpu); | |
476 | u32 ret = 0; | |
477 | ||
478 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
48005f64 | 479 | ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 GC |
480 | return ret & mask; |
481 | } | |
482 | ||
483 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
484 | { | |
485 | struct vcpu_svm *svm = to_svm(vcpu); | |
486 | ||
487 | if (mask == 0) | |
488 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
489 | else | |
490 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
491 | ||
492 | } | |
493 | ||
6aa8b732 AK |
494 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
495 | { | |
a2fa3e9f GH |
496 | struct vcpu_svm *svm = to_svm(vcpu); |
497 | ||
6bc31bdc AP |
498 | if (svm->vmcb->control.next_rip != 0) |
499 | svm->next_rip = svm->vmcb->control.next_rip; | |
500 | ||
a2fa3e9f | 501 | if (!svm->next_rip) { |
51d8b661 | 502 | if (emulate_instruction(vcpu, EMULTYPE_SKIP) != |
f629cf84 GN |
503 | EMULATE_DONE) |
504 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
505 | return; |
506 | } | |
5fdbf976 MT |
507 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
508 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
509 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 510 | |
5fdbf976 | 511 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 512 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
513 | } |
514 | ||
116a4752 | 515 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
516 | bool has_error_code, u32 error_code, |
517 | bool reinject) | |
116a4752 JK |
518 | { |
519 | struct vcpu_svm *svm = to_svm(vcpu); | |
520 | ||
e0231715 JR |
521 | /* |
522 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
523 | * handle the exception | |
524 | */ | |
ce7ddec4 JR |
525 | if (!reinject && |
526 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
527 | return; |
528 | ||
2a6b20b8 | 529 | if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) { |
66b7138f JK |
530 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); |
531 | ||
532 | /* | |
533 | * For guest debugging where we have to reinject #BP if some | |
534 | * INT3 is guest-owned: | |
535 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
536 | * raises a fault that is not intercepted. Still better than | |
537 | * failing in all cases. | |
538 | */ | |
539 | skip_emulated_instruction(&svm->vcpu); | |
540 | rip = kvm_rip_read(&svm->vcpu); | |
541 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
542 | svm->int3_injected = rip - old_rip; | |
543 | } | |
544 | ||
116a4752 JK |
545 | svm->vmcb->control.event_inj = nr |
546 | | SVM_EVTINJ_VALID | |
547 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
548 | | SVM_EVTINJ_TYPE_EXEPT; | |
549 | svm->vmcb->control.event_inj_err = error_code; | |
550 | } | |
551 | ||
67ec6607 JR |
552 | static void svm_init_erratum_383(void) |
553 | { | |
554 | u32 low, high; | |
555 | int err; | |
556 | u64 val; | |
557 | ||
e6ee94d5 | 558 | if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH)) |
67ec6607 JR |
559 | return; |
560 | ||
561 | /* Use _safe variants to not break nested virtualization */ | |
562 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
563 | if (err) | |
564 | return; | |
565 | ||
566 | val |= (1ULL << 47); | |
567 | ||
568 | low = lower_32_bits(val); | |
569 | high = upper_32_bits(val); | |
570 | ||
571 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
572 | ||
573 | erratum_383_found = true; | |
574 | } | |
575 | ||
2b036c6b BO |
576 | static void svm_init_osvw(struct kvm_vcpu *vcpu) |
577 | { | |
578 | /* | |
579 | * Guests should see errata 400 and 415 as fixed (assuming that | |
580 | * HLT and IO instructions are intercepted). | |
581 | */ | |
582 | vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3; | |
583 | vcpu->arch.osvw.status = osvw_status & ~(6ULL); | |
584 | ||
585 | /* | |
586 | * By increasing VCPU's osvw.length to 3 we are telling the guest that | |
587 | * all osvw.status bits inside that length, including bit 0 (which is | |
588 | * reserved for erratum 298), are valid. However, if host processor's | |
589 | * osvw_len is 0 then osvw_status[0] carries no information. We need to | |
590 | * be conservative here and therefore we tell the guest that erratum 298 | |
591 | * is present (because we really don't know). | |
592 | */ | |
593 | if (osvw_len == 0 && boot_cpu_data.x86 == 0x10) | |
594 | vcpu->arch.osvw.status |= 1; | |
595 | } | |
596 | ||
6aa8b732 AK |
597 | static int has_svm(void) |
598 | { | |
63d1142f | 599 | const char *msg; |
6aa8b732 | 600 | |
63d1142f | 601 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 602 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
603 | return 0; |
604 | } | |
605 | ||
6aa8b732 AK |
606 | return 1; |
607 | } | |
608 | ||
609 | static void svm_hardware_disable(void *garbage) | |
610 | { | |
fbc0db76 JR |
611 | /* Make sure we clean up behind us */ |
612 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) | |
613 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
614 | ||
2c8dceeb | 615 | cpu_svm_disable(); |
1018faa6 JR |
616 | |
617 | amd_pmu_disable_virt(); | |
6aa8b732 AK |
618 | } |
619 | ||
10474ae8 | 620 | static int svm_hardware_enable(void *garbage) |
6aa8b732 AK |
621 | { |
622 | ||
0fe1e009 | 623 | struct svm_cpu_data *sd; |
6aa8b732 | 624 | uint64_t efer; |
89a27f4d | 625 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
626 | struct desc_struct *gdt; |
627 | int me = raw_smp_processor_id(); | |
628 | ||
10474ae8 AG |
629 | rdmsrl(MSR_EFER, efer); |
630 | if (efer & EFER_SVME) | |
631 | return -EBUSY; | |
632 | ||
6aa8b732 | 633 | if (!has_svm()) { |
1f5b77f5 | 634 | pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me); |
10474ae8 | 635 | return -EINVAL; |
6aa8b732 | 636 | } |
0fe1e009 | 637 | sd = per_cpu(svm_data, me); |
0fe1e009 | 638 | if (!sd) { |
1f5b77f5 | 639 | pr_err("%s: svm_data is NULL on %d\n", __func__, me); |
10474ae8 | 640 | return -EINVAL; |
6aa8b732 AK |
641 | } |
642 | ||
0fe1e009 TH |
643 | sd->asid_generation = 1; |
644 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
645 | sd->next_asid = sd->max_asid + 1; | |
6aa8b732 | 646 | |
d6ab1ed4 | 647 | native_store_gdt(&gdt_descr); |
89a27f4d | 648 | gdt = (struct desc_struct *)gdt_descr.address; |
0fe1e009 | 649 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 650 | |
9962d032 | 651 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 652 | |
d0316554 | 653 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 654 | |
fbc0db76 JR |
655 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
656 | wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT); | |
657 | __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT; | |
658 | } | |
659 | ||
2b036c6b BO |
660 | |
661 | /* | |
662 | * Get OSVW bits. | |
663 | * | |
664 | * Note that it is possible to have a system with mixed processor | |
665 | * revisions and therefore different OSVW bits. If bits are not the same | |
666 | * on different processors then choose the worst case (i.e. if erratum | |
667 | * is present on one processor and not on another then assume that the | |
668 | * erratum is present everywhere). | |
669 | */ | |
670 | if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) { | |
671 | uint64_t len, status = 0; | |
672 | int err; | |
673 | ||
674 | len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err); | |
675 | if (!err) | |
676 | status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS, | |
677 | &err); | |
678 | ||
679 | if (err) | |
680 | osvw_status = osvw_len = 0; | |
681 | else { | |
682 | if (len < osvw_len) | |
683 | osvw_len = len; | |
684 | osvw_status |= status; | |
685 | osvw_status &= (1ULL << osvw_len) - 1; | |
686 | } | |
687 | } else | |
688 | osvw_status = osvw_len = 0; | |
689 | ||
67ec6607 JR |
690 | svm_init_erratum_383(); |
691 | ||
1018faa6 JR |
692 | amd_pmu_enable_virt(); |
693 | ||
10474ae8 | 694 | return 0; |
6aa8b732 AK |
695 | } |
696 | ||
0da1db75 JR |
697 | static void svm_cpu_uninit(int cpu) |
698 | { | |
0fe1e009 | 699 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 700 | |
0fe1e009 | 701 | if (!sd) |
0da1db75 JR |
702 | return; |
703 | ||
704 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
0fe1e009 TH |
705 | __free_page(sd->save_area); |
706 | kfree(sd); | |
0da1db75 JR |
707 | } |
708 | ||
6aa8b732 AK |
709 | static int svm_cpu_init(int cpu) |
710 | { | |
0fe1e009 | 711 | struct svm_cpu_data *sd; |
6aa8b732 AK |
712 | int r; |
713 | ||
0fe1e009 TH |
714 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
715 | if (!sd) | |
6aa8b732 | 716 | return -ENOMEM; |
0fe1e009 TH |
717 | sd->cpu = cpu; |
718 | sd->save_area = alloc_page(GFP_KERNEL); | |
6aa8b732 | 719 | r = -ENOMEM; |
0fe1e009 | 720 | if (!sd->save_area) |
6aa8b732 AK |
721 | goto err_1; |
722 | ||
0fe1e009 | 723 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
724 | |
725 | return 0; | |
726 | ||
727 | err_1: | |
0fe1e009 | 728 | kfree(sd); |
6aa8b732 AK |
729 | return r; |
730 | ||
731 | } | |
732 | ||
ac72a9b7 JR |
733 | static bool valid_msr_intercept(u32 index) |
734 | { | |
735 | int i; | |
736 | ||
737 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
738 | if (direct_access_msrs[i].index == index) | |
739 | return true; | |
740 | ||
741 | return false; | |
742 | } | |
743 | ||
bfc733a7 RR |
744 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
745 | int read, int write) | |
6aa8b732 | 746 | { |
455716fa JR |
747 | u8 bit_read, bit_write; |
748 | unsigned long tmp; | |
749 | u32 offset; | |
6aa8b732 | 750 | |
ac72a9b7 JR |
751 | /* |
752 | * If this warning triggers extend the direct_access_msrs list at the | |
753 | * beginning of the file | |
754 | */ | |
755 | WARN_ON(!valid_msr_intercept(msr)); | |
756 | ||
455716fa JR |
757 | offset = svm_msrpm_offset(msr); |
758 | bit_read = 2 * (msr & 0x0f); | |
759 | bit_write = 2 * (msr & 0x0f) + 1; | |
760 | tmp = msrpm[offset]; | |
761 | ||
762 | BUG_ON(offset == MSR_INVALID); | |
763 | ||
764 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
765 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
766 | ||
767 | msrpm[offset] = tmp; | |
6aa8b732 AK |
768 | } |
769 | ||
f65c229c | 770 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
771 | { |
772 | int i; | |
773 | ||
f65c229c JR |
774 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
775 | ||
ac72a9b7 JR |
776 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
777 | if (!direct_access_msrs[i].always) | |
778 | continue; | |
779 | ||
780 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
781 | } | |
f65c229c JR |
782 | } |
783 | ||
323c3d80 JR |
784 | static void add_msr_offset(u32 offset) |
785 | { | |
786 | int i; | |
787 | ||
788 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
789 | ||
790 | /* Offset already in list? */ | |
791 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 792 | return; |
323c3d80 JR |
793 | |
794 | /* Slot used by another offset? */ | |
795 | if (msrpm_offsets[i] != MSR_INVALID) | |
796 | continue; | |
797 | ||
798 | /* Add offset to list */ | |
799 | msrpm_offsets[i] = offset; | |
800 | ||
801 | return; | |
6aa8b732 | 802 | } |
323c3d80 JR |
803 | |
804 | /* | |
805 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
806 | * increase MSRPM_OFFSETS in this case. | |
807 | */ | |
bfc733a7 | 808 | BUG(); |
6aa8b732 AK |
809 | } |
810 | ||
323c3d80 | 811 | static void init_msrpm_offsets(void) |
f65c229c | 812 | { |
323c3d80 | 813 | int i; |
f65c229c | 814 | |
323c3d80 JR |
815 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
816 | ||
817 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
818 | u32 offset; | |
819 | ||
820 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
821 | BUG_ON(offset == MSR_INVALID); | |
822 | ||
823 | add_msr_offset(offset); | |
824 | } | |
f65c229c JR |
825 | } |
826 | ||
24e09cbf JR |
827 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
828 | { | |
829 | u32 *msrpm = svm->msrpm; | |
830 | ||
831 | svm->vmcb->control.lbr_ctl = 1; | |
832 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
833 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
834 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
835 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
836 | } | |
837 | ||
838 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
839 | { | |
840 | u32 *msrpm = svm->msrpm; | |
841 | ||
842 | svm->vmcb->control.lbr_ctl = 0; | |
843 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
844 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
845 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
846 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
847 | } | |
848 | ||
6aa8b732 AK |
849 | static __init int svm_hardware_setup(void) |
850 | { | |
851 | int cpu; | |
852 | struct page *iopm_pages; | |
f65c229c | 853 | void *iopm_va; |
6aa8b732 AK |
854 | int r; |
855 | ||
6aa8b732 AK |
856 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
857 | ||
858 | if (!iopm_pages) | |
859 | return -ENOMEM; | |
c8681339 AL |
860 | |
861 | iopm_va = page_address(iopm_pages); | |
862 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
863 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
864 | ||
323c3d80 JR |
865 | init_msrpm_offsets(); |
866 | ||
50a37eb4 JR |
867 | if (boot_cpu_has(X86_FEATURE_NX)) |
868 | kvm_enable_efer_bits(EFER_NX); | |
869 | ||
1b2fd70c AG |
870 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
871 | kvm_enable_efer_bits(EFER_FFXSR); | |
872 | ||
92a1f12d JR |
873 | if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) { |
874 | u64 max; | |
875 | ||
876 | kvm_has_tsc_control = true; | |
877 | ||
878 | /* | |
879 | * Make sure the user can only configure tsc_khz values that | |
880 | * fit into a signed integer. | |
881 | * A min value is not calculated needed because it will always | |
882 | * be 1 on all machines and a value of 0 is used to disable | |
883 | * tsc-scaling for the vcpu. | |
884 | */ | |
885 | max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX)); | |
886 | ||
887 | kvm_max_guest_tsc_khz = max; | |
888 | } | |
889 | ||
236de055 AG |
890 | if (nested) { |
891 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 892 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
893 | } |
894 | ||
3230bb47 | 895 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
896 | r = svm_cpu_init(cpu); |
897 | if (r) | |
f65c229c | 898 | goto err; |
6aa8b732 | 899 | } |
33bd6a0b | 900 | |
2a6b20b8 | 901 | if (!boot_cpu_has(X86_FEATURE_NPT)) |
e3da3acd JR |
902 | npt_enabled = false; |
903 | ||
6c7dac72 JR |
904 | if (npt_enabled && !npt) { |
905 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
906 | npt_enabled = false; | |
907 | } | |
908 | ||
18552672 | 909 | if (npt_enabled) { |
e3da3acd | 910 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 911 | kvm_enable_tdp(); |
5f4cb662 JR |
912 | } else |
913 | kvm_disable_tdp(); | |
e3da3acd | 914 | |
6aa8b732 AK |
915 | return 0; |
916 | ||
f65c229c | 917 | err: |
6aa8b732 AK |
918 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
919 | iopm_base = 0; | |
920 | return r; | |
921 | } | |
922 | ||
923 | static __exit void svm_hardware_unsetup(void) | |
924 | { | |
0da1db75 JR |
925 | int cpu; |
926 | ||
3230bb47 | 927 | for_each_possible_cpu(cpu) |
0da1db75 JR |
928 | svm_cpu_uninit(cpu); |
929 | ||
6aa8b732 | 930 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 931 | iopm_base = 0; |
6aa8b732 AK |
932 | } |
933 | ||
934 | static void init_seg(struct vmcb_seg *seg) | |
935 | { | |
936 | seg->selector = 0; | |
937 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 938 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
939 | seg->limit = 0xffff; |
940 | seg->base = 0; | |
941 | } | |
942 | ||
943 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
944 | { | |
945 | seg->selector = 0; | |
946 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
947 | seg->limit = 0xffff; | |
948 | seg->base = 0; | |
949 | } | |
950 | ||
fbc0db76 JR |
951 | static u64 __scale_tsc(u64 ratio, u64 tsc) |
952 | { | |
953 | u64 mult, frac, _tsc; | |
954 | ||
955 | mult = ratio >> 32; | |
956 | frac = ratio & ((1ULL << 32) - 1); | |
957 | ||
958 | _tsc = tsc; | |
959 | _tsc *= mult; | |
960 | _tsc += (tsc >> 32) * frac; | |
961 | _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32; | |
962 | ||
963 | return _tsc; | |
964 | } | |
965 | ||
966 | static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) | |
967 | { | |
968 | struct vcpu_svm *svm = to_svm(vcpu); | |
969 | u64 _tsc = tsc; | |
970 | ||
971 | if (svm->tsc_ratio != TSC_RATIO_DEFAULT) | |
972 | _tsc = __scale_tsc(svm->tsc_ratio, tsc); | |
973 | ||
974 | return _tsc; | |
975 | } | |
976 | ||
cc578287 | 977 | static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
4051b188 JR |
978 | { |
979 | struct vcpu_svm *svm = to_svm(vcpu); | |
980 | u64 ratio; | |
981 | u64 khz; | |
982 | ||
cc578287 ZA |
983 | /* Guest TSC same frequency as host TSC? */ |
984 | if (!scale) { | |
985 | svm->tsc_ratio = TSC_RATIO_DEFAULT; | |
4051b188 | 986 | return; |
cc578287 | 987 | } |
4051b188 | 988 | |
cc578287 ZA |
989 | /* TSC scaling supported? */ |
990 | if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) { | |
991 | if (user_tsc_khz > tsc_khz) { | |
992 | vcpu->arch.tsc_catchup = 1; | |
993 | vcpu->arch.tsc_always_catchup = 1; | |
994 | } else | |
995 | WARN(1, "user requested TSC rate below hardware speed\n"); | |
4051b188 JR |
996 | return; |
997 | } | |
998 | ||
999 | khz = user_tsc_khz; | |
1000 | ||
1001 | /* TSC scaling required - calculate ratio */ | |
1002 | ratio = khz << 32; | |
1003 | do_div(ratio, tsc_khz); | |
1004 | ||
1005 | if (ratio == 0 || ratio & TSC_RATIO_RSVD) { | |
1006 | WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n", | |
1007 | user_tsc_khz); | |
1008 | return; | |
1009 | } | |
4051b188 JR |
1010 | svm->tsc_ratio = ratio; |
1011 | } | |
1012 | ||
ba904635 WA |
1013 | static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu) |
1014 | { | |
1015 | struct vcpu_svm *svm = to_svm(vcpu); | |
1016 | ||
1017 | return svm->vmcb->control.tsc_offset; | |
1018 | } | |
1019 | ||
f4e1b3c8 ZA |
1020 | static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
1021 | { | |
1022 | struct vcpu_svm *svm = to_svm(vcpu); | |
1023 | u64 g_tsc_offset = 0; | |
1024 | ||
2030753d | 1025 | if (is_guest_mode(vcpu)) { |
f4e1b3c8 ZA |
1026 | g_tsc_offset = svm->vmcb->control.tsc_offset - |
1027 | svm->nested.hsave->control.tsc_offset; | |
1028 | svm->nested.hsave->control.tsc_offset = offset; | |
1029 | } | |
1030 | ||
1031 | svm->vmcb->control.tsc_offset = offset + g_tsc_offset; | |
116a0a23 JR |
1032 | |
1033 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); | |
f4e1b3c8 ZA |
1034 | } |
1035 | ||
f1e2b260 | 1036 | static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host) |
e48672fa ZA |
1037 | { |
1038 | struct vcpu_svm *svm = to_svm(vcpu); | |
1039 | ||
f1e2b260 MT |
1040 | WARN_ON(adjustment < 0); |
1041 | if (host) | |
1042 | adjustment = svm_scale_tsc(vcpu, adjustment); | |
1043 | ||
e48672fa | 1044 | svm->vmcb->control.tsc_offset += adjustment; |
2030753d | 1045 | if (is_guest_mode(vcpu)) |
e48672fa | 1046 | svm->nested.hsave->control.tsc_offset += adjustment; |
116a0a23 | 1047 | mark_dirty(svm->vmcb, VMCB_INTERCEPTS); |
e48672fa ZA |
1048 | } |
1049 | ||
857e4099 JR |
1050 | static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
1051 | { | |
1052 | u64 tsc; | |
1053 | ||
1054 | tsc = svm_scale_tsc(vcpu, native_read_tsc()); | |
1055 | ||
1056 | return target_tsc - tsc; | |
1057 | } | |
1058 | ||
e6101a96 | 1059 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 1060 | { |
e6101a96 JR |
1061 | struct vmcb_control_area *control = &svm->vmcb->control; |
1062 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 1063 | |
bff78274 | 1064 | svm->vcpu.fpu_active = 1; |
4ee546b4 | 1065 | svm->vcpu.arch.hflags = 0; |
bff78274 | 1066 | |
4ee546b4 RJ |
1067 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1068 | set_cr_intercept(svm, INTERCEPT_CR3_READ); | |
1069 | set_cr_intercept(svm, INTERCEPT_CR4_READ); | |
1070 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
1071 | set_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
1072 | set_cr_intercept(svm, INTERCEPT_CR4_WRITE); | |
1073 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
6aa8b732 | 1074 | |
3aed041a JR |
1075 | set_dr_intercept(svm, INTERCEPT_DR0_READ); |
1076 | set_dr_intercept(svm, INTERCEPT_DR1_READ); | |
1077 | set_dr_intercept(svm, INTERCEPT_DR2_READ); | |
1078 | set_dr_intercept(svm, INTERCEPT_DR3_READ); | |
1079 | set_dr_intercept(svm, INTERCEPT_DR4_READ); | |
1080 | set_dr_intercept(svm, INTERCEPT_DR5_READ); | |
1081 | set_dr_intercept(svm, INTERCEPT_DR6_READ); | |
1082 | set_dr_intercept(svm, INTERCEPT_DR7_READ); | |
1083 | ||
1084 | set_dr_intercept(svm, INTERCEPT_DR0_WRITE); | |
1085 | set_dr_intercept(svm, INTERCEPT_DR1_WRITE); | |
1086 | set_dr_intercept(svm, INTERCEPT_DR2_WRITE); | |
1087 | set_dr_intercept(svm, INTERCEPT_DR3_WRITE); | |
1088 | set_dr_intercept(svm, INTERCEPT_DR4_WRITE); | |
1089 | set_dr_intercept(svm, INTERCEPT_DR5_WRITE); | |
1090 | set_dr_intercept(svm, INTERCEPT_DR6_WRITE); | |
1091 | set_dr_intercept(svm, INTERCEPT_DR7_WRITE); | |
6aa8b732 | 1092 | |
18c918c5 JR |
1093 | set_exception_intercept(svm, PF_VECTOR); |
1094 | set_exception_intercept(svm, UD_VECTOR); | |
1095 | set_exception_intercept(svm, MC_VECTOR); | |
6aa8b732 | 1096 | |
8a05a1b8 JR |
1097 | set_intercept(svm, INTERCEPT_INTR); |
1098 | set_intercept(svm, INTERCEPT_NMI); | |
1099 | set_intercept(svm, INTERCEPT_SMI); | |
1100 | set_intercept(svm, INTERCEPT_SELECTIVE_CR0); | |
332b56e4 | 1101 | set_intercept(svm, INTERCEPT_RDPMC); |
8a05a1b8 JR |
1102 | set_intercept(svm, INTERCEPT_CPUID); |
1103 | set_intercept(svm, INTERCEPT_INVD); | |
1104 | set_intercept(svm, INTERCEPT_HLT); | |
1105 | set_intercept(svm, INTERCEPT_INVLPG); | |
1106 | set_intercept(svm, INTERCEPT_INVLPGA); | |
1107 | set_intercept(svm, INTERCEPT_IOIO_PROT); | |
1108 | set_intercept(svm, INTERCEPT_MSR_PROT); | |
1109 | set_intercept(svm, INTERCEPT_TASK_SWITCH); | |
1110 | set_intercept(svm, INTERCEPT_SHUTDOWN); | |
1111 | set_intercept(svm, INTERCEPT_VMRUN); | |
1112 | set_intercept(svm, INTERCEPT_VMMCALL); | |
1113 | set_intercept(svm, INTERCEPT_VMLOAD); | |
1114 | set_intercept(svm, INTERCEPT_VMSAVE); | |
1115 | set_intercept(svm, INTERCEPT_STGI); | |
1116 | set_intercept(svm, INTERCEPT_CLGI); | |
1117 | set_intercept(svm, INTERCEPT_SKINIT); | |
1118 | set_intercept(svm, INTERCEPT_WBINVD); | |
1119 | set_intercept(svm, INTERCEPT_MONITOR); | |
1120 | set_intercept(svm, INTERCEPT_MWAIT); | |
81dd35d4 | 1121 | set_intercept(svm, INTERCEPT_XSETBV); |
6aa8b732 AK |
1122 | |
1123 | control->iopm_base_pa = iopm_base; | |
f65c229c | 1124 | control->msrpm_base_pa = __pa(svm->msrpm); |
6aa8b732 AK |
1125 | control->int_ctl = V_INTR_MASKING_MASK; |
1126 | ||
1127 | init_seg(&save->es); | |
1128 | init_seg(&save->ss); | |
1129 | init_seg(&save->ds); | |
1130 | init_seg(&save->fs); | |
1131 | init_seg(&save->gs); | |
1132 | ||
1133 | save->cs.selector = 0xf000; | |
04b66839 | 1134 | save->cs.base = 0xffff0000; |
6aa8b732 AK |
1135 | /* Executable/Readable Code Segment */ |
1136 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
1137 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
1138 | save->cs.limit = 0xffff; | |
6aa8b732 AK |
1139 | |
1140 | save->gdtr.limit = 0xffff; | |
1141 | save->idtr.limit = 0xffff; | |
1142 | ||
1143 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
1144 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
1145 | ||
eaa48512 | 1146 | svm_set_efer(&svm->vcpu, 0); |
d77c26fc | 1147 | save->dr6 = 0xffff0ff0; |
f6e78475 | 1148 | kvm_set_rflags(&svm->vcpu, 2); |
6aa8b732 | 1149 | save->rip = 0x0000fff0; |
5fdbf976 | 1150 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 1151 | |
e0231715 JR |
1152 | /* |
1153 | * This is the guest-visible cr0 value. | |
18fa000a | 1154 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
6aa8b732 | 1155 | */ |
678041ad MT |
1156 | svm->vcpu.arch.cr0 = 0; |
1157 | (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); | |
18fa000a | 1158 | |
66aee91a | 1159 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 1160 | /* rdx = ?? */ |
709ddebf JR |
1161 | |
1162 | if (npt_enabled) { | |
1163 | /* Setup VMCB for Nested Paging */ | |
1164 | control->nested_ctl = 1; | |
8a05a1b8 | 1165 | clr_intercept(svm, INTERCEPT_INVLPG); |
18c918c5 | 1166 | clr_exception_intercept(svm, PF_VECTOR); |
4ee546b4 RJ |
1167 | clr_cr_intercept(svm, INTERCEPT_CR3_READ); |
1168 | clr_cr_intercept(svm, INTERCEPT_CR3_WRITE); | |
709ddebf | 1169 | save->g_pat = 0x0007040600070406ULL; |
709ddebf JR |
1170 | save->cr3 = 0; |
1171 | save->cr4 = 0; | |
1172 | } | |
f40f6a45 | 1173 | svm->asid_generation = 0; |
1371d904 | 1174 | |
e6aa9abd | 1175 | svm->nested.vmcb = 0; |
2af9194d JR |
1176 | svm->vcpu.arch.hflags = 0; |
1177 | ||
2a6b20b8 | 1178 | if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { |
565d0998 | 1179 | control->pause_filter_count = 3000; |
8a05a1b8 | 1180 | set_intercept(svm, INTERCEPT_PAUSE); |
565d0998 ML |
1181 | } |
1182 | ||
8d28fec4 RJ |
1183 | mark_all_dirty(svm->vmcb); |
1184 | ||
2af9194d | 1185 | enable_gif(svm); |
6aa8b732 AK |
1186 | } |
1187 | ||
57f252f2 | 1188 | static void svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
1189 | { |
1190 | struct vcpu_svm *svm = to_svm(vcpu); | |
66f7b72e JS |
1191 | u32 dummy; |
1192 | u32 eax = 1; | |
04d2cc77 | 1193 | |
e6101a96 | 1194 | init_vmcb(svm); |
70433389 | 1195 | |
66f7b72e JS |
1196 | kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy); |
1197 | kvm_register_write(vcpu, VCPU_REGS_RDX, eax); | |
04d2cc77 AK |
1198 | } |
1199 | ||
fb3f0f51 | 1200 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 1201 | { |
a2fa3e9f | 1202 | struct vcpu_svm *svm; |
6aa8b732 | 1203 | struct page *page; |
f65c229c | 1204 | struct page *msrpm_pages; |
b286d5d8 | 1205 | struct page *hsave_page; |
3d6368ef | 1206 | struct page *nested_msrpm_pages; |
fb3f0f51 | 1207 | int err; |
6aa8b732 | 1208 | |
c16f862d | 1209 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
1210 | if (!svm) { |
1211 | err = -ENOMEM; | |
1212 | goto out; | |
1213 | } | |
1214 | ||
fbc0db76 JR |
1215 | svm->tsc_ratio = TSC_RATIO_DEFAULT; |
1216 | ||
fb3f0f51 RR |
1217 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); |
1218 | if (err) | |
1219 | goto free_svm; | |
1220 | ||
b7af4043 | 1221 | err = -ENOMEM; |
6aa8b732 | 1222 | page = alloc_page(GFP_KERNEL); |
b7af4043 | 1223 | if (!page) |
fb3f0f51 | 1224 | goto uninit; |
6aa8b732 | 1225 | |
f65c229c JR |
1226 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); |
1227 | if (!msrpm_pages) | |
b7af4043 | 1228 | goto free_page1; |
3d6368ef AG |
1229 | |
1230 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
1231 | if (!nested_msrpm_pages) | |
b7af4043 | 1232 | goto free_page2; |
f65c229c | 1233 | |
b286d5d8 AG |
1234 | hsave_page = alloc_page(GFP_KERNEL); |
1235 | if (!hsave_page) | |
b7af4043 TY |
1236 | goto free_page3; |
1237 | ||
e6aa9abd | 1238 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 1239 | |
b7af4043 TY |
1240 | svm->msrpm = page_address(msrpm_pages); |
1241 | svm_vcpu_init_msrpm(svm->msrpm); | |
1242 | ||
e6aa9abd | 1243 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 1244 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 1245 | |
a2fa3e9f GH |
1246 | svm->vmcb = page_address(page); |
1247 | clear_page(svm->vmcb); | |
1248 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
1249 | svm->asid_generation = 0; | |
e6101a96 | 1250 | init_vmcb(svm); |
a2fa3e9f | 1251 | |
ad312c7c | 1252 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 1253 | if (kvm_vcpu_is_bsp(&svm->vcpu)) |
ad312c7c | 1254 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 1255 | |
2b036c6b BO |
1256 | svm_init_osvw(&svm->vcpu); |
1257 | ||
fb3f0f51 | 1258 | return &svm->vcpu; |
36241b8c | 1259 | |
b7af4043 TY |
1260 | free_page3: |
1261 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
1262 | free_page2: | |
1263 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
1264 | free_page1: | |
1265 | __free_page(page); | |
fb3f0f51 RR |
1266 | uninit: |
1267 | kvm_vcpu_uninit(&svm->vcpu); | |
1268 | free_svm: | |
a4770347 | 1269 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
1270 | out: |
1271 | return ERR_PTR(err); | |
6aa8b732 AK |
1272 | } |
1273 | ||
1274 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
1275 | { | |
a2fa3e9f GH |
1276 | struct vcpu_svm *svm = to_svm(vcpu); |
1277 | ||
fb3f0f51 | 1278 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 1279 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
1280 | __free_page(virt_to_page(svm->nested.hsave)); |
1281 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 1282 | kvm_vcpu_uninit(vcpu); |
a4770347 | 1283 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
1284 | } |
1285 | ||
15ad7146 | 1286 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 1287 | { |
a2fa3e9f | 1288 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 1289 | int i; |
0cc5064d | 1290 | |
0cc5064d | 1291 | if (unlikely(cpu != vcpu->cpu)) { |
4b656b12 | 1292 | svm->asid_generation = 0; |
8d28fec4 | 1293 | mark_all_dirty(svm->vmcb); |
0cc5064d | 1294 | } |
94dfbdb3 | 1295 | |
82ca2d10 AK |
1296 | #ifdef CONFIG_X86_64 |
1297 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); | |
1298 | #endif | |
dacccfdd AK |
1299 | savesegment(fs, svm->host.fs); |
1300 | savesegment(gs, svm->host.gs); | |
1301 | svm->host.ldt = kvm_read_ldt(); | |
1302 | ||
94dfbdb3 | 1303 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1304 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
fbc0db76 JR |
1305 | |
1306 | if (static_cpu_has(X86_FEATURE_TSCRATEMSR) && | |
1307 | svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) { | |
1308 | __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio; | |
1309 | wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio); | |
1310 | } | |
6aa8b732 AK |
1311 | } |
1312 | ||
1313 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
1314 | { | |
a2fa3e9f | 1315 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
1316 | int i; |
1317 | ||
e1beb1d3 | 1318 | ++vcpu->stat.host_state_reload; |
dacccfdd AK |
1319 | kvm_load_ldt(svm->host.ldt); |
1320 | #ifdef CONFIG_X86_64 | |
1321 | loadsegment(fs, svm->host.fs); | |
dacccfdd | 1322 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs); |
893a5ab6 | 1323 | load_gs_index(svm->host.gs); |
dacccfdd | 1324 | #else |
831ca609 | 1325 | #ifdef CONFIG_X86_32_LAZY_GS |
dacccfdd | 1326 | loadsegment(gs, svm->host.gs); |
831ca609 | 1327 | #endif |
dacccfdd | 1328 | #endif |
94dfbdb3 | 1329 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1330 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1331 | } |
1332 | ||
ea5e97e8 KW |
1333 | static void svm_update_cpl(struct kvm_vcpu *vcpu) |
1334 | { | |
1335 | struct vcpu_svm *svm = to_svm(vcpu); | |
1336 | int cpl; | |
1337 | ||
1338 | if (!is_protmode(vcpu)) | |
1339 | cpl = 0; | |
1340 | else if (svm->vmcb->save.rflags & X86_EFLAGS_VM) | |
1341 | cpl = 3; | |
1342 | else | |
1343 | cpl = svm->vmcb->save.cs.selector & 0x3; | |
1344 | ||
1345 | svm->vmcb->save.cpl = cpl; | |
1346 | } | |
1347 | ||
6aa8b732 AK |
1348 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
1349 | { | |
a2fa3e9f | 1350 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
1351 | } |
1352 | ||
1353 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
1354 | { | |
4cee4798 KW |
1355 | unsigned long old_rflags = to_svm(vcpu)->vmcb->save.rflags; |
1356 | ||
a2fa3e9f | 1357 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
4cee4798 KW |
1358 | if ((old_rflags ^ rflags) & X86_EFLAGS_VM) |
1359 | svm_update_cpl(vcpu); | |
6aa8b732 AK |
1360 | } |
1361 | ||
6de4f3ad AK |
1362 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
1363 | { | |
1364 | switch (reg) { | |
1365 | case VCPU_EXREG_PDPTR: | |
1366 | BUG_ON(!npt_enabled); | |
9f8fe504 | 1367 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
6de4f3ad AK |
1368 | break; |
1369 | default: | |
1370 | BUG(); | |
1371 | } | |
1372 | } | |
1373 | ||
f0b85051 AG |
1374 | static void svm_set_vintr(struct vcpu_svm *svm) |
1375 | { | |
8a05a1b8 | 1376 | set_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1377 | } |
1378 | ||
1379 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
1380 | { | |
8a05a1b8 | 1381 | clr_intercept(svm, INTERCEPT_VINTR); |
f0b85051 AG |
1382 | } |
1383 | ||
6aa8b732 AK |
1384 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
1385 | { | |
a2fa3e9f | 1386 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
1387 | |
1388 | switch (seg) { | |
1389 | case VCPU_SREG_CS: return &save->cs; | |
1390 | case VCPU_SREG_DS: return &save->ds; | |
1391 | case VCPU_SREG_ES: return &save->es; | |
1392 | case VCPU_SREG_FS: return &save->fs; | |
1393 | case VCPU_SREG_GS: return &save->gs; | |
1394 | case VCPU_SREG_SS: return &save->ss; | |
1395 | case VCPU_SREG_TR: return &save->tr; | |
1396 | case VCPU_SREG_LDTR: return &save->ldtr; | |
1397 | } | |
1398 | BUG(); | |
8b6d44c7 | 1399 | return NULL; |
6aa8b732 AK |
1400 | } |
1401 | ||
1402 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1403 | { | |
1404 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1405 | ||
1406 | return s->base; | |
1407 | } | |
1408 | ||
1409 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
1410 | struct kvm_segment *var, int seg) | |
1411 | { | |
1412 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1413 | ||
1414 | var->base = s->base; | |
1415 | var->limit = s->limit; | |
1416 | var->selector = s->selector; | |
1417 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
1418 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
1419 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
1420 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
1421 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
1422 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
1423 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
1424 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
25022acc | 1425 | |
e0231715 JR |
1426 | /* |
1427 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
1428 | * for cross vendor migration purposes by "not present" |
1429 | */ | |
1430 | var->unusable = !var->present || (var->type == 0); | |
1431 | ||
1fbdc7a5 AP |
1432 | switch (seg) { |
1433 | case VCPU_SREG_CS: | |
1434 | /* | |
1435 | * SVM always stores 0 for the 'G' bit in the CS selector in | |
1436 | * the VMCB on a VMEXIT. This hurts cross-vendor migration: | |
1437 | * Intel's VMENTRY has a check on the 'G' bit. | |
1438 | */ | |
25022acc | 1439 | var->g = s->limit > 0xfffff; |
1fbdc7a5 AP |
1440 | break; |
1441 | case VCPU_SREG_TR: | |
1442 | /* | |
1443 | * Work around a bug where the busy flag in the tr selector | |
1444 | * isn't exposed | |
1445 | */ | |
c0d09828 | 1446 | var->type |= 0x2; |
1fbdc7a5 AP |
1447 | break; |
1448 | case VCPU_SREG_DS: | |
1449 | case VCPU_SREG_ES: | |
1450 | case VCPU_SREG_FS: | |
1451 | case VCPU_SREG_GS: | |
1452 | /* | |
1453 | * The accessed bit must always be set in the segment | |
1454 | * descriptor cache, although it can be cleared in the | |
1455 | * descriptor, the cached bit always remains at 1. Since | |
1456 | * Intel has a check on this, set it here to support | |
1457 | * cross-vendor migration. | |
1458 | */ | |
1459 | if (!var->unusable) | |
1460 | var->type |= 0x1; | |
1461 | break; | |
b586eb02 | 1462 | case VCPU_SREG_SS: |
e0231715 JR |
1463 | /* |
1464 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
1465 | * descriptor is left as 1, although the whole segment has |
1466 | * been made unusable. Clear it here to pass an Intel VMX | |
1467 | * entry check when cross vendor migrating. | |
1468 | */ | |
1469 | if (var->unusable) | |
1470 | var->db = 0; | |
1471 | break; | |
1fbdc7a5 | 1472 | } |
6aa8b732 AK |
1473 | } |
1474 | ||
2e4d2653 IE |
1475 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
1476 | { | |
1477 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
1478 | ||
1479 | return save->cpl; | |
1480 | } | |
1481 | ||
89a27f4d | 1482 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1483 | { |
a2fa3e9f GH |
1484 | struct vcpu_svm *svm = to_svm(vcpu); |
1485 | ||
89a27f4d GN |
1486 | dt->size = svm->vmcb->save.idtr.limit; |
1487 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
1488 | } |
1489 | ||
89a27f4d | 1490 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1491 | { |
a2fa3e9f GH |
1492 | struct vcpu_svm *svm = to_svm(vcpu); |
1493 | ||
89a27f4d GN |
1494 | svm->vmcb->save.idtr.limit = dt->size; |
1495 | svm->vmcb->save.idtr.base = dt->address ; | |
17a703cb | 1496 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1497 | } |
1498 | ||
89a27f4d | 1499 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1500 | { |
a2fa3e9f GH |
1501 | struct vcpu_svm *svm = to_svm(vcpu); |
1502 | ||
89a27f4d GN |
1503 | dt->size = svm->vmcb->save.gdtr.limit; |
1504 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
1505 | } |
1506 | ||
89a27f4d | 1507 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1508 | { |
a2fa3e9f GH |
1509 | struct vcpu_svm *svm = to_svm(vcpu); |
1510 | ||
89a27f4d GN |
1511 | svm->vmcb->save.gdtr.limit = dt->size; |
1512 | svm->vmcb->save.gdtr.base = dt->address ; | |
17a703cb | 1513 | mark_dirty(svm->vmcb, VMCB_DT); |
6aa8b732 AK |
1514 | } |
1515 | ||
e8467fda AK |
1516 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
1517 | { | |
1518 | } | |
1519 | ||
aff48baa AK |
1520 | static void svm_decache_cr3(struct kvm_vcpu *vcpu) |
1521 | { | |
1522 | } | |
1523 | ||
25c4c276 | 1524 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
1525 | { |
1526 | } | |
1527 | ||
d225157b AK |
1528 | static void update_cr0_intercept(struct vcpu_svm *svm) |
1529 | { | |
1530 | ulong gcr0 = svm->vcpu.arch.cr0; | |
1531 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
1532 | ||
1533 | if (!svm->vcpu.fpu_active) | |
1534 | *hcr0 |= SVM_CR0_SELECTIVE_MASK; | |
1535 | else | |
1536 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) | |
1537 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
1538 | ||
dcca1a65 | 1539 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b AK |
1540 | |
1541 | if (gcr0 == *hcr0 && svm->vcpu.fpu_active) { | |
4ee546b4 RJ |
1542 | clr_cr_intercept(svm, INTERCEPT_CR0_READ); |
1543 | clr_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b | 1544 | } else { |
4ee546b4 RJ |
1545 | set_cr_intercept(svm, INTERCEPT_CR0_READ); |
1546 | set_cr_intercept(svm, INTERCEPT_CR0_WRITE); | |
d225157b AK |
1547 | } |
1548 | } | |
1549 | ||
6aa8b732 AK |
1550 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1551 | { | |
a2fa3e9f GH |
1552 | struct vcpu_svm *svm = to_svm(vcpu); |
1553 | ||
05b3e0c2 | 1554 | #ifdef CONFIG_X86_64 |
f6801dff | 1555 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 1556 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 1557 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 1558 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1559 | } |
1560 | ||
d77c26fc | 1561 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 1562 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 1563 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
1564 | } |
1565 | } | |
1566 | #endif | |
ad312c7c | 1567 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
1568 | |
1569 | if (!npt_enabled) | |
1570 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 AK |
1571 | |
1572 | if (!vcpu->fpu_active) | |
334df50a | 1573 | cr0 |= X86_CR0_TS; |
709ddebf JR |
1574 | /* |
1575 | * re-enable caching here because the QEMU bios | |
1576 | * does not do it - this results in some delay at | |
1577 | * reboot | |
1578 | */ | |
1579 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 1580 | svm->vmcb->save.cr0 = cr0; |
dcca1a65 | 1581 | mark_dirty(svm->vmcb, VMCB_CR); |
d225157b | 1582 | update_cr0_intercept(svm); |
6aa8b732 AK |
1583 | } |
1584 | ||
5e1746d6 | 1585 | static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 1586 | { |
6394b649 | 1587 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
e5eab0ce JR |
1588 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
1589 | ||
5e1746d6 NHE |
1590 | if (cr4 & X86_CR4_VMXE) |
1591 | return 1; | |
1592 | ||
e5eab0ce | 1593 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) |
f40f6a45 | 1594 | svm_flush_tlb(vcpu); |
6394b649 | 1595 | |
ec077263 JR |
1596 | vcpu->arch.cr4 = cr4; |
1597 | if (!npt_enabled) | |
1598 | cr4 |= X86_CR4_PAE; | |
6394b649 | 1599 | cr4 |= host_cr4_mce; |
ec077263 | 1600 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
dcca1a65 | 1601 | mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR); |
5e1746d6 | 1602 | return 0; |
6aa8b732 AK |
1603 | } |
1604 | ||
1605 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
1606 | struct kvm_segment *var, int seg) | |
1607 | { | |
a2fa3e9f | 1608 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1609 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
1610 | ||
1611 | s->base = var->base; | |
1612 | s->limit = var->limit; | |
1613 | s->selector = var->selector; | |
1614 | if (var->unusable) | |
1615 | s->attrib = 0; | |
1616 | else { | |
1617 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
1618 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
1619 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
1620 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
1621 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
1622 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
1623 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
1624 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
1625 | } | |
1626 | if (seg == VCPU_SREG_CS) | |
ea5e97e8 | 1627 | svm_update_cpl(vcpu); |
6aa8b732 | 1628 | |
060d0c9a | 1629 | mark_dirty(svm->vmcb, VMCB_SEG); |
6aa8b732 AK |
1630 | } |
1631 | ||
c8639010 | 1632 | static void update_db_bp_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 1633 | { |
d0bfb940 JK |
1634 | struct vcpu_svm *svm = to_svm(vcpu); |
1635 | ||
18c918c5 JR |
1636 | clr_exception_intercept(svm, DB_VECTOR); |
1637 | clr_exception_intercept(svm, BP_VECTOR); | |
44c11430 | 1638 | |
6be7d306 | 1639 | if (svm->nmi_singlestep) |
18c918c5 | 1640 | set_exception_intercept(svm, DB_VECTOR); |
44c11430 | 1641 | |
d0bfb940 JK |
1642 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
1643 | if (vcpu->guest_debug & | |
1644 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
18c918c5 | 1645 | set_exception_intercept(svm, DB_VECTOR); |
d0bfb940 | 1646 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
18c918c5 | 1647 | set_exception_intercept(svm, BP_VECTOR); |
d0bfb940 JK |
1648 | } else |
1649 | vcpu->guest_debug = 0; | |
44c11430 GN |
1650 | } |
1651 | ||
0fe1e009 | 1652 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 1653 | { |
0fe1e009 TH |
1654 | if (sd->next_asid > sd->max_asid) { |
1655 | ++sd->asid_generation; | |
1656 | sd->next_asid = 1; | |
a2fa3e9f | 1657 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
1658 | } |
1659 | ||
0fe1e009 TH |
1660 | svm->asid_generation = sd->asid_generation; |
1661 | svm->vmcb->control.asid = sd->next_asid++; | |
d48086d1 JR |
1662 | |
1663 | mark_dirty(svm->vmcb, VMCB_ASID); | |
6aa8b732 AK |
1664 | } |
1665 | ||
020df079 | 1666 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 1667 | { |
42dbaa5a | 1668 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 1669 | |
020df079 | 1670 | svm->vmcb->save.dr7 = value; |
72214b96 | 1671 | mark_dirty(svm->vmcb, VMCB_DR); |
6aa8b732 AK |
1672 | } |
1673 | ||
851ba692 | 1674 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 1675 | { |
631bc487 | 1676 | u64 fault_address = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1677 | u32 error_code; |
631bc487 | 1678 | int r = 1; |
6aa8b732 | 1679 | |
631bc487 GN |
1680 | switch (svm->apf_reason) { |
1681 | default: | |
1682 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 | 1683 | |
631bc487 GN |
1684 | trace_kvm_page_fault(fault_address, error_code); |
1685 | if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu)) | |
1686 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
dc25e89e AP |
1687 | r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code, |
1688 | svm->vmcb->control.insn_bytes, | |
1689 | svm->vmcb->control.insn_len); | |
631bc487 GN |
1690 | break; |
1691 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
1692 | svm->apf_reason = 0; | |
1693 | local_irq_disable(); | |
1694 | kvm_async_pf_task_wait(fault_address); | |
1695 | local_irq_enable(); | |
1696 | break; | |
1697 | case KVM_PV_REASON_PAGE_READY: | |
1698 | svm->apf_reason = 0; | |
1699 | local_irq_disable(); | |
1700 | kvm_async_pf_task_wake(fault_address); | |
1701 | local_irq_enable(); | |
1702 | break; | |
1703 | } | |
1704 | return r; | |
6aa8b732 AK |
1705 | } |
1706 | ||
851ba692 | 1707 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 1708 | { |
851ba692 AK |
1709 | struct kvm_run *kvm_run = svm->vcpu.run; |
1710 | ||
d0bfb940 | 1711 | if (!(svm->vcpu.guest_debug & |
44c11430 | 1712 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 1713 | !svm->nmi_singlestep) { |
d0bfb940 JK |
1714 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
1715 | return 1; | |
1716 | } | |
44c11430 | 1717 | |
6be7d306 JK |
1718 | if (svm->nmi_singlestep) { |
1719 | svm->nmi_singlestep = false; | |
44c11430 GN |
1720 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) |
1721 | svm->vmcb->save.rflags &= | |
1722 | ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
c8639010 | 1723 | update_db_bp_intercept(&svm->vcpu); |
44c11430 GN |
1724 | } |
1725 | ||
1726 | if (svm->vcpu.guest_debug & | |
e0231715 | 1727 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
1728 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1729 | kvm_run->debug.arch.pc = | |
1730 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1731 | kvm_run->debug.arch.exception = DB_VECTOR; | |
1732 | return 0; | |
1733 | } | |
1734 | ||
1735 | return 1; | |
d0bfb940 JK |
1736 | } |
1737 | ||
851ba692 | 1738 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 1739 | { |
851ba692 AK |
1740 | struct kvm_run *kvm_run = svm->vcpu.run; |
1741 | ||
d0bfb940 JK |
1742 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1743 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1744 | kvm_run->debug.arch.exception = BP_VECTOR; | |
1745 | return 0; | |
1746 | } | |
1747 | ||
851ba692 | 1748 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
1749 | { |
1750 | int er; | |
1751 | ||
51d8b661 | 1752 | er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1753 | if (er != EMULATE_DONE) |
7ee5d940 | 1754 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1755 | return 1; |
1756 | } | |
1757 | ||
6b52d186 | 1758 | static void svm_fpu_activate(struct kvm_vcpu *vcpu) |
7807fa6c | 1759 | { |
6b52d186 | 1760 | struct vcpu_svm *svm = to_svm(vcpu); |
66a562f7 | 1761 | |
18c918c5 | 1762 | clr_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 1763 | |
e756fc62 | 1764 | svm->vcpu.fpu_active = 1; |
d225157b | 1765 | update_cr0_intercept(svm); |
6b52d186 | 1766 | } |
a2fa3e9f | 1767 | |
6b52d186 AK |
1768 | static int nm_interception(struct vcpu_svm *svm) |
1769 | { | |
1770 | svm_fpu_activate(&svm->vcpu); | |
a2fa3e9f | 1771 | return 1; |
7807fa6c AL |
1772 | } |
1773 | ||
67ec6607 JR |
1774 | static bool is_erratum_383(void) |
1775 | { | |
1776 | int err, i; | |
1777 | u64 value; | |
1778 | ||
1779 | if (!erratum_383_found) | |
1780 | return false; | |
1781 | ||
1782 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
1783 | if (err) | |
1784 | return false; | |
1785 | ||
1786 | /* Bit 62 may or may not be set for this mce */ | |
1787 | value &= ~(1ULL << 62); | |
1788 | ||
1789 | if (value != 0xb600000000010015ULL) | |
1790 | return false; | |
1791 | ||
1792 | /* Clear MCi_STATUS registers */ | |
1793 | for (i = 0; i < 6; ++i) | |
1794 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
1795 | ||
1796 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
1797 | if (!err) { | |
1798 | u32 low, high; | |
1799 | ||
1800 | value &= ~(1ULL << 2); | |
1801 | low = lower_32_bits(value); | |
1802 | high = upper_32_bits(value); | |
1803 | ||
1804 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
1805 | } | |
1806 | ||
1807 | /* Flush tlb to evict multi-match entries */ | |
1808 | __flush_tlb_all(); | |
1809 | ||
1810 | return true; | |
1811 | } | |
1812 | ||
fe5913e4 | 1813 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 1814 | { |
67ec6607 JR |
1815 | if (is_erratum_383()) { |
1816 | /* | |
1817 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
1818 | * guest. | |
1819 | */ | |
1820 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
1821 | ||
a8eeb04a | 1822 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
1823 | |
1824 | return; | |
1825 | } | |
1826 | ||
53371b50 JR |
1827 | /* |
1828 | * On an #MC intercept the MCE handler is not called automatically in | |
1829 | * the host. So do it by hand here. | |
1830 | */ | |
1831 | asm volatile ( | |
1832 | "int $0x12\n"); | |
1833 | /* not sure if we ever come back to this point */ | |
1834 | ||
fe5913e4 JR |
1835 | return; |
1836 | } | |
1837 | ||
1838 | static int mc_interception(struct vcpu_svm *svm) | |
1839 | { | |
53371b50 JR |
1840 | return 1; |
1841 | } | |
1842 | ||
851ba692 | 1843 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 1844 | { |
851ba692 AK |
1845 | struct kvm_run *kvm_run = svm->vcpu.run; |
1846 | ||
46fe4ddd JR |
1847 | /* |
1848 | * VMCB is undefined after a SHUTDOWN intercept | |
1849 | * so reinitialize it. | |
1850 | */ | |
a2fa3e9f | 1851 | clear_page(svm->vmcb); |
e6101a96 | 1852 | init_vmcb(svm); |
46fe4ddd JR |
1853 | |
1854 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1855 | return 0; | |
1856 | } | |
1857 | ||
851ba692 | 1858 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 1859 | { |
cf8f70bf | 1860 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 1861 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
34c33d16 | 1862 | int size, in, string; |
039576c0 | 1863 | unsigned port; |
6aa8b732 | 1864 | |
e756fc62 | 1865 | ++svm->vcpu.stat.io_exits; |
e70669ab | 1866 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 1867 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
cf8f70bf | 1868 | if (string || in) |
51d8b661 | 1869 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
cf8f70bf | 1870 | |
039576c0 AK |
1871 | port = io_info >> 16; |
1872 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 1873 | svm->next_rip = svm->vmcb->control.exit_info_2; |
e93f36bc | 1874 | skip_emulated_instruction(&svm->vcpu); |
cf8f70bf GN |
1875 | |
1876 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
1877 | } |
1878 | ||
851ba692 | 1879 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
1880 | { |
1881 | return 1; | |
1882 | } | |
1883 | ||
851ba692 | 1884 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
1885 | { |
1886 | ++svm->vcpu.stat.irq_exits; | |
1887 | return 1; | |
1888 | } | |
1889 | ||
851ba692 | 1890 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
1891 | { |
1892 | return 1; | |
1893 | } | |
1894 | ||
851ba692 | 1895 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 1896 | { |
5fdbf976 | 1897 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 RR |
1898 | skip_emulated_instruction(&svm->vcpu); |
1899 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1900 | } |
1901 | ||
851ba692 | 1902 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 1903 | { |
5fdbf976 | 1904 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
e756fc62 | 1905 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1906 | kvm_emulate_hypercall(&svm->vcpu); |
1907 | return 1; | |
02e235bc AK |
1908 | } |
1909 | ||
5bd2edc3 JR |
1910 | static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) |
1911 | { | |
1912 | struct vcpu_svm *svm = to_svm(vcpu); | |
1913 | ||
1914 | return svm->nested.nested_cr3; | |
1915 | } | |
1916 | ||
e4e517b4 AK |
1917 | static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index) |
1918 | { | |
1919 | struct vcpu_svm *svm = to_svm(vcpu); | |
1920 | u64 cr3 = svm->nested.nested_cr3; | |
1921 | u64 pdpte; | |
1922 | int ret; | |
1923 | ||
1924 | ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte, | |
1925 | offset_in_page(cr3) + index * 8, 8); | |
1926 | if (ret) | |
1927 | return 0; | |
1928 | return pdpte; | |
1929 | } | |
1930 | ||
5bd2edc3 JR |
1931 | static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu, |
1932 | unsigned long root) | |
1933 | { | |
1934 | struct vcpu_svm *svm = to_svm(vcpu); | |
1935 | ||
1936 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 1937 | mark_dirty(svm->vmcb, VMCB_NPT); |
f40f6a45 | 1938 | svm_flush_tlb(vcpu); |
5bd2edc3 JR |
1939 | } |
1940 | ||
6389ee94 AK |
1941 | static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu, |
1942 | struct x86_exception *fault) | |
5bd2edc3 JR |
1943 | { |
1944 | struct vcpu_svm *svm = to_svm(vcpu); | |
1945 | ||
1946 | svm->vmcb->control.exit_code = SVM_EXIT_NPF; | |
1947 | svm->vmcb->control.exit_code_hi = 0; | |
6389ee94 AK |
1948 | svm->vmcb->control.exit_info_1 = fault->error_code; |
1949 | svm->vmcb->control.exit_info_2 = fault->address; | |
5bd2edc3 JR |
1950 | |
1951 | nested_svm_vmexit(svm); | |
1952 | } | |
1953 | ||
4b16184c JR |
1954 | static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) |
1955 | { | |
1956 | int r; | |
1957 | ||
1958 | r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu); | |
1959 | ||
1960 | vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3; | |
1961 | vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3; | |
e4e517b4 | 1962 | vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr; |
4b16184c JR |
1963 | vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit; |
1964 | vcpu->arch.mmu.shadow_root_level = get_npt_level(); | |
1965 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
1966 | ||
1967 | return r; | |
1968 | } | |
1969 | ||
1970 | static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
1971 | { | |
1972 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
1973 | } | |
1974 | ||
c0725420 AG |
1975 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
1976 | { | |
f6801dff | 1977 | if (!(svm->vcpu.arch.efer & EFER_SVME) |
c0725420 AG |
1978 | || !is_paging(&svm->vcpu)) { |
1979 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
1980 | return 1; | |
1981 | } | |
1982 | ||
1983 | if (svm->vmcb->save.cpl) { | |
1984 | kvm_inject_gp(&svm->vcpu, 0); | |
1985 | return 1; | |
1986 | } | |
1987 | ||
1988 | return 0; | |
1989 | } | |
1990 | ||
cf74a78b AG |
1991 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
1992 | bool has_error_code, u32 error_code) | |
1993 | { | |
b8e88bc8 JR |
1994 | int vmexit; |
1995 | ||
2030753d | 1996 | if (!is_guest_mode(&svm->vcpu)) |
0295ad7d | 1997 | return 0; |
cf74a78b | 1998 | |
0295ad7d JR |
1999 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
2000 | svm->vmcb->control.exit_code_hi = 0; | |
2001 | svm->vmcb->control.exit_info_1 = error_code; | |
2002 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
2003 | ||
b8e88bc8 JR |
2004 | vmexit = nested_svm_intercept(svm); |
2005 | if (vmexit == NESTED_EXIT_DONE) | |
2006 | svm->nested.exit_required = true; | |
2007 | ||
2008 | return vmexit; | |
cf74a78b AG |
2009 | } |
2010 | ||
8fe54654 JR |
2011 | /* This function returns true if it is save to enable the irq window */ |
2012 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 2013 | { |
2030753d | 2014 | if (!is_guest_mode(&svm->vcpu)) |
8fe54654 | 2015 | return true; |
cf74a78b | 2016 | |
26666957 | 2017 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 2018 | return true; |
cf74a78b | 2019 | |
26666957 | 2020 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 2021 | return false; |
cf74a78b | 2022 | |
a0a07cd2 GN |
2023 | /* |
2024 | * if vmexit was already requested (by intercepted exception | |
2025 | * for instance) do not overwrite it with "external interrupt" | |
2026 | * vmexit. | |
2027 | */ | |
2028 | if (svm->nested.exit_required) | |
2029 | return false; | |
2030 | ||
197717d5 JR |
2031 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
2032 | svm->vmcb->control.exit_info_1 = 0; | |
2033 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 2034 | |
cd3ff653 JR |
2035 | if (svm->nested.intercept & 1ULL) { |
2036 | /* | |
2037 | * The #vmexit can't be emulated here directly because this | |
c5ec2e56 | 2038 | * code path runs with irqs and preemption disabled. A |
cd3ff653 JR |
2039 | * #vmexit emulation might sleep. Only signal request for |
2040 | * the #vmexit here. | |
2041 | */ | |
2042 | svm->nested.exit_required = true; | |
236649de | 2043 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 2044 | return false; |
cf74a78b AG |
2045 | } |
2046 | ||
8fe54654 | 2047 | return true; |
cf74a78b AG |
2048 | } |
2049 | ||
887f500c JR |
2050 | /* This function returns true if it is save to enable the nmi window */ |
2051 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
2052 | { | |
2030753d | 2053 | if (!is_guest_mode(&svm->vcpu)) |
887f500c JR |
2054 | return true; |
2055 | ||
2056 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
2057 | return true; | |
2058 | ||
2059 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
2060 | svm->nested.exit_required = true; | |
2061 | ||
2062 | return false; | |
cf74a78b AG |
2063 | } |
2064 | ||
7597f129 | 2065 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) |
34f80cfa JR |
2066 | { |
2067 | struct page *page; | |
2068 | ||
6c3bd3d7 JR |
2069 | might_sleep(); |
2070 | ||
34f80cfa | 2071 | page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT); |
34f80cfa JR |
2072 | if (is_error_page(page)) |
2073 | goto error; | |
2074 | ||
7597f129 JR |
2075 | *_page = page; |
2076 | ||
2077 | return kmap(page); | |
34f80cfa JR |
2078 | |
2079 | error: | |
34f80cfa JR |
2080 | kvm_inject_gp(&svm->vcpu, 0); |
2081 | ||
2082 | return NULL; | |
2083 | } | |
2084 | ||
7597f129 | 2085 | static void nested_svm_unmap(struct page *page) |
34f80cfa | 2086 | { |
7597f129 | 2087 | kunmap(page); |
34f80cfa JR |
2088 | kvm_release_page_dirty(page); |
2089 | } | |
34f80cfa | 2090 | |
ce2ac085 JR |
2091 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
2092 | { | |
2093 | unsigned port; | |
2094 | u8 val, bit; | |
2095 | u64 gpa; | |
34f80cfa | 2096 | |
ce2ac085 JR |
2097 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
2098 | return NESTED_EXIT_HOST; | |
34f80cfa | 2099 | |
ce2ac085 JR |
2100 | port = svm->vmcb->control.exit_info_1 >> 16; |
2101 | gpa = svm->nested.vmcb_iopm + (port / 8); | |
2102 | bit = port % 8; | |
2103 | val = 0; | |
2104 | ||
2105 | if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1)) | |
2106 | val &= (1 << bit); | |
2107 | ||
2108 | return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; | |
34f80cfa JR |
2109 | } |
2110 | ||
d2477826 | 2111 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 2112 | { |
0d6b3537 JR |
2113 | u32 offset, msr, value; |
2114 | int write, mask; | |
4c2161ae | 2115 | |
3d62d9aa | 2116 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 2117 | return NESTED_EXIT_HOST; |
3d62d9aa | 2118 | |
0d6b3537 JR |
2119 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
2120 | offset = svm_msrpm_offset(msr); | |
2121 | write = svm->vmcb->control.exit_info_1 & 1; | |
2122 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 2123 | |
0d6b3537 JR |
2124 | if (offset == MSR_INVALID) |
2125 | return NESTED_EXIT_DONE; | |
4c2161ae | 2126 | |
0d6b3537 JR |
2127 | /* Offset is in 32 bit units but need in 8 bit units */ |
2128 | offset *= 4; | |
4c2161ae | 2129 | |
0d6b3537 JR |
2130 | if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4)) |
2131 | return NESTED_EXIT_DONE; | |
3d62d9aa | 2132 | |
0d6b3537 | 2133 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
2134 | } |
2135 | ||
410e4d57 | 2136 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 2137 | { |
cf74a78b | 2138 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 2139 | |
410e4d57 JR |
2140 | switch (exit_code) { |
2141 | case SVM_EXIT_INTR: | |
2142 | case SVM_EXIT_NMI: | |
ff47a49b | 2143 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 2144 | return NESTED_EXIT_HOST; |
410e4d57 | 2145 | case SVM_EXIT_NPF: |
e0231715 | 2146 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
2147 | if (npt_enabled) |
2148 | return NESTED_EXIT_HOST; | |
2149 | break; | |
410e4d57 | 2150 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
631bc487 GN |
2151 | /* When we're shadowing, trap PFs, but not async PF */ |
2152 | if (!npt_enabled && svm->apf_reason == 0) | |
410e4d57 JR |
2153 | return NESTED_EXIT_HOST; |
2154 | break; | |
66a562f7 JR |
2155 | case SVM_EXIT_EXCP_BASE + NM_VECTOR: |
2156 | nm_interception(svm); | |
2157 | break; | |
410e4d57 JR |
2158 | default: |
2159 | break; | |
cf74a78b AG |
2160 | } |
2161 | ||
410e4d57 JR |
2162 | return NESTED_EXIT_CONTINUE; |
2163 | } | |
2164 | ||
2165 | /* | |
2166 | * If this function returns true, this #vmexit was already handled | |
2167 | */ | |
b8e88bc8 | 2168 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
2169 | { |
2170 | u32 exit_code = svm->vmcb->control.exit_code; | |
2171 | int vmexit = NESTED_EXIT_HOST; | |
2172 | ||
cf74a78b | 2173 | switch (exit_code) { |
9c4e40b9 | 2174 | case SVM_EXIT_MSR: |
3d62d9aa | 2175 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 2176 | break; |
ce2ac085 JR |
2177 | case SVM_EXIT_IOIO: |
2178 | vmexit = nested_svm_intercept_ioio(svm); | |
2179 | break; | |
4ee546b4 RJ |
2180 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: { |
2181 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0); | |
2182 | if (svm->nested.intercept_cr & bit) | |
410e4d57 | 2183 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2184 | break; |
2185 | } | |
3aed041a JR |
2186 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: { |
2187 | u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0); | |
2188 | if (svm->nested.intercept_dr & bit) | |
410e4d57 | 2189 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2190 | break; |
2191 | } | |
2192 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
2193 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
aad42c64 | 2194 | if (svm->nested.intercept_exceptions & excp_bits) |
410e4d57 | 2195 | vmexit = NESTED_EXIT_DONE; |
631bc487 GN |
2196 | /* async page fault always cause vmexit */ |
2197 | else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) && | |
2198 | svm->apf_reason != 0) | |
2199 | vmexit = NESTED_EXIT_DONE; | |
cf74a78b AG |
2200 | break; |
2201 | } | |
228070b1 JR |
2202 | case SVM_EXIT_ERR: { |
2203 | vmexit = NESTED_EXIT_DONE; | |
2204 | break; | |
2205 | } | |
cf74a78b AG |
2206 | default: { |
2207 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 2208 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 2209 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
2210 | } |
2211 | } | |
2212 | ||
b8e88bc8 JR |
2213 | return vmexit; |
2214 | } | |
2215 | ||
2216 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
2217 | { | |
2218 | int vmexit; | |
2219 | ||
2220 | vmexit = nested_svm_intercept(svm); | |
2221 | ||
2222 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 2223 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
2224 | |
2225 | return vmexit; | |
cf74a78b AG |
2226 | } |
2227 | ||
0460a979 JR |
2228 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
2229 | { | |
2230 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
2231 | struct vmcb_control_area *from = &from_vmcb->control; | |
2232 | ||
4ee546b4 | 2233 | dst->intercept_cr = from->intercept_cr; |
3aed041a | 2234 | dst->intercept_dr = from->intercept_dr; |
0460a979 JR |
2235 | dst->intercept_exceptions = from->intercept_exceptions; |
2236 | dst->intercept = from->intercept; | |
2237 | dst->iopm_base_pa = from->iopm_base_pa; | |
2238 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
2239 | dst->tsc_offset = from->tsc_offset; | |
2240 | dst->asid = from->asid; | |
2241 | dst->tlb_ctl = from->tlb_ctl; | |
2242 | dst->int_ctl = from->int_ctl; | |
2243 | dst->int_vector = from->int_vector; | |
2244 | dst->int_state = from->int_state; | |
2245 | dst->exit_code = from->exit_code; | |
2246 | dst->exit_code_hi = from->exit_code_hi; | |
2247 | dst->exit_info_1 = from->exit_info_1; | |
2248 | dst->exit_info_2 = from->exit_info_2; | |
2249 | dst->exit_int_info = from->exit_int_info; | |
2250 | dst->exit_int_info_err = from->exit_int_info_err; | |
2251 | dst->nested_ctl = from->nested_ctl; | |
2252 | dst->event_inj = from->event_inj; | |
2253 | dst->event_inj_err = from->event_inj_err; | |
2254 | dst->nested_cr3 = from->nested_cr3; | |
2255 | dst->lbr_ctl = from->lbr_ctl; | |
2256 | } | |
2257 | ||
34f80cfa | 2258 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 2259 | { |
34f80cfa | 2260 | struct vmcb *nested_vmcb; |
e6aa9abd | 2261 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 2262 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2263 | struct page *page; |
cf74a78b | 2264 | |
17897f36 JR |
2265 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
2266 | vmcb->control.exit_info_1, | |
2267 | vmcb->control.exit_info_2, | |
2268 | vmcb->control.exit_int_info, | |
e097e5ff SH |
2269 | vmcb->control.exit_int_info_err, |
2270 | KVM_ISA_SVM); | |
17897f36 | 2271 | |
7597f129 | 2272 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); |
34f80cfa JR |
2273 | if (!nested_vmcb) |
2274 | return 1; | |
2275 | ||
2030753d JR |
2276 | /* Exit Guest-Mode */ |
2277 | leave_guest_mode(&svm->vcpu); | |
06fc7772 JR |
2278 | svm->nested.vmcb = 0; |
2279 | ||
cf74a78b | 2280 | /* Give the current vmcb to the guest */ |
33740e40 JR |
2281 | disable_gif(svm); |
2282 | ||
2283 | nested_vmcb->save.es = vmcb->save.es; | |
2284 | nested_vmcb->save.cs = vmcb->save.cs; | |
2285 | nested_vmcb->save.ss = vmcb->save.ss; | |
2286 | nested_vmcb->save.ds = vmcb->save.ds; | |
2287 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
2288 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
3f6a9d16 | 2289 | nested_vmcb->save.efer = svm->vcpu.arch.efer; |
cdbbdc12 | 2290 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
9f8fe504 | 2291 | nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu); |
33740e40 | 2292 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 2293 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2294 | nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu); |
33740e40 JR |
2295 | nested_vmcb->save.rip = vmcb->save.rip; |
2296 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
2297 | nested_vmcb->save.rax = vmcb->save.rax; | |
2298 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
2299 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
2300 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
2301 | ||
2302 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
2303 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
2304 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
2305 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
2306 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
2307 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
2308 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
2309 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
2310 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
7a190667 | 2311 | nested_vmcb->control.next_rip = vmcb->control.next_rip; |
8d23c466 AG |
2312 | |
2313 | /* | |
2314 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
2315 | * to make sure that we do not lose injected events. So check event_inj | |
2316 | * here and copy it to exit_int_info if it is valid. | |
2317 | * Exit_int_info and event_inj can't be both valid because the case | |
2318 | * below only happens on a VMRUN instruction intercept which has | |
2319 | * no valid exit_int_info set. | |
2320 | */ | |
2321 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
2322 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
2323 | ||
2324 | nc->exit_int_info = vmcb->control.event_inj; | |
2325 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
2326 | } | |
2327 | ||
33740e40 JR |
2328 | nested_vmcb->control.tlb_ctl = 0; |
2329 | nested_vmcb->control.event_inj = 0; | |
2330 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
2331 | |
2332 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
2333 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
2334 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
2335 | ||
cf74a78b | 2336 | /* Restore the original control entries */ |
0460a979 | 2337 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 2338 | |
219b65dc AG |
2339 | kvm_clear_exception_queue(&svm->vcpu); |
2340 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b | 2341 | |
4b16184c JR |
2342 | svm->nested.nested_cr3 = 0; |
2343 | ||
cf74a78b AG |
2344 | /* Restore selected save entries */ |
2345 | svm->vmcb->save.es = hsave->save.es; | |
2346 | svm->vmcb->save.cs = hsave->save.cs; | |
2347 | svm->vmcb->save.ss = hsave->save.ss; | |
2348 | svm->vmcb->save.ds = hsave->save.ds; | |
2349 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
2350 | svm->vmcb->save.idtr = hsave->save.idtr; | |
f6e78475 | 2351 | kvm_set_rflags(&svm->vcpu, hsave->save.rflags); |
cf74a78b AG |
2352 | svm_set_efer(&svm->vcpu, hsave->save.efer); |
2353 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
2354 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
2355 | if (npt_enabled) { | |
2356 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
2357 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
2358 | } else { | |
2390218b | 2359 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b AG |
2360 | } |
2361 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
2362 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
2363 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
2364 | svm->vmcb->save.dr7 = 0; | |
2365 | svm->vmcb->save.cpl = 0; | |
2366 | svm->vmcb->control.exit_int_info = 0; | |
2367 | ||
8d28fec4 RJ |
2368 | mark_all_dirty(svm->vmcb); |
2369 | ||
7597f129 | 2370 | nested_svm_unmap(page); |
cf74a78b | 2371 | |
4b16184c | 2372 | nested_svm_uninit_mmu_context(&svm->vcpu); |
cf74a78b AG |
2373 | kvm_mmu_reset_context(&svm->vcpu); |
2374 | kvm_mmu_load(&svm->vcpu); | |
2375 | ||
2376 | return 0; | |
2377 | } | |
3d6368ef | 2378 | |
9738b2c9 | 2379 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 2380 | { |
323c3d80 JR |
2381 | /* |
2382 | * This function merges the msr permission bitmaps of kvm and the | |
c5ec2e56 | 2383 | * nested vmcb. It is optimized in that it only merges the parts where |
323c3d80 JR |
2384 | * the kvm msr permission bitmap may contain zero bits |
2385 | */ | |
3d6368ef | 2386 | int i; |
9738b2c9 | 2387 | |
323c3d80 JR |
2388 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
2389 | return true; | |
9738b2c9 | 2390 | |
323c3d80 JR |
2391 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
2392 | u32 value, p; | |
2393 | u64 offset; | |
9738b2c9 | 2394 | |
323c3d80 JR |
2395 | if (msrpm_offsets[i] == 0xffffffff) |
2396 | break; | |
3d6368ef | 2397 | |
0d6b3537 JR |
2398 | p = msrpm_offsets[i]; |
2399 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 JR |
2400 | |
2401 | if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4)) | |
2402 | return false; | |
2403 | ||
2404 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
2405 | } | |
3d6368ef | 2406 | |
323c3d80 | 2407 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); |
9738b2c9 JR |
2408 | |
2409 | return true; | |
3d6368ef AG |
2410 | } |
2411 | ||
52c65a30 JR |
2412 | static bool nested_vmcb_checks(struct vmcb *vmcb) |
2413 | { | |
2414 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
2415 | return false; | |
2416 | ||
dbe77584 JR |
2417 | if (vmcb->control.asid == 0) |
2418 | return false; | |
2419 | ||
4b16184c JR |
2420 | if (vmcb->control.nested_ctl && !npt_enabled) |
2421 | return false; | |
2422 | ||
52c65a30 JR |
2423 | return true; |
2424 | } | |
2425 | ||
9738b2c9 | 2426 | static bool nested_svm_vmrun(struct vcpu_svm *svm) |
3d6368ef | 2427 | { |
9738b2c9 | 2428 | struct vmcb *nested_vmcb; |
e6aa9abd | 2429 | struct vmcb *hsave = svm->nested.hsave; |
defbba56 | 2430 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2431 | struct page *page; |
06fc7772 | 2432 | u64 vmcb_gpa; |
3d6368ef | 2433 | |
06fc7772 | 2434 | vmcb_gpa = svm->vmcb->save.rax; |
3d6368ef | 2435 | |
7597f129 | 2436 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9738b2c9 JR |
2437 | if (!nested_vmcb) |
2438 | return false; | |
2439 | ||
52c65a30 JR |
2440 | if (!nested_vmcb_checks(nested_vmcb)) { |
2441 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
2442 | nested_vmcb->control.exit_code_hi = 0; | |
2443 | nested_vmcb->control.exit_info_1 = 0; | |
2444 | nested_vmcb->control.exit_info_2 = 0; | |
2445 | ||
2446 | nested_svm_unmap(page); | |
2447 | ||
2448 | return false; | |
2449 | } | |
2450 | ||
b75f4eb3 | 2451 | trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa, |
0ac406de JR |
2452 | nested_vmcb->save.rip, |
2453 | nested_vmcb->control.int_ctl, | |
2454 | nested_vmcb->control.event_inj, | |
2455 | nested_vmcb->control.nested_ctl); | |
2456 | ||
4ee546b4 RJ |
2457 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, |
2458 | nested_vmcb->control.intercept_cr >> 16, | |
2e554e8d JR |
2459 | nested_vmcb->control.intercept_exceptions, |
2460 | nested_vmcb->control.intercept); | |
2461 | ||
3d6368ef | 2462 | /* Clear internal status */ |
219b65dc AG |
2463 | kvm_clear_exception_queue(&svm->vcpu); |
2464 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3d6368ef | 2465 | |
e0231715 JR |
2466 | /* |
2467 | * Save the old vmcb, so we don't need to pick what we save, but can | |
2468 | * restore everything when a VMEXIT occurs | |
2469 | */ | |
defbba56 JR |
2470 | hsave->save.es = vmcb->save.es; |
2471 | hsave->save.cs = vmcb->save.cs; | |
2472 | hsave->save.ss = vmcb->save.ss; | |
2473 | hsave->save.ds = vmcb->save.ds; | |
2474 | hsave->save.gdtr = vmcb->save.gdtr; | |
2475 | hsave->save.idtr = vmcb->save.idtr; | |
f6801dff | 2476 | hsave->save.efer = svm->vcpu.arch.efer; |
4d4ec087 | 2477 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); |
defbba56 | 2478 | hsave->save.cr4 = svm->vcpu.arch.cr4; |
f6e78475 | 2479 | hsave->save.rflags = kvm_get_rflags(&svm->vcpu); |
b75f4eb3 | 2480 | hsave->save.rip = kvm_rip_read(&svm->vcpu); |
defbba56 JR |
2481 | hsave->save.rsp = vmcb->save.rsp; |
2482 | hsave->save.rax = vmcb->save.rax; | |
2483 | if (npt_enabled) | |
2484 | hsave->save.cr3 = vmcb->save.cr3; | |
2485 | else | |
9f8fe504 | 2486 | hsave->save.cr3 = kvm_read_cr3(&svm->vcpu); |
defbba56 | 2487 | |
0460a979 | 2488 | copy_vmcb_control_area(hsave, vmcb); |
3d6368ef | 2489 | |
f6e78475 | 2490 | if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF) |
3d6368ef AG |
2491 | svm->vcpu.arch.hflags |= HF_HIF_MASK; |
2492 | else | |
2493 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
2494 | ||
4b16184c JR |
2495 | if (nested_vmcb->control.nested_ctl) { |
2496 | kvm_mmu_unload(&svm->vcpu); | |
2497 | svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; | |
2498 | nested_svm_init_mmu_context(&svm->vcpu); | |
2499 | } | |
2500 | ||
3d6368ef AG |
2501 | /* Load the nested guest state */ |
2502 | svm->vmcb->save.es = nested_vmcb->save.es; | |
2503 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
2504 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
2505 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
2506 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
2507 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
f6e78475 | 2508 | kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags); |
3d6368ef AG |
2509 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); |
2510 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
2511 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
2512 | if (npt_enabled) { | |
2513 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
2514 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 2515 | } else |
2390218b | 2516 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
2517 | |
2518 | /* Guest paging mode is active - reset mmu */ | |
2519 | kvm_mmu_reset_context(&svm->vcpu); | |
2520 | ||
defbba56 | 2521 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
2522 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
2523 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
2524 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
e0231715 | 2525 | |
3d6368ef AG |
2526 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
2527 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
2528 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
2529 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
2530 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
2531 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
2532 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
2533 | ||
f7138538 | 2534 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 2535 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 2536 | |
aad42c64 | 2537 | /* cache intercepts */ |
4ee546b4 | 2538 | svm->nested.intercept_cr = nested_vmcb->control.intercept_cr; |
3aed041a | 2539 | svm->nested.intercept_dr = nested_vmcb->control.intercept_dr; |
aad42c64 JR |
2540 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; |
2541 | svm->nested.intercept = nested_vmcb->control.intercept; | |
2542 | ||
f40f6a45 | 2543 | svm_flush_tlb(&svm->vcpu); |
3d6368ef | 2544 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
2545 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
2546 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
2547 | else | |
2548 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
2549 | ||
88ab24ad JR |
2550 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
2551 | /* We only want the cr8 intercept bits of the guest */ | |
4ee546b4 RJ |
2552 | clr_cr_intercept(svm, INTERCEPT_CR8_READ); |
2553 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); | |
88ab24ad JR |
2554 | } |
2555 | ||
0d945bd9 | 2556 | /* We don't want to see VMMCALLs from a nested guest */ |
8a05a1b8 | 2557 | clr_intercept(svm, INTERCEPT_VMMCALL); |
0d945bd9 | 2558 | |
88ab24ad | 2559 | svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl; |
3d6368ef AG |
2560 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
2561 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
2562 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
2563 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
2564 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
2565 | ||
7597f129 | 2566 | nested_svm_unmap(page); |
9738b2c9 | 2567 | |
2030753d JR |
2568 | /* Enter Guest-Mode */ |
2569 | enter_guest_mode(&svm->vcpu); | |
2570 | ||
384c6368 JR |
2571 | /* |
2572 | * Merge guest and host intercepts - must be called with vcpu in | |
2573 | * guest-mode to take affect here | |
2574 | */ | |
2575 | recalc_intercepts(svm); | |
2576 | ||
06fc7772 | 2577 | svm->nested.vmcb = vmcb_gpa; |
9738b2c9 | 2578 | |
2af9194d | 2579 | enable_gif(svm); |
3d6368ef | 2580 | |
8d28fec4 RJ |
2581 | mark_all_dirty(svm->vmcb); |
2582 | ||
9738b2c9 | 2583 | return true; |
3d6368ef AG |
2584 | } |
2585 | ||
9966bf68 | 2586 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
2587 | { |
2588 | to_vmcb->save.fs = from_vmcb->save.fs; | |
2589 | to_vmcb->save.gs = from_vmcb->save.gs; | |
2590 | to_vmcb->save.tr = from_vmcb->save.tr; | |
2591 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
2592 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
2593 | to_vmcb->save.star = from_vmcb->save.star; | |
2594 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
2595 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
2596 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
2597 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
2598 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
2599 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
2600 | } |
2601 | ||
851ba692 | 2602 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 2603 | { |
9966bf68 | 2604 | struct vmcb *nested_vmcb; |
7597f129 | 2605 | struct page *page; |
9966bf68 | 2606 | |
5542675b AG |
2607 | if (nested_svm_check_permissions(svm)) |
2608 | return 1; | |
2609 | ||
7597f129 | 2610 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2611 | if (!nested_vmcb) |
2612 | return 1; | |
2613 | ||
e3e9ed3d JR |
2614 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
2615 | skip_emulated_instruction(&svm->vcpu); | |
2616 | ||
9966bf68 | 2617 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); |
7597f129 | 2618 | nested_svm_unmap(page); |
5542675b AG |
2619 | |
2620 | return 1; | |
2621 | } | |
2622 | ||
851ba692 | 2623 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 2624 | { |
9966bf68 | 2625 | struct vmcb *nested_vmcb; |
7597f129 | 2626 | struct page *page; |
9966bf68 | 2627 | |
5542675b AG |
2628 | if (nested_svm_check_permissions(svm)) |
2629 | return 1; | |
2630 | ||
7597f129 | 2631 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2632 | if (!nested_vmcb) |
2633 | return 1; | |
2634 | ||
e3e9ed3d JR |
2635 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
2636 | skip_emulated_instruction(&svm->vcpu); | |
2637 | ||
9966bf68 | 2638 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); |
7597f129 | 2639 | nested_svm_unmap(page); |
5542675b AG |
2640 | |
2641 | return 1; | |
2642 | } | |
2643 | ||
851ba692 | 2644 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 2645 | { |
3d6368ef AG |
2646 | if (nested_svm_check_permissions(svm)) |
2647 | return 1; | |
2648 | ||
b75f4eb3 RJ |
2649 | /* Save rip after vmrun instruction */ |
2650 | kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3); | |
3d6368ef | 2651 | |
9738b2c9 | 2652 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
2653 | return 1; |
2654 | ||
9738b2c9 | 2655 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
2656 | goto failed; |
2657 | ||
2658 | return 1; | |
2659 | ||
2660 | failed: | |
2661 | ||
2662 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
2663 | svm->vmcb->control.exit_code_hi = 0; | |
2664 | svm->vmcb->control.exit_info_1 = 0; | |
2665 | svm->vmcb->control.exit_info_2 = 0; | |
2666 | ||
2667 | nested_svm_vmexit(svm); | |
3d6368ef AG |
2668 | |
2669 | return 1; | |
2670 | } | |
2671 | ||
851ba692 | 2672 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2673 | { |
2674 | if (nested_svm_check_permissions(svm)) | |
2675 | return 1; | |
2676 | ||
2677 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2678 | skip_emulated_instruction(&svm->vcpu); | |
3842d135 | 2679 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
1371d904 | 2680 | |
2af9194d | 2681 | enable_gif(svm); |
1371d904 AG |
2682 | |
2683 | return 1; | |
2684 | } | |
2685 | ||
851ba692 | 2686 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2687 | { |
2688 | if (nested_svm_check_permissions(svm)) | |
2689 | return 1; | |
2690 | ||
2691 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2692 | skip_emulated_instruction(&svm->vcpu); | |
2693 | ||
2af9194d | 2694 | disable_gif(svm); |
1371d904 AG |
2695 | |
2696 | /* After a CLGI no interrupts should come */ | |
2697 | svm_clear_vintr(svm); | |
2698 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
2699 | ||
decdbf6a JR |
2700 | mark_dirty(svm->vmcb, VMCB_INTR); |
2701 | ||
1371d904 AG |
2702 | return 1; |
2703 | } | |
2704 | ||
851ba692 | 2705 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
2706 | { |
2707 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 2708 | |
ec1ff790 JR |
2709 | trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX], |
2710 | vcpu->arch.regs[VCPU_REGS_RAX]); | |
2711 | ||
ff092385 AG |
2712 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
2713 | kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]); | |
2714 | ||
2715 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2716 | skip_emulated_instruction(&svm->vcpu); | |
2717 | return 1; | |
2718 | } | |
2719 | ||
532a46b9 JR |
2720 | static int skinit_interception(struct vcpu_svm *svm) |
2721 | { | |
2722 | trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]); | |
2723 | ||
2724 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2725 | return 1; | |
2726 | } | |
2727 | ||
81dd35d4 JR |
2728 | static int xsetbv_interception(struct vcpu_svm *svm) |
2729 | { | |
2730 | u64 new_bv = kvm_read_edx_eax(&svm->vcpu); | |
2731 | u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX); | |
2732 | ||
2733 | if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) { | |
2734 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2735 | skip_emulated_instruction(&svm->vcpu); | |
2736 | } | |
2737 | ||
2738 | return 1; | |
2739 | } | |
2740 | ||
851ba692 | 2741 | static int invalid_op_interception(struct vcpu_svm *svm) |
6aa8b732 | 2742 | { |
7ee5d940 | 2743 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
2744 | return 1; |
2745 | } | |
2746 | ||
851ba692 | 2747 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 2748 | { |
37817f29 | 2749 | u16 tss_selector; |
64a7ec06 GN |
2750 | int reason; |
2751 | int int_type = svm->vmcb->control.exit_int_info & | |
2752 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 2753 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
2754 | uint32_t type = |
2755 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
2756 | uint32_t idt_v = | |
2757 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
2758 | bool has_error_code = false; |
2759 | u32 error_code = 0; | |
37817f29 IE |
2760 | |
2761 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 2762 | |
37817f29 IE |
2763 | if (svm->vmcb->control.exit_info_2 & |
2764 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
2765 | reason = TASK_SWITCH_IRET; |
2766 | else if (svm->vmcb->control.exit_info_2 & | |
2767 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
2768 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 2769 | else if (idt_v) |
64a7ec06 GN |
2770 | reason = TASK_SWITCH_GATE; |
2771 | else | |
2772 | reason = TASK_SWITCH_CALL; | |
2773 | ||
fe8e7f83 GN |
2774 | if (reason == TASK_SWITCH_GATE) { |
2775 | switch (type) { | |
2776 | case SVM_EXITINTINFO_TYPE_NMI: | |
2777 | svm->vcpu.arch.nmi_injected = false; | |
2778 | break; | |
2779 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
2780 | if (svm->vmcb->control.exit_info_2 & |
2781 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
2782 | has_error_code = true; | |
2783 | error_code = | |
2784 | (u32)svm->vmcb->control.exit_info_2; | |
2785 | } | |
fe8e7f83 GN |
2786 | kvm_clear_exception_queue(&svm->vcpu); |
2787 | break; | |
2788 | case SVM_EXITINTINFO_TYPE_INTR: | |
2789 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2790 | break; | |
2791 | default: | |
2792 | break; | |
2793 | } | |
2794 | } | |
64a7ec06 | 2795 | |
8317c298 GN |
2796 | if (reason != TASK_SWITCH_GATE || |
2797 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
2798 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
2799 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
2800 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 | 2801 | |
7f3d35fd KW |
2802 | if (int_type != SVM_EXITINTINFO_TYPE_SOFT) |
2803 | int_vec = -1; | |
2804 | ||
2805 | if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason, | |
acb54517 GN |
2806 | has_error_code, error_code) == EMULATE_FAIL) { |
2807 | svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
2808 | svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
2809 | svm->vcpu.run->internal.ndata = 0; | |
2810 | return 0; | |
2811 | } | |
2812 | return 1; | |
6aa8b732 AK |
2813 | } |
2814 | ||
851ba692 | 2815 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 2816 | { |
5fdbf976 | 2817 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2818 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 2819 | return 1; |
6aa8b732 AK |
2820 | } |
2821 | ||
851ba692 | 2822 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
2823 | { |
2824 | ++svm->vcpu.stat.nmi_window_exits; | |
8a05a1b8 | 2825 | clr_intercept(svm, INTERCEPT_IRET); |
44c11430 | 2826 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
bd3d1ec3 | 2827 | svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu); |
95ba8273 GN |
2828 | return 1; |
2829 | } | |
2830 | ||
851ba692 | 2831 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 2832 | { |
df4f3108 AP |
2833 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) |
2834 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; | |
2835 | ||
2836 | kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1); | |
2837 | skip_emulated_instruction(&svm->vcpu); | |
2838 | return 1; | |
a7052897 MT |
2839 | } |
2840 | ||
851ba692 | 2841 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 2842 | { |
51d8b661 | 2843 | return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE; |
6aa8b732 AK |
2844 | } |
2845 | ||
332b56e4 AK |
2846 | static int rdpmc_interception(struct vcpu_svm *svm) |
2847 | { | |
2848 | int err; | |
2849 | ||
2850 | if (!static_cpu_has(X86_FEATURE_NRIPS)) | |
2851 | return emulate_on_interception(svm); | |
2852 | ||
2853 | err = kvm_rdpmc(&svm->vcpu); | |
2854 | kvm_complete_insn_gp(&svm->vcpu, err); | |
2855 | ||
2856 | return 1; | |
2857 | } | |
2858 | ||
628afd2a JR |
2859 | bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val) |
2860 | { | |
2861 | unsigned long cr0 = svm->vcpu.arch.cr0; | |
2862 | bool ret = false; | |
2863 | u64 intercept; | |
2864 | ||
2865 | intercept = svm->nested.intercept; | |
2866 | ||
2867 | if (!is_guest_mode(&svm->vcpu) || | |
2868 | (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))) | |
2869 | return false; | |
2870 | ||
2871 | cr0 &= ~SVM_CR0_SELECTIVE_MASK; | |
2872 | val &= ~SVM_CR0_SELECTIVE_MASK; | |
2873 | ||
2874 | if (cr0 ^ val) { | |
2875 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
2876 | ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE); | |
2877 | } | |
2878 | ||
2879 | return ret; | |
2880 | } | |
2881 | ||
7ff76d58 AP |
2882 | #define CR_VALID (1ULL << 63) |
2883 | ||
2884 | static int cr_interception(struct vcpu_svm *svm) | |
2885 | { | |
2886 | int reg, cr; | |
2887 | unsigned long val; | |
2888 | int err; | |
2889 | ||
2890 | if (!static_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
2891 | return emulate_on_interception(svm); | |
2892 | ||
2893 | if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) | |
2894 | return emulate_on_interception(svm); | |
2895 | ||
2896 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
2897 | cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0; | |
2898 | ||
2899 | err = 0; | |
2900 | if (cr >= 16) { /* mov to cr */ | |
2901 | cr -= 16; | |
2902 | val = kvm_register_read(&svm->vcpu, reg); | |
2903 | switch (cr) { | |
2904 | case 0: | |
628afd2a JR |
2905 | if (!check_selective_cr0_intercepted(svm, val)) |
2906 | err = kvm_set_cr0(&svm->vcpu, val); | |
977b2d03 JR |
2907 | else |
2908 | return 1; | |
2909 | ||
7ff76d58 AP |
2910 | break; |
2911 | case 3: | |
2912 | err = kvm_set_cr3(&svm->vcpu, val); | |
2913 | break; | |
2914 | case 4: | |
2915 | err = kvm_set_cr4(&svm->vcpu, val); | |
2916 | break; | |
2917 | case 8: | |
2918 | err = kvm_set_cr8(&svm->vcpu, val); | |
2919 | break; | |
2920 | default: | |
2921 | WARN(1, "unhandled write to CR%d", cr); | |
2922 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2923 | return 1; | |
2924 | } | |
2925 | } else { /* mov from cr */ | |
2926 | switch (cr) { | |
2927 | case 0: | |
2928 | val = kvm_read_cr0(&svm->vcpu); | |
2929 | break; | |
2930 | case 2: | |
2931 | val = svm->vcpu.arch.cr2; | |
2932 | break; | |
2933 | case 3: | |
9f8fe504 | 2934 | val = kvm_read_cr3(&svm->vcpu); |
7ff76d58 AP |
2935 | break; |
2936 | case 4: | |
2937 | val = kvm_read_cr4(&svm->vcpu); | |
2938 | break; | |
2939 | case 8: | |
2940 | val = kvm_get_cr8(&svm->vcpu); | |
2941 | break; | |
2942 | default: | |
2943 | WARN(1, "unhandled read from CR%d", cr); | |
2944 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2945 | return 1; | |
2946 | } | |
2947 | kvm_register_write(&svm->vcpu, reg, val); | |
2948 | } | |
2949 | kvm_complete_insn_gp(&svm->vcpu, err); | |
2950 | ||
2951 | return 1; | |
2952 | } | |
2953 | ||
cae3797a AP |
2954 | static int dr_interception(struct vcpu_svm *svm) |
2955 | { | |
2956 | int reg, dr; | |
2957 | unsigned long val; | |
2958 | int err; | |
2959 | ||
2960 | if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS)) | |
2961 | return emulate_on_interception(svm); | |
2962 | ||
2963 | reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; | |
2964 | dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0; | |
2965 | ||
2966 | if (dr >= 16) { /* mov to DRn */ | |
2967 | val = kvm_register_read(&svm->vcpu, reg); | |
2968 | kvm_set_dr(&svm->vcpu, dr - 16, val); | |
2969 | } else { | |
2970 | err = kvm_get_dr(&svm->vcpu, dr, &val); | |
2971 | if (!err) | |
2972 | kvm_register_write(&svm->vcpu, reg, val); | |
2973 | } | |
2974 | ||
2c46d2ae JR |
2975 | skip_emulated_instruction(&svm->vcpu); |
2976 | ||
cae3797a AP |
2977 | return 1; |
2978 | } | |
2979 | ||
851ba692 | 2980 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 2981 | { |
851ba692 | 2982 | struct kvm_run *kvm_run = svm->vcpu.run; |
eea1cff9 | 2983 | int r; |
851ba692 | 2984 | |
0a5fff19 GN |
2985 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
2986 | /* instruction emulation calls kvm_set_cr8() */ | |
7ff76d58 | 2987 | r = cr_interception(svm); |
95ba8273 | 2988 | if (irqchip_in_kernel(svm->vcpu.kvm)) { |
4ee546b4 | 2989 | clr_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
7ff76d58 | 2990 | return r; |
95ba8273 | 2991 | } |
0a5fff19 | 2992 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
7ff76d58 | 2993 | return r; |
1d075434 JR |
2994 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2995 | return 0; | |
2996 | } | |
2997 | ||
886b470c | 2998 | u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
d5c1785d NHE |
2999 | { |
3000 | struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu)); | |
3001 | return vmcb->control.tsc_offset + | |
886b470c | 3002 | svm_scale_tsc(vcpu, host_tsc); |
d5c1785d NHE |
3003 | } |
3004 | ||
6aa8b732 AK |
3005 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
3006 | { | |
a2fa3e9f GH |
3007 | struct vcpu_svm *svm = to_svm(vcpu); |
3008 | ||
6aa8b732 | 3009 | switch (ecx) { |
af24a4e4 | 3010 | case MSR_IA32_TSC: { |
45133eca | 3011 | *data = svm->vmcb->control.tsc_offset + |
fbc0db76 JR |
3012 | svm_scale_tsc(vcpu, native_read_tsc()); |
3013 | ||
6aa8b732 AK |
3014 | break; |
3015 | } | |
8c06585d | 3016 | case MSR_STAR: |
a2fa3e9f | 3017 | *data = svm->vmcb->save.star; |
6aa8b732 | 3018 | break; |
0e859cac | 3019 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3020 | case MSR_LSTAR: |
a2fa3e9f | 3021 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
3022 | break; |
3023 | case MSR_CSTAR: | |
a2fa3e9f | 3024 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
3025 | break; |
3026 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 3027 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
3028 | break; |
3029 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 3030 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
3031 | break; |
3032 | #endif | |
3033 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 3034 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
3035 | break; |
3036 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 3037 | *data = svm->sysenter_eip; |
6aa8b732 AK |
3038 | break; |
3039 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 3040 | *data = svm->sysenter_esp; |
6aa8b732 | 3041 | break; |
e0231715 JR |
3042 | /* |
3043 | * Nobody will change the following 5 values in the VMCB so we can | |
3044 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
3045 | * implemented. | |
3046 | */ | |
a2938c80 JR |
3047 | case MSR_IA32_DEBUGCTLMSR: |
3048 | *data = svm->vmcb->save.dbgctl; | |
3049 | break; | |
3050 | case MSR_IA32_LASTBRANCHFROMIP: | |
3051 | *data = svm->vmcb->save.br_from; | |
3052 | break; | |
3053 | case MSR_IA32_LASTBRANCHTOIP: | |
3054 | *data = svm->vmcb->save.br_to; | |
3055 | break; | |
3056 | case MSR_IA32_LASTINTFROMIP: | |
3057 | *data = svm->vmcb->save.last_excp_from; | |
3058 | break; | |
3059 | case MSR_IA32_LASTINTTOIP: | |
3060 | *data = svm->vmcb->save.last_excp_to; | |
3061 | break; | |
b286d5d8 | 3062 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 3063 | *data = svm->nested.hsave_msr; |
b286d5d8 | 3064 | break; |
eb6f302e | 3065 | case MSR_VM_CR: |
4a810181 | 3066 | *data = svm->nested.vm_cr_msr; |
eb6f302e | 3067 | break; |
c8a73f18 AG |
3068 | case MSR_IA32_UCODE_REV: |
3069 | *data = 0x01000065; | |
3070 | break; | |
6aa8b732 | 3071 | default: |
3bab1f5d | 3072 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
3073 | } |
3074 | return 0; | |
3075 | } | |
3076 | ||
851ba692 | 3077 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3078 | { |
ad312c7c | 3079 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
3080 | u64 data; |
3081 | ||
59200273 AK |
3082 | if (svm_get_msr(&svm->vcpu, ecx, &data)) { |
3083 | trace_kvm_msr_read_ex(ecx); | |
c1a5d4f9 | 3084 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 | 3085 | } else { |
229456fc | 3086 | trace_kvm_msr_read(ecx, data); |
af9ca2d7 | 3087 | |
5fdbf976 | 3088 | svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff; |
ad312c7c | 3089 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
5fdbf976 | 3090 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 3091 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
3092 | } |
3093 | return 1; | |
3094 | } | |
3095 | ||
4a810181 JR |
3096 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
3097 | { | |
3098 | struct vcpu_svm *svm = to_svm(vcpu); | |
3099 | int svm_dis, chg_mask; | |
3100 | ||
3101 | if (data & ~SVM_VM_CR_VALID_MASK) | |
3102 | return 1; | |
3103 | ||
3104 | chg_mask = SVM_VM_CR_VALID_MASK; | |
3105 | ||
3106 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
3107 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
3108 | ||
3109 | svm->nested.vm_cr_msr &= ~chg_mask; | |
3110 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
3111 | ||
3112 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
3113 | ||
3114 | /* check for svm_disable while efer.svme is set */ | |
3115 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
3116 | return 1; | |
3117 | ||
3118 | return 0; | |
3119 | } | |
3120 | ||
8fe8ab46 | 3121 | static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
6aa8b732 | 3122 | { |
a2fa3e9f GH |
3123 | struct vcpu_svm *svm = to_svm(vcpu); |
3124 | ||
8fe8ab46 WA |
3125 | u32 ecx = msr->index; |
3126 | u64 data = msr->data; | |
6aa8b732 | 3127 | switch (ecx) { |
f4e1b3c8 | 3128 | case MSR_IA32_TSC: |
8fe8ab46 | 3129 | kvm_write_tsc(vcpu, msr); |
6aa8b732 | 3130 | break; |
8c06585d | 3131 | case MSR_STAR: |
a2fa3e9f | 3132 | svm->vmcb->save.star = data; |
6aa8b732 | 3133 | break; |
49b14f24 | 3134 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3135 | case MSR_LSTAR: |
a2fa3e9f | 3136 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
3137 | break; |
3138 | case MSR_CSTAR: | |
a2fa3e9f | 3139 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
3140 | break; |
3141 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 3142 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
3143 | break; |
3144 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 3145 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
3146 | break; |
3147 | #endif | |
3148 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 3149 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
3150 | break; |
3151 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 3152 | svm->sysenter_eip = data; |
a2fa3e9f | 3153 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
3154 | break; |
3155 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 3156 | svm->sysenter_esp = data; |
a2fa3e9f | 3157 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 3158 | break; |
a2938c80 | 3159 | case MSR_IA32_DEBUGCTLMSR: |
2a6b20b8 | 3160 | if (!boot_cpu_has(X86_FEATURE_LBRV)) { |
a737f256 CD |
3161 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", |
3162 | __func__, data); | |
24e09cbf JR |
3163 | break; |
3164 | } | |
3165 | if (data & DEBUGCTL_RESERVED_BITS) | |
3166 | return 1; | |
3167 | ||
3168 | svm->vmcb->save.dbgctl = data; | |
b53ba3f9 | 3169 | mark_dirty(svm->vmcb, VMCB_LBR); |
24e09cbf JR |
3170 | if (data & (1ULL<<0)) |
3171 | svm_enable_lbrv(svm); | |
3172 | else | |
3173 | svm_disable_lbrv(svm); | |
a2938c80 | 3174 | break; |
b286d5d8 | 3175 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 3176 | svm->nested.hsave_msr = data; |
62b9abaa | 3177 | break; |
3c5d0a44 | 3178 | case MSR_VM_CR: |
4a810181 | 3179 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 3180 | case MSR_VM_IGNNE: |
a737f256 | 3181 | vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
3c5d0a44 | 3182 | break; |
6aa8b732 | 3183 | default: |
8fe8ab46 | 3184 | return kvm_set_msr_common(vcpu, msr); |
6aa8b732 AK |
3185 | } |
3186 | return 0; | |
3187 | } | |
3188 | ||
851ba692 | 3189 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3190 | { |
8fe8ab46 | 3191 | struct msr_data msr; |
ad312c7c | 3192 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
5fdbf976 | 3193 | u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u) |
ad312c7c | 3194 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
af9ca2d7 | 3195 | |
8fe8ab46 WA |
3196 | msr.data = data; |
3197 | msr.index = ecx; | |
3198 | msr.host_initiated = false; | |
af9ca2d7 | 3199 | |
5fdbf976 | 3200 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
8fe8ab46 | 3201 | if (svm_set_msr(&svm->vcpu, &msr)) { |
59200273 | 3202 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 3203 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 AK |
3204 | } else { |
3205 | trace_kvm_msr_write(ecx, data); | |
e756fc62 | 3206 | skip_emulated_instruction(&svm->vcpu); |
59200273 | 3207 | } |
6aa8b732 AK |
3208 | return 1; |
3209 | } | |
3210 | ||
851ba692 | 3211 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 3212 | { |
e756fc62 | 3213 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 3214 | return wrmsr_interception(svm); |
6aa8b732 | 3215 | else |
851ba692 | 3216 | return rdmsr_interception(svm); |
6aa8b732 AK |
3217 | } |
3218 | ||
851ba692 | 3219 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 3220 | { |
851ba692 AK |
3221 | struct kvm_run *kvm_run = svm->vcpu.run; |
3222 | ||
3842d135 | 3223 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
f0b85051 | 3224 | svm_clear_vintr(svm); |
85f455f7 | 3225 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
decdbf6a | 3226 | mark_dirty(svm->vmcb, VMCB_INTR); |
675acb75 | 3227 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
3228 | /* |
3229 | * If the user space waits to inject interrupts, exit as soon as | |
3230 | * possible | |
3231 | */ | |
8061823a GN |
3232 | if (!irqchip_in_kernel(svm->vcpu.kvm) && |
3233 | kvm_run->request_interrupt_window && | |
3234 | !kvm_cpu_has_interrupt(&svm->vcpu)) { | |
c1150d8c DL |
3235 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
3236 | return 0; | |
3237 | } | |
3238 | ||
3239 | return 1; | |
3240 | } | |
3241 | ||
565d0998 ML |
3242 | static int pause_interception(struct vcpu_svm *svm) |
3243 | { | |
3244 | kvm_vcpu_on_spin(&(svm->vcpu)); | |
3245 | return 1; | |
3246 | } | |
3247 | ||
09941fbb | 3248 | static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = { |
7ff76d58 AP |
3249 | [SVM_EXIT_READ_CR0] = cr_interception, |
3250 | [SVM_EXIT_READ_CR3] = cr_interception, | |
3251 | [SVM_EXIT_READ_CR4] = cr_interception, | |
3252 | [SVM_EXIT_READ_CR8] = cr_interception, | |
d225157b | 3253 | [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, |
628afd2a | 3254 | [SVM_EXIT_WRITE_CR0] = cr_interception, |
7ff76d58 AP |
3255 | [SVM_EXIT_WRITE_CR3] = cr_interception, |
3256 | [SVM_EXIT_WRITE_CR4] = cr_interception, | |
e0231715 | 3257 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
cae3797a AP |
3258 | [SVM_EXIT_READ_DR0] = dr_interception, |
3259 | [SVM_EXIT_READ_DR1] = dr_interception, | |
3260 | [SVM_EXIT_READ_DR2] = dr_interception, | |
3261 | [SVM_EXIT_READ_DR3] = dr_interception, | |
3262 | [SVM_EXIT_READ_DR4] = dr_interception, | |
3263 | [SVM_EXIT_READ_DR5] = dr_interception, | |
3264 | [SVM_EXIT_READ_DR6] = dr_interception, | |
3265 | [SVM_EXIT_READ_DR7] = dr_interception, | |
3266 | [SVM_EXIT_WRITE_DR0] = dr_interception, | |
3267 | [SVM_EXIT_WRITE_DR1] = dr_interception, | |
3268 | [SVM_EXIT_WRITE_DR2] = dr_interception, | |
3269 | [SVM_EXIT_WRITE_DR3] = dr_interception, | |
3270 | [SVM_EXIT_WRITE_DR4] = dr_interception, | |
3271 | [SVM_EXIT_WRITE_DR5] = dr_interception, | |
3272 | [SVM_EXIT_WRITE_DR6] = dr_interception, | |
3273 | [SVM_EXIT_WRITE_DR7] = dr_interception, | |
d0bfb940 JK |
3274 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
3275 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 3276 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 JR |
3277 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
3278 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, | |
3279 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, | |
3280 | [SVM_EXIT_INTR] = intr_interception, | |
c47f098d | 3281 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
3282 | [SVM_EXIT_SMI] = nop_on_interception, |
3283 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 3284 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
332b56e4 | 3285 | [SVM_EXIT_RDPMC] = rdpmc_interception, |
6aa8b732 | 3286 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 3287 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 3288 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 3289 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 3290 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 3291 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 3292 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 3293 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
3294 | [SVM_EXIT_MSR] = msr_interception, |
3295 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 3296 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 3297 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 3298 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
3299 | [SVM_EXIT_VMLOAD] = vmload_interception, |
3300 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
3301 | [SVM_EXIT_STGI] = stgi_interception, |
3302 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 3303 | [SVM_EXIT_SKINIT] = skinit_interception, |
cf5a94d1 | 3304 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
3305 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
3306 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
81dd35d4 | 3307 | [SVM_EXIT_XSETBV] = xsetbv_interception, |
709ddebf | 3308 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
3309 | }; |
3310 | ||
ae8cc059 | 3311 | static void dump_vmcb(struct kvm_vcpu *vcpu) |
3f10c846 JR |
3312 | { |
3313 | struct vcpu_svm *svm = to_svm(vcpu); | |
3314 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3315 | struct vmcb_save_area *save = &svm->vmcb->save; | |
3316 | ||
3317 | pr_err("VMCB Control Area:\n"); | |
ae8cc059 JP |
3318 | pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff); |
3319 | pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16); | |
3320 | pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff); | |
3321 | pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16); | |
3322 | pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions); | |
3323 | pr_err("%-20s%016llx\n", "intercepts:", control->intercept); | |
3324 | pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count); | |
3325 | pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa); | |
3326 | pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa); | |
3327 | pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset); | |
3328 | pr_err("%-20s%d\n", "asid:", control->asid); | |
3329 | pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl); | |
3330 | pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl); | |
3331 | pr_err("%-20s%08x\n", "int_vector:", control->int_vector); | |
3332 | pr_err("%-20s%08x\n", "int_state:", control->int_state); | |
3333 | pr_err("%-20s%08x\n", "exit_code:", control->exit_code); | |
3334 | pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1); | |
3335 | pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2); | |
3336 | pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info); | |
3337 | pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err); | |
3338 | pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl); | |
3339 | pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3); | |
3340 | pr_err("%-20s%08x\n", "event_inj:", control->event_inj); | |
3341 | pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err); | |
3342 | pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl); | |
3343 | pr_err("%-20s%016llx\n", "next_rip:", control->next_rip); | |
3f10c846 | 3344 | pr_err("VMCB State Save Area:\n"); |
ae8cc059 JP |
3345 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", |
3346 | "es:", | |
3347 | save->es.selector, save->es.attrib, | |
3348 | save->es.limit, save->es.base); | |
3349 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3350 | "cs:", | |
3351 | save->cs.selector, save->cs.attrib, | |
3352 | save->cs.limit, save->cs.base); | |
3353 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3354 | "ss:", | |
3355 | save->ss.selector, save->ss.attrib, | |
3356 | save->ss.limit, save->ss.base); | |
3357 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3358 | "ds:", | |
3359 | save->ds.selector, save->ds.attrib, | |
3360 | save->ds.limit, save->ds.base); | |
3361 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3362 | "fs:", | |
3363 | save->fs.selector, save->fs.attrib, | |
3364 | save->fs.limit, save->fs.base); | |
3365 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3366 | "gs:", | |
3367 | save->gs.selector, save->gs.attrib, | |
3368 | save->gs.limit, save->gs.base); | |
3369 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3370 | "gdtr:", | |
3371 | save->gdtr.selector, save->gdtr.attrib, | |
3372 | save->gdtr.limit, save->gdtr.base); | |
3373 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3374 | "ldtr:", | |
3375 | save->ldtr.selector, save->ldtr.attrib, | |
3376 | save->ldtr.limit, save->ldtr.base); | |
3377 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3378 | "idtr:", | |
3379 | save->idtr.selector, save->idtr.attrib, | |
3380 | save->idtr.limit, save->idtr.base); | |
3381 | pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n", | |
3382 | "tr:", | |
3383 | save->tr.selector, save->tr.attrib, | |
3384 | save->tr.limit, save->tr.base); | |
3f10c846 JR |
3385 | pr_err("cpl: %d efer: %016llx\n", |
3386 | save->cpl, save->efer); | |
ae8cc059 JP |
3387 | pr_err("%-15s %016llx %-13s %016llx\n", |
3388 | "cr0:", save->cr0, "cr2:", save->cr2); | |
3389 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3390 | "cr3:", save->cr3, "cr4:", save->cr4); | |
3391 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3392 | "dr6:", save->dr6, "dr7:", save->dr7); | |
3393 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3394 | "rip:", save->rip, "rflags:", save->rflags); | |
3395 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3396 | "rsp:", save->rsp, "rax:", save->rax); | |
3397 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3398 | "star:", save->star, "lstar:", save->lstar); | |
3399 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3400 | "cstar:", save->cstar, "sfmask:", save->sfmask); | |
3401 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3402 | "kernel_gs_base:", save->kernel_gs_base, | |
3403 | "sysenter_cs:", save->sysenter_cs); | |
3404 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3405 | "sysenter_esp:", save->sysenter_esp, | |
3406 | "sysenter_eip:", save->sysenter_eip); | |
3407 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3408 | "gpat:", save->g_pat, "dbgctl:", save->dbgctl); | |
3409 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3410 | "br_from:", save->br_from, "br_to:", save->br_to); | |
3411 | pr_err("%-15s %016llx %-13s %016llx\n", | |
3412 | "excp_from:", save->last_excp_from, | |
3413 | "excp_to:", save->last_excp_to); | |
3f10c846 JR |
3414 | } |
3415 | ||
586f9607 AK |
3416 | static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
3417 | { | |
3418 | struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control; | |
3419 | ||
3420 | *info1 = control->exit_info_1; | |
3421 | *info2 = control->exit_info_2; | |
3422 | } | |
3423 | ||
851ba692 | 3424 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 3425 | { |
04d2cc77 | 3426 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 3427 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 3428 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 3429 | |
4ee546b4 | 3430 | if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE)) |
2be4fc7a JR |
3431 | vcpu->arch.cr0 = svm->vmcb->save.cr0; |
3432 | if (npt_enabled) | |
3433 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 3434 | |
cd3ff653 JR |
3435 | if (unlikely(svm->nested.exit_required)) { |
3436 | nested_svm_vmexit(svm); | |
3437 | svm->nested.exit_required = false; | |
3438 | ||
3439 | return 1; | |
3440 | } | |
3441 | ||
2030753d | 3442 | if (is_guest_mode(vcpu)) { |
410e4d57 JR |
3443 | int vmexit; |
3444 | ||
d8cabddf JR |
3445 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
3446 | svm->vmcb->control.exit_info_1, | |
3447 | svm->vmcb->control.exit_info_2, | |
3448 | svm->vmcb->control.exit_int_info, | |
e097e5ff SH |
3449 | svm->vmcb->control.exit_int_info_err, |
3450 | KVM_ISA_SVM); | |
d8cabddf | 3451 | |
410e4d57 JR |
3452 | vmexit = nested_svm_exit_special(svm); |
3453 | ||
3454 | if (vmexit == NESTED_EXIT_CONTINUE) | |
3455 | vmexit = nested_svm_exit_handled(svm); | |
3456 | ||
3457 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 3458 | return 1; |
cf74a78b AG |
3459 | } |
3460 | ||
a5c3832d JR |
3461 | svm_complete_interrupts(svm); |
3462 | ||
04d2cc77 AK |
3463 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
3464 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
3465 | kvm_run->fail_entry.hardware_entry_failure_reason | |
3466 | = svm->vmcb->control.exit_code; | |
3f10c846 JR |
3467 | pr_err("KVM: FAILED VMRUN WITH VMCB:\n"); |
3468 | dump_vmcb(vcpu); | |
04d2cc77 AK |
3469 | return 0; |
3470 | } | |
3471 | ||
a2fa3e9f | 3472 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 3473 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
55c5e464 JR |
3474 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH && |
3475 | exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI) | |
6614c7d0 | 3476 | printk(KERN_ERR "%s: unexpected exit_int_info 0x%x " |
6aa8b732 | 3477 | "exit_code 0x%x\n", |
b8688d51 | 3478 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
3479 | exit_code); |
3480 | ||
9d8f549d | 3481 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 3482 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 3483 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 3484 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
3485 | return 0; |
3486 | } | |
3487 | ||
851ba692 | 3488 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
3489 | } |
3490 | ||
3491 | static void reload_tss(struct kvm_vcpu *vcpu) | |
3492 | { | |
3493 | int cpu = raw_smp_processor_id(); | |
3494 | ||
0fe1e009 TH |
3495 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
3496 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
3497 | load_TR_desc(); |
3498 | } | |
3499 | ||
e756fc62 | 3500 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
3501 | { |
3502 | int cpu = raw_smp_processor_id(); | |
3503 | ||
0fe1e009 | 3504 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 3505 | |
4b656b12 | 3506 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
3507 | if (svm->asid_generation != sd->asid_generation) |
3508 | new_asid(svm, sd); | |
6aa8b732 AK |
3509 | } |
3510 | ||
95ba8273 GN |
3511 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
3512 | { | |
3513 | struct vcpu_svm *svm = to_svm(vcpu); | |
3514 | ||
3515 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
3516 | vcpu->arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3517 | set_intercept(svm, INTERCEPT_IRET); |
95ba8273 GN |
3518 | ++vcpu->stat.nmi_injections; |
3519 | } | |
6aa8b732 | 3520 | |
85f455f7 | 3521 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
3522 | { |
3523 | struct vmcb_control_area *control; | |
3524 | ||
e756fc62 | 3525 | control = &svm->vmcb->control; |
85f455f7 | 3526 | control->int_vector = irq; |
6aa8b732 AK |
3527 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
3528 | control->int_ctl |= V_IRQ_MASK | | |
3529 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
decdbf6a | 3530 | mark_dirty(svm->vmcb, VMCB_INTR); |
6aa8b732 AK |
3531 | } |
3532 | ||
66fd3f7f | 3533 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
3534 | { |
3535 | struct vcpu_svm *svm = to_svm(vcpu); | |
3536 | ||
2af9194d | 3537 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 3538 | |
9fb2d2b4 GN |
3539 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
3540 | ++vcpu->stat.irq_injections; | |
3541 | ||
219b65dc AG |
3542 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
3543 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
3544 | } |
3545 | ||
95ba8273 | 3546 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
3547 | { |
3548 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 3549 | |
2030753d | 3550 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3551 | return; |
3552 | ||
95ba8273 | 3553 | if (irr == -1) |
aaacfc9a JR |
3554 | return; |
3555 | ||
95ba8273 | 3556 | if (tpr >= irr) |
4ee546b4 | 3557 | set_cr_intercept(svm, INTERCEPT_CR8_WRITE); |
95ba8273 | 3558 | } |
aaacfc9a | 3559 | |
8d14695f YZ |
3560 | static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) |
3561 | { | |
3562 | return; | |
3563 | } | |
3564 | ||
c7c9c56c YZ |
3565 | static int svm_vm_has_apicv(struct kvm *kvm) |
3566 | { | |
3567 | return 0; | |
3568 | } | |
3569 | ||
3570 | static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) | |
3571 | { | |
3572 | return; | |
3573 | } | |
3574 | ||
3575 | static void svm_hwapic_isr_update(struct kvm *kvm, int isr) | |
3576 | { | |
3577 | return; | |
3578 | } | |
3579 | ||
a20ed54d YZ |
3580 | static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu) |
3581 | { | |
3582 | return; | |
3583 | } | |
3584 | ||
95ba8273 GN |
3585 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
3586 | { | |
3587 | struct vcpu_svm *svm = to_svm(vcpu); | |
3588 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
3589 | int ret; |
3590 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
3591 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3592 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
3593 | ||
3594 | return ret; | |
aaacfc9a JR |
3595 | } |
3596 | ||
3cfc3092 JK |
3597 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
3598 | { | |
3599 | struct vcpu_svm *svm = to_svm(vcpu); | |
3600 | ||
3601 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3602 | } | |
3603 | ||
3604 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
3605 | { | |
3606 | struct vcpu_svm *svm = to_svm(vcpu); | |
3607 | ||
3608 | if (masked) { | |
3609 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
8a05a1b8 | 3610 | set_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3611 | } else { |
3612 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
8a05a1b8 | 3613 | clr_intercept(svm, INTERCEPT_IRET); |
3cfc3092 JK |
3614 | } |
3615 | } | |
3616 | ||
78646121 GN |
3617 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
3618 | { | |
3619 | struct vcpu_svm *svm = to_svm(vcpu); | |
3620 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
3621 | int ret; |
3622 | ||
3623 | if (!gif_set(svm) || | |
3624 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
3625 | return 0; | |
3626 | ||
f6e78475 | 3627 | ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF); |
7fcdb510 | 3628 | |
2030753d | 3629 | if (is_guest_mode(vcpu)) |
7fcdb510 JR |
3630 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); |
3631 | ||
3632 | return ret; | |
78646121 GN |
3633 | } |
3634 | ||
730dca42 | 3635 | static int enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 3636 | { |
219b65dc | 3637 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 3638 | |
e0231715 JR |
3639 | /* |
3640 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
3641 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
3642 | * get that intercept, this function will be called again though and | |
3643 | * we'll get the vintr intercept. | |
3644 | */ | |
8fe54654 | 3645 | if (gif_set(svm) && nested_svm_intr(svm)) { |
219b65dc AG |
3646 | svm_set_vintr(svm); |
3647 | svm_inject_irq(svm, 0x0); | |
3648 | } | |
730dca42 | 3649 | return 0; |
85f455f7 ED |
3650 | } |
3651 | ||
03b28f81 | 3652 | static int enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 3653 | { |
04d2cc77 | 3654 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 3655 | |
44c11430 GN |
3656 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
3657 | == HF_NMI_MASK) | |
03b28f81 | 3658 | return 0; /* IRET will cause a vm exit */ |
44c11430 | 3659 | |
e0231715 JR |
3660 | /* |
3661 | * Something prevents NMI from been injected. Single step over possible | |
3662 | * problem (IRET or exception injection or interrupt shadow) | |
3663 | */ | |
6be7d306 | 3664 | svm->nmi_singlestep = true; |
44c11430 | 3665 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
c8639010 | 3666 | update_db_bp_intercept(vcpu); |
03b28f81 | 3667 | return 0; |
c1150d8c DL |
3668 | } |
3669 | ||
cbc94022 IE |
3670 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
3671 | { | |
3672 | return 0; | |
3673 | } | |
3674 | ||
d9e368d6 AK |
3675 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
3676 | { | |
38e5e92f JR |
3677 | struct vcpu_svm *svm = to_svm(vcpu); |
3678 | ||
3679 | if (static_cpu_has(X86_FEATURE_FLUSHBYASID)) | |
3680 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID; | |
3681 | else | |
3682 | svm->asid_generation--; | |
d9e368d6 AK |
3683 | } |
3684 | ||
04d2cc77 AK |
3685 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
3686 | { | |
3687 | } | |
3688 | ||
d7bf8221 JR |
3689 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
3690 | { | |
3691 | struct vcpu_svm *svm = to_svm(vcpu); | |
3692 | ||
2030753d | 3693 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3694 | return; |
3695 | ||
4ee546b4 | 3696 | if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) { |
d7bf8221 | 3697 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; |
615d5193 | 3698 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
3699 | } |
3700 | } | |
3701 | ||
649d6864 JR |
3702 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
3703 | { | |
3704 | struct vcpu_svm *svm = to_svm(vcpu); | |
3705 | u64 cr8; | |
3706 | ||
2030753d | 3707 | if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
88ab24ad JR |
3708 | return; |
3709 | ||
649d6864 JR |
3710 | cr8 = kvm_get_cr8(vcpu); |
3711 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
3712 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
3713 | } | |
3714 | ||
9222be18 GN |
3715 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
3716 | { | |
3717 | u8 vector; | |
3718 | int type; | |
3719 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
3720 | unsigned int3_injected = svm->int3_injected; |
3721 | ||
3722 | svm->int3_injected = 0; | |
9222be18 | 3723 | |
bd3d1ec3 AK |
3724 | /* |
3725 | * If we've made progress since setting HF_IRET_MASK, we've | |
3726 | * executed an IRET and can allow NMI injection. | |
3727 | */ | |
3728 | if ((svm->vcpu.arch.hflags & HF_IRET_MASK) | |
3729 | && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) { | |
44c11430 | 3730 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); |
3842d135 AK |
3731 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3732 | } | |
44c11430 | 3733 | |
9222be18 GN |
3734 | svm->vcpu.arch.nmi_injected = false; |
3735 | kvm_clear_exception_queue(&svm->vcpu); | |
3736 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3737 | ||
3738 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
3739 | return; | |
3740 | ||
3842d135 AK |
3741 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3742 | ||
9222be18 GN |
3743 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; |
3744 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
3745 | ||
3746 | switch (type) { | |
3747 | case SVM_EXITINTINFO_TYPE_NMI: | |
3748 | svm->vcpu.arch.nmi_injected = true; | |
3749 | break; | |
3750 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
3751 | /* |
3752 | * In case of software exceptions, do not reinject the vector, | |
3753 | * but re-execute the instruction instead. Rewind RIP first | |
3754 | * if we emulated INT3 before. | |
3755 | */ | |
3756 | if (kvm_exception_is_soft(vector)) { | |
3757 | if (vector == BP_VECTOR && int3_injected && | |
3758 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
3759 | kvm_rip_write(&svm->vcpu, | |
3760 | kvm_rip_read(&svm->vcpu) - | |
3761 | int3_injected); | |
9222be18 | 3762 | break; |
66b7138f | 3763 | } |
9222be18 GN |
3764 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
3765 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 3766 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
3767 | |
3768 | } else | |
ce7ddec4 | 3769 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
3770 | break; |
3771 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 3772 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
3773 | break; |
3774 | default: | |
3775 | break; | |
3776 | } | |
3777 | } | |
3778 | ||
b463a6f7 AK |
3779 | static void svm_cancel_injection(struct kvm_vcpu *vcpu) |
3780 | { | |
3781 | struct vcpu_svm *svm = to_svm(vcpu); | |
3782 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3783 | ||
3784 | control->exit_int_info = control->event_inj; | |
3785 | control->exit_int_info_err = control->event_inj_err; | |
3786 | control->event_inj = 0; | |
3787 | svm_complete_interrupts(svm); | |
3788 | } | |
3789 | ||
851ba692 | 3790 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 3791 | { |
a2fa3e9f | 3792 | struct vcpu_svm *svm = to_svm(vcpu); |
d9e368d6 | 3793 | |
2041a06a JR |
3794 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
3795 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
3796 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
3797 | ||
cd3ff653 JR |
3798 | /* |
3799 | * A vmexit emulation is required before the vcpu can be executed | |
3800 | * again. | |
3801 | */ | |
3802 | if (unlikely(svm->nested.exit_required)) | |
3803 | return; | |
3804 | ||
e756fc62 | 3805 | pre_svm_run(svm); |
6aa8b732 | 3806 | |
649d6864 JR |
3807 | sync_lapic_to_cr8(vcpu); |
3808 | ||
cda0ffdd | 3809 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 3810 | |
04d2cc77 AK |
3811 | clgi(); |
3812 | ||
3813 | local_irq_enable(); | |
36241b8c | 3814 | |
6aa8b732 | 3815 | asm volatile ( |
7454766f AK |
3816 | "push %%" _ASM_BP "; \n\t" |
3817 | "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t" | |
3818 | "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t" | |
3819 | "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t" | |
3820 | "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t" | |
3821 | "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t" | |
3822 | "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 3823 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3824 | "mov %c[r8](%[svm]), %%r8 \n\t" |
3825 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
3826 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
3827 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
3828 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
3829 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
3830 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
3831 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
3832 | #endif |
3833 | ||
6aa8b732 | 3834 | /* Enter guest mode */ |
7454766f AK |
3835 | "push %%" _ASM_AX " \n\t" |
3836 | "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t" | |
4ecac3fd AK |
3837 | __ex(SVM_VMLOAD) "\n\t" |
3838 | __ex(SVM_VMRUN) "\n\t" | |
3839 | __ex(SVM_VMSAVE) "\n\t" | |
7454766f | 3840 | "pop %%" _ASM_AX " \n\t" |
6aa8b732 AK |
3841 | |
3842 | /* Save guest registers, load host registers */ | |
7454766f AK |
3843 | "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t" |
3844 | "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t" | |
3845 | "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t" | |
3846 | "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t" | |
3847 | "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t" | |
3848 | "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 3849 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3850 | "mov %%r8, %c[r8](%[svm]) \n\t" |
3851 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
3852 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
3853 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
3854 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
3855 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
3856 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
3857 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 3858 | #endif |
7454766f | 3859 | "pop %%" _ASM_BP |
6aa8b732 | 3860 | : |
fb3f0f51 | 3861 | : [svm]"a"(svm), |
6aa8b732 | 3862 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
3863 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
3864 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
3865 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
3866 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
3867 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
3868 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 3869 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
3870 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
3871 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
3872 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
3873 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
3874 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
3875 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
3876 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
3877 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 3878 | #endif |
54a08c04 LV |
3879 | : "cc", "memory" |
3880 | #ifdef CONFIG_X86_64 | |
7454766f | 3881 | , "rbx", "rcx", "rdx", "rsi", "rdi" |
54a08c04 | 3882 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
7454766f AK |
3883 | #else |
3884 | , "ebx", "ecx", "edx", "esi", "edi" | |
54a08c04 LV |
3885 | #endif |
3886 | ); | |
6aa8b732 | 3887 | |
82ca2d10 AK |
3888 | #ifdef CONFIG_X86_64 |
3889 | wrmsrl(MSR_GS_BASE, svm->host.gs_base); | |
3890 | #else | |
dacccfdd | 3891 | loadsegment(fs, svm->host.fs); |
831ca609 AK |
3892 | #ifndef CONFIG_X86_32_LAZY_GS |
3893 | loadsegment(gs, svm->host.gs); | |
3894 | #endif | |
9581d442 | 3895 | #endif |
6aa8b732 AK |
3896 | |
3897 | reload_tss(vcpu); | |
3898 | ||
56ba47dd AK |
3899 | local_irq_disable(); |
3900 | ||
13c34e07 AK |
3901 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
3902 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
3903 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
3904 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
3905 | ||
1e2b1dd7 JK |
3906 | trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM); |
3907 | ||
3781c01c JR |
3908 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) |
3909 | kvm_before_handle_nmi(&svm->vcpu); | |
3910 | ||
3911 | stgi(); | |
3912 | ||
3913 | /* Any pending NMI will happen here */ | |
3914 | ||
3915 | if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) | |
3916 | kvm_after_handle_nmi(&svm->vcpu); | |
3917 | ||
d7bf8221 JR |
3918 | sync_cr8_to_lapic(vcpu); |
3919 | ||
a2fa3e9f | 3920 | svm->next_rip = 0; |
9222be18 | 3921 | |
38e5e92f JR |
3922 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
3923 | ||
631bc487 GN |
3924 | /* if exit due to PF check for async PF */ |
3925 | if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
3926 | svm->apf_reason = kvm_read_and_reset_pf_reason(); | |
3927 | ||
6de4f3ad AK |
3928 | if (npt_enabled) { |
3929 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
3930 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
3931 | } | |
fe5913e4 JR |
3932 | |
3933 | /* | |
3934 | * We need to handle MC intercepts here before the vcpu has a chance to | |
3935 | * change the physical cpu | |
3936 | */ | |
3937 | if (unlikely(svm->vmcb->control.exit_code == | |
3938 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
3939 | svm_handle_mce(svm); | |
8d28fec4 RJ |
3940 | |
3941 | mark_all_clean(svm->vmcb); | |
6aa8b732 AK |
3942 | } |
3943 | ||
6aa8b732 AK |
3944 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3945 | { | |
a2fa3e9f GH |
3946 | struct vcpu_svm *svm = to_svm(vcpu); |
3947 | ||
3948 | svm->vmcb->save.cr3 = root; | |
dcca1a65 | 3949 | mark_dirty(svm->vmcb, VMCB_CR); |
f40f6a45 | 3950 | svm_flush_tlb(vcpu); |
6aa8b732 AK |
3951 | } |
3952 | ||
1c97f0a0 JR |
3953 | static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3954 | { | |
3955 | struct vcpu_svm *svm = to_svm(vcpu); | |
3956 | ||
3957 | svm->vmcb->control.nested_cr3 = root; | |
b2747166 | 3958 | mark_dirty(svm->vmcb, VMCB_NPT); |
1c97f0a0 JR |
3959 | |
3960 | /* Also sync guest cr3 here in case we live migrate */ | |
9f8fe504 | 3961 | svm->vmcb->save.cr3 = kvm_read_cr3(vcpu); |
dcca1a65 | 3962 | mark_dirty(svm->vmcb, VMCB_CR); |
1c97f0a0 | 3963 | |
f40f6a45 | 3964 | svm_flush_tlb(vcpu); |
1c97f0a0 JR |
3965 | } |
3966 | ||
6aa8b732 AK |
3967 | static int is_disabled(void) |
3968 | { | |
6031a61c JR |
3969 | u64 vm_cr; |
3970 | ||
3971 | rdmsrl(MSR_VM_CR, vm_cr); | |
3972 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
3973 | return 1; | |
3974 | ||
6aa8b732 AK |
3975 | return 0; |
3976 | } | |
3977 | ||
102d8325 IM |
3978 | static void |
3979 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
3980 | { | |
3981 | /* | |
3982 | * Patch in the VMMCALL instruction: | |
3983 | */ | |
3984 | hypercall[0] = 0x0f; | |
3985 | hypercall[1] = 0x01; | |
3986 | hypercall[2] = 0xd9; | |
102d8325 IM |
3987 | } |
3988 | ||
002c7f7c YS |
3989 | static void svm_check_processor_compat(void *rtn) |
3990 | { | |
3991 | *(int *)rtn = 0; | |
3992 | } | |
3993 | ||
774ead3a AK |
3994 | static bool svm_cpu_has_accelerated_tpr(void) |
3995 | { | |
3996 | return false; | |
3997 | } | |
3998 | ||
4b12f0de | 3999 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 SY |
4000 | { |
4001 | return 0; | |
4002 | } | |
4003 | ||
0e851880 SY |
4004 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
4005 | { | |
4006 | } | |
4007 | ||
d4330ef2 JR |
4008 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
4009 | { | |
c2c63a49 | 4010 | switch (func) { |
4c62a2dc JR |
4011 | case 0x80000001: |
4012 | if (nested) | |
4013 | entry->ecx |= (1 << 2); /* Set SVM bit */ | |
4014 | break; | |
c2c63a49 JR |
4015 | case 0x8000000A: |
4016 | entry->eax = 1; /* SVM revision 1 */ | |
4017 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
4018 | ASID emulation to nested SVM */ | |
4019 | entry->ecx = 0; /* Reserved */ | |
7a190667 JR |
4020 | entry->edx = 0; /* Per default do not support any |
4021 | additional features */ | |
4022 | ||
4023 | /* Support next_rip if host supports it */ | |
2a6b20b8 | 4024 | if (boot_cpu_has(X86_FEATURE_NRIPS)) |
7a190667 | 4025 | entry->edx |= SVM_FEATURE_NRIP; |
c2c63a49 | 4026 | |
3d4aeaad JR |
4027 | /* Support NPT for the guest if enabled */ |
4028 | if (npt_enabled) | |
4029 | entry->edx |= SVM_FEATURE_NPT; | |
4030 | ||
c2c63a49 JR |
4031 | break; |
4032 | } | |
d4330ef2 JR |
4033 | } |
4034 | ||
17cc3935 | 4035 | static int svm_get_lpage_level(void) |
344f414f | 4036 | { |
17cc3935 | 4037 | return PT_PDPE_LEVEL; |
344f414f JR |
4038 | } |
4039 | ||
4e47c7a6 SY |
4040 | static bool svm_rdtscp_supported(void) |
4041 | { | |
4042 | return false; | |
4043 | } | |
4044 | ||
ad756a16 MJ |
4045 | static bool svm_invpcid_supported(void) |
4046 | { | |
4047 | return false; | |
4048 | } | |
4049 | ||
f5f48ee1 SY |
4050 | static bool svm_has_wbinvd_exit(void) |
4051 | { | |
4052 | return true; | |
4053 | } | |
4054 | ||
02daab21 AK |
4055 | static void svm_fpu_deactivate(struct kvm_vcpu *vcpu) |
4056 | { | |
4057 | struct vcpu_svm *svm = to_svm(vcpu); | |
4058 | ||
18c918c5 | 4059 | set_exception_intercept(svm, NM_VECTOR); |
66a562f7 | 4060 | update_cr0_intercept(svm); |
02daab21 AK |
4061 | } |
4062 | ||
8061252e | 4063 | #define PRE_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 4064 | .stage = X86_ICPT_PRE_EXCEPT, } |
cfec82cb | 4065 | #define POST_EX(exit) { .exit_code = (exit), \ |
40e19b51 | 4066 | .stage = X86_ICPT_POST_EXCEPT, } |
d7eb8203 | 4067 | #define POST_MEM(exit) { .exit_code = (exit), \ |
40e19b51 | 4068 | .stage = X86_ICPT_POST_MEMACCESS, } |
cfec82cb | 4069 | |
09941fbb | 4070 | static const struct __x86_intercept { |
cfec82cb JR |
4071 | u32 exit_code; |
4072 | enum x86_intercept_stage stage; | |
cfec82cb JR |
4073 | } x86_intercept_map[] = { |
4074 | [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0), | |
4075 | [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4076 | [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4077 | [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0), | |
4078 | [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0), | |
3b88e41a JR |
4079 | [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0), |
4080 | [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0), | |
dee6bb70 JR |
4081 | [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ), |
4082 | [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ), | |
4083 | [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE), | |
4084 | [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE), | |
4085 | [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ), | |
4086 | [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ), | |
4087 | [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE), | |
4088 | [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE), | |
01de8b09 JR |
4089 | [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN), |
4090 | [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL), | |
4091 | [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD), | |
4092 | [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE), | |
4093 | [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI), | |
4094 | [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI), | |
4095 | [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT), | |
4096 | [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA), | |
d7eb8203 JR |
4097 | [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP), |
4098 | [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR), | |
4099 | [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT), | |
8061252e JR |
4100 | [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG), |
4101 | [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD), | |
4102 | [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD), | |
4103 | [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR), | |
4104 | [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC), | |
4105 | [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR), | |
4106 | [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC), | |
4107 | [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID), | |
4108 | [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM), | |
bf608f88 JR |
4109 | [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE), |
4110 | [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF), | |
4111 | [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF), | |
4112 | [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT), | |
4113 | [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET), | |
4114 | [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP), | |
4115 | [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT), | |
f6511935 JR |
4116 | [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO), |
4117 | [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO), | |
4118 | [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO), | |
4119 | [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO), | |
cfec82cb JR |
4120 | }; |
4121 | ||
8061252e | 4122 | #undef PRE_EX |
cfec82cb | 4123 | #undef POST_EX |
d7eb8203 | 4124 | #undef POST_MEM |
cfec82cb | 4125 | |
8a76d7f2 JR |
4126 | static int svm_check_intercept(struct kvm_vcpu *vcpu, |
4127 | struct x86_instruction_info *info, | |
4128 | enum x86_intercept_stage stage) | |
4129 | { | |
cfec82cb JR |
4130 | struct vcpu_svm *svm = to_svm(vcpu); |
4131 | int vmexit, ret = X86EMUL_CONTINUE; | |
4132 | struct __x86_intercept icpt_info; | |
4133 | struct vmcb *vmcb = svm->vmcb; | |
4134 | ||
4135 | if (info->intercept >= ARRAY_SIZE(x86_intercept_map)) | |
4136 | goto out; | |
4137 | ||
4138 | icpt_info = x86_intercept_map[info->intercept]; | |
4139 | ||
40e19b51 | 4140 | if (stage != icpt_info.stage) |
cfec82cb JR |
4141 | goto out; |
4142 | ||
4143 | switch (icpt_info.exit_code) { | |
4144 | case SVM_EXIT_READ_CR0: | |
4145 | if (info->intercept == x86_intercept_cr_read) | |
4146 | icpt_info.exit_code += info->modrm_reg; | |
4147 | break; | |
4148 | case SVM_EXIT_WRITE_CR0: { | |
4149 | unsigned long cr0, val; | |
4150 | u64 intercept; | |
4151 | ||
4152 | if (info->intercept == x86_intercept_cr_write) | |
4153 | icpt_info.exit_code += info->modrm_reg; | |
4154 | ||
4155 | if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0) | |
4156 | break; | |
4157 | ||
4158 | intercept = svm->nested.intercept; | |
4159 | ||
4160 | if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))) | |
4161 | break; | |
4162 | ||
4163 | cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK; | |
4164 | val = info->src_val & ~SVM_CR0_SELECTIVE_MASK; | |
4165 | ||
4166 | if (info->intercept == x86_intercept_lmsw) { | |
4167 | cr0 &= 0xfUL; | |
4168 | val &= 0xfUL; | |
4169 | /* lmsw can't clear PE - catch this here */ | |
4170 | if (cr0 & X86_CR0_PE) | |
4171 | val |= X86_CR0_PE; | |
4172 | } | |
4173 | ||
4174 | if (cr0 ^ val) | |
4175 | icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
4176 | ||
4177 | break; | |
4178 | } | |
3b88e41a JR |
4179 | case SVM_EXIT_READ_DR0: |
4180 | case SVM_EXIT_WRITE_DR0: | |
4181 | icpt_info.exit_code += info->modrm_reg; | |
4182 | break; | |
8061252e JR |
4183 | case SVM_EXIT_MSR: |
4184 | if (info->intercept == x86_intercept_wrmsr) | |
4185 | vmcb->control.exit_info_1 = 1; | |
4186 | else | |
4187 | vmcb->control.exit_info_1 = 0; | |
4188 | break; | |
bf608f88 JR |
4189 | case SVM_EXIT_PAUSE: |
4190 | /* | |
4191 | * We get this for NOP only, but pause | |
4192 | * is rep not, check this here | |
4193 | */ | |
4194 | if (info->rep_prefix != REPE_PREFIX) | |
4195 | goto out; | |
f6511935 JR |
4196 | case SVM_EXIT_IOIO: { |
4197 | u64 exit_info; | |
4198 | u32 bytes; | |
4199 | ||
4200 | exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16; | |
4201 | ||
4202 | if (info->intercept == x86_intercept_in || | |
4203 | info->intercept == x86_intercept_ins) { | |
4204 | exit_info |= SVM_IOIO_TYPE_MASK; | |
4205 | bytes = info->src_bytes; | |
4206 | } else { | |
4207 | bytes = info->dst_bytes; | |
4208 | } | |
4209 | ||
4210 | if (info->intercept == x86_intercept_outs || | |
4211 | info->intercept == x86_intercept_ins) | |
4212 | exit_info |= SVM_IOIO_STR_MASK; | |
4213 | ||
4214 | if (info->rep_prefix) | |
4215 | exit_info |= SVM_IOIO_REP_MASK; | |
4216 | ||
4217 | bytes = min(bytes, 4u); | |
4218 | ||
4219 | exit_info |= bytes << SVM_IOIO_SIZE_SHIFT; | |
4220 | ||
4221 | exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1); | |
4222 | ||
4223 | vmcb->control.exit_info_1 = exit_info; | |
4224 | vmcb->control.exit_info_2 = info->next_rip; | |
4225 | ||
4226 | break; | |
4227 | } | |
cfec82cb JR |
4228 | default: |
4229 | break; | |
4230 | } | |
4231 | ||
4232 | vmcb->control.next_rip = info->next_rip; | |
4233 | vmcb->control.exit_code = icpt_info.exit_code; | |
4234 | vmexit = nested_svm_exit_handled(svm); | |
4235 | ||
4236 | ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED | |
4237 | : X86EMUL_CONTINUE; | |
4238 | ||
4239 | out: | |
4240 | return ret; | |
8a76d7f2 JR |
4241 | } |
4242 | ||
a547c6db YZ |
4243 | static void svm_handle_external_intr(struct kvm_vcpu *vcpu) |
4244 | { | |
4245 | local_irq_enable(); | |
4246 | } | |
4247 | ||
cbdd1bea | 4248 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
4249 | .cpu_has_kvm_support = has_svm, |
4250 | .disabled_by_bios = is_disabled, | |
4251 | .hardware_setup = svm_hardware_setup, | |
4252 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 4253 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
4254 | .hardware_enable = svm_hardware_enable, |
4255 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 4256 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
4257 | |
4258 | .vcpu_create = svm_create_vcpu, | |
4259 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 4260 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 4261 | |
04d2cc77 | 4262 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
4263 | .vcpu_load = svm_vcpu_load, |
4264 | .vcpu_put = svm_vcpu_put, | |
4265 | ||
c8639010 | 4266 | .update_db_bp_intercept = update_db_bp_intercept, |
6aa8b732 AK |
4267 | .get_msr = svm_get_msr, |
4268 | .set_msr = svm_set_msr, | |
4269 | .get_segment_base = svm_get_segment_base, | |
4270 | .get_segment = svm_get_segment, | |
4271 | .set_segment = svm_set_segment, | |
2e4d2653 | 4272 | .get_cpl = svm_get_cpl, |
1747fb71 | 4273 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 4274 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
aff48baa | 4275 | .decache_cr3 = svm_decache_cr3, |
25c4c276 | 4276 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 4277 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
4278 | .set_cr3 = svm_set_cr3, |
4279 | .set_cr4 = svm_set_cr4, | |
4280 | .set_efer = svm_set_efer, | |
4281 | .get_idt = svm_get_idt, | |
4282 | .set_idt = svm_set_idt, | |
4283 | .get_gdt = svm_get_gdt, | |
4284 | .set_gdt = svm_set_gdt, | |
020df079 | 4285 | .set_dr7 = svm_set_dr7, |
6de4f3ad | 4286 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
4287 | .get_rflags = svm_get_rflags, |
4288 | .set_rflags = svm_set_rflags, | |
6b52d186 | 4289 | .fpu_activate = svm_fpu_activate, |
02daab21 | 4290 | .fpu_deactivate = svm_fpu_deactivate, |
6aa8b732 | 4291 | |
6aa8b732 | 4292 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 4293 | |
6aa8b732 | 4294 | .run = svm_vcpu_run, |
04d2cc77 | 4295 | .handle_exit = handle_exit, |
6aa8b732 | 4296 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
4297 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
4298 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 4299 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 4300 | .set_irq = svm_set_irq, |
95ba8273 | 4301 | .set_nmi = svm_inject_nmi, |
298101da | 4302 | .queue_exception = svm_queue_exception, |
b463a6f7 | 4303 | .cancel_injection = svm_cancel_injection, |
78646121 | 4304 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 4305 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
4306 | .get_nmi_mask = svm_get_nmi_mask, |
4307 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
4308 | .enable_nmi_window = enable_nmi_window, |
4309 | .enable_irq_window = enable_irq_window, | |
4310 | .update_cr8_intercept = update_cr8_intercept, | |
8d14695f | 4311 | .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode, |
c7c9c56c YZ |
4312 | .vm_has_apicv = svm_vm_has_apicv, |
4313 | .load_eoi_exitmap = svm_load_eoi_exitmap, | |
4314 | .hwapic_isr_update = svm_hwapic_isr_update, | |
a20ed54d | 4315 | .sync_pir_to_irr = svm_sync_pir_to_irr, |
cbc94022 IE |
4316 | |
4317 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 4318 | .get_tdp_level = get_npt_level, |
4b12f0de | 4319 | .get_mt_mask = svm_get_mt_mask, |
229456fc | 4320 | |
586f9607 | 4321 | .get_exit_info = svm_get_exit_info, |
586f9607 | 4322 | |
17cc3935 | 4323 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
4324 | |
4325 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
4326 | |
4327 | .rdtscp_supported = svm_rdtscp_supported, | |
ad756a16 | 4328 | .invpcid_supported = svm_invpcid_supported, |
d4330ef2 JR |
4329 | |
4330 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
4331 | |
4332 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
99e3e30a | 4333 | |
4051b188 | 4334 | .set_tsc_khz = svm_set_tsc_khz, |
ba904635 | 4335 | .read_tsc_offset = svm_read_tsc_offset, |
99e3e30a | 4336 | .write_tsc_offset = svm_write_tsc_offset, |
e48672fa | 4337 | .adjust_tsc_offset = svm_adjust_tsc_offset, |
857e4099 | 4338 | .compute_tsc_offset = svm_compute_tsc_offset, |
d5c1785d | 4339 | .read_l1_tsc = svm_read_l1_tsc, |
1c97f0a0 JR |
4340 | |
4341 | .set_tdp_cr3 = set_tdp_cr3, | |
8a76d7f2 JR |
4342 | |
4343 | .check_intercept = svm_check_intercept, | |
a547c6db | 4344 | .handle_external_intr = svm_handle_external_intr, |
6aa8b732 AK |
4345 | }; |
4346 | ||
4347 | static int __init svm_init(void) | |
4348 | { | |
cb498ea2 | 4349 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 4350 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
4351 | } |
4352 | ||
4353 | static void __exit svm_exit(void) | |
4354 | { | |
cb498ea2 | 4355 | kvm_exit(); |
6aa8b732 AK |
4356 | } |
4357 | ||
4358 | module_init(svm_init) | |
4359 | module_exit(svm_exit) |