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KVM: SVM: Reset MMU on nested_svm_vmrun for NPT too
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
5a0e3ad6 29#include <linux/slab.h>
6aa8b732 30
e495606d 31#include <asm/desc.h>
6aa8b732 32
63d1142f 33#include <asm/virtext.h>
229456fc 34#include "trace.h"
63d1142f 35
4ecac3fd
AK		 36#define __ex(x) __kvm_handle_fault_on_reboot(x)
37
6aa8b732
AK		 38MODULE_AUTHOR("Qumranet");
39MODULE_LICENSE("GPL");
40
41#define IOPM_ALLOC_ORDER 2
42#define MSRPM_ALLOC_ORDER 1
43
6aa8b732
AK		 44#define SEG_TYPE_LDT 2
45#define SEG_TYPE_BUSY_TSS16 3
46
80b7706e
JR		 47#define SVM_FEATURE_NPT (1 << 0)
48#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 49#define SVM_FEATURE_SVML (1 << 2)
66b7138f 50#define SVM_FEATURE_NRIP (1 << 3)
565d0998 51#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 52
410e4d57
JR		 53#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
54#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
55#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
56
24e09cbf
JR		 57#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
58
6c8166a7
AK		 59static const u32 host_save_user_msrs[] = {
60#ifdef CONFIG_X86_64
61 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
62 MSR_FS_BASE,
63#endif
64 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
65};
66
67#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
68
69struct kvm_vcpu;
70
e6aa9abd
JR		 71struct nested_state {
72 struct vmcb *hsave;
73 u64 hsave_msr;
74 u64 vmcb;
75
76 /* These are the merged vectors */
77 u32 *msrpm;
78
79 /* gpa pointers to the real vectors */
80 u64 vmcb_msrpm;
aad42c64 81
cd3ff653
JR		 82 /* A VMEXIT is required but not yet emulated */
83 bool exit_required;
84
aad42c64
JR		 85 /* cache for intercepts of the guest */
86 u16 intercept_cr_read;
87 u16 intercept_cr_write;
88 u16 intercept_dr_read;
89 u16 intercept_dr_write;
90 u32 intercept_exceptions;
91 u64 intercept;
92
e6aa9abd
JR		 93};
94
6c8166a7
AK		 95struct vcpu_svm {
96 struct kvm_vcpu vcpu;
97 struct vmcb *vmcb;
98 unsigned long vmcb_pa;
99 struct svm_cpu_data *svm_data;
100 uint64_t asid_generation;
101 uint64_t sysenter_esp;
102 uint64_t sysenter_eip;
103
104 u64 next_rip;
105
106 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
107 u64 host_gs_base;
6c8166a7
AK		 108
109 u32 *msrpm;
6c8166a7 110
e6aa9abd 111 struct nested_state nested;
6be7d306
JK		 112
113 bool nmi_singlestep;
66b7138f
JK		 114
115 unsigned int3_injected;
116 unsigned long int3_rip;
6c8166a7
AK		 117};
118
709ddebf
JR		 119/* enable NPT for AMD64 and X86 with PAE */
120#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
121static bool npt_enabled = true;
122#else
e0231715 123static bool npt_enabled;
709ddebf 124#endif
6c7dac72
JR		 125static int npt = 1;
126
127module_param(npt, int, S_IRUGO);
e3da3acd 128
4b6e4dca 129static int nested = 1;
236de055
AG		 130module_param(nested, int, S_IRUGO);
131
44874f84 132static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 133static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 134
410e4d57 135static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 136static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 137static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 138static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
139 bool has_error_code, u32 error_code);
140
a2fa3e9f
GH		 141static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
142{
fb3f0f51 143 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 144}
145
3d6368ef
AG		 146static inline bool is_nested(struct vcpu_svm *svm)
147{
e6aa9abd 148 return svm->nested.vmcb;
3d6368ef
AG		 149}
150
2af9194d
JR		 151static inline void enable_gif(struct vcpu_svm *svm)
152{
153 svm->vcpu.arch.hflags |= HF_GIF_MASK;
154}
155
156static inline void disable_gif(struct vcpu_svm *svm)
157{
158 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
159}
160
161static inline bool gif_set(struct vcpu_svm *svm)
162{
163 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
164}
165
4866d5e3 166static unsigned long iopm_base;
6aa8b732
AK		 167
168struct kvm_ldttss_desc {
169 u16 limit0;
170 u16 base0;
e0231715
JR		 171 unsigned base1:8, type:5, dpl:2, p:1;
172 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 173 u32 base3;
174 u32 zero1;
175} __attribute__((packed));
176
177struct svm_cpu_data {
178 int cpu;
179
5008fdf5
AK		 180 u64 asid_generation;
181 u32 max_asid;
182 u32 next_asid;
6aa8b732
AK		 183 struct kvm_ldttss_desc *tss_desc;
184
185 struct page *save_area;
186};
187
188static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 189static uint32_t svm_features;
6aa8b732
AK		 190
191struct svm_init_data {
192 int cpu;
193 int r;
194};
195
196static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
197
9d8f549d 198#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 199#define MSRS_RANGE_SIZE 2048
200#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
201
202#define MAX_INST_SIZE 15
203
80b7706e
JR		 204static inline u32 svm_has(u32 feat)
205{
206 return svm_features & feat;
207}
208
6aa8b732
AK		 209static inline void clgi(void)
210{
4ecac3fd 211 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 212}
213
214static inline void stgi(void)
215{
4ecac3fd 216 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 217}
218
219static inline void invlpga(unsigned long addr, u32 asid)
220{
e0231715 221 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 222}
223
6aa8b732
AK		 224static inline void force_new_asid(struct kvm_vcpu *vcpu)
225{
a2fa3e9f 226 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 227}
228
229static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
230{
231 force_new_asid(vcpu);
232}
233
234static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
235{
709ddebf 236 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 237 efer &= ~EFER_LME;
6aa8b732 238
9962d032 239 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
f6801dff 240 vcpu->arch.efer = efer;
6aa8b732
AK		 241}
242
6aa8b732
AK		 243static int is_external_interrupt(u32 info)
244{
245 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
246 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
247}
248
2809f5d2
GC		 249static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
250{
251 struct vcpu_svm *svm = to_svm(vcpu);
252 u32 ret = 0;
253
254 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 255 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 256 return ret & mask;
257}
258
259static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
260{
261 struct vcpu_svm *svm = to_svm(vcpu);
262
263 if (mask == 0)
264 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
265 else
266 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
267
268}
269
6aa8b732
AK		 270static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
271{
a2fa3e9f
GH		 272 struct vcpu_svm *svm = to_svm(vcpu);
273
274 if (!svm->next_rip) {
851ba692 275 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 276 EMULATE_DONE)
277 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 278 return;
279 }
5fdbf976
MT		 280 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
281 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
282 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 283
5fdbf976 284 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 285 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 286}
287
116a4752
JK		 288static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
289 bool has_error_code, u32 error_code)
290{
291 struct vcpu_svm *svm = to_svm(vcpu);
292
e0231715
JR		 293 /*
294 * If we are within a nested VM we'd better #VMEXIT and let the guest
295 * handle the exception
296 */
116a4752
JK		 297 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
298 return;
299
66b7138f
JK		 300 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
301 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
302
303 /*
304 * For guest debugging where we have to reinject #BP if some
305 * INT3 is guest-owned:
306 * Emulate nRIP by moving RIP forward. Will fail if injection
307 * raises a fault that is not intercepted. Still better than
308 * failing in all cases.
309 */
310 skip_emulated_instruction(&svm->vcpu);
311 rip = kvm_rip_read(&svm->vcpu);
312 svm->int3_rip = rip + svm->vmcb->save.cs.base;
313 svm->int3_injected = rip - old_rip;
314 }
315
116a4752
JK		 316 svm->vmcb->control.event_inj = nr
317 | SVM_EVTINJ_VALID
318 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
319 | SVM_EVTINJ_TYPE_EXEPT;
320 svm->vmcb->control.event_inj_err = error_code;
321}
322
6aa8b732
AK		 323static int has_svm(void)
324{
63d1142f 325 const char *msg;
6aa8b732 326
63d1142f 327 if (!cpu_has_svm(&msg)) {
ff81ff10 328 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 329 return 0;
330 }
331
6aa8b732
AK		 332 return 1;
333}
334
335static void svm_hardware_disable(void *garbage)
336{
2c8dceeb 337 cpu_svm_disable();
6aa8b732
AK		 338}
339
10474ae8 340static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 341{
342
0fe1e009 343 struct svm_cpu_data *sd;
6aa8b732 344 uint64_t efer;
89a27f4d 345 struct desc_ptr gdt_descr;
6aa8b732
AK		 346 struct desc_struct *gdt;
347 int me = raw_smp_processor_id();
348
10474ae8
AG		 349 rdmsrl(MSR_EFER, efer);
350 if (efer & EFER_SVME)
351 return -EBUSY;
352
6aa8b732 353 if (!has_svm()) {
e6732a5a
ZA		 354 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
355 me);
10474ae8 356 return -EINVAL;
6aa8b732 357 }
0fe1e009 358 sd = per_cpu(svm_data, me);
6aa8b732 359
0fe1e009 360 if (!sd) {
e6732a5a 361 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 362 me);
10474ae8 363 return -EINVAL;
6aa8b732
AK		 364 }
365
0fe1e009
TH		 366 sd->asid_generation = 1;
367 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
368 sd->next_asid = sd->max_asid + 1;
6aa8b732 369
b792c344 370 kvm_get_gdt(&gdt_descr);
89a27f4d 371 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 372 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 373
9962d032 374 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 375
d0316554 376 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8
AG		 377
378 return 0;
6aa8b732
AK		 379}
380
0da1db75
JR		 381static void svm_cpu_uninit(int cpu)
382{
0fe1e009 383 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 384
0fe1e009 385 if (!sd)
0da1db75
JR		 386 return;
387
388 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 389 __free_page(sd->save_area);
390 kfree(sd);
0da1db75
JR		 391}
392
6aa8b732
AK		 393static int svm_cpu_init(int cpu)
394{
0fe1e009 395 struct svm_cpu_data *sd;
6aa8b732
AK		 396 int r;
397
0fe1e009
TH		 398 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
399 if (!sd)
6aa8b732 400 return -ENOMEM;
0fe1e009
TH		 401 sd->cpu = cpu;
402 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 403 r = -ENOMEM;
0fe1e009 404 if (!sd->save_area)
6aa8b732
AK		 405 goto err_1;
406
0fe1e009 407 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 408
409 return 0;
410
411err_1:
0fe1e009 412 kfree(sd);
6aa8b732
AK		 413 return r;
414
415}
416
bfc733a7
RR		 417static void set_msr_interception(u32 *msrpm, unsigned msr,
418 int read, int write)
6aa8b732
AK		 419{
420 int i;
421
422 for (i = 0; i < NUM_MSR_MAPS; i++) {
423 if (msr >= msrpm_ranges[i] &&
424 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
425 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
426 msrpm_ranges[i]) * 2;
427
428 u32 *base = msrpm + (msr_offset / 32);
429 u32 msr_shift = msr_offset % 32;
430 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
431 *base = (*base & ~(0x3 << msr_shift)) |
432 (mask << msr_shift);
bfc733a7 433 return;
6aa8b732
AK		 434 }
435 }
bfc733a7 436 BUG();
6aa8b732
AK		 437}
438
f65c229c
JR		 439static void svm_vcpu_init_msrpm(u32 *msrpm)
440{
441 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
442
443#ifdef CONFIG_X86_64
444 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
445 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
446 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
447 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
448 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
449 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
450#endif
451 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
452 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
f65c229c
JR		 453}
454
24e09cbf
JR		 455static void svm_enable_lbrv(struct vcpu_svm *svm)
456{
457 u32 *msrpm = svm->msrpm;
458
459 svm->vmcb->control.lbr_ctl = 1;
460 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
461 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
462 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
463 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
464}
465
466static void svm_disable_lbrv(struct vcpu_svm *svm)
467{
468 u32 *msrpm = svm->msrpm;
469
470 svm->vmcb->control.lbr_ctl = 0;
471 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
472 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
473 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
474 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
475}
476
6aa8b732
AK		 477static __init int svm_hardware_setup(void)
478{
479 int cpu;
480 struct page *iopm_pages;
f65c229c 481 void *iopm_va;
6aa8b732
AK		 482 int r;
483
6aa8b732
AK		 484 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
485
486 if (!iopm_pages)
487 return -ENOMEM;
c8681339
AL		 488
489 iopm_va = page_address(iopm_pages);
490 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 491 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
492
50a37eb4
JR		 493 if (boot_cpu_has(X86_FEATURE_NX))
494 kvm_enable_efer_bits(EFER_NX);
495
1b2fd70c
AG		 496 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
497 kvm_enable_efer_bits(EFER_FFXSR);
498
236de055
AG		 499 if (nested) {
500 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
501 kvm_enable_efer_bits(EFER_SVME);
502 }
503
3230bb47 504 for_each_possible_cpu(cpu) {
6aa8b732
AK		 505 r = svm_cpu_init(cpu);
506 if (r)
f65c229c 507 goto err;
6aa8b732 508 }
33bd6a0b
JR		 509
510 svm_features = cpuid_edx(SVM_CPUID_FUNC);
511
e3da3acd
JR		 512 if (!svm_has(SVM_FEATURE_NPT))
513 npt_enabled = false;
514
6c7dac72
JR		 515 if (npt_enabled && !npt) {
516 printk(KERN_INFO "kvm: Nested Paging disabled\n");
517 npt_enabled = false;
518 }
519
18552672 520 if (npt_enabled) {
e3da3acd 521 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 522 kvm_enable_tdp();
5f4cb662
JR		 523 } else
524 kvm_disable_tdp();
e3da3acd 525
6aa8b732
AK		 526 return 0;
527
f65c229c 528err:
6aa8b732
AK		 529 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
530 iopm_base = 0;
531 return r;
532}
533
534static __exit void svm_hardware_unsetup(void)
535{
0da1db75
JR		 536 int cpu;
537
3230bb47 538 for_each_possible_cpu(cpu)
0da1db75
JR		 539 svm_cpu_uninit(cpu);
540
6aa8b732 541 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 542 iopm_base = 0;
6aa8b732
AK		 543}
544
545static void init_seg(struct vmcb_seg *seg)
546{
547 seg->selector = 0;
548 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 549 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 550 seg->limit = 0xffff;
551 seg->base = 0;
552}
553
554static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
555{
556 seg->selector = 0;
557 seg->attrib = SVM_SELECTOR_P_MASK | type;
558 seg->limit = 0xffff;
559 seg->base = 0;
560}
561
e6101a96 562static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 563{
e6101a96
JR		 564 struct vmcb_control_area *control = &svm->vmcb->control;
565 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 566
bff78274
AK		 567 svm->vcpu.fpu_active = 1;
568
e0231715 569 control->intercept_cr_read = INTERCEPT_CR0_MASK |
6aa8b732 570 INTERCEPT_CR3_MASK |
649d6864 571 INTERCEPT_CR4_MASK;
6aa8b732 572
e0231715 573 control->intercept_cr_write = INTERCEPT_CR0_MASK |
6aa8b732 574 INTERCEPT_CR3_MASK |
80a8119c
AK		 575 INTERCEPT_CR4_MASK |
576 INTERCEPT_CR8_MASK;
6aa8b732 577
e0231715 578 control->intercept_dr_read = INTERCEPT_DR0_MASK |
6aa8b732
AK		 579 INTERCEPT_DR1_MASK |
580 INTERCEPT_DR2_MASK |
727f5a23
JK		 581 INTERCEPT_DR3_MASK |
582 INTERCEPT_DR4_MASK |
583 INTERCEPT_DR5_MASK |
584 INTERCEPT_DR6_MASK |
585 INTERCEPT_DR7_MASK;
6aa8b732 586
e0231715 587 control->intercept_dr_write = INTERCEPT_DR0_MASK |
6aa8b732
AK		 588 INTERCEPT_DR1_MASK |
589 INTERCEPT_DR2_MASK |
590 INTERCEPT_DR3_MASK |
727f5a23 591 INTERCEPT_DR4_MASK |
6aa8b732 592 INTERCEPT_DR5_MASK |
727f5a23 593 INTERCEPT_DR6_MASK |
6aa8b732
AK		 594 INTERCEPT_DR7_MASK;
595
7aa81cc0 596 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 597 (1 << UD_VECTOR) |
598 (1 << MC_VECTOR);
6aa8b732
AK		 599
600
e0231715 601 control->intercept = (1ULL << INTERCEPT_INTR) |
6aa8b732 602 (1ULL << INTERCEPT_NMI) |
0152527b 603 (1ULL << INTERCEPT_SMI) |
d225157b 604 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 605 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 606 (1ULL << INTERCEPT_INVD) |
6aa8b732 607 (1ULL << INTERCEPT_HLT) |
a7052897 608 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 609 (1ULL << INTERCEPT_INVLPGA) |
610 (1ULL << INTERCEPT_IOIO_PROT) |
611 (1ULL << INTERCEPT_MSR_PROT) |
612 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 613 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 614 (1ULL << INTERCEPT_VMRUN) |
615 (1ULL << INTERCEPT_VMMCALL) |
616 (1ULL << INTERCEPT_VMLOAD) |
617 (1ULL << INTERCEPT_VMSAVE) |
618 (1ULL << INTERCEPT_STGI) |
619 (1ULL << INTERCEPT_CLGI) |
916ce236 620 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 621 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 622 (1ULL << INTERCEPT_MONITOR) |
623 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 624
625 control->iopm_base_pa = iopm_base;
f65c229c 626 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 627 control->tsc_offset = 0;
6aa8b732
AK		 628 control->int_ctl = V_INTR_MASKING_MASK;
629
630 init_seg(&save->es);
631 init_seg(&save->ss);
632 init_seg(&save->ds);
633 init_seg(&save->fs);
634 init_seg(&save->gs);
635
636 save->cs.selector = 0xf000;
637 /* Executable/Readable Code Segment */
638 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
639 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
640 save->cs.limit = 0xffff;
d92899a0
AK		 641 /*
642 * cs.base should really be 0xffff0000, but vmx can't handle that, so
643 * be consistent with it.
644 *
645 * Replace when we have real mode working for vmx.
646 */
647 save->cs.base = 0xf0000;
6aa8b732
AK		 648
649 save->gdtr.limit = 0xffff;
650 save->idtr.limit = 0xffff;
651
652 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
653 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
654
9962d032 655 save->efer = EFER_SVME;
d77c26fc 656 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 657 save->dr7 = 0x400;
658 save->rflags = 2;
659 save->rip = 0x0000fff0;
5fdbf976 660 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 661
e0231715
JR		 662 /*
663 * This is the guest-visible cr0 value.
18fa000a 664 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 665 */
18fa000a
EH		 666 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
667 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
668
66aee91a 669 save->cr4 = X86_CR4_PAE;
6aa8b732 670 /* rdx = ?? */
709ddebf
JR		 671
672 if (npt_enabled) {
673 /* Setup VMCB for Nested Paging */
674 control->nested_ctl = 1;
a7052897
MT		 675 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
676 (1ULL << INTERCEPT_INVLPG));
709ddebf 677 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 678 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
679 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 680 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 681 save->cr3 = 0;
682 save->cr4 = 0;
683 }
a79d2f18 684 force_new_asid(&svm->vcpu);
1371d904 685
e6aa9abd 686 svm->nested.vmcb = 0;
2af9194d
JR		 687 svm->vcpu.arch.hflags = 0;
688
565d0998
ML		 689 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
690 control->pause_filter_count = 3000;
691 control->intercept |= (1ULL << INTERCEPT_PAUSE);
692 }
693
2af9194d 694 enable_gif(svm);
6aa8b732
AK		 695}
696
e00c8cf2 697static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 698{
699 struct vcpu_svm *svm = to_svm(vcpu);
700
e6101a96 701 init_vmcb(svm);
70433389 702
c5af89b6 703 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 704 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 705 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
706 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 707 }
5fdbf976
MT		 708 vcpu->arch.regs_avail = ~0;
709 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 710
711 return 0;
04d2cc77
AK		 712}
713
fb3f0f51 714static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 715{
a2fa3e9f 716 struct vcpu_svm *svm;
6aa8b732 717 struct page *page;
f65c229c 718 struct page *msrpm_pages;
b286d5d8 719 struct page *hsave_page;
3d6368ef 720 struct page *nested_msrpm_pages;
fb3f0f51 721 int err;
6aa8b732 722
c16f862d 723 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 724 if (!svm) {
725 err = -ENOMEM;
726 goto out;
727 }
728
729 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
730 if (err)
731 goto free_svm;
732
b7af4043 733 err = -ENOMEM;
6aa8b732 734 page = alloc_page(GFP_KERNEL);
b7af4043 735 if (!page)
fb3f0f51 736 goto uninit;
6aa8b732 737
f65c229c
JR		 738 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
739 if (!msrpm_pages)
b7af4043 740 goto free_page1;
3d6368ef
AG		 741
742 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
743 if (!nested_msrpm_pages)
b7af4043 744 goto free_page2;
f65c229c 745
b286d5d8
AG		 746 hsave_page = alloc_page(GFP_KERNEL);
747 if (!hsave_page)
b7af4043
TY		 748 goto free_page3;
749
e6aa9abd 750 svm->nested.hsave = page_address(hsave_page);
b286d5d8 751
b7af4043
TY		 752 svm->msrpm = page_address(msrpm_pages);
753 svm_vcpu_init_msrpm(svm->msrpm);
754
e6aa9abd 755 svm->nested.msrpm = page_address(nested_msrpm_pages);
3d6368ef 756
a2fa3e9f
GH		 757 svm->vmcb = page_address(page);
758 clear_page(svm->vmcb);
759 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
760 svm->asid_generation = 0;
e6101a96 761 init_vmcb(svm);
a2fa3e9f 762
fb3f0f51 763 fx_init(&svm->vcpu);
ad312c7c 764 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 765 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 766 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 767
fb3f0f51 768 return &svm->vcpu;
36241b8c 769
b7af4043
TY		 770free_page3:
771 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
772free_page2:
773 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
774free_page1:
775 __free_page(page);
fb3f0f51
RR		 776uninit:
777 kvm_vcpu_uninit(&svm->vcpu);
778free_svm:
a4770347 779 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 780out:
781 return ERR_PTR(err);
6aa8b732
AK		 782}
783
784static void svm_free_vcpu(struct kvm_vcpu *vcpu)
785{
a2fa3e9f
GH		 786 struct vcpu_svm *svm = to_svm(vcpu);
787
fb3f0f51 788 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 789 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 790 __free_page(virt_to_page(svm->nested.hsave));
791 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 792 kvm_vcpu_uninit(vcpu);
a4770347 793 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 794}
795
15ad7146 796static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 797{
a2fa3e9f 798 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 799 int i;
0cc5064d 800
0cc5064d 801 if (unlikely(cpu != vcpu->cpu)) {
e935d48e 802 u64 delta;
0cc5064d 803
953899b6
JR		 804 if (check_tsc_unstable()) {
805 /*
806 * Make sure that the guest sees a monotonically
807 * increasing TSC.
808 */
809 delta = vcpu->arch.host_tsc - native_read_tsc();
810 svm->vmcb->control.tsc_offset += delta;
811 if (is_nested(svm))
812 svm->nested.hsave->control.tsc_offset += delta;
813 }
0cc5064d 814 vcpu->cpu = cpu;
2f599714 815 kvm_migrate_timers(vcpu);
4b656b12 816 svm->asid_generation = 0;
0cc5064d 817 }
94dfbdb3
AL		 818
819 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 820 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 821}
822
823static void svm_vcpu_put(struct kvm_vcpu *vcpu)
824{
a2fa3e9f 825 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 826 int i;
827
e1beb1d3 828 ++vcpu->stat.host_state_reload;
94dfbdb3 829 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 830 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 831
e935d48e 832 vcpu->arch.host_tsc = native_read_tsc();
6aa8b732
AK		 833}
834
6aa8b732
AK		 835static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
836{
a2fa3e9f 837 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 838}
839
840static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
841{
a2fa3e9f 842 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 843}
844
6de4f3ad
AK		 845static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
846{
847 switch (reg) {
848 case VCPU_EXREG_PDPTR:
849 BUG_ON(!npt_enabled);
850 load_pdptrs(vcpu, vcpu->arch.cr3);
851 break;
852 default:
853 BUG();
854 }
855}
856
f0b85051
AG		 857static void svm_set_vintr(struct vcpu_svm *svm)
858{
859 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
860}
861
862static void svm_clear_vintr(struct vcpu_svm *svm)
863{
864 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
865}
866
6aa8b732
AK		 867static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
868{
a2fa3e9f 869 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 870
871 switch (seg) {
872 case VCPU_SREG_CS: return &save->cs;
873 case VCPU_SREG_DS: return &save->ds;
874 case VCPU_SREG_ES: return &save->es;
875 case VCPU_SREG_FS: return &save->fs;
876 case VCPU_SREG_GS: return &save->gs;
877 case VCPU_SREG_SS: return &save->ss;
878 case VCPU_SREG_TR: return &save->tr;
879 case VCPU_SREG_LDTR: return &save->ldtr;
880 }
881 BUG();
8b6d44c7 882 return NULL;
6aa8b732
AK		 883}
884
885static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
886{
887 struct vmcb_seg *s = svm_seg(vcpu, seg);
888
889 return s->base;
890}
891
892static void svm_get_segment(struct kvm_vcpu *vcpu,
893 struct kvm_segment *var, int seg)
894{
895 struct vmcb_seg *s = svm_seg(vcpu, seg);
896
897 var->base = s->base;
898 var->limit = s->limit;
899 var->selector = s->selector;
900 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
901 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
902 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
903 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
904 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
905 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
906 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
907 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 908
e0231715
JR		 909 /*
910 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 911 * for cross vendor migration purposes by "not present"
912 */
913 var->unusable = !var->present || (var->type == 0);
914
1fbdc7a5
AP		 915 switch (seg) {
916 case VCPU_SREG_CS:
917 /*
918 * SVM always stores 0 for the 'G' bit in the CS selector in
919 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
920 * Intel's VMENTRY has a check on the 'G' bit.
921 */
25022acc 922 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 923 break;
924 case VCPU_SREG_TR:
925 /*
926 * Work around a bug where the busy flag in the tr selector
927 * isn't exposed
928 */
c0d09828 929 var->type |= 0x2;
1fbdc7a5
AP		 930 break;
931 case VCPU_SREG_DS:
932 case VCPU_SREG_ES:
933 case VCPU_SREG_FS:
934 case VCPU_SREG_GS:
935 /*
936 * The accessed bit must always be set in the segment
937 * descriptor cache, although it can be cleared in the
938 * descriptor, the cached bit always remains at 1. Since
939 * Intel has a check on this, set it here to support
940 * cross-vendor migration.
941 */
942 if (!var->unusable)
943 var->type |= 0x1;
944 break;
b586eb02 945 case VCPU_SREG_SS:
e0231715
JR		 946 /*
947 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 948 * descriptor is left as 1, although the whole segment has
949 * been made unusable. Clear it here to pass an Intel VMX
950 * entry check when cross vendor migrating.
951 */
952 if (var->unusable)
953 var->db = 0;
954 break;
1fbdc7a5 955 }
6aa8b732
AK		 956}
957
2e4d2653
IE		 958static int svm_get_cpl(struct kvm_vcpu *vcpu)
959{
960 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
961
962 return save->cpl;
963}
964
89a27f4d 965static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 966{
a2fa3e9f
GH		 967 struct vcpu_svm *svm = to_svm(vcpu);
968
89a27f4d
GN		 969 dt->size = svm->vmcb->save.idtr.limit;
970 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 971}
972
89a27f4d 973static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 974{
a2fa3e9f
GH		 975 struct vcpu_svm *svm = to_svm(vcpu);
976
89a27f4d
GN		 977 svm->vmcb->save.idtr.limit = dt->size;
978 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 979}
980
89a27f4d 981static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 982{
a2fa3e9f
GH		 983 struct vcpu_svm *svm = to_svm(vcpu);
984
89a27f4d
GN		 985 dt->size = svm->vmcb->save.gdtr.limit;
986 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 987}
988
89a27f4d 989static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 990{
a2fa3e9f
GH		 991 struct vcpu_svm *svm = to_svm(vcpu);
992
89a27f4d
GN		 993 svm->vmcb->save.gdtr.limit = dt->size;
994 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 995}
996
e8467fda
AK		 997static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
998{
999}
1000
25c4c276 1001static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1002{
1003}
1004
d225157b
AK		 1005static void update_cr0_intercept(struct vcpu_svm *svm)
1006{
66a562f7 1007 struct vmcb *vmcb = svm->vmcb;
d225157b
AK		 1008 ulong gcr0 = svm->vcpu.arch.cr0;
1009 u64 *hcr0 = &svm->vmcb->save.cr0;
1010
1011 if (!svm->vcpu.fpu_active)
1012 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1013 else
1014 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1015 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1016
1017
1018 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
66a562f7
JR		 1019 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1020 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1021 if (is_nested(svm)) {
1022 struct vmcb *hsave = svm->nested.hsave;
1023
1024 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1025 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1026 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1027 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1028 }
d225157b
AK		 1029 } else {
1030 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1031 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
66a562f7
JR		 1032 if (is_nested(svm)) {
1033 struct vmcb *hsave = svm->nested.hsave;
1034
1035 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1036 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1037 }
d225157b
AK		 1038 }
1039}
1040
6aa8b732
AK		 1041static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1042{
a2fa3e9f
GH		 1043 struct vcpu_svm *svm = to_svm(vcpu);
1044
05b3e0c2 1045#ifdef CONFIG_X86_64
f6801dff 1046 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1047 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1048 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1049 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1050 }
1051
d77c26fc 1052 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1053 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1054 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1055 }
1056 }
1057#endif
ad312c7c 1058 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1059
1060 if (!npt_enabled)
1061 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1062
1063 if (!vcpu->fpu_active)
334df50a 1064 cr0 |= X86_CR0_TS;
709ddebf
JR		 1065 /*
1066 * re-enable caching here because the QEMU bios
1067 * does not do it - this results in some delay at
1068 * reboot
1069 */
1070 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1071 svm->vmcb->save.cr0 = cr0;
d225157b 1072 update_cr0_intercept(svm);
6aa8b732
AK		 1073}
1074
1075static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1076{
6394b649 1077 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1078 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1079
1080 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1081 force_new_asid(vcpu);
6394b649 1082
ec077263
JR		 1083 vcpu->arch.cr4 = cr4;
1084 if (!npt_enabled)
1085 cr4 |= X86_CR4_PAE;
6394b649 1086 cr4 |= host_cr4_mce;
ec077263 1087 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1088}
1089
1090static void svm_set_segment(struct kvm_vcpu *vcpu,
1091 struct kvm_segment *var, int seg)
1092{
a2fa3e9f 1093 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1094 struct vmcb_seg *s = svm_seg(vcpu, seg);
1095
1096 s->base = var->base;
1097 s->limit = var->limit;
1098 s->selector = var->selector;
1099 if (var->unusable)
1100 s->attrib = 0;
1101 else {
1102 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1103 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1104 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1105 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1106 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1107 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1108 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1109 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1110 }
1111 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1112 svm->vmcb->save.cpl
1113 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1114 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1115
1116}
1117
44c11430 1118static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1119{
d0bfb940
JK		 1120 struct vcpu_svm *svm = to_svm(vcpu);
1121
d0bfb940
JK		 1122 svm->vmcb->control.intercept_exceptions &=
1123 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1124
6be7d306 1125 if (svm->nmi_singlestep)
44c11430
GN		 1126 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1127
d0bfb940
JK		 1128 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1129 if (vcpu->guest_debug &
1130 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1131 svm->vmcb->control.intercept_exceptions |=
1132 1 << DB_VECTOR;
1133 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1134 svm->vmcb->control.intercept_exceptions |=
1135 1 << BP_VECTOR;
1136 } else
1137 vcpu->guest_debug = 0;
44c11430
GN		 1138}
1139
355be0b9 1140static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1141{
44c11430
GN		 1142 struct vcpu_svm *svm = to_svm(vcpu);
1143
ae675ef0
JK		 1144 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1145 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1146 else
1147 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1148
355be0b9 1149 update_db_intercept(vcpu);
6aa8b732
AK		 1150}
1151
1152static void load_host_msrs(struct kvm_vcpu *vcpu)
1153{
94dfbdb3 1154#ifdef CONFIG_X86_64
a2fa3e9f 1155 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1156#endif
6aa8b732
AK		 1157}
1158
1159static void save_host_msrs(struct kvm_vcpu *vcpu)
1160{
94dfbdb3 1161#ifdef CONFIG_X86_64
a2fa3e9f 1162 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1163#endif
6aa8b732
AK		 1164}
1165
0fe1e009 1166static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1167{
0fe1e009
TH		 1168 if (sd->next_asid > sd->max_asid) {
1169 ++sd->asid_generation;
1170 sd->next_asid = 1;
a2fa3e9f 1171 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1172 }
1173
0fe1e009
TH		 1174 svm->asid_generation = sd->asid_generation;
1175 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1176}
1177
c76de350 1178static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest)
6aa8b732 1179{
42dbaa5a 1180 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a
JK		 1181
1182 switch (dr) {
1183 case 0 ... 3:
c76de350 1184 *dest = vcpu->arch.db[dr];
42dbaa5a 1185 break;
c76de350
JK		 1186 case 4:
1187 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1188 return EMULATE_FAIL; /* will re-inject UD */
1189 /* fall through */
42dbaa5a
JK		 1190 case 6:
1191 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1192 *dest = vcpu->arch.dr6;
42dbaa5a 1193 else
c76de350 1194 *dest = svm->vmcb->save.dr6;
42dbaa5a 1195 break;
c76de350
JK		 1196 case 5:
1197 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1198 return EMULATE_FAIL; /* will re-inject UD */
1199 /* fall through */
42dbaa5a
JK		 1200 case 7:
1201 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1202 *dest = vcpu->arch.dr7;
42dbaa5a 1203 else
c76de350 1204 *dest = svm->vmcb->save.dr7;
42dbaa5a 1205 break;
42dbaa5a
JK		 1206 }
1207
c76de350 1208 return EMULATE_DONE;
6aa8b732
AK		 1209}
1210
c76de350 1211static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value)
6aa8b732 1212{
a2fa3e9f
GH		 1213 struct vcpu_svm *svm = to_svm(vcpu);
1214
6aa8b732
AK		 1215 switch (dr) {
1216 case 0 ... 3:
42dbaa5a
JK		 1217 vcpu->arch.db[dr] = value;
1218 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1219 vcpu->arch.eff_db[dr] = value;
c76de350
JK		 1220 break;
1221 case 4:
1222 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1223 return EMULATE_FAIL; /* will re-inject UD */
1224 /* fall through */
42dbaa5a 1225 case 6:
42dbaa5a 1226 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
c76de350
JK		 1227 break;
1228 case 5:
1229 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1230 return EMULATE_FAIL; /* will re-inject UD */
1231 /* fall through */
42dbaa5a 1232 case 7:
42dbaa5a
JK		 1233 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1234 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1235 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1236 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1237 }
c76de350 1238 break;
6aa8b732 1239 }
c76de350
JK		 1240
1241 return EMULATE_DONE;
6aa8b732
AK		 1242}
1243
851ba692 1244static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1245{
6aa8b732
AK		 1246 u64 fault_address;
1247 u32 error_code;
6aa8b732 1248
a2fa3e9f
GH		 1249 fault_address = svm->vmcb->control.exit_info_2;
1250 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1251
229456fc 1252 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1253 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1254 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1255 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1256}
1257
851ba692 1258static int db_interception(struct vcpu_svm *svm)
d0bfb940 1259{
851ba692
AK		 1260 struct kvm_run *kvm_run = svm->vcpu.run;
1261
d0bfb940 1262 if (!(svm->vcpu.guest_debug &
44c11430 1263 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1264 !svm->nmi_singlestep) {
d0bfb940
JK		 1265 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1266 return 1;
1267 }
44c11430 1268
6be7d306
JK		 1269 if (svm->nmi_singlestep) {
1270 svm->nmi_singlestep = false;
44c11430
GN		 1271 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1272 svm->vmcb->save.rflags &=
1273 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1274 update_db_intercept(&svm->vcpu);
1275 }
1276
1277 if (svm->vcpu.guest_debug &
e0231715 1278 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1279 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1280 kvm_run->debug.arch.pc =
1281 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1282 kvm_run->debug.arch.exception = DB_VECTOR;
1283 return 0;
1284 }
1285
1286 return 1;
d0bfb940
JK		 1287}
1288
851ba692 1289static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1290{
851ba692
AK		 1291 struct kvm_run *kvm_run = svm->vcpu.run;
1292
d0bfb940
JK		 1293 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1294 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1295 kvm_run->debug.arch.exception = BP_VECTOR;
1296 return 0;
1297}
1298
851ba692 1299static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1300{
1301 int er;
1302
851ba692 1303 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1304 if (er != EMULATE_DONE)
7ee5d940 1305 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1306 return 1;
1307}
1308
6b52d186 1309static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1310{
6b52d186 1311 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7
JR		 1312 u32 excp;
1313
1314 if (is_nested(svm)) {
1315 u32 h_excp, n_excp;
1316
1317 h_excp = svm->nested.hsave->control.intercept_exceptions;
1318 n_excp = svm->nested.intercept_exceptions;
1319 h_excp &= ~(1 << NM_VECTOR);
1320 excp = h_excp | n_excp;
1321 } else {
1322 excp = svm->vmcb->control.intercept_exceptions;
e0231715 1323 excp &= ~(1 << NM_VECTOR);
66a562f7
JR		 1324 }
1325
1326 svm->vmcb->control.intercept_exceptions = excp;
1327
e756fc62 1328 svm->vcpu.fpu_active = 1;
d225157b 1329 update_cr0_intercept(svm);
6b52d186 1330}
a2fa3e9f 1331
6b52d186
AK		 1332static int nm_interception(struct vcpu_svm *svm)
1333{
1334 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1335 return 1;
7807fa6c
AL		 1336}
1337
851ba692 1338static int mc_interception(struct vcpu_svm *svm)
53371b50
JR		 1339{
1340 /*
1341 * On an #MC intercept the MCE handler is not called automatically in
1342 * the host. So do it by hand here.
1343 */
1344 asm volatile (
1345 "int $0x12\n");
1346 /* not sure if we ever come back to this point */
1347
1348 return 1;
1349}
1350
851ba692 1351static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1352{
851ba692
AK		 1353 struct kvm_run *kvm_run = svm->vcpu.run;
1354
46fe4ddd
JR		 1355 /*
1356 * VMCB is undefined after a SHUTDOWN intercept
1357 * so reinitialize it.
1358 */
a2fa3e9f 1359 clear_page(svm->vmcb);
e6101a96 1360 init_vmcb(svm);
46fe4ddd
JR		 1361
1362 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1363 return 0;
1364}
1365
851ba692 1366static int io_interception(struct vcpu_svm *svm)
6aa8b732 1367{
d77c26fc 1368 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1369 int size, in, string;
039576c0 1370 unsigned port;
6aa8b732 1371
e756fc62 1372 ++svm->vcpu.stat.io_exits;
6aa8b732 1373
a2fa3e9f 1374 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1375
e70669ab
LV		 1376 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1377
1378 if (string) {
3427318f 1379 if (emulate_instruction(&svm->vcpu,
851ba692 1380 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1381 return 0;
1382 return 1;
1383 }
1384
039576c0
AK		 1385 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1386 port = io_info >> 16;
1387 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1388
e93f36bc 1389 skip_emulated_instruction(&svm->vcpu);
851ba692 1390 return kvm_emulate_pio(&svm->vcpu, in, size, port);
6aa8b732
AK		 1391}
1392
851ba692 1393static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1394{
1395 return 1;
1396}
1397
851ba692 1398static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1399{
1400 ++svm->vcpu.stat.irq_exits;
1401 return 1;
1402}
1403
851ba692 1404static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1405{
1406 return 1;
1407}
1408
851ba692 1409static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1410{
5fdbf976 1411 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1412 skip_emulated_instruction(&svm->vcpu);
1413 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1414}
1415
851ba692 1416static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1417{
5fdbf976 1418 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1419 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1420 kvm_emulate_hypercall(&svm->vcpu);
1421 return 1;
02e235bc
AK		 1422}
1423
c0725420
AG		 1424static int nested_svm_check_permissions(struct vcpu_svm *svm)
1425{
f6801dff 1426 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1427 || !is_paging(&svm->vcpu)) {
1428 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1429 return 1;
1430 }
1431
1432 if (svm->vmcb->save.cpl) {
1433 kvm_inject_gp(&svm->vcpu, 0);
1434 return 1;
1435 }
1436
1437 return 0;
1438}
1439
cf74a78b
AG		 1440static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1441 bool has_error_code, u32 error_code)
1442{
b8e88bc8
JR		 1443 int vmexit;
1444
0295ad7d
JR		 1445 if (!is_nested(svm))
1446 return 0;
cf74a78b 1447
0295ad7d
JR		 1448 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1449 svm->vmcb->control.exit_code_hi = 0;
1450 svm->vmcb->control.exit_info_1 = error_code;
1451 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1452
b8e88bc8
JR		 1453 vmexit = nested_svm_intercept(svm);
1454 if (vmexit == NESTED_EXIT_DONE)
1455 svm->nested.exit_required = true;
1456
1457 return vmexit;
cf74a78b
AG		 1458}
1459
8fe54654
JR		 1460/* This function returns true if it is save to enable the irq window */
1461static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1462{
26666957 1463 if (!is_nested(svm))
8fe54654 1464 return true;
cf74a78b 1465
26666957 1466 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1467 return true;
cf74a78b 1468
26666957 1469 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1470 return false;
cf74a78b 1471
26666957
JR		 1472 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1473
cd3ff653
JR		 1474 if (svm->nested.intercept & 1ULL) {
1475 /*
1476 * The #vmexit can't be emulated here directly because this
1477 * code path runs with irqs and preemtion disabled. A
1478 * #vmexit emulation might sleep. Only signal request for
1479 * the #vmexit here.
1480 */
1481 svm->nested.exit_required = true;
236649de 1482 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1483 return false;
cf74a78b
AG		 1484 }
1485
8fe54654 1486 return true;
cf74a78b
AG		 1487}
1488
7597f129 1489static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1490{
1491 struct page *page;
1492
6c3bd3d7
JR		 1493 might_sleep();
1494
34f80cfa 1495 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1496 if (is_error_page(page))
1497 goto error;
1498
7597f129
JR		 1499 *_page = page;
1500
1501 return kmap(page);
34f80cfa
JR		 1502
1503error:
1504 kvm_release_page_clean(page);
1505 kvm_inject_gp(&svm->vcpu, 0);
1506
1507 return NULL;
1508}
1509
7597f129 1510static void nested_svm_unmap(struct page *page)
34f80cfa 1511{
7597f129 1512 kunmap(page);
34f80cfa
JR		 1513 kvm_release_page_dirty(page);
1514}
1515
3d62d9aa 1516static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1517{
4c2161ae 1518 u32 param = svm->vmcb->control.exit_info_1 & 1;
3d62d9aa
JR		 1519 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1520 bool ret = false;
1521 u32 t0, t1;
4c7da8cb 1522 u8 val;
4c2161ae 1523
3d62d9aa
JR		 1524 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1525 return false;
1526
4c2161ae
JR		 1527 switch (msr) {
1528 case 0 ... 0x1fff:
1529 t0 = (msr * 2) % 8;
1530 t1 = msr / 8;
1531 break;
1532 case 0xc0000000 ... 0xc0001fff:
1533 t0 = (8192 + msr - 0xc0000000) * 2;
1534 t1 = (t0 / 8);
1535 t0 %= 8;
1536 break;
1537 case 0xc0010000 ... 0xc0011fff:
1538 t0 = (16384 + msr - 0xc0010000) * 2;
1539 t1 = (t0 / 8);
1540 t0 %= 8;
1541 break;
1542 default:
3d62d9aa
JR		 1543 ret = true;
1544 goto out;
4c2161ae 1545 }
4c2161ae 1546
4c7da8cb
JR		 1547 if (!kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + t1, &val, 1))
1548 ret = val & ((1 << param) << t0);
3d62d9aa
JR		 1549
1550out:
3d62d9aa 1551 return ret;
4c2161ae
JR		 1552}
1553
410e4d57 1554static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1555{
cf74a78b 1556 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1557
410e4d57
JR		 1558 switch (exit_code) {
1559 case SVM_EXIT_INTR:
1560 case SVM_EXIT_NMI:
1561 return NESTED_EXIT_HOST;
410e4d57 1562 case SVM_EXIT_NPF:
e0231715 1563 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1564 if (npt_enabled)
1565 return NESTED_EXIT_HOST;
1566 break;
410e4d57 1567 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
e0231715 1568 /* When we're shadowing, trap PFs */
410e4d57
JR		 1569 if (!npt_enabled)
1570 return NESTED_EXIT_HOST;
1571 break;
66a562f7
JR		 1572 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1573 nm_interception(svm);
1574 break;
410e4d57
JR		 1575 default:
1576 break;
cf74a78b
AG		 1577 }
1578
410e4d57
JR		 1579 return NESTED_EXIT_CONTINUE;
1580}
1581
1582/*
1583 * If this function returns true, this #vmexit was already handled
1584 */
b8e88bc8 1585static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1586{
1587 u32 exit_code = svm->vmcb->control.exit_code;
1588 int vmexit = NESTED_EXIT_HOST;
1589
cf74a78b 1590 switch (exit_code) {
9c4e40b9 1591 case SVM_EXIT_MSR:
3d62d9aa 1592 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1593 break;
cf74a78b
AG		 1594 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1595 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1596 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1597 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1598 break;
1599 }
1600 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1601 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1602 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1603 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1604 break;
1605 }
1606 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1607 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1608 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1609 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1610 break;
1611 }
1612 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1613 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1614 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1615 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1616 break;
1617 }
1618 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1619 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1620 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1621 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1622 break;
1623 }
1624 default: {
1625 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1626 if (svm->nested.intercept & exit_bits)
410e4d57 1627 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1628 }
1629 }
1630
b8e88bc8
JR		 1631 return vmexit;
1632}
1633
1634static int nested_svm_exit_handled(struct vcpu_svm *svm)
1635{
1636 int vmexit;
1637
1638 vmexit = nested_svm_intercept(svm);
1639
1640 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1641 nested_svm_vmexit(svm);
9c4e40b9
JR		 1642
1643 return vmexit;
cf74a78b
AG		 1644}
1645
0460a979
JR		 1646static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1647{
1648 struct vmcb_control_area *dst = &dst_vmcb->control;
1649 struct vmcb_control_area *from = &from_vmcb->control;
1650
1651 dst->intercept_cr_read = from->intercept_cr_read;
1652 dst->intercept_cr_write = from->intercept_cr_write;
1653 dst->intercept_dr_read = from->intercept_dr_read;
1654 dst->intercept_dr_write = from->intercept_dr_write;
1655 dst->intercept_exceptions = from->intercept_exceptions;
1656 dst->intercept = from->intercept;
1657 dst->iopm_base_pa = from->iopm_base_pa;
1658 dst->msrpm_base_pa = from->msrpm_base_pa;
1659 dst->tsc_offset = from->tsc_offset;
1660 dst->asid = from->asid;
1661 dst->tlb_ctl = from->tlb_ctl;
1662 dst->int_ctl = from->int_ctl;
1663 dst->int_vector = from->int_vector;
1664 dst->int_state = from->int_state;
1665 dst->exit_code = from->exit_code;
1666 dst->exit_code_hi = from->exit_code_hi;
1667 dst->exit_info_1 = from->exit_info_1;
1668 dst->exit_info_2 = from->exit_info_2;
1669 dst->exit_int_info = from->exit_int_info;
1670 dst->exit_int_info_err = from->exit_int_info_err;
1671 dst->nested_ctl = from->nested_ctl;
1672 dst->event_inj = from->event_inj;
1673 dst->event_inj_err = from->event_inj_err;
1674 dst->nested_cr3 = from->nested_cr3;
1675 dst->lbr_ctl = from->lbr_ctl;
1676}
1677
34f80cfa 1678static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1679{
34f80cfa 1680 struct vmcb *nested_vmcb;
e6aa9abd 1681 struct vmcb *hsave = svm->nested.hsave;
33740e40 1682 struct vmcb *vmcb = svm->vmcb;
7597f129 1683 struct page *page;
cf74a78b 1684
17897f36
JR		 1685 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1686 vmcb->control.exit_info_1,
1687 vmcb->control.exit_info_2,
1688 vmcb->control.exit_int_info,
1689 vmcb->control.exit_int_info_err);
1690
7597f129 1691 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 1692 if (!nested_vmcb)
1693 return 1;
1694
06fc7772
JR		 1695 /* Exit nested SVM mode */
1696 svm->nested.vmcb = 0;
1697
cf74a78b 1698 /* Give the current vmcb to the guest */
33740e40
JR		 1699 disable_gif(svm);
1700
1701 nested_vmcb->save.es = vmcb->save.es;
1702 nested_vmcb->save.cs = vmcb->save.cs;
1703 nested_vmcb->save.ss = vmcb->save.ss;
1704 nested_vmcb->save.ds = vmcb->save.ds;
1705 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1706 nested_vmcb->save.idtr = vmcb->save.idtr;
cdbbdc12 1707 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
33740e40
JR		 1708 if (npt_enabled)
1709 nested_vmcb->save.cr3 = vmcb->save.cr3;
cdbbdc12
JR		 1710 else
1711 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 1712 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 1713 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 1714 nested_vmcb->save.rflags = vmcb->save.rflags;
1715 nested_vmcb->save.rip = vmcb->save.rip;
1716 nested_vmcb->save.rsp = vmcb->save.rsp;
1717 nested_vmcb->save.rax = vmcb->save.rax;
1718 nested_vmcb->save.dr7 = vmcb->save.dr7;
1719 nested_vmcb->save.dr6 = vmcb->save.dr6;
1720 nested_vmcb->save.cpl = vmcb->save.cpl;
1721
1722 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1723 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1724 nested_vmcb->control.int_state = vmcb->control.int_state;
1725 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1726 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1727 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1728 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1729 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1730 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
8d23c466
AG		 1731
1732 /*
1733 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1734 * to make sure that we do not lose injected events. So check event_inj
1735 * here and copy it to exit_int_info if it is valid.
1736 * Exit_int_info and event_inj can't be both valid because the case
1737 * below only happens on a VMRUN instruction intercept which has
1738 * no valid exit_int_info set.
1739 */
1740 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1741 struct vmcb_control_area *nc = &nested_vmcb->control;
1742
1743 nc->exit_int_info = vmcb->control.event_inj;
1744 nc->exit_int_info_err = vmcb->control.event_inj_err;
1745 }
1746
33740e40
JR		 1747 nested_vmcb->control.tlb_ctl = 0;
1748 nested_vmcb->control.event_inj = 0;
1749 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1750
1751 /* We always set V_INTR_MASKING and remember the old value in hflags */
1752 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1753 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1754
cf74a78b 1755 /* Restore the original control entries */
0460a979 1756 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1757
219b65dc
AG		 1758 kvm_clear_exception_queue(&svm->vcpu);
1759 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1760
1761 /* Restore selected save entries */
1762 svm->vmcb->save.es = hsave->save.es;
1763 svm->vmcb->save.cs = hsave->save.cs;
1764 svm->vmcb->save.ss = hsave->save.ss;
1765 svm->vmcb->save.ds = hsave->save.ds;
1766 svm->vmcb->save.gdtr = hsave->save.gdtr;
1767 svm->vmcb->save.idtr = hsave->save.idtr;
1768 svm->vmcb->save.rflags = hsave->save.rflags;
1769 svm_set_efer(&svm->vcpu, hsave->save.efer);
1770 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1771 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1772 if (npt_enabled) {
1773 svm->vmcb->save.cr3 = hsave->save.cr3;
1774 svm->vcpu.arch.cr3 = hsave->save.cr3;
1775 } else {
1776 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1777 }
1778 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1779 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1780 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1781 svm->vmcb->save.dr7 = 0;
1782 svm->vmcb->save.cpl = 0;
1783 svm->vmcb->control.exit_int_info = 0;
1784
7597f129 1785 nested_svm_unmap(page);
cf74a78b
AG		 1786
1787 kvm_mmu_reset_context(&svm->vcpu);
1788 kvm_mmu_load(&svm->vcpu);
1789
1790 return 0;
1791}
3d6368ef 1792
9738b2c9 1793static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1794{
9738b2c9 1795 u32 *nested_msrpm;
7597f129 1796 struct page *page;
3d6368ef 1797 int i;
9738b2c9 1798
7597f129 1799 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, &page);
9738b2c9
JR		 1800 if (!nested_msrpm)
1801 return false;
1802
e0231715 1803 for (i = 0; i < PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
e6aa9abd 1804 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
9738b2c9 1805
e6aa9abd 1806 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
3d6368ef 1807
7597f129 1808 nested_svm_unmap(page);
9738b2c9
JR		 1809
1810 return true;
3d6368ef
AG		 1811}
1812
9738b2c9 1813static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 1814{
9738b2c9 1815 struct vmcb *nested_vmcb;
e6aa9abd 1816 struct vmcb *hsave = svm->nested.hsave;
defbba56 1817 struct vmcb *vmcb = svm->vmcb;
7597f129 1818 struct page *page;
06fc7772
JR		 1819 u64 vmcb_gpa;
1820
1821 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 1822
7597f129 1823 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 1824 if (!nested_vmcb)
1825 return false;
1826
0ac406de
JR		 1827 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1828 nested_vmcb->save.rip,
1829 nested_vmcb->control.int_ctl,
1830 nested_vmcb->control.event_inj,
1831 nested_vmcb->control.nested_ctl);
1832
3d6368ef 1833 /* Clear internal status */
219b65dc
AG		 1834 kvm_clear_exception_queue(&svm->vcpu);
1835 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 1836
e0231715
JR		 1837 /*
1838 * Save the old vmcb, so we don't need to pick what we save, but can
1839 * restore everything when a VMEXIT occurs
1840 */
defbba56
JR		 1841 hsave->save.es = vmcb->save.es;
1842 hsave->save.cs = vmcb->save.cs;
1843 hsave->save.ss = vmcb->save.ss;
1844 hsave->save.ds = vmcb->save.ds;
1845 hsave->save.gdtr = vmcb->save.gdtr;
1846 hsave->save.idtr = vmcb->save.idtr;
f6801dff 1847 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 1848 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 1849 hsave->save.cr4 = svm->vcpu.arch.cr4;
1850 hsave->save.rflags = vmcb->save.rflags;
1851 hsave->save.rip = svm->next_rip;
1852 hsave->save.rsp = vmcb->save.rsp;
1853 hsave->save.rax = vmcb->save.rax;
1854 if (npt_enabled)
1855 hsave->save.cr3 = vmcb->save.cr3;
1856 else
1857 hsave->save.cr3 = svm->vcpu.arch.cr3;
1858
0460a979 1859 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 1860
1861 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1862 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1863 else
1864 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1865
1866 /* Load the nested guest state */
1867 svm->vmcb->save.es = nested_vmcb->save.es;
1868 svm->vmcb->save.cs = nested_vmcb->save.cs;
1869 svm->vmcb->save.ss = nested_vmcb->save.ss;
1870 svm->vmcb->save.ds = nested_vmcb->save.ds;
1871 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1872 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1873 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1874 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1875 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1876 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1877 if (npt_enabled) {
1878 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1879 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 1880 } else
3d6368ef 1881 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 1882
1883 /* Guest paging mode is active - reset mmu */
1884 kvm_mmu_reset_context(&svm->vcpu);
1885
defbba56 1886 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 1887 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1888 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1889 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 1890
3d6368ef
AG		 1891 /* In case we don't even reach vcpu_run, the fields are not updated */
1892 svm->vmcb->save.rax = nested_vmcb->save.rax;
1893 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1894 svm->vmcb->save.rip = nested_vmcb->save.rip;
1895 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1896 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1897 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1898
e6aa9abd 1899 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
3d6368ef 1900
aad42c64
JR		 1901 /* cache intercepts */
1902 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1903 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1904 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1905 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1906 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1907 svm->nested.intercept = nested_vmcb->control.intercept;
1908
3d6368ef 1909 force_new_asid(&svm->vcpu);
3d6368ef 1910 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 1911 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1912 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1913 else
1914 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1915
88ab24ad
JR		 1916 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
1917 /* We only want the cr8 intercept bits of the guest */
1918 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
1919 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1920 }
1921
e0231715
JR		 1922 /*
1923 * We don't want a nested guest to be more powerful than the guest, so
1924 * all intercepts are ORed
1925 */
88ab24ad
JR		 1926 svm->vmcb->control.intercept_cr_read |=
1927 nested_vmcb->control.intercept_cr_read;
1928 svm->vmcb->control.intercept_cr_write |=
1929 nested_vmcb->control.intercept_cr_write;
1930 svm->vmcb->control.intercept_dr_read |=
1931 nested_vmcb->control.intercept_dr_read;
1932 svm->vmcb->control.intercept_dr_write |=
1933 nested_vmcb->control.intercept_dr_write;
1934 svm->vmcb->control.intercept_exceptions |=
1935 nested_vmcb->control.intercept_exceptions;
1936
1937 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1938
1939 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 1940 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1941 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1942 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 1943 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1944 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1945
7597f129 1946 nested_svm_unmap(page);
9738b2c9 1947
06fc7772
JR		 1948 /* nested_vmcb is our indicator if nested SVM is activated */
1949 svm->nested.vmcb = vmcb_gpa;
1950
2af9194d 1951 enable_gif(svm);
3d6368ef 1952
9738b2c9 1953 return true;
3d6368ef
AG		 1954}
1955
9966bf68 1956static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 1957{
1958 to_vmcb->save.fs = from_vmcb->save.fs;
1959 to_vmcb->save.gs = from_vmcb->save.gs;
1960 to_vmcb->save.tr = from_vmcb->save.tr;
1961 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1962 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1963 to_vmcb->save.star = from_vmcb->save.star;
1964 to_vmcb->save.lstar = from_vmcb->save.lstar;
1965 to_vmcb->save.cstar = from_vmcb->save.cstar;
1966 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1967 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1968 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1969 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 1970}
1971
851ba692 1972static int vmload_interception(struct vcpu_svm *svm)
5542675b 1973{
9966bf68 1974 struct vmcb *nested_vmcb;
7597f129 1975 struct page *page;
9966bf68 1976
5542675b
AG		 1977 if (nested_svm_check_permissions(svm))
1978 return 1;
1979
1980 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1981 skip_emulated_instruction(&svm->vcpu);
1982
7597f129 1983 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 1984 if (!nested_vmcb)
1985 return 1;
1986
1987 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 1988 nested_svm_unmap(page);
5542675b
AG		 1989
1990 return 1;
1991}
1992
851ba692 1993static int vmsave_interception(struct vcpu_svm *svm)
5542675b 1994{
9966bf68 1995 struct vmcb *nested_vmcb;
7597f129 1996 struct page *page;
9966bf68 1997
5542675b
AG		 1998 if (nested_svm_check_permissions(svm))
1999 return 1;
2000
2001 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2002 skip_emulated_instruction(&svm->vcpu);
2003
7597f129 2004 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2005 if (!nested_vmcb)
2006 return 1;
2007
2008 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2009 nested_svm_unmap(page);
5542675b
AG		 2010
2011 return 1;
2012}
2013
851ba692 2014static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2015{
3d6368ef
AG		 2016 if (nested_svm_check_permissions(svm))
2017 return 1;
2018
2019 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2020 skip_emulated_instruction(&svm->vcpu);
2021
9738b2c9 2022 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2023 return 1;
2024
9738b2c9 2025 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2026 goto failed;
2027
2028 return 1;
2029
2030failed:
2031
2032 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2033 svm->vmcb->control.exit_code_hi = 0;
2034 svm->vmcb->control.exit_info_1 = 0;
2035 svm->vmcb->control.exit_info_2 = 0;
2036
2037 nested_svm_vmexit(svm);
3d6368ef
AG		 2038
2039 return 1;
2040}
2041
851ba692 2042static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2043{
2044 if (nested_svm_check_permissions(svm))
2045 return 1;
2046
2047 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2048 skip_emulated_instruction(&svm->vcpu);
2049
2af9194d 2050 enable_gif(svm);
1371d904
AG		 2051
2052 return 1;
2053}
2054
851ba692 2055static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2056{
2057 if (nested_svm_check_permissions(svm))
2058 return 1;
2059
2060 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2061 skip_emulated_instruction(&svm->vcpu);
2062
2af9194d 2063 disable_gif(svm);
1371d904
AG		 2064
2065 /* After a CLGI no interrupts should come */
2066 svm_clear_vintr(svm);
2067 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2068
2069 return 1;
2070}
2071
851ba692 2072static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2073{
2074 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2075
ec1ff790
JR		 2076 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2077 vcpu->arch.regs[VCPU_REGS_RAX]);
2078
ff092385
AG		 2079 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2080 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2081
2082 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2083 skip_emulated_instruction(&svm->vcpu);
2084 return 1;
2085}
2086
532a46b9
JR		 2087static int skinit_interception(struct vcpu_svm *svm)
2088{
2089 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2090
2091 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2092 return 1;
2093}
2094
851ba692 2095static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2096{
7ee5d940 2097 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2098 return 1;
2099}
2100
851ba692 2101static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2102{
37817f29 2103 u16 tss_selector;
64a7ec06
GN		 2104 int reason;
2105 int int_type = svm->vmcb->control.exit_int_info &
2106 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2107 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2108 uint32_t type =
2109 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2110 uint32_t idt_v =
2111 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 2112
2113 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2114
37817f29
IE		 2115 if (svm->vmcb->control.exit_info_2 &
2116 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2117 reason = TASK_SWITCH_IRET;
2118 else if (svm->vmcb->control.exit_info_2 &
2119 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2120 reason = TASK_SWITCH_JMP;
fe8e7f83 2121 else if (idt_v)
64a7ec06
GN		 2122 reason = TASK_SWITCH_GATE;
2123 else
2124 reason = TASK_SWITCH_CALL;
2125
fe8e7f83
GN		 2126 if (reason == TASK_SWITCH_GATE) {
2127 switch (type) {
2128 case SVM_EXITINTINFO_TYPE_NMI:
2129 svm->vcpu.arch.nmi_injected = false;
2130 break;
2131 case SVM_EXITINTINFO_TYPE_EXEPT:
2132 kvm_clear_exception_queue(&svm->vcpu);
2133 break;
2134 case SVM_EXITINTINFO_TYPE_INTR:
2135 kvm_clear_interrupt_queue(&svm->vcpu);
2136 break;
2137 default:
2138 break;
2139 }
2140 }
64a7ec06 2141
8317c298
GN		 2142 if (reason != TASK_SWITCH_GATE ||
2143 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2144 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2145 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2146 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2147
2148 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2149}
2150
851ba692 2151static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2152{
5fdbf976 2153 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2154 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2155 return 1;
6aa8b732
AK		 2156}
2157
851ba692 2158static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2159{
2160 ++svm->vcpu.stat.nmi_window_exits;
2161 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2162 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2163 return 1;
2164}
2165
851ba692 2166static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2167{
851ba692 2168 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
a7052897
MT		 2169 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2170 return 1;
2171}
2172
851ba692 2173static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2174{
851ba692 2175 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
b8688d51 2176 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2177 return 1;
2178}
2179
851ba692 2180static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2181{
851ba692
AK		 2182 struct kvm_run *kvm_run = svm->vcpu.run;
2183
0a5fff19
GN		 2184 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2185 /* instruction emulation calls kvm_set_cr8() */
851ba692 2186 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2187 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2188 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2189 return 1;
95ba8273 2190 }
0a5fff19
GN		 2191 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2192 return 1;
1d075434
JR		 2193 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2194 return 0;
2195}
2196
6aa8b732
AK		 2197static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2198{
a2fa3e9f
GH		 2199 struct vcpu_svm *svm = to_svm(vcpu);
2200
6aa8b732 2201 switch (ecx) {
af24a4e4 2202 case MSR_IA32_TSC: {
20824f30 2203 u64 tsc_offset;
6aa8b732 2204
20824f30
JR		 2205 if (is_nested(svm))
2206 tsc_offset = svm->nested.hsave->control.tsc_offset;
2207 else
2208 tsc_offset = svm->vmcb->control.tsc_offset;
2209
2210 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2211 break;
2212 }
0e859cac 2213 case MSR_K6_STAR:
a2fa3e9f 2214 *data = svm->vmcb->save.star;
6aa8b732 2215 break;
0e859cac 2216#ifdef CONFIG_X86_64
6aa8b732 2217 case MSR_LSTAR:
a2fa3e9f 2218 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2219 break;
2220 case MSR_CSTAR:
a2fa3e9f 2221 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2222 break;
2223 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2224 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2225 break;
2226 case MSR_SYSCALL_MASK:
a2fa3e9f 2227 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2228 break;
2229#endif
2230 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2231 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2232 break;
2233 case MSR_IA32_SYSENTER_EIP:
017cb99e 2234 *data = svm->sysenter_eip;
6aa8b732
AK		 2235 break;
2236 case MSR_IA32_SYSENTER_ESP:
017cb99e 2237 *data = svm->sysenter_esp;
6aa8b732 2238 break;
e0231715
JR		 2239 /*
2240 * Nobody will change the following 5 values in the VMCB so we can
2241 * safely return them on rdmsr. They will always be 0 until LBRV is
2242 * implemented.
2243 */
a2938c80
JR		 2244 case MSR_IA32_DEBUGCTLMSR:
2245 *data = svm->vmcb->save.dbgctl;
2246 break;
2247 case MSR_IA32_LASTBRANCHFROMIP:
2248 *data = svm->vmcb->save.br_from;
2249 break;
2250 case MSR_IA32_LASTBRANCHTOIP:
2251 *data = svm->vmcb->save.br_to;
2252 break;
2253 case MSR_IA32_LASTINTFROMIP:
2254 *data = svm->vmcb->save.last_excp_from;
2255 break;
2256 case MSR_IA32_LASTINTTOIP:
2257 *data = svm->vmcb->save.last_excp_to;
2258 break;
b286d5d8 2259 case MSR_VM_HSAVE_PA:
e6aa9abd 2260 *data = svm->nested.hsave_msr;
b286d5d8 2261 break;
eb6f302e
JR		 2262 case MSR_VM_CR:
2263 *data = 0;
2264 break;
c8a73f18
AG		 2265 case MSR_IA32_UCODE_REV:
2266 *data = 0x01000065;
2267 break;
6aa8b732 2268 default:
3bab1f5d 2269 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2270 }
2271 return 0;
2272}
2273
851ba692 2274static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2275{
ad312c7c 2276 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2277 u64 data;
2278
59200273
AK		 2279 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2280 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2281 kvm_inject_gp(&svm->vcpu, 0);
59200273 2282 } else {
229456fc 2283 trace_kvm_msr_read(ecx, data);
af9ca2d7 2284
5fdbf976 2285 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2286 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2287 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2288 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2289 }
2290 return 1;
2291}
2292
2293static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2294{
a2fa3e9f
GH		 2295 struct vcpu_svm *svm = to_svm(vcpu);
2296
6aa8b732 2297 switch (ecx) {
af24a4e4 2298 case MSR_IA32_TSC: {
20824f30
JR		 2299 u64 tsc_offset = data - native_read_tsc();
2300 u64 g_tsc_offset = 0;
2301
2302 if (is_nested(svm)) {
2303 g_tsc_offset = svm->vmcb->control.tsc_offset -
2304 svm->nested.hsave->control.tsc_offset;
2305 svm->nested.hsave->control.tsc_offset = tsc_offset;
2306 }
2307
2308 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
6aa8b732 2309
6aa8b732
AK		 2310 break;
2311 }
0e859cac 2312 case MSR_K6_STAR:
a2fa3e9f 2313 svm->vmcb->save.star = data;
6aa8b732 2314 break;
49b14f24 2315#ifdef CONFIG_X86_64
6aa8b732 2316 case MSR_LSTAR:
a2fa3e9f 2317 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2318 break;
2319 case MSR_CSTAR:
a2fa3e9f 2320 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2321 break;
2322 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2323 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2324 break;
2325 case MSR_SYSCALL_MASK:
a2fa3e9f 2326 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2327 break;
2328#endif
2329 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2330 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2331 break;
2332 case MSR_IA32_SYSENTER_EIP:
017cb99e 2333 svm->sysenter_eip = data;
a2fa3e9f 2334 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2335 break;
2336 case MSR_IA32_SYSENTER_ESP:
017cb99e 2337 svm->sysenter_esp = data;
a2fa3e9f 2338 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2339 break;
a2938c80 2340 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2341 if (!svm_has(SVM_FEATURE_LBRV)) {
2342 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2343 __func__, data);
24e09cbf
JR		 2344 break;
2345 }
2346 if (data & DEBUGCTL_RESERVED_BITS)
2347 return 1;
2348
2349 svm->vmcb->save.dbgctl = data;
2350 if (data & (1ULL<<0))
2351 svm_enable_lbrv(svm);
2352 else
2353 svm_disable_lbrv(svm);
a2938c80 2354 break;
b286d5d8 2355 case MSR_VM_HSAVE_PA:
e6aa9abd 2356 svm->nested.hsave_msr = data;
62b9abaa 2357 break;
3c5d0a44
AG		 2358 case MSR_VM_CR:
2359 case MSR_VM_IGNNE:
3c5d0a44
AG		 2360 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2361 break;
6aa8b732 2362 default:
3bab1f5d 2363 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2364 }
2365 return 0;
2366}
2367
851ba692 2368static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2369{
ad312c7c 2370 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2371 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2372 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2373
af9ca2d7 2374
5fdbf976 2375 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2376 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2377 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2378 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2379 } else {
2380 trace_kvm_msr_write(ecx, data);
e756fc62 2381 skip_emulated_instruction(&svm->vcpu);
59200273 2382 }
6aa8b732
AK		 2383 return 1;
2384}
2385
851ba692 2386static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2387{
e756fc62 2388 if (svm->vmcb->control.exit_info_1)
851ba692 2389 return wrmsr_interception(svm);
6aa8b732 2390 else
851ba692 2391 return rdmsr_interception(svm);
6aa8b732
AK		 2392}
2393
851ba692 2394static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2395{
851ba692
AK		 2396 struct kvm_run *kvm_run = svm->vcpu.run;
2397
f0b85051 2398 svm_clear_vintr(svm);
85f455f7 2399 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2400 /*
2401 * If the user space waits to inject interrupts, exit as soon as
2402 * possible
2403 */
8061823a
GN		 2404 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2405 kvm_run->request_interrupt_window &&
2406 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2407 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2408 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2409 return 0;
2410 }
2411
2412 return 1;
2413}
2414
565d0998
ML		 2415static int pause_interception(struct vcpu_svm *svm)
2416{
2417 kvm_vcpu_on_spin(&(svm->vcpu));
2418 return 1;
2419}
2420
851ba692 2421static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2422 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2423 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2424 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2425 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2426 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
e0231715
JR		 2427 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2428 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2429 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2430 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2431 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2432 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2433 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2434 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2435 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2436 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2437 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2438 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2439 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2440 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2441 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2442 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2443 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2444 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2445 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2446 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2447 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2448 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2449 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2450 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2451 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2452 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2453 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2454 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2455 [SVM_EXIT_SMI] = nop_on_interception,
2456 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2457 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2458 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2459 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2460 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2461 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2462 [SVM_EXIT_HLT] = halt_interception,
a7052897 2463 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2464 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2465 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2466 [SVM_EXIT_MSR] = msr_interception,
2467 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2468 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2469 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2470 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2471 [SVM_EXIT_VMLOAD] = vmload_interception,
2472 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2473 [SVM_EXIT_STGI] = stgi_interception,
2474 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2475 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2476 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2477 [SVM_EXIT_MONITOR] = invalid_op_interception,
2478 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2479 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2480};
2481
851ba692 2482static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2483{
04d2cc77 2484 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2485 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2486 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2487
229456fc 2488 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
af9ca2d7 2489
cd3ff653
JR		 2490 if (unlikely(svm->nested.exit_required)) {
2491 nested_svm_vmexit(svm);
2492 svm->nested.exit_required = false;
2493
2494 return 1;
2495 }
2496
cf74a78b 2497 if (is_nested(svm)) {
410e4d57
JR		 2498 int vmexit;
2499
d8cabddf
JR		 2500 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2501 svm->vmcb->control.exit_info_1,
2502 svm->vmcb->control.exit_info_2,
2503 svm->vmcb->control.exit_int_info,
2504 svm->vmcb->control.exit_int_info_err);
2505
410e4d57
JR		 2506 vmexit = nested_svm_exit_special(svm);
2507
2508 if (vmexit == NESTED_EXIT_CONTINUE)
2509 vmexit = nested_svm_exit_handled(svm);
2510
2511 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2512 return 1;
cf74a78b
AG		 2513 }
2514
a5c3832d
JR		 2515 svm_complete_interrupts(svm);
2516
888f9f3e 2517 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
709ddebf 2518 vcpu->arch.cr0 = svm->vmcb->save.cr0;
888f9f3e 2519 if (npt_enabled)
709ddebf 2520 vcpu->arch.cr3 = svm->vmcb->save.cr3;
04d2cc77
AK		 2521
2522 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2523 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2524 kvm_run->fail_entry.hardware_entry_failure_reason
2525 = svm->vmcb->control.exit_code;
2526 return 0;
2527 }
2528
a2fa3e9f 2529 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2530 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2531 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2532 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2533 "exit_code 0x%x\n",
b8688d51 2534 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2535 exit_code);
2536
9d8f549d 2537 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2538 || !svm_exit_handlers[exit_code]) {
6aa8b732 2539 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2540 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2541 return 0;
2542 }
2543
851ba692 2544 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2545}
2546
2547static void reload_tss(struct kvm_vcpu *vcpu)
2548{
2549 int cpu = raw_smp_processor_id();
2550
0fe1e009
TH		 2551 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2552 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2553 load_TR_desc();
2554}
2555
e756fc62 2556static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2557{
2558 int cpu = raw_smp_processor_id();
2559
0fe1e009 2560 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2561
a2fa3e9f 2562 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2563 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2564 if (svm->asid_generation != sd->asid_generation)
2565 new_asid(svm, sd);
6aa8b732
AK		 2566}
2567
95ba8273
GN		 2568static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2569{
2570 struct vcpu_svm *svm = to_svm(vcpu);
2571
2572 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2573 vcpu->arch.hflags |= HF_NMI_MASK;
2574 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2575 ++vcpu->stat.nmi_injections;
2576}
6aa8b732 2577
85f455f7 2578static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2579{
2580 struct vmcb_control_area *control;
2581
229456fc 2582 trace_kvm_inj_virq(irq);
af9ca2d7 2583
fa89a817 2584 ++svm->vcpu.stat.irq_injections;
e756fc62 2585 control = &svm->vmcb->control;
85f455f7 2586 control->int_vector = irq;
6aa8b732
AK		 2587 control->int_ctl &= ~V_INTR_PRIO_MASK;
2588 control->int_ctl |= V_IRQ_MASK |
2589 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2590}
2591
66fd3f7f 2592static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2593{
2594 struct vcpu_svm *svm = to_svm(vcpu);
2595
2af9194d 2596 BUG_ON(!(gif_set(svm)));
cf74a78b 2597
219b65dc
AG		 2598 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2599 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2600}
2601
95ba8273 2602static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2603{
2604 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2605
88ab24ad
JR		 2606 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2607 return;
2608
95ba8273 2609 if (irr == -1)
aaacfc9a
JR		 2610 return;
2611
95ba8273
GN		 2612 if (tpr >= irr)
2613 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2614}
aaacfc9a 2615
95ba8273
GN		 2616static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2617{
2618 struct vcpu_svm *svm = to_svm(vcpu);
2619 struct vmcb *vmcb = svm->vmcb;
2620 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2621 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2622}
2623
3cfc3092
JK		 2624static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2625{
2626 struct vcpu_svm *svm = to_svm(vcpu);
2627
2628 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2629}
2630
2631static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2632{
2633 struct vcpu_svm *svm = to_svm(vcpu);
2634
2635 if (masked) {
2636 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2637 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2638 } else {
2639 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2640 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2641 }
2642}
2643
78646121
GN		 2644static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2645{
2646 struct vcpu_svm *svm = to_svm(vcpu);
2647 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 2648 int ret;
2649
2650 if (!gif_set(svm) ||
2651 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2652 return 0;
2653
2654 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2655
2656 if (is_nested(svm))
2657 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2658
2659 return ret;
78646121
GN		 2660}
2661
9222be18 2662static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2663{
219b65dc 2664 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 2665
e0231715
JR		 2666 /*
2667 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
2668 * 1, because that's a separate STGI/VMRUN intercept. The next time we
2669 * get that intercept, this function will be called again though and
2670 * we'll get the vintr intercept.
2671 */
8fe54654 2672 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 2673 svm_set_vintr(svm);
2674 svm_inject_irq(svm, 0x0);
2675 }
85f455f7
ED		 2676}
2677
95ba8273 2678static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2679{
04d2cc77 2680 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2681
44c11430
GN		 2682 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2683 == HF_NMI_MASK)
2684 return; /* IRET will cause a vm exit */
2685
e0231715
JR		 2686 /*
2687 * Something prevents NMI from been injected. Single step over possible
2688 * problem (IRET or exception injection or interrupt shadow)
2689 */
6be7d306 2690 svm->nmi_singlestep = true;
44c11430
GN		 2691 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2692 update_db_intercept(vcpu);
c1150d8c
DL		 2693}
2694
cbc94022
IE		 2695static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2696{
2697 return 0;
2698}
2699
d9e368d6
AK		 2700static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2701{
2702 force_new_asid(vcpu);
2703}
2704
04d2cc77
AK		 2705static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2706{
2707}
2708
d7bf8221
JR		 2709static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2710{
2711 struct vcpu_svm *svm = to_svm(vcpu);
2712
88ab24ad
JR		 2713 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2714 return;
2715
d7bf8221
JR		 2716 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2717 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2718 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2719 }
2720}
2721
649d6864
JR		 2722static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2723{
2724 struct vcpu_svm *svm = to_svm(vcpu);
2725 u64 cr8;
2726
88ab24ad
JR		 2727 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2728 return;
2729
649d6864
JR		 2730 cr8 = kvm_get_cr8(vcpu);
2731 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2732 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2733}
2734
9222be18
GN		 2735static void svm_complete_interrupts(struct vcpu_svm *svm)
2736{
2737 u8 vector;
2738 int type;
2739 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 2740 unsigned int3_injected = svm->int3_injected;
2741
2742 svm->int3_injected = 0;
9222be18 2743
44c11430
GN		 2744 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2745 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2746
9222be18
GN		 2747 svm->vcpu.arch.nmi_injected = false;
2748 kvm_clear_exception_queue(&svm->vcpu);
2749 kvm_clear_interrupt_queue(&svm->vcpu);
2750
2751 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2752 return;
2753
2754 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2755 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2756
2757 switch (type) {
2758 case SVM_EXITINTINFO_TYPE_NMI:
2759 svm->vcpu.arch.nmi_injected = true;
2760 break;
2761 case SVM_EXITINTINFO_TYPE_EXEPT:
219b65dc
AG		 2762 if (is_nested(svm))
2763 break;
66b7138f
JK		 2764 /*
2765 * In case of software exceptions, do not reinject the vector,
2766 * but re-execute the instruction instead. Rewind RIP first
2767 * if we emulated INT3 before.
2768 */
2769 if (kvm_exception_is_soft(vector)) {
2770 if (vector == BP_VECTOR && int3_injected &&
2771 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
2772 kvm_rip_write(&svm->vcpu,
2773 kvm_rip_read(&svm->vcpu) -
2774 int3_injected);
9222be18 2775 break;
66b7138f 2776 }
9222be18
GN		 2777 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2778 u32 err = svm->vmcb->control.exit_int_info_err;
2779 kvm_queue_exception_e(&svm->vcpu, vector, err);
2780
2781 } else
2782 kvm_queue_exception(&svm->vcpu, vector);
2783 break;
2784 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2785 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2786 break;
2787 default:
2788 break;
2789 }
2790}
2791
80e31d4f
AK		 2792#ifdef CONFIG_X86_64
2793#define R "r"
2794#else
2795#define R "e"
2796#endif
2797
851ba692 2798static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 2799{
a2fa3e9f 2800 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2801 u16 fs_selector;
2802 u16 gs_selector;
2803 u16 ldt_selector;
d9e368d6 2804
cd3ff653
JR		 2805 /*
2806 * A vmexit emulation is required before the vcpu can be executed
2807 * again.
2808 */
2809 if (unlikely(svm->nested.exit_required))
2810 return;
2811
5fdbf976
MT		 2812 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2813 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2814 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2815
e756fc62 2816 pre_svm_run(svm);
6aa8b732 2817
649d6864
JR		 2818 sync_lapic_to_cr8(vcpu);
2819
6aa8b732 2820 save_host_msrs(vcpu);
d6e88aec
AK		 2821 fs_selector = kvm_read_fs();
2822 gs_selector = kvm_read_gs();
2823 ldt_selector = kvm_read_ldt();
cda0ffdd 2824 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2825 /* required for live migration with NPT */
2826 if (npt_enabled)
2827 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2828
04d2cc77
AK		 2829 clgi();
2830
2831 local_irq_enable();
36241b8c 2832
6aa8b732 2833 asm volatile (
80e31d4f
AK		 2834 "push %%"R"bp; \n\t"
2835 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2836 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2837 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2838 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2839 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2840 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2841#ifdef CONFIG_X86_64
fb3f0f51
RR		 2842 "mov %c[r8](%[svm]), %%r8 \n\t"
2843 "mov %c[r9](%[svm]), %%r9 \n\t"
2844 "mov %c[r10](%[svm]), %%r10 \n\t"
2845 "mov %c[r11](%[svm]), %%r11 \n\t"
2846 "mov %c[r12](%[svm]), %%r12 \n\t"
2847 "mov %c[r13](%[svm]), %%r13 \n\t"
2848 "mov %c[r14](%[svm]), %%r14 \n\t"
2849 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2850#endif
2851
6aa8b732 2852 /* Enter guest mode */
80e31d4f
AK		 2853 "push %%"R"ax \n\t"
2854 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2855 __ex(SVM_VMLOAD) "\n\t"
2856 __ex(SVM_VMRUN) "\n\t"
2857 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2858 "pop %%"R"ax \n\t"
6aa8b732
AK		 2859
2860 /* Save guest registers, load host registers */
80e31d4f
AK		 2861 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2862 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2863 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2864 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2865 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2866 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2867#ifdef CONFIG_X86_64
fb3f0f51
RR		 2868 "mov %%r8, %c[r8](%[svm]) \n\t"
2869 "mov %%r9, %c[r9](%[svm]) \n\t"
2870 "mov %%r10, %c[r10](%[svm]) \n\t"
2871 "mov %%r11, %c[r11](%[svm]) \n\t"
2872 "mov %%r12, %c[r12](%[svm]) \n\t"
2873 "mov %%r13, %c[r13](%[svm]) \n\t"
2874 "mov %%r14, %c[r14](%[svm]) \n\t"
2875 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2876#endif
80e31d4f 2877 "pop %%"R"bp"
6aa8b732 2878 :
fb3f0f51 2879 : [svm]"a"(svm),
6aa8b732 2880 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2881 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2882 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2883 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2884 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2885 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2886 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2887#ifdef CONFIG_X86_64
ad312c7c
ZX		 2888 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2889 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2890 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2891 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2892 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2893 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2894 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2895 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2896#endif
54a08c04 2897 : "cc", "memory"
80e31d4f 2898 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2899#ifdef CONFIG_X86_64
54a08c04
LV		 2900 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2901#endif
2902 );
6aa8b732 2903
ad312c7c 2904 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2905 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2906 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2907 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2908
d6e88aec
AK		 2909 kvm_load_fs(fs_selector);
2910 kvm_load_gs(gs_selector);
2911 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2912 load_host_msrs(vcpu);
2913
2914 reload_tss(vcpu);
2915
56ba47dd
AK		 2916 local_irq_disable();
2917
2918 stgi();
2919
d7bf8221
JR		 2920 sync_cr8_to_lapic(vcpu);
2921
a2fa3e9f 2922 svm->next_rip = 0;
9222be18 2923
6de4f3ad
AK		 2924 if (npt_enabled) {
2925 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2926 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2927 }
6aa8b732
AK		 2928}
2929
80e31d4f
AK		 2930#undef R
2931
6aa8b732
AK		 2932static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2933{
a2fa3e9f
GH		 2934 struct vcpu_svm *svm = to_svm(vcpu);
2935
709ddebf
JR		 2936 if (npt_enabled) {
2937 svm->vmcb->control.nested_cr3 = root;
2938 force_new_asid(vcpu);
2939 return;
2940 }
2941
a2fa3e9f 2942 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 2943 force_new_asid(vcpu);
2944}
2945
6aa8b732
AK		 2946static int is_disabled(void)
2947{
6031a61c
JR		 2948 u64 vm_cr;
2949
2950 rdmsrl(MSR_VM_CR, vm_cr);
2951 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2952 return 1;
2953
6aa8b732
AK		 2954 return 0;
2955}
2956
102d8325
IM		 2957static void
2958svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2959{
2960 /*
2961 * Patch in the VMMCALL instruction:
2962 */
2963 hypercall[0] = 0x0f;
2964 hypercall[1] = 0x01;
2965 hypercall[2] = 0xd9;
102d8325
IM		 2966}
2967
002c7f7c
YS		 2968static void svm_check_processor_compat(void *rtn)
2969{
2970 *(int *)rtn = 0;
2971}
2972
774ead3a
AK		 2973static bool svm_cpu_has_accelerated_tpr(void)
2974{
2975 return false;
2976}
2977
67253af5
SY		 2978static int get_npt_level(void)
2979{
2980#ifdef CONFIG_X86_64
2981 return PT64_ROOT_LEVEL;
2982#else
2983 return PT32E_ROOT_LEVEL;
2984#endif
2985}
2986
4b12f0de 2987static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 2988{
2989 return 0;
2990}
2991
0e851880
SY		 2992static void svm_cpuid_update(struct kvm_vcpu *vcpu)
2993{
2994}
2995
229456fc 2996static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 2997 { SVM_EXIT_READ_CR0, "read_cr0" },
2998 { SVM_EXIT_READ_CR3, "read_cr3" },
2999 { SVM_EXIT_READ_CR4, "read_cr4" },
3000 { SVM_EXIT_READ_CR8, "read_cr8" },
3001 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3002 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3003 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3004 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3005 { SVM_EXIT_READ_DR0, "read_dr0" },
3006 { SVM_EXIT_READ_DR1, "read_dr1" },
3007 { SVM_EXIT_READ_DR2, "read_dr2" },
3008 { SVM_EXIT_READ_DR3, "read_dr3" },
3009 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3010 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3011 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3012 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3013 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3014 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3015 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3016 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3017 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3018 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3019 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3020 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3021 { SVM_EXIT_INTR, "interrupt" },
3022 { SVM_EXIT_NMI, "nmi" },
3023 { SVM_EXIT_SMI, "smi" },
3024 { SVM_EXIT_INIT, "init" },
3025 { SVM_EXIT_VINTR, "vintr" },
3026 { SVM_EXIT_CPUID, "cpuid" },
3027 { SVM_EXIT_INVD, "invd" },
3028 { SVM_EXIT_HLT, "hlt" },
3029 { SVM_EXIT_INVLPG, "invlpg" },
3030 { SVM_EXIT_INVLPGA, "invlpga" },
3031 { SVM_EXIT_IOIO, "io" },
3032 { SVM_EXIT_MSR, "msr" },
3033 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3034 { SVM_EXIT_SHUTDOWN, "shutdown" },
3035 { SVM_EXIT_VMRUN, "vmrun" },
3036 { SVM_EXIT_VMMCALL, "hypercall" },
3037 { SVM_EXIT_VMLOAD, "vmload" },
3038 { SVM_EXIT_VMSAVE, "vmsave" },
3039 { SVM_EXIT_STGI, "stgi" },
3040 { SVM_EXIT_CLGI, "clgi" },
3041 { SVM_EXIT_SKINIT, "skinit" },
3042 { SVM_EXIT_WBINVD, "wbinvd" },
3043 { SVM_EXIT_MONITOR, "monitor" },
3044 { SVM_EXIT_MWAIT, "mwait" },
3045 { SVM_EXIT_NPF, "npf" },
3046 { -1, NULL }
3047};
3048
17cc3935 3049static int svm_get_lpage_level(void)
344f414f 3050{
17cc3935 3051 return PT_PDPE_LEVEL;
344f414f
JR		 3052}
3053
4e47c7a6
SY		 3054static bool svm_rdtscp_supported(void)
3055{
3056 return false;
3057}
3058
02daab21
AK		 3059static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3060{
3061 struct vcpu_svm *svm = to_svm(vcpu);
3062
02daab21 3063 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
66a562f7
JR		 3064 if (is_nested(svm))
3065 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3066 update_cr0_intercept(svm);
02daab21
AK		 3067}
3068
cbdd1bea 3069static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3070 .cpu_has_kvm_support = has_svm,
3071 .disabled_by_bios = is_disabled,
3072 .hardware_setup = svm_hardware_setup,
3073 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3074 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3075 .hardware_enable = svm_hardware_enable,
3076 .hardware_disable = svm_hardware_disable,
774ead3a 3077 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3078
3079 .vcpu_create = svm_create_vcpu,
3080 .vcpu_free = svm_free_vcpu,
04d2cc77 3081 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3082
04d2cc77 3083 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3084 .vcpu_load = svm_vcpu_load,
3085 .vcpu_put = svm_vcpu_put,
3086
3087 .set_guest_debug = svm_guest_debug,
3088 .get_msr = svm_get_msr,
3089 .set_msr = svm_set_msr,
3090 .get_segment_base = svm_get_segment_base,
3091 .get_segment = svm_get_segment,
3092 .set_segment = svm_set_segment,
2e4d2653 3093 .get_cpl = svm_get_cpl,
1747fb71 3094 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3095 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3096 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3097 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3098 .set_cr3 = svm_set_cr3,
3099 .set_cr4 = svm_set_cr4,
3100 .set_efer = svm_set_efer,
3101 .get_idt = svm_get_idt,
3102 .set_idt = svm_set_idt,
3103 .get_gdt = svm_get_gdt,
3104 .set_gdt = svm_set_gdt,
3105 .get_dr = svm_get_dr,
3106 .set_dr = svm_set_dr,
6de4f3ad 3107 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3108 .get_rflags = svm_get_rflags,
3109 .set_rflags = svm_set_rflags,
6b52d186 3110 .fpu_activate = svm_fpu_activate,
02daab21 3111 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3112
6aa8b732 3113 .tlb_flush = svm_flush_tlb,
6aa8b732 3114
6aa8b732 3115 .run = svm_vcpu_run,
04d2cc77 3116 .handle_exit = handle_exit,
6aa8b732 3117 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3118 .set_interrupt_shadow = svm_set_interrupt_shadow,
3119 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3120 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3121 .set_irq = svm_set_irq,
95ba8273 3122 .set_nmi = svm_inject_nmi,
298101da 3123 .queue_exception = svm_queue_exception,
78646121 3124 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3125 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3126 .get_nmi_mask = svm_get_nmi_mask,
3127 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3128 .enable_nmi_window = enable_nmi_window,
3129 .enable_irq_window = enable_irq_window,
3130 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3131
3132 .set_tss_addr = svm_set_tss_addr,
67253af5 3133 .get_tdp_level = get_npt_level,
4b12f0de 3134 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3135
3136 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3137 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3138
3139 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3140
3141 .rdtscp_supported = svm_rdtscp_supported,
6aa8b732
AK		 3142};
3143
3144static int __init svm_init(void)
3145{
cb498ea2 3146 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 3147 THIS_MODULE);
6aa8b732
AK		 3148}
3149
3150static void __exit svm_exit(void)
3151{
cb498ea2 3152 kvm_exit();
6aa8b732
AK		 3153}
3154
3155module_init(svm_init)
3156module_exit(svm_exit)
kernel source for telekom puls (alcatel/mediatek)