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KVM: Add generic RDPMC support
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
9611c187 7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
edf88417
AK		 17#include <linux/kvm_host.h>
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
5fdbf976 21#include "kvm_cache_regs.h"
fe4c7b19 22#include "x86.h"
e495606d 23
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/vmalloc.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
6aa8b732 31
67ec6607 32#include <asm/tlbflush.h>
e495606d 33#include <asm/desc.h>
631bc487 34#include <asm/kvm_para.h>
6aa8b732 35
63d1142f 36#include <asm/virtext.h>
229456fc 37#include "trace.h"
63d1142f 38
4ecac3fd
AK		 39#define __ex(x) __kvm_handle_fault_on_reboot(x)
40
6aa8b732
AK		 41MODULE_AUTHOR("Qumranet");
42MODULE_LICENSE("GPL");
43
44#define IOPM_ALLOC_ORDER 2
45#define MSRPM_ALLOC_ORDER 1
46
6aa8b732
AK		 47#define SEG_TYPE_LDT 2
48#define SEG_TYPE_BUSY_TSS16 3
49
6bc31bdc
AP		 50#define SVM_FEATURE_NPT (1 << 0)
51#define SVM_FEATURE_LBRV (1 << 1)
52#define SVM_FEATURE_SVML (1 << 2)
53#define SVM_FEATURE_NRIP (1 << 3)
ddce97aa
AP		 54#define SVM_FEATURE_TSC_RATE (1 << 4)
55#define SVM_FEATURE_VMCB_CLEAN (1 << 5)
56#define SVM_FEATURE_FLUSH_ASID (1 << 6)
57#define SVM_FEATURE_DECODE_ASSIST (1 << 7)
6bc31bdc 58#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 59
410e4d57
JR		 60#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
61#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
62#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
63
24e09cbf
JR		 64#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
65
fbc0db76 66#define TSC_RATIO_RSVD 0xffffff0000000000ULL
92a1f12d
JR		 67#define TSC_RATIO_MIN 0x0000000000000001ULL
68#define TSC_RATIO_MAX 0x000000ffffffffffULL
fbc0db76 69
67ec6607
JR		 70static bool erratum_383_found __read_mostly;
71
6c8166a7
AK		 72static const u32 host_save_user_msrs[] = {
73#ifdef CONFIG_X86_64
74 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
75 MSR_FS_BASE,
76#endif
77 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
78};
79
80#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
81
82struct kvm_vcpu;
83
e6aa9abd
JR		 84struct nested_state {
85 struct vmcb *hsave;
86 u64 hsave_msr;
4a810181 87 u64 vm_cr_msr;
e6aa9abd
JR		 88 u64 vmcb;
89
90 /* These are the merged vectors */
91 u32 *msrpm;
92
93 /* gpa pointers to the real vectors */
94 u64 vmcb_msrpm;
ce2ac085 95 u64 vmcb_iopm;
aad42c64 96
cd3ff653
JR		 97 /* A VMEXIT is required but not yet emulated */
98 bool exit_required;
99
aad42c64 100 /* cache for intercepts of the guest */
4ee546b4 101 u32 intercept_cr;
3aed041a 102 u32 intercept_dr;
aad42c64
JR		 103 u32 intercept_exceptions;
104 u64 intercept;
105
5bd2edc3
JR		 106 /* Nested Paging related state */
107 u64 nested_cr3;
e6aa9abd
JR		 108};
109
323c3d80
JR		 110#define MSRPM_OFFSETS 16
111static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
112
6c8166a7
AK		 113struct vcpu_svm {
114 struct kvm_vcpu vcpu;
115 struct vmcb *vmcb;
116 unsigned long vmcb_pa;
117 struct svm_cpu_data *svm_data;
118 uint64_t asid_generation;
119 uint64_t sysenter_esp;
120 uint64_t sysenter_eip;
121
122 u64 next_rip;
123
124 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
afe9e66f 125 struct {
dacccfdd
AK		 126 u16 fs;
127 u16 gs;
128 u16 ldt;
afe9e66f
AK		 129 u64 gs_base;
130 } host;
6c8166a7
AK		 131
132 u32 *msrpm;
6c8166a7 133
bd3d1ec3
AK		 134 ulong nmi_iret_rip;
135
e6aa9abd 136 struct nested_state nested;
6be7d306
JK		 137
138 bool nmi_singlestep;
66b7138f
JK		 139
140 unsigned int3_injected;
141 unsigned long int3_rip;
631bc487 142 u32 apf_reason;
fbc0db76
JR		 143
144 u64 tsc_ratio;
6c8166a7
AK		 145};
146
fbc0db76
JR		 147static DEFINE_PER_CPU(u64, current_tsc_ratio);
148#define TSC_RATIO_DEFAULT 0x0100000000ULL
149
455716fa
JR		 150#define MSR_INVALID 0xffffffffU
151
ac72a9b7
JR		 152static struct svm_direct_access_msrs {
153 u32 index; /* Index of the MSR */
154 bool always; /* True if intercept is always on */
155} direct_access_msrs[] = {
8c06585d 156 { .index = MSR_STAR, .always = true },
ac72a9b7
JR		 157 { .index = MSR_IA32_SYSENTER_CS, .always = true },
158#ifdef CONFIG_X86_64
159 { .index = MSR_GS_BASE, .always = true },
160 { .index = MSR_FS_BASE, .always = true },
161 { .index = MSR_KERNEL_GS_BASE, .always = true },
162 { .index = MSR_LSTAR, .always = true },
163 { .index = MSR_CSTAR, .always = true },
164 { .index = MSR_SYSCALL_MASK, .always = true },
165#endif
166 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
167 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
168 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
169 { .index = MSR_IA32_LASTINTTOIP, .always = false },
170 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 171};
172
709ddebf
JR		 173/* enable NPT for AMD64 and X86 with PAE */
174#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
175static bool npt_enabled = true;
176#else
e0231715 177static bool npt_enabled;
709ddebf 178#endif
6c7dac72
JR		 179static int npt = 1;
180
181module_param(npt, int, S_IRUGO);
e3da3acd 182
4b6e4dca 183static int nested = 1;
236de055
AG		 184module_param(nested, int, S_IRUGO);
185
44874f84 186static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 187static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 188
410e4d57 189static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 190static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 191static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 192static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
193 bool has_error_code, u32 error_code);
92a1f12d 194static u64 __scale_tsc(u64 ratio, u64 tsc);
cf74a78b 195
8d28fec4 196enum {
116a0a23
JR		 197 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
198 pause filter count */
f56838e4 199 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
d48086d1 200 VMCB_ASID, /* ASID */
decdbf6a 201 VMCB_INTR, /* int_ctl, int_vector */
b2747166 202 VMCB_NPT, /* npt_en, nCR3, gPAT */
dcca1a65 203 VMCB_CR, /* CR0, CR3, CR4, EFER */
72214b96 204 VMCB_DR, /* DR6, DR7 */
17a703cb 205 VMCB_DT, /* GDT, IDT */
060d0c9a 206 VMCB_SEG, /* CS, DS, SS, ES, CPL */
0574dec0 207 VMCB_CR2, /* CR2 only */
b53ba3f9 208 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
8d28fec4
RJ		 209 VMCB_DIRTY_MAX,
210};
211
0574dec0
JR		 212/* TPR and CR2 are always written before VMRUN */
213#define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
8d28fec4
RJ		 214
215static inline void mark_all_dirty(struct vmcb *vmcb)
216{
217 vmcb->control.clean = 0;
218}
219
220static inline void mark_all_clean(struct vmcb *vmcb)
221{
222 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
223 & ~VMCB_ALWAYS_DIRTY_MASK;
224}
225
226static inline void mark_dirty(struct vmcb *vmcb, int bit)
227{
228 vmcb->control.clean &= ~(1 << bit);
229}
230
a2fa3e9f
GH		 231static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
232{
fb3f0f51 233 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 234}
235
384c6368
JR		 236static void recalc_intercepts(struct vcpu_svm *svm)
237{
238 struct vmcb_control_area *c, *h;
239 struct nested_state *g;
240
116a0a23
JR		 241 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
242
384c6368
JR		 243 if (!is_guest_mode(&svm->vcpu))
244 return;
245
246 c = &svm->vmcb->control;
247 h = &svm->nested.hsave->control;
248 g = &svm->nested;
249
4ee546b4 250 c->intercept_cr = h->intercept_cr | g->intercept_cr;
3aed041a 251 c->intercept_dr = h->intercept_dr | g->intercept_dr;
384c6368
JR		 252 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
253 c->intercept = h->intercept | g->intercept;
254}
255
4ee546b4
RJ		 256static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
257{
258 if (is_guest_mode(&svm->vcpu))
259 return svm->nested.hsave;
260 else
261 return svm->vmcb;
262}
263
264static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
265{
266 struct vmcb *vmcb = get_host_vmcb(svm);
267
268 vmcb->control.intercept_cr |= (1U << bit);
269
270 recalc_intercepts(svm);
271}
272
273static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
274{
275 struct vmcb *vmcb = get_host_vmcb(svm);
276
277 vmcb->control.intercept_cr &= ~(1U << bit);
278
279 recalc_intercepts(svm);
280}
281
282static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
283{
284 struct vmcb *vmcb = get_host_vmcb(svm);
285
286 return vmcb->control.intercept_cr & (1U << bit);
287}
288
3aed041a
JR		 289static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
290{
291 struct vmcb *vmcb = get_host_vmcb(svm);
292
293 vmcb->control.intercept_dr |= (1U << bit);
294
295 recalc_intercepts(svm);
296}
297
298static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
299{
300 struct vmcb *vmcb = get_host_vmcb(svm);
301
302 vmcb->control.intercept_dr &= ~(1U << bit);
303
304 recalc_intercepts(svm);
305}
306
18c918c5
JR		 307static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
308{
309 struct vmcb *vmcb = get_host_vmcb(svm);
310
311 vmcb->control.intercept_exceptions |= (1U << bit);
312
313 recalc_intercepts(svm);
314}
315
316static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
317{
318 struct vmcb *vmcb = get_host_vmcb(svm);
319
320 vmcb->control.intercept_exceptions &= ~(1U << bit);
321
322 recalc_intercepts(svm);
323}
324
8a05a1b8
JR		 325static inline void set_intercept(struct vcpu_svm *svm, int bit)
326{
327 struct vmcb *vmcb = get_host_vmcb(svm);
328
329 vmcb->control.intercept |= (1ULL << bit);
330
331 recalc_intercepts(svm);
332}
333
334static inline void clr_intercept(struct vcpu_svm *svm, int bit)
335{
336 struct vmcb *vmcb = get_host_vmcb(svm);
337
338 vmcb->control.intercept &= ~(1ULL << bit);
339
340 recalc_intercepts(svm);
341}
342
2af9194d
JR		 343static inline void enable_gif(struct vcpu_svm *svm)
344{
345 svm->vcpu.arch.hflags |= HF_GIF_MASK;
346}
347
348static inline void disable_gif(struct vcpu_svm *svm)
349{
350 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
351}
352
353static inline bool gif_set(struct vcpu_svm *svm)
354{
355 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
356}
357
4866d5e3 358static unsigned long iopm_base;
6aa8b732
AK		 359
360struct kvm_ldttss_desc {
361 u16 limit0;
362 u16 base0;
e0231715
JR		 363 unsigned base1:8, type:5, dpl:2, p:1;
364 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 365 u32 base3;
366 u32 zero1;
367} __attribute__((packed));
368
369struct svm_cpu_data {
370 int cpu;
371
5008fdf5
AK		 372 u64 asid_generation;
373 u32 max_asid;
374 u32 next_asid;
6aa8b732
AK		 375 struct kvm_ldttss_desc *tss_desc;
376
377 struct page *save_area;
378};
379
380static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
381
382struct svm_init_data {
383 int cpu;
384 int r;
385};
386
387static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
388
9d8f549d 389#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 390#define MSRS_RANGE_SIZE 2048
391#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
392
455716fa
JR		 393static u32 svm_msrpm_offset(u32 msr)
394{
395 u32 offset;
396 int i;
397
398 for (i = 0; i < NUM_MSR_MAPS; i++) {
399 if (msr < msrpm_ranges[i] ||
400 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
401 continue;
402
403 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
404 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
405
406 /* Now we have the u8 offset - but need the u32 offset */
407 return offset / 4;
408 }
409
410 /* MSR not in any range */
411 return MSR_INVALID;
412}
413
6aa8b732
AK		 414#define MAX_INST_SIZE 15
415
6aa8b732
AK		 416static inline void clgi(void)
417{
4ecac3fd 418 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 419}
420
421static inline void stgi(void)
422{
4ecac3fd 423 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 424}
425
426static inline void invlpga(unsigned long addr, u32 asid)
427{
e0231715 428 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 429}
430
4b16184c
JR		 431static int get_npt_level(void)
432{
433#ifdef CONFIG_X86_64
434 return PT64_ROOT_LEVEL;
435#else
436 return PT32E_ROOT_LEVEL;
437#endif
438}
439
6aa8b732
AK		 440static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
441{
6dc696d4 442 vcpu->arch.efer = efer;
709ddebf 443 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 444 efer &= ~EFER_LME;
6aa8b732 445
9962d032 446 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
dcca1a65 447 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
6aa8b732
AK		 448}
449
6aa8b732
AK		 450static int is_external_interrupt(u32 info)
451{
452 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
453 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
454}
455
2809f5d2
GC		 456static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
457{
458 struct vcpu_svm *svm = to_svm(vcpu);
459 u32 ret = 0;
460
461 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 462 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 463 return ret & mask;
464}
465
466static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
467{
468 struct vcpu_svm *svm = to_svm(vcpu);
469
470 if (mask == 0)
471 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
472 else
473 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
474
475}
476
6aa8b732
AK		 477static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
478{
a2fa3e9f
GH		 479 struct vcpu_svm *svm = to_svm(vcpu);
480
6bc31bdc
AP		 481 if (svm->vmcb->control.next_rip != 0)
482 svm->next_rip = svm->vmcb->control.next_rip;
483
a2fa3e9f 484 if (!svm->next_rip) {
51d8b661 485 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
f629cf84
GN		 486 EMULATE_DONE)
487 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 488 return;
489 }
5fdbf976
MT		 490 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
491 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
492 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 493
5fdbf976 494 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 495 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 496}
497
116a4752 498static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 499 bool has_error_code, u32 error_code,
500 bool reinject)
116a4752
JK		 501{
502 struct vcpu_svm *svm = to_svm(vcpu);
503
e0231715
JR		 504 /*
505 * If we are within a nested VM we'd better #VMEXIT and let the guest
506 * handle the exception
507 */
ce7ddec4
JR		 508 if (!reinject &&
509 nested_svm_check_exception(svm, nr, has_error_code, error_code))
116a4752
JK		 510 return;
511
2a6b20b8 512 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
66b7138f
JK		 513 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
514
515 /*
516 * For guest debugging where we have to reinject #BP if some
517 * INT3 is guest-owned:
518 * Emulate nRIP by moving RIP forward. Will fail if injection
519 * raises a fault that is not intercepted. Still better than
520 * failing in all cases.
521 */
522 skip_emulated_instruction(&svm->vcpu);
523 rip = kvm_rip_read(&svm->vcpu);
524 svm->int3_rip = rip + svm->vmcb->save.cs.base;
525 svm->int3_injected = rip - old_rip;
526 }
527
116a4752
JK		 528 svm->vmcb->control.event_inj = nr
529 | SVM_EVTINJ_VALID
530 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
531 | SVM_EVTINJ_TYPE_EXEPT;
532 svm->vmcb->control.event_inj_err = error_code;
533}
534
67ec6607
JR		 535static void svm_init_erratum_383(void)
536{
537 u32 low, high;
538 int err;
539 u64 val;
540
1be85a6d 541 if (!cpu_has_amd_erratum(amd_erratum_383))
67ec6607
JR		 542 return;
543
544 /* Use _safe variants to not break nested virtualization */
545 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
546 if (err)
547 return;
548
549 val |= (1ULL << 47);
550
551 low = lower_32_bits(val);
552 high = upper_32_bits(val);
553
554 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
555
556 erratum_383_found = true;
557}
558
6aa8b732
AK		 559static int has_svm(void)
560{
63d1142f 561 const char *msg;
6aa8b732 562
63d1142f 563 if (!cpu_has_svm(&msg)) {
ff81ff10 564 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 565 return 0;
566 }
567
6aa8b732
AK		 568 return 1;
569}
570
571static void svm_hardware_disable(void *garbage)
572{
fbc0db76
JR		 573 /* Make sure we clean up behind us */
574 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
575 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
576
2c8dceeb 577 cpu_svm_disable();
6aa8b732
AK		 578}
579
10474ae8 580static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 581{
582
0fe1e009 583 struct svm_cpu_data *sd;
6aa8b732 584 uint64_t efer;
89a27f4d 585 struct desc_ptr gdt_descr;
6aa8b732
AK		 586 struct desc_struct *gdt;
587 int me = raw_smp_processor_id();
588
10474ae8
AG		 589 rdmsrl(MSR_EFER, efer);
590 if (efer & EFER_SVME)
591 return -EBUSY;
592
6aa8b732 593 if (!has_svm()) {
e6732a5a
ZA		 594 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
595 me);
10474ae8 596 return -EINVAL;
6aa8b732 597 }
0fe1e009 598 sd = per_cpu(svm_data, me);
6aa8b732 599
0fe1e009 600 if (!sd) {
e6732a5a 601 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 602 me);
10474ae8 603 return -EINVAL;
6aa8b732
AK		 604 }
605
0fe1e009
TH		 606 sd->asid_generation = 1;
607 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
608 sd->next_asid = sd->max_asid + 1;
6aa8b732 609
d6ab1ed4 610 native_store_gdt(&gdt_descr);
89a27f4d 611 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 612 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 613
9962d032 614 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 615
d0316554 616 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8 617
fbc0db76
JR		 618 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
619 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
620 __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
621 }
622
67ec6607
JR		 623 svm_init_erratum_383();
624
10474ae8 625 return 0;
6aa8b732
AK		 626}
627
0da1db75
JR		 628static void svm_cpu_uninit(int cpu)
629{
0fe1e009 630 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 631
0fe1e009 632 if (!sd)
0da1db75
JR		 633 return;
634
635 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 636 __free_page(sd->save_area);
637 kfree(sd);
0da1db75
JR		 638}
639
6aa8b732
AK		 640static int svm_cpu_init(int cpu)
641{
0fe1e009 642 struct svm_cpu_data *sd;
6aa8b732
AK		 643 int r;
644
0fe1e009
TH		 645 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
646 if (!sd)
6aa8b732 647 return -ENOMEM;
0fe1e009
TH		 648 sd->cpu = cpu;
649 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 650 r = -ENOMEM;
0fe1e009 651 if (!sd->save_area)
6aa8b732
AK		 652 goto err_1;
653
0fe1e009 654 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 655
656 return 0;
657
658err_1:
0fe1e009 659 kfree(sd);
6aa8b732
AK		 660 return r;
661
662}
663
ac72a9b7
JR		 664static bool valid_msr_intercept(u32 index)
665{
666 int i;
667
668 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
669 if (direct_access_msrs[i].index == index)
670 return true;
671
672 return false;
673}
674
bfc733a7
RR		 675static void set_msr_interception(u32 *msrpm, unsigned msr,
676 int read, int write)
6aa8b732 677{
455716fa
JR		 678 u8 bit_read, bit_write;
679 unsigned long tmp;
680 u32 offset;
6aa8b732 681
ac72a9b7
JR		 682 /*
683 * If this warning triggers extend the direct_access_msrs list at the
684 * beginning of the file
685 */
686 WARN_ON(!valid_msr_intercept(msr));
687
455716fa
JR		 688 offset = svm_msrpm_offset(msr);
689 bit_read = 2 * (msr & 0x0f);
690 bit_write = 2 * (msr & 0x0f) + 1;
691 tmp = msrpm[offset];
692
693 BUG_ON(offset == MSR_INVALID);
694
695 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
696 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
697
698 msrpm[offset] = tmp;
6aa8b732
AK		 699}
700
f65c229c 701static void svm_vcpu_init_msrpm(u32 *msrpm)
6aa8b732
AK		 702{
703 int i;
704
f65c229c
JR		 705 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
706
ac72a9b7
JR		 707 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
708 if (!direct_access_msrs[i].always)
709 continue;
710
711 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
712 }
f65c229c
JR		 713}
714
323c3d80
JR		 715static void add_msr_offset(u32 offset)
716{
717 int i;
718
719 for (i = 0; i < MSRPM_OFFSETS; ++i) {
720
721 /* Offset already in list? */
722 if (msrpm_offsets[i] == offset)
bfc733a7 723 return;
323c3d80
JR		 724
725 /* Slot used by another offset? */
726 if (msrpm_offsets[i] != MSR_INVALID)
727 continue;
728
729 /* Add offset to list */
730 msrpm_offsets[i] = offset;
731
732 return;
6aa8b732 733 }
323c3d80
JR		 734
735 /*
736 * If this BUG triggers the msrpm_offsets table has an overflow. Just
737 * increase MSRPM_OFFSETS in this case.
738 */
bfc733a7 739 BUG();
6aa8b732
AK		 740}
741
323c3d80 742static void init_msrpm_offsets(void)
f65c229c 743{
323c3d80 744 int i;
f65c229c 745
323c3d80
JR		 746 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
747
748 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
749 u32 offset;
750
751 offset = svm_msrpm_offset(direct_access_msrs[i].index);
752 BUG_ON(offset == MSR_INVALID);
753
754 add_msr_offset(offset);
755 }
f65c229c
JR		 756}
757
24e09cbf
JR		 758static void svm_enable_lbrv(struct vcpu_svm *svm)
759{
760 u32 *msrpm = svm->msrpm;
761
762 svm->vmcb->control.lbr_ctl = 1;
763 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
764 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
765 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
766 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
767}
768
769static void svm_disable_lbrv(struct vcpu_svm *svm)
770{
771 u32 *msrpm = svm->msrpm;
772
773 svm->vmcb->control.lbr_ctl = 0;
774 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
775 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
776 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
777 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
778}
779
6aa8b732
AK		 780static __init int svm_hardware_setup(void)
781{
782 int cpu;
783 struct page *iopm_pages;
f65c229c 784 void *iopm_va;
6aa8b732
AK		 785 int r;
786
6aa8b732
AK		 787 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
788
789 if (!iopm_pages)
790 return -ENOMEM;
c8681339
AL		 791
792 iopm_va = page_address(iopm_pages);
793 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 794 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
795
323c3d80
JR		 796 init_msrpm_offsets();
797
50a37eb4
JR		 798 if (boot_cpu_has(X86_FEATURE_NX))
799 kvm_enable_efer_bits(EFER_NX);
800
1b2fd70c
AG		 801 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
802 kvm_enable_efer_bits(EFER_FFXSR);
803
92a1f12d
JR		 804 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
805 u64 max;
806
807 kvm_has_tsc_control = true;
808
809 /*
810 * Make sure the user can only configure tsc_khz values that
811 * fit into a signed integer.
812 * A min value is not calculated needed because it will always
813 * be 1 on all machines and a value of 0 is used to disable
814 * tsc-scaling for the vcpu.
815 */
816 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
817
818 kvm_max_guest_tsc_khz = max;
819 }
820
236de055
AG		 821 if (nested) {
822 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
eec4b140 823 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
236de055
AG		 824 }
825
3230bb47 826 for_each_possible_cpu(cpu) {
6aa8b732
AK		 827 r = svm_cpu_init(cpu);
828 if (r)
f65c229c 829 goto err;
6aa8b732 830 }
33bd6a0b 831
2a6b20b8 832 if (!boot_cpu_has(X86_FEATURE_NPT))
e3da3acd
JR		 833 npt_enabled = false;
834
6c7dac72
JR		 835 if (npt_enabled && !npt) {
836 printk(KERN_INFO "kvm: Nested Paging disabled\n");
837 npt_enabled = false;
838 }
839
18552672 840 if (npt_enabled) {
e3da3acd 841 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 842 kvm_enable_tdp();
5f4cb662
JR		 843 } else
844 kvm_disable_tdp();
e3da3acd 845
6aa8b732
AK		 846 return 0;
847
f65c229c 848err:
6aa8b732
AK		 849 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
850 iopm_base = 0;
851 return r;
852}
853
854static __exit void svm_hardware_unsetup(void)
855{
0da1db75
JR		 856 int cpu;
857
3230bb47 858 for_each_possible_cpu(cpu)
0da1db75
JR		 859 svm_cpu_uninit(cpu);
860
6aa8b732 861 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 862 iopm_base = 0;
6aa8b732
AK		 863}
864
865static void init_seg(struct vmcb_seg *seg)
866{
867 seg->selector = 0;
868 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 869 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 870 seg->limit = 0xffff;
871 seg->base = 0;
872}
873
874static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
875{
876 seg->selector = 0;
877 seg->attrib = SVM_SELECTOR_P_MASK | type;
878 seg->limit = 0xffff;
879 seg->base = 0;
880}
881
fbc0db76
JR		 882static u64 __scale_tsc(u64 ratio, u64 tsc)
883{
884 u64 mult, frac, _tsc;
885
886 mult = ratio >> 32;
887 frac = ratio & ((1ULL << 32) - 1);
888
889 _tsc = tsc;
890 _tsc *= mult;
891 _tsc += (tsc >> 32) * frac;
892 _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
893
894 return _tsc;
895}
896
897static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
898{
899 struct vcpu_svm *svm = to_svm(vcpu);
900 u64 _tsc = tsc;
901
902 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
903 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
904
905 return _tsc;
906}
907
4051b188
JR		 908static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
909{
910 struct vcpu_svm *svm = to_svm(vcpu);
911 u64 ratio;
912 u64 khz;
913
914 /* TSC scaling supported? */
915 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR))
916 return;
917
918 /* TSC-Scaling disabled or guest TSC same frequency as host TSC? */
919 if (user_tsc_khz == 0) {
920 vcpu->arch.virtual_tsc_khz = 0;
921 svm->tsc_ratio = TSC_RATIO_DEFAULT;
922 return;
923 }
924
925 khz = user_tsc_khz;
926
927 /* TSC scaling required - calculate ratio */
928 ratio = khz << 32;
929 do_div(ratio, tsc_khz);
930
931 if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
932 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
933 user_tsc_khz);
934 return;
935 }
936 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
937 svm->tsc_ratio = ratio;
938}
939
f4e1b3c8
ZA		 940static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
941{
942 struct vcpu_svm *svm = to_svm(vcpu);
943 u64 g_tsc_offset = 0;
944
2030753d 945 if (is_guest_mode(vcpu)) {
f4e1b3c8
ZA		 946 g_tsc_offset = svm->vmcb->control.tsc_offset -
947 svm->nested.hsave->control.tsc_offset;
948 svm->nested.hsave->control.tsc_offset = offset;
949 }
950
951 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
116a0a23
JR		 952
953 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
f4e1b3c8
ZA		 954}
955
e48672fa
ZA		 956static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
957{
958 struct vcpu_svm *svm = to_svm(vcpu);
959
960 svm->vmcb->control.tsc_offset += adjustment;
2030753d 961 if (is_guest_mode(vcpu))
e48672fa 962 svm->nested.hsave->control.tsc_offset += adjustment;
116a0a23 963 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
e48672fa
ZA		 964}
965
857e4099
JR		 966static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
967{
968 u64 tsc;
969
970 tsc = svm_scale_tsc(vcpu, native_read_tsc());
971
972 return target_tsc - tsc;
973}
974
e6101a96 975static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 976{
e6101a96
JR		 977 struct vmcb_control_area *control = &svm->vmcb->control;
978 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 979
bff78274 980 svm->vcpu.fpu_active = 1;
4ee546b4 981 svm->vcpu.arch.hflags = 0;
bff78274 982
4ee546b4
RJ		 983 set_cr_intercept(svm, INTERCEPT_CR0_READ);
984 set_cr_intercept(svm, INTERCEPT_CR3_READ);
985 set_cr_intercept(svm, INTERCEPT_CR4_READ);
986 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
987 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
988 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
989 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
6aa8b732 990
3aed041a
JR		 991 set_dr_intercept(svm, INTERCEPT_DR0_READ);
992 set_dr_intercept(svm, INTERCEPT_DR1_READ);
993 set_dr_intercept(svm, INTERCEPT_DR2_READ);
994 set_dr_intercept(svm, INTERCEPT_DR3_READ);
995 set_dr_intercept(svm, INTERCEPT_DR4_READ);
996 set_dr_intercept(svm, INTERCEPT_DR5_READ);
997 set_dr_intercept(svm, INTERCEPT_DR6_READ);
998 set_dr_intercept(svm, INTERCEPT_DR7_READ);
999
1000 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
1001 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
1002 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
1003 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
1004 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
1005 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
1006 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
1007 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
6aa8b732 1008
18c918c5
JR		 1009 set_exception_intercept(svm, PF_VECTOR);
1010 set_exception_intercept(svm, UD_VECTOR);
1011 set_exception_intercept(svm, MC_VECTOR);
6aa8b732 1012
8a05a1b8
JR		 1013 set_intercept(svm, INTERCEPT_INTR);
1014 set_intercept(svm, INTERCEPT_NMI);
1015 set_intercept(svm, INTERCEPT_SMI);
1016 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1017 set_intercept(svm, INTERCEPT_CPUID);
1018 set_intercept(svm, INTERCEPT_INVD);
1019 set_intercept(svm, INTERCEPT_HLT);
1020 set_intercept(svm, INTERCEPT_INVLPG);
1021 set_intercept(svm, INTERCEPT_INVLPGA);
1022 set_intercept(svm, INTERCEPT_IOIO_PROT);
1023 set_intercept(svm, INTERCEPT_MSR_PROT);
1024 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1025 set_intercept(svm, INTERCEPT_SHUTDOWN);
1026 set_intercept(svm, INTERCEPT_VMRUN);
1027 set_intercept(svm, INTERCEPT_VMMCALL);
1028 set_intercept(svm, INTERCEPT_VMLOAD);
1029 set_intercept(svm, INTERCEPT_VMSAVE);
1030 set_intercept(svm, INTERCEPT_STGI);
1031 set_intercept(svm, INTERCEPT_CLGI);
1032 set_intercept(svm, INTERCEPT_SKINIT);
1033 set_intercept(svm, INTERCEPT_WBINVD);
1034 set_intercept(svm, INTERCEPT_MONITOR);
1035 set_intercept(svm, INTERCEPT_MWAIT);
81dd35d4 1036 set_intercept(svm, INTERCEPT_XSETBV);
6aa8b732
AK		 1037
1038 control->iopm_base_pa = iopm_base;
f65c229c 1039 control->msrpm_base_pa = __pa(svm->msrpm);
6aa8b732
AK		 1040 control->int_ctl = V_INTR_MASKING_MASK;
1041
1042 init_seg(&save->es);
1043 init_seg(&save->ss);
1044 init_seg(&save->ds);
1045 init_seg(&save->fs);
1046 init_seg(&save->gs);
1047
1048 save->cs.selector = 0xf000;
1049 /* Executable/Readable Code Segment */
1050 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1051 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1052 save->cs.limit = 0xffff;
d92899a0
AK		 1053 /*
1054 * cs.base should really be 0xffff0000, but vmx can't handle that, so
1055 * be consistent with it.
1056 *
1057 * Replace when we have real mode working for vmx.
1058 */
1059 save->cs.base = 0xf0000;
6aa8b732
AK		 1060
1061 save->gdtr.limit = 0xffff;
1062 save->idtr.limit = 0xffff;
1063
1064 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1065 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1066
eaa48512 1067 svm_set_efer(&svm->vcpu, 0);
d77c26fc 1068 save->dr6 = 0xffff0ff0;
6aa8b732 1069 save->dr7 = 0x400;
f6e78475 1070 kvm_set_rflags(&svm->vcpu, 2);
6aa8b732 1071 save->rip = 0x0000fff0;
5fdbf976 1072 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 1073
e0231715
JR		 1074 /*
1075 * This is the guest-visible cr0 value.
18fa000a 1076 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 1077 */
678041ad
MT		 1078 svm->vcpu.arch.cr0 = 0;
1079 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
18fa000a 1080
66aee91a 1081 save->cr4 = X86_CR4_PAE;
6aa8b732 1082 /* rdx = ?? */
709ddebf
JR		 1083
1084 if (npt_enabled) {
1085 /* Setup VMCB for Nested Paging */
1086 control->nested_ctl = 1;
8a05a1b8 1087 clr_intercept(svm, INTERCEPT_INVLPG);
18c918c5 1088 clr_exception_intercept(svm, PF_VECTOR);
4ee546b4
RJ		 1089 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1090 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
709ddebf 1091 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 1092 save->cr3 = 0;
1093 save->cr4 = 0;
1094 }
f40f6a45 1095 svm->asid_generation = 0;
1371d904 1096
e6aa9abd 1097 svm->nested.vmcb = 0;
2af9194d
JR		 1098 svm->vcpu.arch.hflags = 0;
1099
2a6b20b8 1100 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
565d0998 1101 control->pause_filter_count = 3000;
8a05a1b8 1102 set_intercept(svm, INTERCEPT_PAUSE);
565d0998
ML		 1103 }
1104
8d28fec4
RJ		 1105 mark_all_dirty(svm->vmcb);
1106
2af9194d 1107 enable_gif(svm);
6aa8b732
AK		 1108}
1109
e00c8cf2 1110static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 1111{
1112 struct vcpu_svm *svm = to_svm(vcpu);
1113
e6101a96 1114 init_vmcb(svm);
70433389 1115
c5af89b6 1116 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 1117 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 1118 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1119 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 1120 }
5fdbf976
MT		 1121 vcpu->arch.regs_avail = ~0;
1122 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 1123
1124 return 0;
04d2cc77
AK		 1125}
1126
fb3f0f51 1127static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 1128{
a2fa3e9f 1129 struct vcpu_svm *svm;
6aa8b732 1130 struct page *page;
f65c229c 1131 struct page *msrpm_pages;
b286d5d8 1132 struct page *hsave_page;
3d6368ef 1133 struct page *nested_msrpm_pages;
fb3f0f51 1134 int err;
6aa8b732 1135
c16f862d 1136 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 1137 if (!svm) {
1138 err = -ENOMEM;
1139 goto out;
1140 }
1141
fbc0db76
JR		 1142 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1143
fb3f0f51
RR		 1144 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1145 if (err)
1146 goto free_svm;
1147
b7af4043 1148 err = -ENOMEM;
6aa8b732 1149 page = alloc_page(GFP_KERNEL);
b7af4043 1150 if (!page)
fb3f0f51 1151 goto uninit;
6aa8b732 1152
f65c229c
JR		 1153 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1154 if (!msrpm_pages)
b7af4043 1155 goto free_page1;
3d6368ef
AG		 1156
1157 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1158 if (!nested_msrpm_pages)
b7af4043 1159 goto free_page2;
f65c229c 1160
b286d5d8
AG		 1161 hsave_page = alloc_page(GFP_KERNEL);
1162 if (!hsave_page)
b7af4043
TY		 1163 goto free_page3;
1164
e6aa9abd 1165 svm->nested.hsave = page_address(hsave_page);
b286d5d8 1166
b7af4043
TY		 1167 svm->msrpm = page_address(msrpm_pages);
1168 svm_vcpu_init_msrpm(svm->msrpm);
1169
e6aa9abd 1170 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 1171 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 1172
a2fa3e9f
GH		 1173 svm->vmcb = page_address(page);
1174 clear_page(svm->vmcb);
1175 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1176 svm->asid_generation = 0;
e6101a96 1177 init_vmcb(svm);
99e3e30a 1178 kvm_write_tsc(&svm->vcpu, 0);
a2fa3e9f 1179
10ab25cd
JK		 1180 err = fx_init(&svm->vcpu);
1181 if (err)
1182 goto free_page4;
1183
ad312c7c 1184 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 1185 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 1186 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 1187
fb3f0f51 1188 return &svm->vcpu;
36241b8c 1189
10ab25cd
JK		 1190free_page4:
1191 __free_page(hsave_page);
b7af4043
TY		 1192free_page3:
1193 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1194free_page2:
1195 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1196free_page1:
1197 __free_page(page);
fb3f0f51
RR		 1198uninit:
1199 kvm_vcpu_uninit(&svm->vcpu);
1200free_svm:
a4770347 1201 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 1202out:
1203 return ERR_PTR(err);
6aa8b732
AK		 1204}
1205
1206static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1207{
a2fa3e9f
GH		 1208 struct vcpu_svm *svm = to_svm(vcpu);
1209
fb3f0f51 1210 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 1211 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 1212 __free_page(virt_to_page(svm->nested.hsave));
1213 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 1214 kvm_vcpu_uninit(vcpu);
a4770347 1215 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 1216}
1217
15ad7146 1218static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1219{
a2fa3e9f 1220 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 1221 int i;
0cc5064d 1222
0cc5064d 1223 if (unlikely(cpu != vcpu->cpu)) {
4b656b12 1224 svm->asid_generation = 0;
8d28fec4 1225 mark_all_dirty(svm->vmcb);
0cc5064d 1226 }
94dfbdb3 1227
82ca2d10
AK		 1228#ifdef CONFIG_X86_64
1229 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1230#endif
dacccfdd
AK		 1231 savesegment(fs, svm->host.fs);
1232 savesegment(gs, svm->host.gs);
1233 svm->host.ldt = kvm_read_ldt();
1234
94dfbdb3 1235 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1236 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
fbc0db76
JR		 1237
1238 if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1239 svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) {
1240 __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio;
1241 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1242 }
6aa8b732
AK		 1243}
1244
1245static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1246{
a2fa3e9f 1247 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 1248 int i;
1249
e1beb1d3 1250 ++vcpu->stat.host_state_reload;
dacccfdd
AK		 1251 kvm_load_ldt(svm->host.ldt);
1252#ifdef CONFIG_X86_64
1253 loadsegment(fs, svm->host.fs);
dacccfdd 1254 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
893a5ab6 1255 load_gs_index(svm->host.gs);
dacccfdd 1256#else
831ca609 1257#ifdef CONFIG_X86_32_LAZY_GS
dacccfdd 1258 loadsegment(gs, svm->host.gs);
831ca609 1259#endif
dacccfdd 1260#endif
94dfbdb3 1261 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1262 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 1263}
1264
6aa8b732
AK		 1265static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1266{
a2fa3e9f 1267 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 1268}
1269
1270static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1271{
a2fa3e9f 1272 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 1273}
1274
6de4f3ad
AK		 1275static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1276{
1277 switch (reg) {
1278 case VCPU_EXREG_PDPTR:
1279 BUG_ON(!npt_enabled);
9f8fe504 1280 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6de4f3ad
AK		 1281 break;
1282 default:
1283 BUG();
1284 }
1285}
1286
f0b85051
AG		 1287static void svm_set_vintr(struct vcpu_svm *svm)
1288{
8a05a1b8 1289 set_intercept(svm, INTERCEPT_VINTR);
f0b85051
AG		 1290}
1291
1292static void svm_clear_vintr(struct vcpu_svm *svm)
1293{
8a05a1b8 1294 clr_intercept(svm, INTERCEPT_VINTR);
f0b85051
AG		 1295}
1296
6aa8b732
AK		 1297static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1298{
a2fa3e9f 1299 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 1300
1301 switch (seg) {
1302 case VCPU_SREG_CS: return &save->cs;
1303 case VCPU_SREG_DS: return &save->ds;
1304 case VCPU_SREG_ES: return &save->es;
1305 case VCPU_SREG_FS: return &save->fs;
1306 case VCPU_SREG_GS: return &save->gs;
1307 case VCPU_SREG_SS: return &save->ss;
1308 case VCPU_SREG_TR: return &save->tr;
1309 case VCPU_SREG_LDTR: return &save->ldtr;
1310 }
1311 BUG();
8b6d44c7 1312 return NULL;
6aa8b732
AK		 1313}
1314
1315static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1316{
1317 struct vmcb_seg *s = svm_seg(vcpu, seg);
1318
1319 return s->base;
1320}
1321
1322static void svm_get_segment(struct kvm_vcpu *vcpu,
1323 struct kvm_segment *var, int seg)
1324{
1325 struct vmcb_seg *s = svm_seg(vcpu, seg);
1326
1327 var->base = s->base;
1328 var->limit = s->limit;
1329 var->selector = s->selector;
1330 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1331 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1332 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1333 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1334 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1335 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1336 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1337 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 1338
e0231715
JR		 1339 /*
1340 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1341 * for cross vendor migration purposes by "not present"
1342 */
1343 var->unusable = !var->present || (var->type == 0);
1344
1fbdc7a5
AP		 1345 switch (seg) {
1346 case VCPU_SREG_CS:
1347 /*
1348 * SVM always stores 0 for the 'G' bit in the CS selector in
1349 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1350 * Intel's VMENTRY has a check on the 'G' bit.
1351 */
25022acc 1352 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 1353 break;
1354 case VCPU_SREG_TR:
1355 /*
1356 * Work around a bug where the busy flag in the tr selector
1357 * isn't exposed
1358 */
c0d09828 1359 var->type |= 0x2;
1fbdc7a5
AP		 1360 break;
1361 case VCPU_SREG_DS:
1362 case VCPU_SREG_ES:
1363 case VCPU_SREG_FS:
1364 case VCPU_SREG_GS:
1365 /*
1366 * The accessed bit must always be set in the segment
1367 * descriptor cache, although it can be cleared in the
1368 * descriptor, the cached bit always remains at 1. Since
1369 * Intel has a check on this, set it here to support
1370 * cross-vendor migration.
1371 */
1372 if (!var->unusable)
1373 var->type |= 0x1;
1374 break;
b586eb02 1375 case VCPU_SREG_SS:
e0231715
JR		 1376 /*
1377 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1378 * descriptor is left as 1, although the whole segment has
1379 * been made unusable. Clear it here to pass an Intel VMX
1380 * entry check when cross vendor migrating.
1381 */
1382 if (var->unusable)
1383 var->db = 0;
1384 break;
1fbdc7a5 1385 }
6aa8b732
AK		 1386}
1387
2e4d2653
IE		 1388static int svm_get_cpl(struct kvm_vcpu *vcpu)
1389{
1390 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1391
1392 return save->cpl;
1393}
1394
89a27f4d 1395static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1396{
a2fa3e9f
GH		 1397 struct vcpu_svm *svm = to_svm(vcpu);
1398
89a27f4d
GN		 1399 dt->size = svm->vmcb->save.idtr.limit;
1400 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1401}
1402
89a27f4d 1403static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1404{
a2fa3e9f
GH		 1405 struct vcpu_svm *svm = to_svm(vcpu);
1406
89a27f4d
GN		 1407 svm->vmcb->save.idtr.limit = dt->size;
1408 svm->vmcb->save.idtr.base = dt->address ;
17a703cb 1409 mark_dirty(svm->vmcb, VMCB_DT);
6aa8b732
AK		 1410}
1411
89a27f4d 1412static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1413{
a2fa3e9f
GH		 1414 struct vcpu_svm *svm = to_svm(vcpu);
1415
89a27f4d
GN		 1416 dt->size = svm->vmcb->save.gdtr.limit;
1417 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1418}
1419
89a27f4d 1420static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1421{
a2fa3e9f
GH		 1422 struct vcpu_svm *svm = to_svm(vcpu);
1423
89a27f4d
GN		 1424 svm->vmcb->save.gdtr.limit = dt->size;
1425 svm->vmcb->save.gdtr.base = dt->address ;
17a703cb 1426 mark_dirty(svm->vmcb, VMCB_DT);
6aa8b732
AK		 1427}
1428
e8467fda
AK		 1429static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1430{
1431}
1432
aff48baa
AK		 1433static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1434{
1435}
1436
25c4c276 1437static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1438{
1439}
1440
d225157b
AK		 1441static void update_cr0_intercept(struct vcpu_svm *svm)
1442{
1443 ulong gcr0 = svm->vcpu.arch.cr0;
1444 u64 *hcr0 = &svm->vmcb->save.cr0;
1445
1446 if (!svm->vcpu.fpu_active)
1447 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1448 else
1449 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1450 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1451
dcca1a65 1452 mark_dirty(svm->vmcb, VMCB_CR);
d225157b
AK		 1453
1454 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
4ee546b4
RJ		 1455 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1456 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
d225157b 1457 } else {
4ee546b4
RJ		 1458 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1459 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
d225157b
AK		 1460 }
1461}
1462
6aa8b732
AK		 1463static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1464{
a2fa3e9f
GH		 1465 struct vcpu_svm *svm = to_svm(vcpu);
1466
05b3e0c2 1467#ifdef CONFIG_X86_64
f6801dff 1468 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1469 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1470 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1471 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1472 }
1473
d77c26fc 1474 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1475 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1476 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1477 }
1478 }
1479#endif
ad312c7c 1480 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1481
1482 if (!npt_enabled)
1483 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1484
1485 if (!vcpu->fpu_active)
334df50a 1486 cr0 |= X86_CR0_TS;
709ddebf
JR		 1487 /*
1488 * re-enable caching here because the QEMU bios
1489 * does not do it - this results in some delay at
1490 * reboot
1491 */
1492 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1493 svm->vmcb->save.cr0 = cr0;
dcca1a65 1494 mark_dirty(svm->vmcb, VMCB_CR);
d225157b 1495 update_cr0_intercept(svm);
6aa8b732
AK		 1496}
1497
5e1746d6 1498static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 1499{
6394b649 1500 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1501 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1502
5e1746d6
NHE		 1503 if (cr4 & X86_CR4_VMXE)
1504 return 1;
1505
e5eab0ce 1506 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
f40f6a45 1507 svm_flush_tlb(vcpu);
6394b649 1508
ec077263
JR		 1509 vcpu->arch.cr4 = cr4;
1510 if (!npt_enabled)
1511 cr4 |= X86_CR4_PAE;
6394b649 1512 cr4 |= host_cr4_mce;
ec077263 1513 to_svm(vcpu)->vmcb->save.cr4 = cr4;
dcca1a65 1514 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
5e1746d6 1515 return 0;
6aa8b732
AK		 1516}
1517
1518static void svm_set_segment(struct kvm_vcpu *vcpu,
1519 struct kvm_segment *var, int seg)
1520{
a2fa3e9f 1521 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1522 struct vmcb_seg *s = svm_seg(vcpu, seg);
1523
1524 s->base = var->base;
1525 s->limit = var->limit;
1526 s->selector = var->selector;
1527 if (var->unusable)
1528 s->attrib = 0;
1529 else {
1530 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1531 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1532 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1533 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1534 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1535 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1536 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1537 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1538 }
1539 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1540 svm->vmcb->save.cpl
1541 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1542 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1543
060d0c9a 1544 mark_dirty(svm->vmcb, VMCB_SEG);
6aa8b732
AK		 1545}
1546
44c11430 1547static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1548{
d0bfb940
JK		 1549 struct vcpu_svm *svm = to_svm(vcpu);
1550
18c918c5
JR		 1551 clr_exception_intercept(svm, DB_VECTOR);
1552 clr_exception_intercept(svm, BP_VECTOR);
44c11430 1553
6be7d306 1554 if (svm->nmi_singlestep)
18c918c5 1555 set_exception_intercept(svm, DB_VECTOR);
44c11430 1556
d0bfb940
JK		 1557 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1558 if (vcpu->guest_debug &
1559 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
18c918c5 1560 set_exception_intercept(svm, DB_VECTOR);
d0bfb940 1561 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
18c918c5 1562 set_exception_intercept(svm, BP_VECTOR);
d0bfb940
JK		 1563 } else
1564 vcpu->guest_debug = 0;
44c11430
GN		 1565}
1566
355be0b9 1567static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1568{
44c11430
GN		 1569 struct vcpu_svm *svm = to_svm(vcpu);
1570
ae675ef0
JK		 1571 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1572 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1573 else
1574 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1575
72214b96
JR		 1576 mark_dirty(svm->vmcb, VMCB_DR);
1577
355be0b9 1578 update_db_intercept(vcpu);
6aa8b732
AK		 1579}
1580
0fe1e009 1581static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1582{
0fe1e009
TH		 1583 if (sd->next_asid > sd->max_asid) {
1584 ++sd->asid_generation;
1585 sd->next_asid = 1;
a2fa3e9f 1586 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1587 }
1588
0fe1e009
TH		 1589 svm->asid_generation = sd->asid_generation;
1590 svm->vmcb->control.asid = sd->next_asid++;
d48086d1
JR		 1591
1592 mark_dirty(svm->vmcb, VMCB_ASID);
6aa8b732
AK		 1593}
1594
020df079 1595static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1596{
42dbaa5a 1597 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1598
020df079 1599 svm->vmcb->save.dr7 = value;
72214b96 1600 mark_dirty(svm->vmcb, VMCB_DR);
6aa8b732
AK		 1601}
1602
851ba692 1603static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1604{
631bc487 1605 u64 fault_address = svm->vmcb->control.exit_info_2;
6aa8b732 1606 u32 error_code;
631bc487 1607 int r = 1;
6aa8b732 1608
631bc487
GN		 1609 switch (svm->apf_reason) {
1610 default:
1611 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1612
631bc487
GN		 1613 trace_kvm_page_fault(fault_address, error_code);
1614 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1615 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
dc25e89e
AP		 1616 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1617 svm->vmcb->control.insn_bytes,
1618 svm->vmcb->control.insn_len);
631bc487
GN		 1619 break;
1620 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1621 svm->apf_reason = 0;
1622 local_irq_disable();
1623 kvm_async_pf_task_wait(fault_address);
1624 local_irq_enable();
1625 break;
1626 case KVM_PV_REASON_PAGE_READY:
1627 svm->apf_reason = 0;
1628 local_irq_disable();
1629 kvm_async_pf_task_wake(fault_address);
1630 local_irq_enable();
1631 break;
1632 }
1633 return r;
6aa8b732
AK		 1634}
1635
851ba692 1636static int db_interception(struct vcpu_svm *svm)
d0bfb940 1637{
851ba692
AK		 1638 struct kvm_run *kvm_run = svm->vcpu.run;
1639
d0bfb940 1640 if (!(svm->vcpu.guest_debug &
44c11430 1641 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1642 !svm->nmi_singlestep) {
d0bfb940
JK		 1643 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1644 return 1;
1645 }
44c11430 1646
6be7d306
JK		 1647 if (svm->nmi_singlestep) {
1648 svm->nmi_singlestep = false;
44c11430
GN		 1649 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1650 svm->vmcb->save.rflags &=
1651 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1652 update_db_intercept(&svm->vcpu);
1653 }
1654
1655 if (svm->vcpu.guest_debug &
e0231715 1656 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1657 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1658 kvm_run->debug.arch.pc =
1659 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1660 kvm_run->debug.arch.exception = DB_VECTOR;
1661 return 0;
1662 }
1663
1664 return 1;
d0bfb940
JK		 1665}
1666
851ba692 1667static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1668{
851ba692
AK		 1669 struct kvm_run *kvm_run = svm->vcpu.run;
1670
d0bfb940
JK		 1671 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1672 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1673 kvm_run->debug.arch.exception = BP_VECTOR;
1674 return 0;
1675}
1676
851ba692 1677static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1678{
1679 int er;
1680
51d8b661 1681 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 1682 if (er != EMULATE_DONE)
7ee5d940 1683 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1684 return 1;
1685}
1686
6b52d186 1687static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1688{
6b52d186 1689 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7 1690
18c918c5 1691 clr_exception_intercept(svm, NM_VECTOR);
66a562f7 1692
e756fc62 1693 svm->vcpu.fpu_active = 1;
d225157b 1694 update_cr0_intercept(svm);
6b52d186 1695}
a2fa3e9f 1696
6b52d186
AK		 1697static int nm_interception(struct vcpu_svm *svm)
1698{
1699 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1700 return 1;
7807fa6c
AL		 1701}
1702
67ec6607
JR		 1703static bool is_erratum_383(void)
1704{
1705 int err, i;
1706 u64 value;
1707
1708 if (!erratum_383_found)
1709 return false;
1710
1711 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1712 if (err)
1713 return false;
1714
1715 /* Bit 62 may or may not be set for this mce */
1716 value &= ~(1ULL << 62);
1717
1718 if (value != 0xb600000000010015ULL)
1719 return false;
1720
1721 /* Clear MCi_STATUS registers */
1722 for (i = 0; i < 6; ++i)
1723 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1724
1725 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1726 if (!err) {
1727 u32 low, high;
1728
1729 value &= ~(1ULL << 2);
1730 low = lower_32_bits(value);
1731 high = upper_32_bits(value);
1732
1733 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1734 }
1735
1736 /* Flush tlb to evict multi-match entries */
1737 __flush_tlb_all();
1738
1739 return true;
1740}
1741
fe5913e4 1742static void svm_handle_mce(struct vcpu_svm *svm)
53371b50 1743{
67ec6607
JR		 1744 if (is_erratum_383()) {
1745 /*
1746 * Erratum 383 triggered. Guest state is corrupt so kill the
1747 * guest.
1748 */
1749 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1750
a8eeb04a 1751 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
67ec6607
JR		 1752
1753 return;
1754 }
1755
53371b50
JR		 1756 /*
1757 * On an #MC intercept the MCE handler is not called automatically in
1758 * the host. So do it by hand here.
1759 */
1760 asm volatile (
1761 "int $0x12\n");
1762 /* not sure if we ever come back to this point */
1763
fe5913e4
JR		 1764 return;
1765}
1766
1767static int mc_interception(struct vcpu_svm *svm)
1768{
53371b50
JR		 1769 return 1;
1770}
1771
851ba692 1772static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1773{
851ba692
AK		 1774 struct kvm_run *kvm_run = svm->vcpu.run;
1775
46fe4ddd
JR		 1776 /*
1777 * VMCB is undefined after a SHUTDOWN intercept
1778 * so reinitialize it.
1779 */
a2fa3e9f 1780 clear_page(svm->vmcb);
e6101a96 1781 init_vmcb(svm);
46fe4ddd
JR		 1782
1783 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1784 return 0;
1785}
1786
851ba692 1787static int io_interception(struct vcpu_svm *svm)
6aa8b732 1788{
cf8f70bf 1789 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1790 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1791 int size, in, string;
039576c0 1792 unsigned port;
6aa8b732 1793
e756fc62 1794 ++svm->vcpu.stat.io_exits;
e70669ab 1795 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1796 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
cf8f70bf 1797 if (string || in)
51d8b661 1798 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
cf8f70bf 1799
039576c0
AK		 1800 port = io_info >> 16;
1801 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1802 svm->next_rip = svm->vmcb->control.exit_info_2;
e93f36bc 1803 skip_emulated_instruction(&svm->vcpu);
cf8f70bf
GN		 1804
1805 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 1806}
1807
851ba692 1808static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1809{
1810 return 1;
1811}
1812
851ba692 1813static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1814{
1815 ++svm->vcpu.stat.irq_exits;
1816 return 1;
1817}
1818
851ba692 1819static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1820{
1821 return 1;
1822}
1823
851ba692 1824static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1825{
5fdbf976 1826 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1827 skip_emulated_instruction(&svm->vcpu);
1828 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1829}
1830
851ba692 1831static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1832{
5fdbf976 1833 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1834 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1835 kvm_emulate_hypercall(&svm->vcpu);
1836 return 1;
02e235bc
AK		 1837}
1838
5bd2edc3
JR		 1839static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1840{
1841 struct vcpu_svm *svm = to_svm(vcpu);
1842
1843 return svm->nested.nested_cr3;
1844}
1845
e4e517b4
AK		 1846static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1847{
1848 struct vcpu_svm *svm = to_svm(vcpu);
1849 u64 cr3 = svm->nested.nested_cr3;
1850 u64 pdpte;
1851 int ret;
1852
1853 ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte,
1854 offset_in_page(cr3) + index * 8, 8);
1855 if (ret)
1856 return 0;
1857 return pdpte;
1858}
1859
5bd2edc3
JR		 1860static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1861 unsigned long root)
1862{
1863 struct vcpu_svm *svm = to_svm(vcpu);
1864
1865 svm->vmcb->control.nested_cr3 = root;
b2747166 1866 mark_dirty(svm->vmcb, VMCB_NPT);
f40f6a45 1867 svm_flush_tlb(vcpu);
5bd2edc3
JR		 1868}
1869
6389ee94
AK		 1870static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1871 struct x86_exception *fault)
5bd2edc3
JR		 1872{
1873 struct vcpu_svm *svm = to_svm(vcpu);
1874
1875 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1876 svm->vmcb->control.exit_code_hi = 0;
6389ee94
AK		 1877 svm->vmcb->control.exit_info_1 = fault->error_code;
1878 svm->vmcb->control.exit_info_2 = fault->address;
5bd2edc3
JR		 1879
1880 nested_svm_vmexit(svm);
1881}
1882
4b16184c
JR		 1883static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1884{
1885 int r;
1886
1887 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1888
1889 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1890 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
e4e517b4 1891 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
4b16184c
JR		 1892 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1893 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1894 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1895
1896 return r;
1897}
1898
1899static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1900{
1901 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1902}
1903
c0725420
AG		 1904static int nested_svm_check_permissions(struct vcpu_svm *svm)
1905{
f6801dff 1906 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1907 || !is_paging(&svm->vcpu)) {
1908 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1909 return 1;
1910 }
1911
1912 if (svm->vmcb->save.cpl) {
1913 kvm_inject_gp(&svm->vcpu, 0);
1914 return 1;
1915 }
1916
1917 return 0;
1918}
1919
cf74a78b
AG		 1920static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1921 bool has_error_code, u32 error_code)
1922{
b8e88bc8
JR		 1923 int vmexit;
1924
2030753d 1925 if (!is_guest_mode(&svm->vcpu))
0295ad7d 1926 return 0;
cf74a78b 1927
0295ad7d
JR		 1928 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1929 svm->vmcb->control.exit_code_hi = 0;
1930 svm->vmcb->control.exit_info_1 = error_code;
1931 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1932
b8e88bc8
JR		 1933 vmexit = nested_svm_intercept(svm);
1934 if (vmexit == NESTED_EXIT_DONE)
1935 svm->nested.exit_required = true;
1936
1937 return vmexit;
cf74a78b
AG		 1938}
1939
8fe54654
JR		 1940/* This function returns true if it is save to enable the irq window */
1941static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1942{
2030753d 1943 if (!is_guest_mode(&svm->vcpu))
8fe54654 1944 return true;
cf74a78b 1945
26666957 1946 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1947 return true;
cf74a78b 1948
26666957 1949 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1950 return false;
cf74a78b 1951
a0a07cd2
GN		 1952 /*
1953 * if vmexit was already requested (by intercepted exception
1954 * for instance) do not overwrite it with "external interrupt"
1955 * vmexit.
1956 */
1957 if (svm->nested.exit_required)
1958 return false;
1959
197717d5
JR		 1960 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1961 svm->vmcb->control.exit_info_1 = 0;
1962 svm->vmcb->control.exit_info_2 = 0;
26666957 1963
cd3ff653
JR		 1964 if (svm->nested.intercept & 1ULL) {
1965 /*
1966 * The #vmexit can't be emulated here directly because this
1967 * code path runs with irqs and preemtion disabled. A
1968 * #vmexit emulation might sleep. Only signal request for
1969 * the #vmexit here.
1970 */
1971 svm->nested.exit_required = true;
236649de 1972 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1973 return false;
cf74a78b
AG		 1974 }
1975
8fe54654 1976 return true;
cf74a78b
AG		 1977}
1978
887f500c
JR		 1979/* This function returns true if it is save to enable the nmi window */
1980static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1981{
2030753d 1982 if (!is_guest_mode(&svm->vcpu))
887f500c
JR		 1983 return true;
1984
1985 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1986 return true;
1987
1988 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1989 svm->nested.exit_required = true;
1990
1991 return false;
cf74a78b
AG		 1992}
1993
7597f129 1994static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1995{
1996 struct page *page;
1997
6c3bd3d7
JR		 1998 might_sleep();
1999
34f80cfa 2000 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 2001 if (is_error_page(page))
2002 goto error;
2003
7597f129
JR		 2004 *_page = page;
2005
2006 return kmap(page);
34f80cfa
JR		 2007
2008error:
2009 kvm_release_page_clean(page);
2010 kvm_inject_gp(&svm->vcpu, 0);
2011
2012 return NULL;
2013}
2014
7597f129 2015static void nested_svm_unmap(struct page *page)
34f80cfa 2016{
7597f129 2017 kunmap(page);
34f80cfa
JR		 2018 kvm_release_page_dirty(page);
2019}
34f80cfa 2020
ce2ac085
JR		 2021static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2022{
2023 unsigned port;
2024 u8 val, bit;
2025 u64 gpa;
34f80cfa 2026
ce2ac085
JR		 2027 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2028 return NESTED_EXIT_HOST;
34f80cfa 2029
ce2ac085
JR		 2030 port = svm->vmcb->control.exit_info_1 >> 16;
2031 gpa = svm->nested.vmcb_iopm + (port / 8);
2032 bit = port % 8;
2033 val = 0;
2034
2035 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
2036 val &= (1 << bit);
2037
2038 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
34f80cfa
JR		 2039}
2040
d2477826 2041static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 2042{
0d6b3537
JR		 2043 u32 offset, msr, value;
2044 int write, mask;
4c2161ae 2045
3d62d9aa 2046 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 2047 return NESTED_EXIT_HOST;
3d62d9aa 2048
0d6b3537
JR		 2049 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2050 offset = svm_msrpm_offset(msr);
2051 write = svm->vmcb->control.exit_info_1 & 1;
2052 mask = 1 << ((2 * (msr & 0xf)) + write);
3d62d9aa 2053
0d6b3537
JR		 2054 if (offset == MSR_INVALID)
2055 return NESTED_EXIT_DONE;
4c2161ae 2056
0d6b3537
JR		 2057 /* Offset is in 32 bit units but need in 8 bit units */
2058 offset *= 4;
4c2161ae 2059
0d6b3537
JR		 2060 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
2061 return NESTED_EXIT_DONE;
3d62d9aa 2062
0d6b3537 2063 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
4c2161ae
JR		 2064}
2065
410e4d57 2066static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 2067{
cf74a78b 2068 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 2069
410e4d57
JR		 2070 switch (exit_code) {
2071 case SVM_EXIT_INTR:
2072 case SVM_EXIT_NMI:
ff47a49b 2073 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
410e4d57 2074 return NESTED_EXIT_HOST;
410e4d57 2075 case SVM_EXIT_NPF:
e0231715 2076 /* For now we are always handling NPFs when using them */
410e4d57
JR		 2077 if (npt_enabled)
2078 return NESTED_EXIT_HOST;
2079 break;
410e4d57 2080 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
631bc487
GN		 2081 /* When we're shadowing, trap PFs, but not async PF */
2082 if (!npt_enabled && svm->apf_reason == 0)
410e4d57
JR		 2083 return NESTED_EXIT_HOST;
2084 break;
66a562f7
JR		 2085 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2086 nm_interception(svm);
2087 break;
410e4d57
JR		 2088 default:
2089 break;
cf74a78b
AG		 2090 }
2091
410e4d57
JR		 2092 return NESTED_EXIT_CONTINUE;
2093}
2094
2095/*
2096 * If this function returns true, this #vmexit was already handled
2097 */
b8e88bc8 2098static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 2099{
2100 u32 exit_code = svm->vmcb->control.exit_code;
2101 int vmexit = NESTED_EXIT_HOST;
2102
cf74a78b 2103 switch (exit_code) {
9c4e40b9 2104 case SVM_EXIT_MSR:
3d62d9aa 2105 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 2106 break;
ce2ac085
JR		 2107 case SVM_EXIT_IOIO:
2108 vmexit = nested_svm_intercept_ioio(svm);
2109 break;
4ee546b4
RJ		 2110 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2111 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2112 if (svm->nested.intercept_cr & bit)
410e4d57 2113 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 2114 break;
2115 }
3aed041a
JR		 2116 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2117 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2118 if (svm->nested.intercept_dr & bit)
410e4d57 2119 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 2120 break;
2121 }
2122 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2123 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 2124 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 2125 vmexit = NESTED_EXIT_DONE;
631bc487
GN		 2126 /* async page fault always cause vmexit */
2127 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2128 svm->apf_reason != 0)
2129 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 2130 break;
2131 }
228070b1
JR		 2132 case SVM_EXIT_ERR: {
2133 vmexit = NESTED_EXIT_DONE;
2134 break;
2135 }
cf74a78b
AG		 2136 default: {
2137 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 2138 if (svm->nested.intercept & exit_bits)
410e4d57 2139 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 2140 }
2141 }
2142
b8e88bc8
JR		 2143 return vmexit;
2144}
2145
2146static int nested_svm_exit_handled(struct vcpu_svm *svm)
2147{
2148 int vmexit;
2149
2150 vmexit = nested_svm_intercept(svm);
2151
2152 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 2153 nested_svm_vmexit(svm);
9c4e40b9
JR		 2154
2155 return vmexit;
cf74a78b
AG		 2156}
2157
0460a979
JR		 2158static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2159{
2160 struct vmcb_control_area *dst = &dst_vmcb->control;
2161 struct vmcb_control_area *from = &from_vmcb->control;
2162
4ee546b4 2163 dst->intercept_cr = from->intercept_cr;
3aed041a 2164 dst->intercept_dr = from->intercept_dr;
0460a979
JR		 2165 dst->intercept_exceptions = from->intercept_exceptions;
2166 dst->intercept = from->intercept;
2167 dst->iopm_base_pa = from->iopm_base_pa;
2168 dst->msrpm_base_pa = from->msrpm_base_pa;
2169 dst->tsc_offset = from->tsc_offset;
2170 dst->asid = from->asid;
2171 dst->tlb_ctl = from->tlb_ctl;
2172 dst->int_ctl = from->int_ctl;
2173 dst->int_vector = from->int_vector;
2174 dst->int_state = from->int_state;
2175 dst->exit_code = from->exit_code;
2176 dst->exit_code_hi = from->exit_code_hi;
2177 dst->exit_info_1 = from->exit_info_1;
2178 dst->exit_info_2 = from->exit_info_2;
2179 dst->exit_int_info = from->exit_int_info;
2180 dst->exit_int_info_err = from->exit_int_info_err;
2181 dst->nested_ctl = from->nested_ctl;
2182 dst->event_inj = from->event_inj;
2183 dst->event_inj_err = from->event_inj_err;
2184 dst->nested_cr3 = from->nested_cr3;
2185 dst->lbr_ctl = from->lbr_ctl;
2186}
2187
34f80cfa 2188static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 2189{
34f80cfa 2190 struct vmcb *nested_vmcb;
e6aa9abd 2191 struct vmcb *hsave = svm->nested.hsave;
33740e40 2192 struct vmcb *vmcb = svm->vmcb;
7597f129 2193 struct page *page;
cf74a78b 2194
17897f36
JR		 2195 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2196 vmcb->control.exit_info_1,
2197 vmcb->control.exit_info_2,
2198 vmcb->control.exit_int_info,
e097e5ff
SH		 2199 vmcb->control.exit_int_info_err,
2200 KVM_ISA_SVM);
17897f36 2201
7597f129 2202 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 2203 if (!nested_vmcb)
2204 return 1;
2205
2030753d
JR		 2206 /* Exit Guest-Mode */
2207 leave_guest_mode(&svm->vcpu);
06fc7772
JR		 2208 svm->nested.vmcb = 0;
2209
cf74a78b 2210 /* Give the current vmcb to the guest */
33740e40
JR		 2211 disable_gif(svm);
2212
2213 nested_vmcb->save.es = vmcb->save.es;
2214 nested_vmcb->save.cs = vmcb->save.cs;
2215 nested_vmcb->save.ss = vmcb->save.ss;
2216 nested_vmcb->save.ds = vmcb->save.ds;
2217 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2218 nested_vmcb->save.idtr = vmcb->save.idtr;
3f6a9d16 2219 nested_vmcb->save.efer = svm->vcpu.arch.efer;
cdbbdc12 2220 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
9f8fe504 2221 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
33740e40 2222 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 2223 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
f6e78475 2224 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
33740e40
JR		 2225 nested_vmcb->save.rip = vmcb->save.rip;
2226 nested_vmcb->save.rsp = vmcb->save.rsp;
2227 nested_vmcb->save.rax = vmcb->save.rax;
2228 nested_vmcb->save.dr7 = vmcb->save.dr7;
2229 nested_vmcb->save.dr6 = vmcb->save.dr6;
2230 nested_vmcb->save.cpl = vmcb->save.cpl;
2231
2232 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2233 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2234 nested_vmcb->control.int_state = vmcb->control.int_state;
2235 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2236 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2237 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2238 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2239 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2240 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
7a190667 2241 nested_vmcb->control.next_rip = vmcb->control.next_rip;
8d23c466
AG		 2242
2243 /*
2244 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2245 * to make sure that we do not lose injected events. So check event_inj
2246 * here and copy it to exit_int_info if it is valid.
2247 * Exit_int_info and event_inj can't be both valid because the case
2248 * below only happens on a VMRUN instruction intercept which has
2249 * no valid exit_int_info set.
2250 */
2251 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2252 struct vmcb_control_area *nc = &nested_vmcb->control;
2253
2254 nc->exit_int_info = vmcb->control.event_inj;
2255 nc->exit_int_info_err = vmcb->control.event_inj_err;
2256 }
2257
33740e40
JR		 2258 nested_vmcb->control.tlb_ctl = 0;
2259 nested_vmcb->control.event_inj = 0;
2260 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 2261
2262 /* We always set V_INTR_MASKING and remember the old value in hflags */
2263 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2264 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2265
cf74a78b 2266 /* Restore the original control entries */
0460a979 2267 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 2268
219b65dc
AG		 2269 kvm_clear_exception_queue(&svm->vcpu);
2270 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b 2271
4b16184c
JR		 2272 svm->nested.nested_cr3 = 0;
2273
cf74a78b
AG		 2274 /* Restore selected save entries */
2275 svm->vmcb->save.es = hsave->save.es;
2276 svm->vmcb->save.cs = hsave->save.cs;
2277 svm->vmcb->save.ss = hsave->save.ss;
2278 svm->vmcb->save.ds = hsave->save.ds;
2279 svm->vmcb->save.gdtr = hsave->save.gdtr;
2280 svm->vmcb->save.idtr = hsave->save.idtr;
f6e78475 2281 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
cf74a78b
AG		 2282 svm_set_efer(&svm->vcpu, hsave->save.efer);
2283 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2284 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2285 if (npt_enabled) {
2286 svm->vmcb->save.cr3 = hsave->save.cr3;
2287 svm->vcpu.arch.cr3 = hsave->save.cr3;
2288 } else {
2390218b 2289 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
cf74a78b
AG		 2290 }
2291 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2292 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2293 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2294 svm->vmcb->save.dr7 = 0;
2295 svm->vmcb->save.cpl = 0;
2296 svm->vmcb->control.exit_int_info = 0;
2297
8d28fec4
RJ		 2298 mark_all_dirty(svm->vmcb);
2299
7597f129 2300 nested_svm_unmap(page);
cf74a78b 2301
4b16184c 2302 nested_svm_uninit_mmu_context(&svm->vcpu);
cf74a78b
AG		 2303 kvm_mmu_reset_context(&svm->vcpu);
2304 kvm_mmu_load(&svm->vcpu);
2305
2306 return 0;
2307}
3d6368ef 2308
9738b2c9 2309static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 2310{
323c3d80
JR		 2311 /*
2312 * This function merges the msr permission bitmaps of kvm and the
2313 * nested vmcb. It is omptimized in that it only merges the parts where
2314 * the kvm msr permission bitmap may contain zero bits
2315 */
3d6368ef 2316 int i;
9738b2c9 2317
323c3d80
JR		 2318 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2319 return true;
9738b2c9 2320
323c3d80
JR		 2321 for (i = 0; i < MSRPM_OFFSETS; i++) {
2322 u32 value, p;
2323 u64 offset;
9738b2c9 2324
323c3d80
JR		 2325 if (msrpm_offsets[i] == 0xffffffff)
2326 break;
3d6368ef 2327
0d6b3537
JR		 2328 p = msrpm_offsets[i];
2329 offset = svm->nested.vmcb_msrpm + (p * 4);
323c3d80
JR		 2330
2331 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2332 return false;
2333
2334 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2335 }
3d6368ef 2336
323c3d80 2337 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
9738b2c9
JR		 2338
2339 return true;
3d6368ef
AG		 2340}
2341
52c65a30
JR		 2342static bool nested_vmcb_checks(struct vmcb *vmcb)
2343{
2344 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2345 return false;
2346
dbe77584
JR		 2347 if (vmcb->control.asid == 0)
2348 return false;
2349
4b16184c
JR		 2350 if (vmcb->control.nested_ctl && !npt_enabled)
2351 return false;
2352
52c65a30
JR		 2353 return true;
2354}
2355
9738b2c9 2356static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 2357{
9738b2c9 2358 struct vmcb *nested_vmcb;
e6aa9abd 2359 struct vmcb *hsave = svm->nested.hsave;
defbba56 2360 struct vmcb *vmcb = svm->vmcb;
7597f129 2361 struct page *page;
06fc7772 2362 u64 vmcb_gpa;
3d6368ef 2363
06fc7772 2364 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 2365
7597f129 2366 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 2367 if (!nested_vmcb)
2368 return false;
2369
52c65a30
JR		 2370 if (!nested_vmcb_checks(nested_vmcb)) {
2371 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2372 nested_vmcb->control.exit_code_hi = 0;
2373 nested_vmcb->control.exit_info_1 = 0;
2374 nested_vmcb->control.exit_info_2 = 0;
2375
2376 nested_svm_unmap(page);
2377
2378 return false;
2379 }
2380
b75f4eb3 2381 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
0ac406de
JR		 2382 nested_vmcb->save.rip,
2383 nested_vmcb->control.int_ctl,
2384 nested_vmcb->control.event_inj,
2385 nested_vmcb->control.nested_ctl);
2386
4ee546b4
RJ		 2387 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2388 nested_vmcb->control.intercept_cr >> 16,
2e554e8d
JR		 2389 nested_vmcb->control.intercept_exceptions,
2390 nested_vmcb->control.intercept);
2391
3d6368ef 2392 /* Clear internal status */
219b65dc
AG		 2393 kvm_clear_exception_queue(&svm->vcpu);
2394 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 2395
e0231715
JR		 2396 /*
2397 * Save the old vmcb, so we don't need to pick what we save, but can
2398 * restore everything when a VMEXIT occurs
2399 */
defbba56
JR		 2400 hsave->save.es = vmcb->save.es;
2401 hsave->save.cs = vmcb->save.cs;
2402 hsave->save.ss = vmcb->save.ss;
2403 hsave->save.ds = vmcb->save.ds;
2404 hsave->save.gdtr = vmcb->save.gdtr;
2405 hsave->save.idtr = vmcb->save.idtr;
f6801dff 2406 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 2407 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56 2408 hsave->save.cr4 = svm->vcpu.arch.cr4;
f6e78475 2409 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
b75f4eb3 2410 hsave->save.rip = kvm_rip_read(&svm->vcpu);
defbba56
JR		 2411 hsave->save.rsp = vmcb->save.rsp;
2412 hsave->save.rax = vmcb->save.rax;
2413 if (npt_enabled)
2414 hsave->save.cr3 = vmcb->save.cr3;
2415 else
9f8fe504 2416 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
defbba56 2417
0460a979 2418 copy_vmcb_control_area(hsave, vmcb);
3d6368ef 2419
f6e78475 2420 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3d6368ef
AG		 2421 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2422 else
2423 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2424
4b16184c
JR		 2425 if (nested_vmcb->control.nested_ctl) {
2426 kvm_mmu_unload(&svm->vcpu);
2427 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2428 nested_svm_init_mmu_context(&svm->vcpu);
2429 }
2430
3d6368ef
AG		 2431 /* Load the nested guest state */
2432 svm->vmcb->save.es = nested_vmcb->save.es;
2433 svm->vmcb->save.cs = nested_vmcb->save.cs;
2434 svm->vmcb->save.ss = nested_vmcb->save.ss;
2435 svm->vmcb->save.ds = nested_vmcb->save.ds;
2436 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2437 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
f6e78475 2438 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3d6368ef
AG		 2439 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2440 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2441 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2442 if (npt_enabled) {
2443 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2444 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 2445 } else
2390218b 2446 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 2447
2448 /* Guest paging mode is active - reset mmu */
2449 kvm_mmu_reset_context(&svm->vcpu);
2450
defbba56 2451 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 2452 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2453 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2454 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 2455
3d6368ef
AG		 2456 /* In case we don't even reach vcpu_run, the fields are not updated */
2457 svm->vmcb->save.rax = nested_vmcb->save.rax;
2458 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2459 svm->vmcb->save.rip = nested_vmcb->save.rip;
2460 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2461 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2462 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2463
f7138538 2464 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
ce2ac085 2465 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3d6368ef 2466
aad42c64 2467 /* cache intercepts */
4ee546b4 2468 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
3aed041a 2469 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
aad42c64
JR		 2470 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2471 svm->nested.intercept = nested_vmcb->control.intercept;
2472
f40f6a45 2473 svm_flush_tlb(&svm->vcpu);
3d6368ef 2474 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 2475 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2476 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2477 else
2478 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2479
88ab24ad
JR		 2480 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2481 /* We only want the cr8 intercept bits of the guest */
4ee546b4
RJ		 2482 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2483 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
88ab24ad
JR		 2484 }
2485
0d945bd9 2486 /* We don't want to see VMMCALLs from a nested guest */
8a05a1b8 2487 clr_intercept(svm, INTERCEPT_VMMCALL);
0d945bd9 2488
88ab24ad 2489 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2490 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2491 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2492 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2493 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2494 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2495
7597f129 2496 nested_svm_unmap(page);
9738b2c9 2497
2030753d
JR		 2498 /* Enter Guest-Mode */
2499 enter_guest_mode(&svm->vcpu);
2500
384c6368
JR		 2501 /*
2502 * Merge guest and host intercepts - must be called with vcpu in
2503 * guest-mode to take affect here
2504 */
2505 recalc_intercepts(svm);
2506
06fc7772 2507 svm->nested.vmcb = vmcb_gpa;
9738b2c9 2508
2af9194d 2509 enable_gif(svm);
3d6368ef 2510
8d28fec4
RJ		 2511 mark_all_dirty(svm->vmcb);
2512
9738b2c9 2513 return true;
3d6368ef
AG		 2514}
2515
9966bf68 2516static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2517{
2518 to_vmcb->save.fs = from_vmcb->save.fs;
2519 to_vmcb->save.gs = from_vmcb->save.gs;
2520 to_vmcb->save.tr = from_vmcb->save.tr;
2521 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2522 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2523 to_vmcb->save.star = from_vmcb->save.star;
2524 to_vmcb->save.lstar = from_vmcb->save.lstar;
2525 to_vmcb->save.cstar = from_vmcb->save.cstar;
2526 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2527 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2528 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2529 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2530}
2531
851ba692 2532static int vmload_interception(struct vcpu_svm *svm)
5542675b 2533{
9966bf68 2534 struct vmcb *nested_vmcb;
7597f129 2535 struct page *page;
9966bf68 2536
5542675b
AG		 2537 if (nested_svm_check_permissions(svm))
2538 return 1;
2539
7597f129 2540 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2541 if (!nested_vmcb)
2542 return 1;
2543
e3e9ed3d
JR		 2544 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2545 skip_emulated_instruction(&svm->vcpu);
2546
9966bf68 2547 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2548 nested_svm_unmap(page);
5542675b
AG		 2549
2550 return 1;
2551}
2552
851ba692 2553static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2554{
9966bf68 2555 struct vmcb *nested_vmcb;
7597f129 2556 struct page *page;
9966bf68 2557
5542675b
AG		 2558 if (nested_svm_check_permissions(svm))
2559 return 1;
2560
7597f129 2561 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2562 if (!nested_vmcb)
2563 return 1;
2564
e3e9ed3d
JR		 2565 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2566 skip_emulated_instruction(&svm->vcpu);
2567
9966bf68 2568 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2569 nested_svm_unmap(page);
5542675b
AG		 2570
2571 return 1;
2572}
2573
851ba692 2574static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2575{
3d6368ef
AG		 2576 if (nested_svm_check_permissions(svm))
2577 return 1;
2578
b75f4eb3
RJ		 2579 /* Save rip after vmrun instruction */
2580 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3d6368ef 2581
9738b2c9 2582 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2583 return 1;
2584
9738b2c9 2585 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2586 goto failed;
2587
2588 return 1;
2589
2590failed:
2591
2592 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2593 svm->vmcb->control.exit_code_hi = 0;
2594 svm->vmcb->control.exit_info_1 = 0;
2595 svm->vmcb->control.exit_info_2 = 0;
2596
2597 nested_svm_vmexit(svm);
3d6368ef
AG		 2598
2599 return 1;
2600}
2601
851ba692 2602static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2603{
2604 if (nested_svm_check_permissions(svm))
2605 return 1;
2606
2607 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2608 skip_emulated_instruction(&svm->vcpu);
3842d135 2609 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
1371d904 2610
2af9194d 2611 enable_gif(svm);
1371d904
AG		 2612
2613 return 1;
2614}
2615
851ba692 2616static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2617{
2618 if (nested_svm_check_permissions(svm))
2619 return 1;
2620
2621 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2622 skip_emulated_instruction(&svm->vcpu);
2623
2af9194d 2624 disable_gif(svm);
1371d904
AG		 2625
2626 /* After a CLGI no interrupts should come */
2627 svm_clear_vintr(svm);
2628 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2629
decdbf6a
JR		 2630 mark_dirty(svm->vmcb, VMCB_INTR);
2631
1371d904
AG		 2632 return 1;
2633}
2634
851ba692 2635static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2636{
2637 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2638
ec1ff790
JR		 2639 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2640 vcpu->arch.regs[VCPU_REGS_RAX]);
2641
ff092385
AG		 2642 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2643 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2644
2645 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2646 skip_emulated_instruction(&svm->vcpu);
2647 return 1;
2648}
2649
532a46b9
JR		 2650static int skinit_interception(struct vcpu_svm *svm)
2651{
2652 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2653
2654 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2655 return 1;
2656}
2657
81dd35d4
JR		 2658static int xsetbv_interception(struct vcpu_svm *svm)
2659{
2660 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2661 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2662
2663 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2664 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2665 skip_emulated_instruction(&svm->vcpu);
2666 }
2667
2668 return 1;
2669}
2670
851ba692 2671static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2672{
7ee5d940 2673 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2674 return 1;
2675}
2676
851ba692 2677static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2678{
37817f29 2679 u16 tss_selector;
64a7ec06
GN		 2680 int reason;
2681 int int_type = svm->vmcb->control.exit_int_info &
2682 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2683 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2684 uint32_t type =
2685 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2686 uint32_t idt_v =
2687 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2688 bool has_error_code = false;
2689 u32 error_code = 0;
37817f29
IE		 2690
2691 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2692
37817f29
IE		 2693 if (svm->vmcb->control.exit_info_2 &
2694 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2695 reason = TASK_SWITCH_IRET;
2696 else if (svm->vmcb->control.exit_info_2 &
2697 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2698 reason = TASK_SWITCH_JMP;
fe8e7f83 2699 else if (idt_v)
64a7ec06
GN		 2700 reason = TASK_SWITCH_GATE;
2701 else
2702 reason = TASK_SWITCH_CALL;
2703
fe8e7f83
GN		 2704 if (reason == TASK_SWITCH_GATE) {
2705 switch (type) {
2706 case SVM_EXITINTINFO_TYPE_NMI:
2707 svm->vcpu.arch.nmi_injected = false;
2708 break;
2709 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2710 if (svm->vmcb->control.exit_info_2 &
2711 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2712 has_error_code = true;
2713 error_code =
2714 (u32)svm->vmcb->control.exit_info_2;
2715 }
fe8e7f83
GN		 2716 kvm_clear_exception_queue(&svm->vcpu);
2717 break;
2718 case SVM_EXITINTINFO_TYPE_INTR:
2719 kvm_clear_interrupt_queue(&svm->vcpu);
2720 break;
2721 default:
2722 break;
2723 }
2724 }
64a7ec06 2725
8317c298
GN		 2726 if (reason != TASK_SWITCH_GATE ||
2727 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2728 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2729 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2730 skip_emulated_instruction(&svm->vcpu);
64a7ec06 2731
acb54517
GN		 2732 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2733 has_error_code, error_code) == EMULATE_FAIL) {
2734 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2735 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2736 svm->vcpu.run->internal.ndata = 0;
2737 return 0;
2738 }
2739 return 1;
6aa8b732
AK		 2740}
2741
851ba692 2742static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2743{
5fdbf976 2744 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2745 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2746 return 1;
6aa8b732
AK		 2747}
2748
851ba692 2749static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2750{
2751 ++svm->vcpu.stat.nmi_window_exits;
8a05a1b8 2752 clr_intercept(svm, INTERCEPT_IRET);
44c11430 2753 svm->vcpu.arch.hflags |= HF_IRET_MASK;
bd3d1ec3 2754 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
95ba8273
GN		 2755 return 1;
2756}
2757
851ba692 2758static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2759{
df4f3108
AP		 2760 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2761 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2762
2763 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2764 skip_emulated_instruction(&svm->vcpu);
2765 return 1;
a7052897
MT		 2766}
2767
851ba692 2768static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2769{
51d8b661 2770 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
6aa8b732
AK		 2771}
2772
628afd2a
JR		 2773bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val)
2774{
2775 unsigned long cr0 = svm->vcpu.arch.cr0;
2776 bool ret = false;
2777 u64 intercept;
2778
2779 intercept = svm->nested.intercept;
2780
2781 if (!is_guest_mode(&svm->vcpu) ||
2782 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2783 return false;
2784
2785 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2786 val &= ~SVM_CR0_SELECTIVE_MASK;
2787
2788 if (cr0 ^ val) {
2789 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2790 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2791 }
2792
2793 return ret;
2794}
2795
7ff76d58
AP		 2796#define CR_VALID (1ULL << 63)
2797
2798static int cr_interception(struct vcpu_svm *svm)
2799{
2800 int reg, cr;
2801 unsigned long val;
2802 int err;
2803
2804 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2805 return emulate_on_interception(svm);
2806
2807 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2808 return emulate_on_interception(svm);
2809
2810 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2811 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2812
2813 err = 0;
2814 if (cr >= 16) { /* mov to cr */
2815 cr -= 16;
2816 val = kvm_register_read(&svm->vcpu, reg);
2817 switch (cr) {
2818 case 0:
628afd2a
JR		 2819 if (!check_selective_cr0_intercepted(svm, val))
2820 err = kvm_set_cr0(&svm->vcpu, val);
977b2d03
JR		 2821 else
2822 return 1;
2823
7ff76d58
AP		 2824 break;
2825 case 3:
2826 err = kvm_set_cr3(&svm->vcpu, val);
2827 break;
2828 case 4:
2829 err = kvm_set_cr4(&svm->vcpu, val);
2830 break;
2831 case 8:
2832 err = kvm_set_cr8(&svm->vcpu, val);
2833 break;
2834 default:
2835 WARN(1, "unhandled write to CR%d", cr);
2836 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2837 return 1;
2838 }
2839 } else { /* mov from cr */
2840 switch (cr) {
2841 case 0:
2842 val = kvm_read_cr0(&svm->vcpu);
2843 break;
2844 case 2:
2845 val = svm->vcpu.arch.cr2;
2846 break;
2847 case 3:
9f8fe504 2848 val = kvm_read_cr3(&svm->vcpu);
7ff76d58
AP		 2849 break;
2850 case 4:
2851 val = kvm_read_cr4(&svm->vcpu);
2852 break;
2853 case 8:
2854 val = kvm_get_cr8(&svm->vcpu);
2855 break;
2856 default:
2857 WARN(1, "unhandled read from CR%d", cr);
2858 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2859 return 1;
2860 }
2861 kvm_register_write(&svm->vcpu, reg, val);
2862 }
2863 kvm_complete_insn_gp(&svm->vcpu, err);
2864
2865 return 1;
2866}
2867
cae3797a
AP		 2868static int dr_interception(struct vcpu_svm *svm)
2869{
2870 int reg, dr;
2871 unsigned long val;
2872 int err;
2873
2874 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2875 return emulate_on_interception(svm);
2876
2877 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2878 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2879
2880 if (dr >= 16) { /* mov to DRn */
2881 val = kvm_register_read(&svm->vcpu, reg);
2882 kvm_set_dr(&svm->vcpu, dr - 16, val);
2883 } else {
2884 err = kvm_get_dr(&svm->vcpu, dr, &val);
2885 if (!err)
2886 kvm_register_write(&svm->vcpu, reg, val);
2887 }
2888
2c46d2ae
JR		 2889 skip_emulated_instruction(&svm->vcpu);
2890
cae3797a
AP		 2891 return 1;
2892}
2893
851ba692 2894static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2895{
851ba692 2896 struct kvm_run *kvm_run = svm->vcpu.run;
eea1cff9 2897 int r;
851ba692 2898
0a5fff19
GN		 2899 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2900 /* instruction emulation calls kvm_set_cr8() */
7ff76d58 2901 r = cr_interception(svm);
95ba8273 2902 if (irqchip_in_kernel(svm->vcpu.kvm)) {
4ee546b4 2903 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
7ff76d58 2904 return r;
95ba8273 2905 }
0a5fff19 2906 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
7ff76d58 2907 return r;
1d075434
JR		 2908 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2909 return 0;
2910}
2911
d5c1785d
NHE		 2912u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu)
2913{
2914 struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
2915 return vmcb->control.tsc_offset +
2916 svm_scale_tsc(vcpu, native_read_tsc());
2917}
2918
6aa8b732
AK		 2919static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2920{
a2fa3e9f
GH		 2921 struct vcpu_svm *svm = to_svm(vcpu);
2922
6aa8b732 2923 switch (ecx) {
af24a4e4 2924 case MSR_IA32_TSC: {
45133eca 2925 *data = svm->vmcb->control.tsc_offset +
fbc0db76
JR		 2926 svm_scale_tsc(vcpu, native_read_tsc());
2927
6aa8b732
AK		 2928 break;
2929 }
8c06585d 2930 case MSR_STAR:
a2fa3e9f 2931 *data = svm->vmcb->save.star;
6aa8b732 2932 break;
0e859cac 2933#ifdef CONFIG_X86_64
6aa8b732 2934 case MSR_LSTAR:
a2fa3e9f 2935 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2936 break;
2937 case MSR_CSTAR:
a2fa3e9f 2938 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2939 break;
2940 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2941 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2942 break;
2943 case MSR_SYSCALL_MASK:
a2fa3e9f 2944 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2945 break;
2946#endif
2947 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2948 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2949 break;
2950 case MSR_IA32_SYSENTER_EIP:
017cb99e 2951 *data = svm->sysenter_eip;
6aa8b732
AK		 2952 break;
2953 case MSR_IA32_SYSENTER_ESP:
017cb99e 2954 *data = svm->sysenter_esp;
6aa8b732 2955 break;
e0231715
JR		 2956 /*
2957 * Nobody will change the following 5 values in the VMCB so we can
2958 * safely return them on rdmsr. They will always be 0 until LBRV is
2959 * implemented.
2960 */
a2938c80
JR		 2961 case MSR_IA32_DEBUGCTLMSR:
2962 *data = svm->vmcb->save.dbgctl;
2963 break;
2964 case MSR_IA32_LASTBRANCHFROMIP:
2965 *data = svm->vmcb->save.br_from;
2966 break;
2967 case MSR_IA32_LASTBRANCHTOIP:
2968 *data = svm->vmcb->save.br_to;
2969 break;
2970 case MSR_IA32_LASTINTFROMIP:
2971 *data = svm->vmcb->save.last_excp_from;
2972 break;
2973 case MSR_IA32_LASTINTTOIP:
2974 *data = svm->vmcb->save.last_excp_to;
2975 break;
b286d5d8 2976 case MSR_VM_HSAVE_PA:
e6aa9abd 2977 *data = svm->nested.hsave_msr;
b286d5d8 2978 break;
eb6f302e 2979 case MSR_VM_CR:
4a810181 2980 *data = svm->nested.vm_cr_msr;
eb6f302e 2981 break;
c8a73f18
AG		 2982 case MSR_IA32_UCODE_REV:
2983 *data = 0x01000065;
2984 break;
6aa8b732 2985 default:
3bab1f5d 2986 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2987 }
2988 return 0;
2989}
2990
851ba692 2991static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2992{
ad312c7c 2993 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2994 u64 data;
2995
59200273
AK		 2996 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2997 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2998 kvm_inject_gp(&svm->vcpu, 0);
59200273 2999 } else {
229456fc 3000 trace_kvm_msr_read(ecx, data);
af9ca2d7 3001
5fdbf976 3002 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 3003 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 3004 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 3005 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 3006 }
3007 return 1;
3008}
3009
4a810181
JR		 3010static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3011{
3012 struct vcpu_svm *svm = to_svm(vcpu);
3013 int svm_dis, chg_mask;
3014
3015 if (data & ~SVM_VM_CR_VALID_MASK)
3016 return 1;
3017
3018 chg_mask = SVM_VM_CR_VALID_MASK;
3019
3020 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3021 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3022
3023 svm->nested.vm_cr_msr &= ~chg_mask;
3024 svm->nested.vm_cr_msr |= (data & chg_mask);
3025
3026 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3027
3028 /* check for svm_disable while efer.svme is set */
3029 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3030 return 1;
3031
3032 return 0;
3033}
3034
6aa8b732
AK		 3035static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
3036{
a2fa3e9f
GH		 3037 struct vcpu_svm *svm = to_svm(vcpu);
3038
6aa8b732 3039 switch (ecx) {
f4e1b3c8 3040 case MSR_IA32_TSC:
99e3e30a 3041 kvm_write_tsc(vcpu, data);
6aa8b732 3042 break;
8c06585d 3043 case MSR_STAR:
a2fa3e9f 3044 svm->vmcb->save.star = data;
6aa8b732 3045 break;
49b14f24 3046#ifdef CONFIG_X86_64
6aa8b732 3047 case MSR_LSTAR:
a2fa3e9f 3048 svm->vmcb->save.lstar = data;
6aa8b732
AK		 3049 break;
3050 case MSR_CSTAR:
a2fa3e9f 3051 svm->vmcb->save.cstar = data;
6aa8b732
AK		 3052 break;
3053 case MSR_KERNEL_GS_BASE:
a2fa3e9f 3054 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 3055 break;
3056 case MSR_SYSCALL_MASK:
a2fa3e9f 3057 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 3058 break;
3059#endif
3060 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 3061 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 3062 break;
3063 case MSR_IA32_SYSENTER_EIP:
017cb99e 3064 svm->sysenter_eip = data;
a2fa3e9f 3065 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 3066 break;
3067 case MSR_IA32_SYSENTER_ESP:
017cb99e 3068 svm->sysenter_esp = data;
a2fa3e9f 3069 svm->vmcb->save.sysenter_esp = data;
6aa8b732 3070 break;
a2938c80 3071 case MSR_IA32_DEBUGCTLMSR:
2a6b20b8 3072 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
24e09cbf 3073 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 3074 __func__, data);
24e09cbf
JR		 3075 break;
3076 }
3077 if (data & DEBUGCTL_RESERVED_BITS)
3078 return 1;
3079
3080 svm->vmcb->save.dbgctl = data;
b53ba3f9 3081 mark_dirty(svm->vmcb, VMCB_LBR);
24e09cbf
JR		 3082 if (data & (1ULL<<0))
3083 svm_enable_lbrv(svm);
3084 else
3085 svm_disable_lbrv(svm);
a2938c80 3086 break;
b286d5d8 3087 case MSR_VM_HSAVE_PA:
e6aa9abd 3088 svm->nested.hsave_msr = data;
62b9abaa 3089 break;
3c5d0a44 3090 case MSR_VM_CR:
4a810181 3091 return svm_set_vm_cr(vcpu, data);
3c5d0a44 3092 case MSR_VM_IGNNE:
3c5d0a44
AG		 3093 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3094 break;
6aa8b732 3095 default:
3bab1f5d 3096 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 3097 }
3098 return 0;
3099}
3100
851ba692 3101static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 3102{
ad312c7c 3103 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 3104 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 3105 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 3106
af9ca2d7 3107
5fdbf976 3108 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 3109 if (svm_set_msr(&svm->vcpu, ecx, data)) {
3110 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3111 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 3112 } else {
3113 trace_kvm_msr_write(ecx, data);
e756fc62 3114 skip_emulated_instruction(&svm->vcpu);
59200273 3115 }
6aa8b732
AK		 3116 return 1;
3117}
3118
851ba692 3119static int msr_interception(struct vcpu_svm *svm)
6aa8b732 3120{
e756fc62 3121 if (svm->vmcb->control.exit_info_1)
851ba692 3122 return wrmsr_interception(svm);
6aa8b732 3123 else
851ba692 3124 return rdmsr_interception(svm);
6aa8b732
AK		 3125}
3126
851ba692 3127static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 3128{
851ba692
AK		 3129 struct kvm_run *kvm_run = svm->vcpu.run;
3130
3842d135 3131 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
f0b85051 3132 svm_clear_vintr(svm);
85f455f7 3133 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
decdbf6a 3134 mark_dirty(svm->vmcb, VMCB_INTR);
c1150d8c
DL		 3135 /*
3136 * If the user space waits to inject interrupts, exit as soon as
3137 * possible
3138 */
8061823a
GN		 3139 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3140 kvm_run->request_interrupt_window &&
3141 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 3142 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 3143 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3144 return 0;
3145 }
3146
3147 return 1;
3148}
3149
565d0998
ML		 3150static int pause_interception(struct vcpu_svm *svm)
3151{
3152 kvm_vcpu_on_spin(&(svm->vcpu));
3153 return 1;
3154}
3155
851ba692 3156static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
7ff76d58
AP		 3157 [SVM_EXIT_READ_CR0] = cr_interception,
3158 [SVM_EXIT_READ_CR3] = cr_interception,
3159 [SVM_EXIT_READ_CR4] = cr_interception,
3160 [SVM_EXIT_READ_CR8] = cr_interception,
d225157b 3161 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
628afd2a 3162 [SVM_EXIT_WRITE_CR0] = cr_interception,
7ff76d58
AP		 3163 [SVM_EXIT_WRITE_CR3] = cr_interception,
3164 [SVM_EXIT_WRITE_CR4] = cr_interception,
e0231715 3165 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
cae3797a
AP		 3166 [SVM_EXIT_READ_DR0] = dr_interception,
3167 [SVM_EXIT_READ_DR1] = dr_interception,
3168 [SVM_EXIT_READ_DR2] = dr_interception,
3169 [SVM_EXIT_READ_DR3] = dr_interception,
3170 [SVM_EXIT_READ_DR4] = dr_interception,
3171 [SVM_EXIT_READ_DR5] = dr_interception,
3172 [SVM_EXIT_READ_DR6] = dr_interception,
3173 [SVM_EXIT_READ_DR7] = dr_interception,
3174 [SVM_EXIT_WRITE_DR0] = dr_interception,
3175 [SVM_EXIT_WRITE_DR1] = dr_interception,
3176 [SVM_EXIT_WRITE_DR2] = dr_interception,
3177 [SVM_EXIT_WRITE_DR3] = dr_interception,
3178 [SVM_EXIT_WRITE_DR4] = dr_interception,
3179 [SVM_EXIT_WRITE_DR5] = dr_interception,
3180 [SVM_EXIT_WRITE_DR6] = dr_interception,
3181 [SVM_EXIT_WRITE_DR7] = dr_interception,
d0bfb940
JK		 3182 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3183 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 3184 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 3185 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3186 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3187 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3188 [SVM_EXIT_INTR] = intr_interception,
c47f098d 3189 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 3190 [SVM_EXIT_SMI] = nop_on_interception,
3191 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 3192 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 3193 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 3194 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 3195 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 3196 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 3197 [SVM_EXIT_HLT] = halt_interception,
a7052897 3198 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 3199 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 3200 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 3201 [SVM_EXIT_MSR] = msr_interception,
3202 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 3203 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 3204 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 3205 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 3206 [SVM_EXIT_VMLOAD] = vmload_interception,
3207 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 3208 [SVM_EXIT_STGI] = stgi_interception,
3209 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 3210 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 3211 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 3212 [SVM_EXIT_MONITOR] = invalid_op_interception,
3213 [SVM_EXIT_MWAIT] = invalid_op_interception,
81dd35d4 3214 [SVM_EXIT_XSETBV] = xsetbv_interception,
709ddebf 3215 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 3216};
3217
ae8cc059 3218static void dump_vmcb(struct kvm_vcpu *vcpu)
3f10c846
JR		 3219{
3220 struct vcpu_svm *svm = to_svm(vcpu);
3221 struct vmcb_control_area *control = &svm->vmcb->control;
3222 struct vmcb_save_area *save = &svm->vmcb->save;
3223
3224 pr_err("VMCB Control Area:\n");
ae8cc059
JP		 3225 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3226 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3227 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3228 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3229 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3230 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3231 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3232 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3233 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3234 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3235 pr_err("%-20s%d\n", "asid:", control->asid);
3236 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3237 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3238 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3239 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3240 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3241 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3242 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3243 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3244 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3245 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3246 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3247 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3248 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3249 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3250 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3f10c846 3251 pr_err("VMCB State Save Area:\n");
ae8cc059
JP		 3252 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3253 "es:",
3254 save->es.selector, save->es.attrib,
3255 save->es.limit, save->es.base);
3256 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3257 "cs:",
3258 save->cs.selector, save->cs.attrib,
3259 save->cs.limit, save->cs.base);
3260 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3261 "ss:",
3262 save->ss.selector, save->ss.attrib,
3263 save->ss.limit, save->ss.base);
3264 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3265 "ds:",
3266 save->ds.selector, save->ds.attrib,
3267 save->ds.limit, save->ds.base);
3268 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3269 "fs:",
3270 save->fs.selector, save->fs.attrib,
3271 save->fs.limit, save->fs.base);
3272 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3273 "gs:",
3274 save->gs.selector, save->gs.attrib,
3275 save->gs.limit, save->gs.base);
3276 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3277 "gdtr:",
3278 save->gdtr.selector, save->gdtr.attrib,
3279 save->gdtr.limit, save->gdtr.base);
3280 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3281 "ldtr:",
3282 save->ldtr.selector, save->ldtr.attrib,
3283 save->ldtr.limit, save->ldtr.base);
3284 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3285 "idtr:",
3286 save->idtr.selector, save->idtr.attrib,
3287 save->idtr.limit, save->idtr.base);
3288 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3289 "tr:",
3290 save->tr.selector, save->tr.attrib,
3291 save->tr.limit, save->tr.base);
3f10c846
JR		 3292 pr_err("cpl: %d efer: %016llx\n",
3293 save->cpl, save->efer);
ae8cc059
JP		 3294 pr_err("%-15s %016llx %-13s %016llx\n",
3295 "cr0:", save->cr0, "cr2:", save->cr2);
3296 pr_err("%-15s %016llx %-13s %016llx\n",
3297 "cr3:", save->cr3, "cr4:", save->cr4);
3298 pr_err("%-15s %016llx %-13s %016llx\n",
3299 "dr6:", save->dr6, "dr7:", save->dr7);
3300 pr_err("%-15s %016llx %-13s %016llx\n",
3301 "rip:", save->rip, "rflags:", save->rflags);
3302 pr_err("%-15s %016llx %-13s %016llx\n",
3303 "rsp:", save->rsp, "rax:", save->rax);
3304 pr_err("%-15s %016llx %-13s %016llx\n",
3305 "star:", save->star, "lstar:", save->lstar);
3306 pr_err("%-15s %016llx %-13s %016llx\n",
3307 "cstar:", save->cstar, "sfmask:", save->sfmask);
3308 pr_err("%-15s %016llx %-13s %016llx\n",
3309 "kernel_gs_base:", save->kernel_gs_base,
3310 "sysenter_cs:", save->sysenter_cs);
3311 pr_err("%-15s %016llx %-13s %016llx\n",
3312 "sysenter_esp:", save->sysenter_esp,
3313 "sysenter_eip:", save->sysenter_eip);
3314 pr_err("%-15s %016llx %-13s %016llx\n",
3315 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3316 pr_err("%-15s %016llx %-13s %016llx\n",
3317 "br_from:", save->br_from, "br_to:", save->br_to);
3318 pr_err("%-15s %016llx %-13s %016llx\n",
3319 "excp_from:", save->last_excp_from,
3320 "excp_to:", save->last_excp_to);
3f10c846
JR		 3321}
3322
586f9607
AK		 3323static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3324{
3325 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3326
3327 *info1 = control->exit_info_1;
3328 *info2 = control->exit_info_2;
3329}
3330
851ba692 3331static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3332{
04d2cc77 3333 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 3334 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 3335 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 3336
4ee546b4 3337 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
2be4fc7a
JR		 3338 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3339 if (npt_enabled)
3340 vcpu->arch.cr3 = svm->vmcb->save.cr3;
af9ca2d7 3341
cd3ff653
JR		 3342 if (unlikely(svm->nested.exit_required)) {
3343 nested_svm_vmexit(svm);
3344 svm->nested.exit_required = false;
3345
3346 return 1;
3347 }
3348
2030753d 3349 if (is_guest_mode(vcpu)) {
410e4d57
JR		 3350 int vmexit;
3351
d8cabddf
JR		 3352 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3353 svm->vmcb->control.exit_info_1,
3354 svm->vmcb->control.exit_info_2,
3355 svm->vmcb->control.exit_int_info,
e097e5ff
SH		 3356 svm->vmcb->control.exit_int_info_err,
3357 KVM_ISA_SVM);
d8cabddf 3358
410e4d57
JR		 3359 vmexit = nested_svm_exit_special(svm);
3360
3361 if (vmexit == NESTED_EXIT_CONTINUE)
3362 vmexit = nested_svm_exit_handled(svm);
3363
3364 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 3365 return 1;
cf74a78b
AG		 3366 }
3367
a5c3832d
JR		 3368 svm_complete_interrupts(svm);
3369
04d2cc77
AK		 3370 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3371 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3372 kvm_run->fail_entry.hardware_entry_failure_reason
3373 = svm->vmcb->control.exit_code;
3f10c846
JR		 3374 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3375 dump_vmcb(vcpu);
04d2cc77
AK		 3376 return 0;
3377 }
3378
a2fa3e9f 3379 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 3380 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
55c5e464
JR		 3381 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3382 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
6aa8b732
AK		 3383 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3384 "exit_code 0x%x\n",
b8688d51 3385 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 3386 exit_code);
3387
9d8f549d 3388 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 3389 || !svm_exit_handlers[exit_code]) {
6aa8b732 3390 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 3391 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 3392 return 0;
3393 }
3394
851ba692 3395 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 3396}
3397
3398static void reload_tss(struct kvm_vcpu *vcpu)
3399{
3400 int cpu = raw_smp_processor_id();
3401
0fe1e009
TH		 3402 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3403 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 3404 load_TR_desc();
3405}
3406
e756fc62 3407static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 3408{
3409 int cpu = raw_smp_processor_id();
3410
0fe1e009 3411 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 3412
4b656b12 3413 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 3414 if (svm->asid_generation != sd->asid_generation)
3415 new_asid(svm, sd);
6aa8b732
AK		 3416}
3417
95ba8273
GN		 3418static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3419{
3420 struct vcpu_svm *svm = to_svm(vcpu);
3421
3422 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3423 vcpu->arch.hflags |= HF_NMI_MASK;
8a05a1b8 3424 set_intercept(svm, INTERCEPT_IRET);
95ba8273
GN		 3425 ++vcpu->stat.nmi_injections;
3426}
6aa8b732 3427
85f455f7 3428static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 3429{
3430 struct vmcb_control_area *control;
3431
e756fc62 3432 control = &svm->vmcb->control;
85f455f7 3433 control->int_vector = irq;
6aa8b732
AK		 3434 control->int_ctl &= ~V_INTR_PRIO_MASK;
3435 control->int_ctl |= V_IRQ_MASK |
3436 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
decdbf6a 3437 mark_dirty(svm->vmcb, VMCB_INTR);
6aa8b732
AK		 3438}
3439
66fd3f7f 3440static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 3441{
3442 struct vcpu_svm *svm = to_svm(vcpu);
3443
2af9194d 3444 BUG_ON(!(gif_set(svm)));
cf74a78b 3445
9fb2d2b4
GN		 3446 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3447 ++vcpu->stat.irq_injections;
3448
219b65dc
AG		 3449 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3450 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 3451}
3452
95ba8273 3453static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 3454{
3455 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 3456
2030753d 3457 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
88ab24ad
JR		 3458 return;
3459
95ba8273 3460 if (irr == -1)
aaacfc9a
JR		 3461 return;
3462
95ba8273 3463 if (tpr >= irr)
4ee546b4 3464 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
95ba8273 3465}
aaacfc9a 3466
95ba8273
GN		 3467static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3468{
3469 struct vcpu_svm *svm = to_svm(vcpu);
3470 struct vmcb *vmcb = svm->vmcb;
924584cc
JR		 3471 int ret;
3472 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3473 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3474 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3475
3476 return ret;
aaacfc9a
JR		 3477}
3478
3cfc3092
JK		 3479static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3480{
3481 struct vcpu_svm *svm = to_svm(vcpu);
3482
3483 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3484}
3485
3486static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3487{
3488 struct vcpu_svm *svm = to_svm(vcpu);
3489
3490 if (masked) {
3491 svm->vcpu.arch.hflags |= HF_NMI_MASK;
8a05a1b8 3492 set_intercept(svm, INTERCEPT_IRET);
3cfc3092
JK		 3493 } else {
3494 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
8a05a1b8 3495 clr_intercept(svm, INTERCEPT_IRET);
3cfc3092
JK		 3496 }
3497}
3498
78646121
GN		 3499static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3500{
3501 struct vcpu_svm *svm = to_svm(vcpu);
3502 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 3503 int ret;
3504
3505 if (!gif_set(svm) ||
3506 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3507 return 0;
3508
f6e78475 3509 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
7fcdb510 3510
2030753d 3511 if (is_guest_mode(vcpu))
7fcdb510
JR		 3512 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3513
3514 return ret;
78646121
GN		 3515}
3516
9222be18 3517static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 3518{
219b65dc 3519 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 3520
e0231715
JR		 3521 /*
3522 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3523 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3524 * get that intercept, this function will be called again though and
3525 * we'll get the vintr intercept.
3526 */
8fe54654 3527 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 3528 svm_set_vintr(svm);
3529 svm_inject_irq(svm, 0x0);
3530 }
85f455f7
ED		 3531}
3532
95ba8273 3533static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 3534{
04d2cc77 3535 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 3536
44c11430
GN		 3537 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3538 == HF_NMI_MASK)
3539 return; /* IRET will cause a vm exit */
3540
e0231715
JR		 3541 /*
3542 * Something prevents NMI from been injected. Single step over possible
3543 * problem (IRET or exception injection or interrupt shadow)
3544 */
6be7d306 3545 svm->nmi_singlestep = true;
44c11430
GN		 3546 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3547 update_db_intercept(vcpu);
c1150d8c
DL		 3548}
3549
cbc94022
IE		 3550static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3551{
3552 return 0;
3553}
3554
d9e368d6
AK		 3555static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3556{
38e5e92f
JR		 3557 struct vcpu_svm *svm = to_svm(vcpu);
3558
3559 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3560 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3561 else
3562 svm->asid_generation--;
d9e368d6
AK		 3563}
3564
04d2cc77
AK		 3565static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3566{
3567}
3568
d7bf8221
JR		 3569static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3570{
3571 struct vcpu_svm *svm = to_svm(vcpu);
3572
2030753d 3573 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
88ab24ad
JR		 3574 return;
3575
4ee546b4 3576 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
d7bf8221 3577 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 3578 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 3579 }
3580}
3581
649d6864
JR		 3582static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3583{
3584 struct vcpu_svm *svm = to_svm(vcpu);
3585 u64 cr8;
3586
2030753d 3587 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
88ab24ad
JR		 3588 return;
3589
649d6864
JR		 3590 cr8 = kvm_get_cr8(vcpu);
3591 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3592 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3593}
3594
9222be18
GN		 3595static void svm_complete_interrupts(struct vcpu_svm *svm)
3596{
3597 u8 vector;
3598 int type;
3599 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 3600 unsigned int3_injected = svm->int3_injected;
3601
3602 svm->int3_injected = 0;
9222be18 3603
bd3d1ec3
AK		 3604 /*
3605 * If we've made progress since setting HF_IRET_MASK, we've
3606 * executed an IRET and can allow NMI injection.
3607 */
3608 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3609 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
44c11430 3610 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3842d135
AK		 3611 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3612 }
44c11430 3613
9222be18
GN		 3614 svm->vcpu.arch.nmi_injected = false;
3615 kvm_clear_exception_queue(&svm->vcpu);
3616 kvm_clear_interrupt_queue(&svm->vcpu);
3617
3618 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3619 return;
3620
3842d135
AK		 3621 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3622
9222be18
GN		 3623 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3624 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3625
3626 switch (type) {
3627 case SVM_EXITINTINFO_TYPE_NMI:
3628 svm->vcpu.arch.nmi_injected = true;
3629 break;
3630 case SVM_EXITINTINFO_TYPE_EXEPT:
66b7138f
JK		 3631 /*
3632 * In case of software exceptions, do not reinject the vector,
3633 * but re-execute the instruction instead. Rewind RIP first
3634 * if we emulated INT3 before.
3635 */
3636 if (kvm_exception_is_soft(vector)) {
3637 if (vector == BP_VECTOR && int3_injected &&
3638 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3639 kvm_rip_write(&svm->vcpu,
3640 kvm_rip_read(&svm->vcpu) -
3641 int3_injected);
9222be18 3642 break;
66b7138f 3643 }
9222be18
GN		 3644 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3645 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 3646 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 3647
3648 } else
ce7ddec4 3649 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 3650 break;
3651 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 3652 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 3653 break;
3654 default:
3655 break;
3656 }
3657}
3658
b463a6f7
AK		 3659static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3660{
3661 struct vcpu_svm *svm = to_svm(vcpu);
3662 struct vmcb_control_area *control = &svm->vmcb->control;
3663
3664 control->exit_int_info = control->event_inj;
3665 control->exit_int_info_err = control->event_inj_err;
3666 control->event_inj = 0;
3667 svm_complete_interrupts(svm);
3668}
3669
80e31d4f
AK		 3670#ifdef CONFIG_X86_64
3671#define R "r"
3672#else
3673#define R "e"
3674#endif
3675
851ba692 3676static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3677{
a2fa3e9f 3678 struct vcpu_svm *svm = to_svm(vcpu);
d9e368d6 3679
2041a06a
JR		 3680 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3681 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3682 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3683
cd3ff653
JR		 3684 /*
3685 * A vmexit emulation is required before the vcpu can be executed
3686 * again.
3687 */
3688 if (unlikely(svm->nested.exit_required))
3689 return;
3690
e756fc62 3691 pre_svm_run(svm);
6aa8b732 3692
649d6864
JR		 3693 sync_lapic_to_cr8(vcpu);
3694
cda0ffdd 3695 svm->vmcb->save.cr2 = vcpu->arch.cr2;
6aa8b732 3696
04d2cc77
AK		 3697 clgi();
3698
3699 local_irq_enable();
36241b8c 3700
6aa8b732 3701 asm volatile (
80e31d4f
AK		 3702 "push %%"R"bp; \n\t"
3703 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3704 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3705 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3706 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3707 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3708 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 3709#ifdef CONFIG_X86_64
fb3f0f51
RR		 3710 "mov %c[r8](%[svm]), %%r8 \n\t"
3711 "mov %c[r9](%[svm]), %%r9 \n\t"
3712 "mov %c[r10](%[svm]), %%r10 \n\t"
3713 "mov %c[r11](%[svm]), %%r11 \n\t"
3714 "mov %c[r12](%[svm]), %%r12 \n\t"
3715 "mov %c[r13](%[svm]), %%r13 \n\t"
3716 "mov %c[r14](%[svm]), %%r14 \n\t"
3717 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 3718#endif
3719
6aa8b732 3720 /* Enter guest mode */
80e31d4f
AK		 3721 "push %%"R"ax \n\t"
3722 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 3723 __ex(SVM_VMLOAD) "\n\t"
3724 __ex(SVM_VMRUN) "\n\t"
3725 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 3726 "pop %%"R"ax \n\t"
6aa8b732
AK		 3727
3728 /* Save guest registers, load host registers */
80e31d4f
AK		 3729 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3730 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3731 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3732 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3733 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3734 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 3735#ifdef CONFIG_X86_64
fb3f0f51
RR		 3736 "mov %%r8, %c[r8](%[svm]) \n\t"
3737 "mov %%r9, %c[r9](%[svm]) \n\t"
3738 "mov %%r10, %c[r10](%[svm]) \n\t"
3739 "mov %%r11, %c[r11](%[svm]) \n\t"
3740 "mov %%r12, %c[r12](%[svm]) \n\t"
3741 "mov %%r13, %c[r13](%[svm]) \n\t"
3742 "mov %%r14, %c[r14](%[svm]) \n\t"
3743 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 3744#endif
80e31d4f 3745 "pop %%"R"bp"
6aa8b732 3746 :
fb3f0f51 3747 : [svm]"a"(svm),
6aa8b732 3748 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 3749 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3750 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3751 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3752 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3753 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3754 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 3755#ifdef CONFIG_X86_64
ad312c7c
ZX		 3756 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3757 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3758 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3759 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3760 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3761 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3762 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3763 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 3764#endif
54a08c04 3765 : "cc", "memory"
80e31d4f 3766 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 3767#ifdef CONFIG_X86_64
54a08c04
LV		 3768 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3769#endif
3770 );
6aa8b732 3771
82ca2d10
AK		 3772#ifdef CONFIG_X86_64
3773 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3774#else
dacccfdd 3775 loadsegment(fs, svm->host.fs);
831ca609
AK		 3776#ifndef CONFIG_X86_32_LAZY_GS
3777 loadsegment(gs, svm->host.gs);
3778#endif
9581d442 3779#endif
6aa8b732
AK		 3780
3781 reload_tss(vcpu);
3782
56ba47dd
AK		 3783 local_irq_disable();
3784
13c34e07
AK		 3785 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3786 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3787 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3788 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3789
1e2b1dd7
JK		 3790 trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3791
3781c01c
JR		 3792 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3793 kvm_before_handle_nmi(&svm->vcpu);
3794
3795 stgi();
3796
3797 /* Any pending NMI will happen here */
3798
3799 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3800 kvm_after_handle_nmi(&svm->vcpu);
3801
d7bf8221
JR		 3802 sync_cr8_to_lapic(vcpu);
3803
a2fa3e9f 3804 svm->next_rip = 0;
9222be18 3805
38e5e92f
JR		 3806 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3807
631bc487
GN		 3808 /* if exit due to PF check for async PF */
3809 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3810 svm->apf_reason = kvm_read_and_reset_pf_reason();
3811
6de4f3ad
AK		 3812 if (npt_enabled) {
3813 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3814 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3815 }
fe5913e4
JR		 3816
3817 /*
3818 * We need to handle MC intercepts here before the vcpu has a chance to
3819 * change the physical cpu
3820 */
3821 if (unlikely(svm->vmcb->control.exit_code ==
3822 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3823 svm_handle_mce(svm);
8d28fec4
RJ		 3824
3825 mark_all_clean(svm->vmcb);
6aa8b732
AK		 3826}
3827
80e31d4f
AK		 3828#undef R
3829
6aa8b732
AK		 3830static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3831{
a2fa3e9f
GH		 3832 struct vcpu_svm *svm = to_svm(vcpu);
3833
3834 svm->vmcb->save.cr3 = root;
dcca1a65 3835 mark_dirty(svm->vmcb, VMCB_CR);
f40f6a45 3836 svm_flush_tlb(vcpu);
6aa8b732
AK		 3837}
3838
1c97f0a0
JR		 3839static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3840{
3841 struct vcpu_svm *svm = to_svm(vcpu);
3842
3843 svm->vmcb->control.nested_cr3 = root;
b2747166 3844 mark_dirty(svm->vmcb, VMCB_NPT);
1c97f0a0
JR		 3845
3846 /* Also sync guest cr3 here in case we live migrate */
9f8fe504 3847 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
dcca1a65 3848 mark_dirty(svm->vmcb, VMCB_CR);
1c97f0a0 3849
f40f6a45 3850 svm_flush_tlb(vcpu);
1c97f0a0
JR		 3851}
3852
6aa8b732
AK		 3853static int is_disabled(void)
3854{
6031a61c
JR		 3855 u64 vm_cr;
3856
3857 rdmsrl(MSR_VM_CR, vm_cr);
3858 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3859 return 1;
3860
6aa8b732
AK		 3861 return 0;
3862}
3863
102d8325
IM		 3864static void
3865svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3866{
3867 /*
3868 * Patch in the VMMCALL instruction:
3869 */
3870 hypercall[0] = 0x0f;
3871 hypercall[1] = 0x01;
3872 hypercall[2] = 0xd9;
102d8325
IM		 3873}
3874
002c7f7c
YS		 3875static void svm_check_processor_compat(void *rtn)
3876{
3877 *(int *)rtn = 0;
3878}
3879
774ead3a
AK		 3880static bool svm_cpu_has_accelerated_tpr(void)
3881{
3882 return false;
3883}
3884
4b12f0de 3885static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3886{
3887 return 0;
3888}
3889
0e851880
SY		 3890static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3891{
3892}
3893
d4330ef2
JR		 3894static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3895{
c2c63a49 3896 switch (func) {
4c62a2dc
JR		 3897 case 0x80000001:
3898 if (nested)
3899 entry->ecx |= (1 << 2); /* Set SVM bit */
3900 break;
c2c63a49
JR		 3901 case 0x8000000A:
3902 entry->eax = 1; /* SVM revision 1 */
3903 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3904 ASID emulation to nested SVM */
3905 entry->ecx = 0; /* Reserved */
7a190667
JR		 3906 entry->edx = 0; /* Per default do not support any
3907 additional features */
3908
3909 /* Support next_rip if host supports it */
2a6b20b8 3910 if (boot_cpu_has(X86_FEATURE_NRIPS))
7a190667 3911 entry->edx |= SVM_FEATURE_NRIP;
c2c63a49 3912
3d4aeaad
JR		 3913 /* Support NPT for the guest if enabled */
3914 if (npt_enabled)
3915 entry->edx |= SVM_FEATURE_NPT;
3916
c2c63a49
JR		 3917 break;
3918 }
d4330ef2
JR		 3919}
3920
17cc3935 3921static int svm_get_lpage_level(void)
344f414f 3922{
17cc3935 3923 return PT_PDPE_LEVEL;
344f414f
JR		 3924}
3925
4e47c7a6
SY		 3926static bool svm_rdtscp_supported(void)
3927{
3928 return false;
3929}
3930
f5f48ee1
SY		 3931static bool svm_has_wbinvd_exit(void)
3932{
3933 return true;
3934}
3935
02daab21
AK		 3936static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3937{
3938 struct vcpu_svm *svm = to_svm(vcpu);
3939
18c918c5 3940 set_exception_intercept(svm, NM_VECTOR);
66a562f7 3941 update_cr0_intercept(svm);
02daab21
AK		 3942}
3943
8061252e 3944#define PRE_EX(exit) { .exit_code = (exit), \
40e19b51 3945 .stage = X86_ICPT_PRE_EXCEPT, }
cfec82cb 3946#define POST_EX(exit) { .exit_code = (exit), \
40e19b51 3947 .stage = X86_ICPT_POST_EXCEPT, }
d7eb8203 3948#define POST_MEM(exit) { .exit_code = (exit), \
40e19b51 3949 .stage = X86_ICPT_POST_MEMACCESS, }
cfec82cb
JR		 3950
3951static struct __x86_intercept {
3952 u32 exit_code;
3953 enum x86_intercept_stage stage;
cfec82cb
JR		 3954} x86_intercept_map[] = {
3955 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
3956 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
3957 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
3958 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
3959 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
3b88e41a
JR		 3960 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
3961 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
dee6bb70
JR		 3962 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
3963 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
3964 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
3965 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
3966 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
3967 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
3968 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
3969 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
01de8b09
JR		 3970 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
3971 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
3972 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
3973 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
3974 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
3975 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
3976 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
3977 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
d7eb8203
JR		 3978 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
3979 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
3980 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
8061252e
JR		 3981 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
3982 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
3983 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
3984 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
3985 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
3986 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
3987 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
3988 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
3989 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
bf608f88
JR		 3990 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
3991 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
3992 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
3993 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
3994 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
3995 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
3996 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
f6511935
JR		 3997 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
3998 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
3999 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4000 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
cfec82cb
JR		 4001};
4002
8061252e 4003#undef PRE_EX
cfec82cb 4004#undef POST_EX
d7eb8203 4005#undef POST_MEM
cfec82cb 4006
8a76d7f2
JR		 4007static int svm_check_intercept(struct kvm_vcpu *vcpu,
4008 struct x86_instruction_info *info,
4009 enum x86_intercept_stage stage)
4010{
cfec82cb
JR		 4011 struct vcpu_svm *svm = to_svm(vcpu);
4012 int vmexit, ret = X86EMUL_CONTINUE;
4013 struct __x86_intercept icpt_info;
4014 struct vmcb *vmcb = svm->vmcb;
4015
4016 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4017 goto out;
4018
4019 icpt_info = x86_intercept_map[info->intercept];
4020
40e19b51 4021 if (stage != icpt_info.stage)
cfec82cb
JR		 4022 goto out;
4023
4024 switch (icpt_info.exit_code) {
4025 case SVM_EXIT_READ_CR0:
4026 if (info->intercept == x86_intercept_cr_read)
4027 icpt_info.exit_code += info->modrm_reg;
4028 break;
4029 case SVM_EXIT_WRITE_CR0: {
4030 unsigned long cr0, val;
4031 u64 intercept;
4032
4033 if (info->intercept == x86_intercept_cr_write)
4034 icpt_info.exit_code += info->modrm_reg;
4035
4036 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0)
4037 break;
4038
4039 intercept = svm->nested.intercept;
4040
4041 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4042 break;
4043
4044 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4045 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4046
4047 if (info->intercept == x86_intercept_lmsw) {
4048 cr0 &= 0xfUL;
4049 val &= 0xfUL;
4050 /* lmsw can't clear PE - catch this here */
4051 if (cr0 & X86_CR0_PE)
4052 val |= X86_CR0_PE;
4053 }
4054
4055 if (cr0 ^ val)
4056 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4057
4058 break;
4059 }
3b88e41a
JR		 4060 case SVM_EXIT_READ_DR0:
4061 case SVM_EXIT_WRITE_DR0:
4062 icpt_info.exit_code += info->modrm_reg;
4063 break;
8061252e
JR		 4064 case SVM_EXIT_MSR:
4065 if (info->intercept == x86_intercept_wrmsr)
4066 vmcb->control.exit_info_1 = 1;
4067 else
4068 vmcb->control.exit_info_1 = 0;
4069 break;
bf608f88
JR		 4070 case SVM_EXIT_PAUSE:
4071 /*
4072 * We get this for NOP only, but pause
4073 * is rep not, check this here
4074 */
4075 if (info->rep_prefix != REPE_PREFIX)
4076 goto out;
f6511935
JR		 4077 case SVM_EXIT_IOIO: {
4078 u64 exit_info;
4079 u32 bytes;
4080
4081 exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16;
4082
4083 if (info->intercept == x86_intercept_in ||
4084 info->intercept == x86_intercept_ins) {
4085 exit_info |= SVM_IOIO_TYPE_MASK;
4086 bytes = info->src_bytes;
4087 } else {
4088 bytes = info->dst_bytes;
4089 }
4090
4091 if (info->intercept == x86_intercept_outs ||
4092 info->intercept == x86_intercept_ins)
4093 exit_info |= SVM_IOIO_STR_MASK;
4094
4095 if (info->rep_prefix)
4096 exit_info |= SVM_IOIO_REP_MASK;
4097
4098 bytes = min(bytes, 4u);
4099
4100 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4101
4102 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4103
4104 vmcb->control.exit_info_1 = exit_info;
4105 vmcb->control.exit_info_2 = info->next_rip;
4106
4107 break;
4108 }
cfec82cb
JR		 4109 default:
4110 break;
4111 }
4112
4113 vmcb->control.next_rip = info->next_rip;
4114 vmcb->control.exit_code = icpt_info.exit_code;
4115 vmexit = nested_svm_exit_handled(svm);
4116
4117 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4118 : X86EMUL_CONTINUE;
4119
4120out:
4121 return ret;
8a76d7f2
JR		 4122}
4123
cbdd1bea 4124static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 4125 .cpu_has_kvm_support = has_svm,
4126 .disabled_by_bios = is_disabled,
4127 .hardware_setup = svm_hardware_setup,
4128 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 4129 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 4130 .hardware_enable = svm_hardware_enable,
4131 .hardware_disable = svm_hardware_disable,
774ead3a 4132 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 4133
4134 .vcpu_create = svm_create_vcpu,
4135 .vcpu_free = svm_free_vcpu,
04d2cc77 4136 .vcpu_reset = svm_vcpu_reset,
6aa8b732 4137
04d2cc77 4138 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 4139 .vcpu_load = svm_vcpu_load,
4140 .vcpu_put = svm_vcpu_put,
4141
4142 .set_guest_debug = svm_guest_debug,
4143 .get_msr = svm_get_msr,
4144 .set_msr = svm_set_msr,
4145 .get_segment_base = svm_get_segment_base,
4146 .get_segment = svm_get_segment,
4147 .set_segment = svm_set_segment,
2e4d2653 4148 .get_cpl = svm_get_cpl,
1747fb71 4149 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 4150 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
aff48baa 4151 .decache_cr3 = svm_decache_cr3,
25c4c276 4152 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 4153 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 4154 .set_cr3 = svm_set_cr3,
4155 .set_cr4 = svm_set_cr4,
4156 .set_efer = svm_set_efer,
4157 .get_idt = svm_get_idt,
4158 .set_idt = svm_set_idt,
4159 .get_gdt = svm_get_gdt,
4160 .set_gdt = svm_set_gdt,
020df079 4161 .set_dr7 = svm_set_dr7,
6de4f3ad 4162 .cache_reg = svm_cache_reg,
6aa8b732
AK		 4163 .get_rflags = svm_get_rflags,
4164 .set_rflags = svm_set_rflags,
6b52d186 4165 .fpu_activate = svm_fpu_activate,
02daab21 4166 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 4167
6aa8b732 4168 .tlb_flush = svm_flush_tlb,
6aa8b732 4169
6aa8b732 4170 .run = svm_vcpu_run,
04d2cc77 4171 .handle_exit = handle_exit,
6aa8b732 4172 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4173 .set_interrupt_shadow = svm_set_interrupt_shadow,
4174 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 4175 .patch_hypercall = svm_patch_hypercall,
2a8067f1 4176 .set_irq = svm_set_irq,
95ba8273 4177 .set_nmi = svm_inject_nmi,
298101da 4178 .queue_exception = svm_queue_exception,
b463a6f7 4179 .cancel_injection = svm_cancel_injection,
78646121 4180 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 4181 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 4182 .get_nmi_mask = svm_get_nmi_mask,
4183 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 4184 .enable_nmi_window = enable_nmi_window,
4185 .enable_irq_window = enable_irq_window,
4186 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 4187
4188 .set_tss_addr = svm_set_tss_addr,
67253af5 4189 .get_tdp_level = get_npt_level,
4b12f0de 4190 .get_mt_mask = svm_get_mt_mask,
229456fc 4191
586f9607 4192 .get_exit_info = svm_get_exit_info,
586f9607 4193
17cc3935 4194 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 4195
4196 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 4197
4198 .rdtscp_supported = svm_rdtscp_supported,
d4330ef2
JR		 4199
4200 .set_supported_cpuid = svm_set_supported_cpuid,
f5f48ee1
SY		 4201
4202 .has_wbinvd_exit = svm_has_wbinvd_exit,
99e3e30a 4203
4051b188 4204 .set_tsc_khz = svm_set_tsc_khz,
99e3e30a 4205 .write_tsc_offset = svm_write_tsc_offset,
e48672fa 4206 .adjust_tsc_offset = svm_adjust_tsc_offset,
857e4099 4207 .compute_tsc_offset = svm_compute_tsc_offset,
d5c1785d 4208 .read_l1_tsc = svm_read_l1_tsc,
1c97f0a0
JR		 4209
4210 .set_tdp_cr3 = set_tdp_cr3,
8a76d7f2
JR		 4211
4212 .check_intercept = svm_check_intercept,
6aa8b732
AK		 4213};
4214
4215static int __init svm_init(void)
4216{
cb498ea2 4217 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
0ee75bea 4218 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 4219}
4220
4221static void __exit svm_exit(void)
4222{
cb498ea2 4223 kvm_exit();
6aa8b732
AK		 4224}
4225
4226module_init(svm_init)
4227module_exit(svm_exit)
kernel source for telekom puls (alcatel/mediatek)