[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / i8254.c

/*
 * 8253/8254 interval timer emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 * Copyright (c) 2006 Intel Corporation
 * Copyright (c) 2007 Keir Fraser, XenSource Inc
 * Copyright (c) 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 *
 * Authors:
 *   Sheng Yang <sheng.yang@intel.com>
 *   Based on QEMU and Xen.
 */

#include <linux/kvm_host.h>

#include "irq.h"
#include "i8254.h"

#ifndef CONFIG_X86_64
#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
#else
#define mod_64(x, y) ((x) % (y))
#endif

#define RW_STATE_LSB 1
#define RW_STATE_MSB 2
#define RW_STATE_WORD0 3
#define RW_STATE_WORD1 4

/* Compute with 96 bit intermediate result: (a*b)/c */
static u64 muldiv64(u64 a, u32 b, u32 c)
{
	union {
		u64 ll;
		struct {
			u32 low, high;
		} l;
	} u, res;
	u64 rl, rh;

	u.ll = a;
	rl = (u64)u.l.low * (u64)b;
	rh = (u64)u.l.high * (u64)b;
	rh += (rl >> 32);
	res.l.high = div64_u64(rh, c);
	res.l.low = div64_u64(((mod_64(rh, c) << 32) + (rl & 0xffffffff)), c);
	return res.ll;
}

static void pit_set_gate(struct kvm *kvm, int channel, u32 val)
{
	struct kvm_kpit_channel_state *c =
		&kvm->arch.vpit->pit_state.channels[channel];

	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	switch (c->mode) {
	default:
	case 0:
	case 4:
		/* XXX: just disable/enable counting */
		break;
	case 1:
	case 2:
	case 3:
	case 5:
		/* Restart counting on rising edge. */
		if (c->gate < val)
			c->count_load_time = ktime_get();
		break;
	}

	c->gate = val;
}

int pit_get_gate(struct kvm *kvm, int channel)
{
	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	return kvm->arch.vpit->pit_state.channels[channel].gate;
}

static int pit_get_count(struct kvm *kvm, int channel)
{
	struct kvm_kpit_channel_state *c =
		&kvm->arch.vpit->pit_state.channels[channel];
	s64 d, t;
	int counter;

	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	t = ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time));
	d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);

	switch (c->mode) {
	case 0:
	case 1:
	case 4:
	case 5:
		counter = (c->count - d) & 0xffff;
		break;
	case 3:
		/* XXX: may be incorrect for odd counts */
		counter = c->count - (mod_64((2 * d), c->count));
		break;
	default:
		counter = c->count - mod_64(d, c->count);
		break;
	}
	return counter;
}

static int pit_get_out(struct kvm *kvm, int channel)
{
	struct kvm_kpit_channel_state *c =
		&kvm->arch.vpit->pit_state.channels[channel];
	s64 d, t;
	int out;

	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	t = ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time));
	d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);

	switch (c->mode) {
	default:
	case 0:
		out = (d >= c->count);
		break;
	case 1:
		out = (d < c->count);
		break;
	case 2:
		out = ((mod_64(d, c->count) == 0) && (d != 0));
		break;
	case 3:
		out = (mod_64(d, c->count) < ((c->count + 1) >> 1));
		break;
	case 4:
	case 5:
		out = (d == c->count);
		break;
	}

	return out;
}

static void pit_latch_count(struct kvm *kvm, int channel)
{
	struct kvm_kpit_channel_state *c =
		&kvm->arch.vpit->pit_state.channels[channel];

	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	if (!c->count_latched) {
		c->latched_count = pit_get_count(kvm, channel);
		c->count_latched = c->rw_mode;
	}
}

static void pit_latch_status(struct kvm *kvm, int channel)
{
	struct kvm_kpit_channel_state *c =
		&kvm->arch.vpit->pit_state.channels[channel];

	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	if (!c->status_latched) {
		/* TODO: Return NULL COUNT (bit 6). */
		c->status = ((pit_get_out(kvm, channel) << 7) |
				(c->rw_mode << 4) |
				(c->mode << 1) |
				c->bcd);
		c->status_latched = 1;
	}
}

int __pit_timer_fn(struct kvm_kpit_state *ps)
{
	struct kvm_vcpu *vcpu0 = ps->pit->kvm->vcpus[0];
	struct kvm_kpit_timer *pt = &ps->pit_timer;

	atomic_inc(&pt->pending);
	smp_mb__after_atomic_inc();
	/* FIXME: handle case where the guest is in guest mode */
	if (vcpu0 && waitqueue_active(&vcpu0->wq)) {
		vcpu0->arch.mp_state = KVM_MP_STATE_RUNNABLE;
		wake_up_interruptible(&vcpu0->wq);
	}

	pt->timer.expires = ktime_add_ns(pt->timer.expires, pt->period);
	pt->scheduled = ktime_to_ns(pt->timer.expires);

	return (pt->period == 0 ? 0 : 1);
}

int pit_has_pending_timer(struct kvm_vcpu *vcpu)
{
	struct kvm_pit *pit = vcpu->kvm->arch.vpit;

	if (pit && vcpu->vcpu_id == 0 && pit->pit_state.inject_pending)
		return atomic_read(&pit->pit_state.pit_timer.pending);

	return 0;
}

static enum hrtimer_restart pit_timer_fn(struct hrtimer *data)
{
	struct kvm_kpit_state *ps;
	int restart_timer = 0;

	ps = container_of(data, struct kvm_kpit_state, pit_timer.timer);

	restart_timer = __pit_timer_fn(ps);

	if (restart_timer)
		return HRTIMER_RESTART;
	else
		return HRTIMER_NORESTART;
}

static void destroy_pit_timer(struct kvm_kpit_timer *pt)
{
	pr_debug("pit: execute del timer!\n");
	hrtimer_cancel(&pt->timer);
}

static void create_pit_timer(struct kvm_kpit_timer *pt, u32 val, int is_period)
{
	s64 interval;

	interval = muldiv64(val, NSEC_PER_SEC, KVM_PIT_FREQ);

	pr_debug("pit: create pit timer, interval is %llu nsec\n", interval);

	/* TODO The new value only affected after the retriggered */
	hrtimer_cancel(&pt->timer);
	pt->period = (is_period == 0) ? 0 : interval;
	pt->timer.function = pit_timer_fn;
	atomic_set(&pt->pending, 0);

	hrtimer_start(&pt->timer, ktime_add_ns(ktime_get(), interval),
		      HRTIMER_MODE_ABS);
}

static void pit_load_count(struct kvm *kvm, int channel, u32 val)
{
	struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state;

	WARN_ON(!mutex_is_locked(&ps->lock));

	pr_debug("pit: load_count val is %d, channel is %d\n", val, channel);

	/*
	 * Though spec said the state of 8254 is undefined after power-up,
	 * seems some tricky OS like Windows XP depends on IRQ0 interrupt
	 * when booting up.
	 * So here setting initialize rate for it, and not a specific number
	 */
	if (val == 0)
		val = 0x10000;

	ps->channels[channel].count_load_time = ktime_get();
	ps->channels[channel].count = val;

	if (channel != 0)
		return;

	/* Two types of timer
	 * mode 1 is one shot, mode 2 is period, otherwise del timer */
	switch (ps->channels[0].mode) {
	case 1:
        /* FIXME: enhance mode 4 precision */
	case 4:
		create_pit_timer(&ps->pit_timer, val, 0);
		break;
	case 2:
		create_pit_timer(&ps->pit_timer, val, 1);
		break;
	default:
		destroy_pit_timer(&ps->pit_timer);
	}
}

void kvm_pit_load_count(struct kvm *kvm, int channel, u32 val)
{
	mutex_lock(&kvm->arch.vpit->pit_state.lock);
	pit_load_count(kvm, channel, val);
	mutex_unlock(&kvm->arch.vpit->pit_state.lock);
}

static void pit_ioport_write(struct kvm_io_device *this,
			     gpa_t addr, int len, const void *data)
{
	struct kvm_pit *pit = (struct kvm_pit *)this->private;
	struct kvm_kpit_state *pit_state = &pit->pit_state;
	struct kvm *kvm = pit->kvm;
	int channel, access;
	struct kvm_kpit_channel_state *s;
	u32 val = *(u32 *) data;

	val  &= 0xff;
	addr &= KVM_PIT_CHANNEL_MASK;

	mutex_lock(&pit_state->lock);

	if (val != 0)
		pr_debug("pit: write addr is 0x%x, len is %d, val is 0x%x\n",
			  (unsigned int)addr, len, val);

	if (addr == 3) {
		channel = val >> 6;
		if (channel == 3) {
			/* Read-Back Command. */
			for (channel = 0; channel < 3; channel++) {
				s = &pit_state->channels[channel];
				if (val & (2 << channel)) {
					if (!(val & 0x20))
						pit_latch_count(kvm, channel);
					if (!(val & 0x10))
						pit_latch_status(kvm, channel);
				}
			}
		} else {
			/* Select Counter <channel>. */
			s = &pit_state->channels[channel];
			access = (val >> 4) & KVM_PIT_CHANNEL_MASK;
			if (access == 0) {
				pit_latch_count(kvm, channel);
			} else {
				s->rw_mode = access;
				s->read_state = access;
				s->write_state = access;
				s->mode = (val >> 1) & 7;
				if (s->mode > 5)
					s->mode -= 4;
				s->bcd = val & 1;
			}
		}
	} else {
		/* Write Count. */
		s = &pit_state->channels[addr];
		switch (s->write_state) {
		default:
		case RW_STATE_LSB:
			pit_load_count(kvm, addr, val);
			break;
		case RW_STATE_MSB:
			pit_load_count(kvm, addr, val << 8);
			break;
		case RW_STATE_WORD0:
			s->write_latch = val;
			s->write_state = RW_STATE_WORD1;
			break;
		case RW_STATE_WORD1:
			pit_load_count(kvm, addr, s->write_latch | (val << 8));
			s->write_state = RW_STATE_WORD0;
			break;
		}
	}

	mutex_unlock(&pit_state->lock);
}

static void pit_ioport_read(struct kvm_io_device *this,
			    gpa_t addr, int len, void *data)
{
	struct kvm_pit *pit = (struct kvm_pit *)this->private;
	struct kvm_kpit_state *pit_state = &pit->pit_state;
	struct kvm *kvm = pit->kvm;
	int ret, count;
	struct kvm_kpit_channel_state *s;

	addr &= KVM_PIT_CHANNEL_MASK;
	s = &pit_state->channels[addr];

	mutex_lock(&pit_state->lock);

	if (s->status_latched) {
		s->status_latched = 0;
		ret = s->status;
	} else if (s->count_latched) {
		switch (s->count_latched) {
		default:
		case RW_STATE_LSB:
			ret = s->latched_count & 0xff;
			s->count_latched = 0;
			break;
		case RW_STATE_MSB:
			ret = s->latched_count >> 8;
			s->count_latched = 0;
			break;
		case RW_STATE_WORD0:
			ret = s->latched_count & 0xff;
			s->count_latched = RW_STATE_MSB;
			break;
		}
	} else {
		switch (s->read_state) {
		default:
		case RW_STATE_LSB:
			count = pit_get_count(kvm, addr);
			ret = count & 0xff;
			break;
		case RW_STATE_MSB:
			count = pit_get_count(kvm, addr);
			ret = (count >> 8) & 0xff;
			break;
		case RW_STATE_WORD0:
			count = pit_get_count(kvm, addr);
			ret = count & 0xff;
			s->read_state = RW_STATE_WORD1;
			break;
		case RW_STATE_WORD1:
			count = pit_get_count(kvm, addr);
			ret = (count >> 8) & 0xff;
			s->read_state = RW_STATE_WORD0;
			break;
		}
	}

	if (len > sizeof(ret))
		len = sizeof(ret);
	memcpy(data, (char *)&ret, len);

	mutex_unlock(&pit_state->lock);
}

static int pit_in_range(struct kvm_io_device *this, gpa_t addr)
{
	return ((addr >= KVM_PIT_BASE_ADDRESS) &&
		(addr < KVM_PIT_BASE_ADDRESS + KVM_PIT_MEM_LENGTH));
}

static void speaker_ioport_write(struct kvm_io_device *this,
				 gpa_t addr, int len, const void *data)
{
	struct kvm_pit *pit = (struct kvm_pit *)this->private;
	struct kvm_kpit_state *pit_state = &pit->pit_state;
	struct kvm *kvm = pit->kvm;
	u32 val = *(u32 *) data;

	mutex_lock(&pit_state->lock);
	pit_state->speaker_data_on = (val >> 1) & 1;
	pit_set_gate(kvm, 2, val & 1);
	mutex_unlock(&pit_state->lock);
}

static void speaker_ioport_read(struct kvm_io_device *this,
				gpa_t addr, int len, void *data)
{
	struct kvm_pit *pit = (struct kvm_pit *)this->private;
	struct kvm_kpit_state *pit_state = &pit->pit_state;
	struct kvm *kvm = pit->kvm;
	unsigned int refresh_clock;
	int ret;

	/* Refresh clock toggles at about 15us. We approximate as 2^14ns. */
	refresh_clock = ((unsigned int)ktime_to_ns(ktime_get()) >> 14) & 1;

	mutex_lock(&pit_state->lock);
	ret = ((pit_state->speaker_data_on << 1) | pit_get_gate(kvm, 2) |
		(pit_get_out(kvm, 2) << 5) | (refresh_clock << 4));
	if (len > sizeof(ret))
		len = sizeof(ret);
	memcpy(data, (char *)&ret, len);
	mutex_unlock(&pit_state->lock);
}

static int speaker_in_range(struct kvm_io_device *this, gpa_t addr)
{
	return (addr == KVM_SPEAKER_BASE_ADDRESS);
}

void kvm_pit_reset(struct kvm_pit *pit)
{
	int i;
	struct kvm_kpit_channel_state *c;

	mutex_lock(&pit->pit_state.lock);
	for (i = 0; i < 3; i++) {
		c = &pit->pit_state.channels[i];
		c->mode = 0xff;
		c->gate = (i != 2);
		pit_load_count(pit->kvm, i, 0);
	}
	mutex_unlock(&pit->pit_state.lock);

	atomic_set(&pit->pit_state.pit_timer.pending, 0);
	pit->pit_state.inject_pending = 1;
}

struct kvm_pit *kvm_create_pit(struct kvm *kvm)
{
	struct kvm_pit *pit;
	struct kvm_kpit_state *pit_state;

	pit = kzalloc(sizeof(struct kvm_pit), GFP_KERNEL);
	if (!pit)
		return NULL;

	mutex_init(&pit->pit_state.lock);
	mutex_lock(&pit->pit_state.lock);

	/* Initialize PIO device */
	pit->dev.read = pit_ioport_read;
	pit->dev.write = pit_ioport_write;
	pit->dev.in_range = pit_in_range;
	pit->dev.private = pit;
	kvm_io_bus_register_dev(&kvm->pio_bus, &pit->dev);

	pit->speaker_dev.read = speaker_ioport_read;
	pit->speaker_dev.write = speaker_ioport_write;
	pit->speaker_dev.in_range = speaker_in_range;
	pit->speaker_dev.private = pit;
	kvm_io_bus_register_dev(&kvm->pio_bus, &pit->speaker_dev);

	kvm->arch.vpit = pit;
	pit->kvm = kvm;

	pit_state = &pit->pit_state;
	pit_state->pit = pit;
	hrtimer_init(&pit_state->pit_timer.timer,
		     CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
	mutex_unlock(&pit->pit_state.lock);

	kvm_pit_reset(pit);

	return pit;
}

void kvm_free_pit(struct kvm *kvm)
{
	struct hrtimer *timer;

	if (kvm->arch.vpit) {
		mutex_lock(&kvm->arch.vpit->pit_state.lock);
		timer = &kvm->arch.vpit->pit_state.pit_timer.timer;
		hrtimer_cancel(timer);
		mutex_unlock(&kvm->arch.vpit->pit_state.lock);
		kfree(kvm->arch.vpit);
	}
}

void __inject_pit_timer_intr(struct kvm *kvm)
{
	mutex_lock(&kvm->lock);
	kvm_ioapic_set_irq(kvm->arch.vioapic, 0, 1);
	kvm_ioapic_set_irq(kvm->arch.vioapic, 0, 0);
	kvm_pic_set_irq(pic_irqchip(kvm), 0, 1);
	kvm_pic_set_irq(pic_irqchip(kvm), 0, 0);
	mutex_unlock(&kvm->lock);
}

void kvm_inject_pit_timer_irqs(struct kvm_vcpu *vcpu)
{
	struct kvm_pit *pit = vcpu->kvm->arch.vpit;
	struct kvm *kvm = vcpu->kvm;
	struct kvm_kpit_state *ps;

	if (vcpu && pit) {
		ps = &pit->pit_state;

		/* Try to inject pending interrupts when:
		 * 1. Pending exists
		 * 2. Last interrupt was accepted or waited for too long time*/
		if (atomic_read(&ps->pit_timer.pending) &&
		    (ps->inject_pending ||
		    (jiffies - ps->last_injected_time
				>= KVM_MAX_PIT_INTR_INTERVAL))) {
			ps->inject_pending = 0;
			__inject_pit_timer_intr(kvm);
			ps->last_injected_time = jiffies;
		}
	}
}

void kvm_pit_timer_intr_post(struct kvm_vcpu *vcpu, int vec)
{
	struct kvm_arch *arch = &vcpu->kvm->arch;
	struct kvm_kpit_state *ps;

	if (vcpu && arch->vpit) {
		ps = &arch->vpit->pit_state;
		if (atomic_read(&ps->pit_timer.pending) &&
		(((arch->vpic->pics[0].imr & 1) == 0 &&
		  arch->vpic->pics[0].irq_base == vec) ||
		  (arch->vioapic->redirtbl[0].fields.vector == vec &&
		  arch->vioapic->redirtbl[0].fields.mask != 1))) {
			ps->inject_pending = 1;
			atomic_dec(&ps->pit_timer.pending);
			ps->channels[0].count_load_time = ktime_get();
		}
	}
}
Commit	Line	Data
7837699f SY	1	/*
	2	* 8253/8254 interval timer emulation
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	* Copyright (c) 2006 Intel Corporation
	6	* Copyright (c) 2007 Keir Fraser, XenSource Inc
	7	* Copyright (c) 2008 Intel Corporation
	8	*
	9	* Permission is hereby granted, free of charge, to any person obtaining a copy
	10	* of this software and associated documentation files (the "Software"), to deal
	11	* in the Software without restriction, including without limitation the rights
	12	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	13	* copies of the Software, and to permit persons to whom the Software is
	14	* furnished to do so, subject to the following conditions:
	15	*
	16	* The above copyright notice and this permission notice shall be included in
	17	* all copies or substantial portions of the Software.
	18	*
	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	20	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	21	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	22	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	23	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	24	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	25	* THE SOFTWARE.
	26	*
	27	* Authors:
	28	* Sheng Yang <sheng.yang@intel.com>
	29	* Based on QEMU and Xen.
	30	*/
	31
	32	#include <linux/kvm_host.h>
	33
	34	#include "irq.h"
	35	#include "i8254.h"
	36
	37	#ifndef CONFIG_X86_64
6f6d6a1a	38	#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
7837699f SY	39	#else
	40	#define mod_64(x, y) ((x) % (y))
	41	#endif
	42
	43	#define RW_STATE_LSB 1
	44	#define RW_STATE_MSB 2
	45	#define RW_STATE_WORD0 3
	46	#define RW_STATE_WORD1 4
	47
	48	/* Compute with 96 bit intermediate result: (ab)/c /
	49	static u64 muldiv64(u64 a, u32 b, u32 c)
	50	{
	51	union {
	52	u64 ll;
	53	struct {
	54	u32 low, high;
	55	} l;
	56	} u, res;
	57	u64 rl, rh;
	58
	59	u.ll = a;
	60	rl = (u64)u.l.low * (u64)b;
	61	rh = (u64)u.l.high * (u64)b;
	62	rh += (rl >> 32);
6f6d6a1a RZ	63	res.l.high = div64_u64(rh, c);
6f6d6a1a RZ	64	res.l.low = div64_u64(((mod_64(rh, c) << 32) + (rl & 0xffffffff)), c);
7837699f SY	65	return res.ll;
	66	}
	67
	68	static void pit_set_gate(struct kvm *kvm, int channel, u32 val)
	69	{
	70	struct kvm_kpit_channel_state *c =
	71	&kvm->arch.vpit->pit_state.channels[channel];
	72
	73	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
	74
	75	switch (c->mode) {
	76	default:
	77	case 0:
	78	case 4:
	79	/* XXX: just disable/enable counting */
	80	break;
	81	case 1:
	82	case 2:
	83	case 3:
	84	case 5:
	85	/* Restart counting on rising edge. */
	86	if (c->gate < val)
	87	c->count_load_time = ktime_get();
	88	break;
	89	}
	90
	91	c->gate = val;
	92	}
	93
	94	int pit_get_gate(struct kvm *kvm, int channel)
	95	{
	96	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
	97
	98	return kvm->arch.vpit->pit_state.channels[channel].gate;
	99	}
	100
	101	static int pit_get_count(struct kvm *kvm, int channel)
	102	{
	103	struct kvm_kpit_channel_state *c =
	104	&kvm->arch.vpit->pit_state.channels[channel];
	105	s64 d, t;
	106	int counter;
	107
	108	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
	109
	110	t = ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time));
	111	d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);
	112
	113	switch (c->mode) {
	114	case 0:
	115	case 1:
	116	case 4:
	117	case 5:
	118	counter = (c->count - d) & 0xffff;
	119	break;
	120	case 3:
	121	/* XXX: may be incorrect for odd counts */
	122	counter = c->count - (mod_64((2 * d), c->count));
	123	break;
	124	default:
	125	counter = c->count - mod_64(d, c->count);
	126	break;
	127	}
	128	return counter;
129	}
130
131	static int pit_get_out(struct kvm *kvm, int channel)
132	{
133	struct kvm_kpit_channel_state *c =
134	&kvm->arch.vpit->pit_state.channels[channel];
135	s64 d, t;
136	int out;
137
138	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
139
140	t = ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time));
141	d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);
142
143	switch (c->mode) {
144	default:
145	case 0:
146	out = (d >= c->count);
147	break;
148	case 1:
149	out = (d < c->count);
150	break;
151	case 2:
152	out = ((mod_64(d, c->count) == 0) && (d != 0));
153	break;
154	case 3:
155	out = (mod_64(d, c->count) < ((c->count + 1) >> 1));
156	break;
157	case 4:
158	case 5:
159	out = (d == c->count);
160	break;
161	}
162
163	return out;
164	}
165
166	static void pit_latch_count(struct kvm *kvm, int channel)
167	{
168	struct kvm_kpit_channel_state *c =
169	&kvm->arch.vpit->pit_state.channels[channel];
170
171	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
172
173	if (!c->count_latched) {
174	c->latched_count = pit_get_count(kvm, channel);
175	c->count_latched = c->rw_mode;
176	}
177	}
178
179	static void pit_latch_status(struct kvm *kvm, int channel)
180	{
181	struct kvm_kpit_channel_state *c =
182	&kvm->arch.vpit->pit_state.channels[channel];
183
184	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
185
186	if (!c->status_latched) {
187	/* TODO: Return NULL COUNT (bit 6). */
188	c->status = ((pit_get_out(kvm, channel) << 7) \|
189	(c->rw_mode << 4) \|
190	(c->mode << 1) \|
191	c->bcd);
192	c->status_latched = 1;
193	}
194	}
195
196	int __pit_timer_fn(struct kvm_kpit_state *ps)
197	{
198	struct kvm_vcpu *vcpu0 = ps->pit->kvm->vcpus[0];
199	struct kvm_kpit_timer *pt = &ps->pit_timer;
200
201	atomic_inc(&pt->pending);
202	smp_mb__after_atomic_inc();
203	/* FIXME: handle case where the guest is in guest mode */
204	if (vcpu0 && waitqueue_active(&vcpu0->wq)) {
a4535290	205	vcpu0->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7837699f SY	206	wake_up_interruptible(&vcpu0->wq);
	207	}
	208
	209	pt->timer.expires = ktime_add_ns(pt->timer.expires, pt->period);
	210	pt->scheduled = ktime_to_ns(pt->timer.expires);
	211
	212	return (pt->period == 0 ? 0 : 1);
	213	}
	214
3d80840d MT	215	int pit_has_pending_timer(struct kvm_vcpu *vcpu)
	216	{
	217	struct kvm_pit *pit = vcpu->kvm->arch.vpit;
	218
eedaa4e2	219	if (pit && vcpu->vcpu_id == 0 && pit->pit_state.inject_pending)
3d80840d MT	220	return atomic_read(&pit->pit_state.pit_timer.pending);
	221
	222	return 0;
	223	}
	224
7837699f SY	225	static enum hrtimer_restart pit_timer_fn(struct hrtimer *data)
	226	{
	227	struct kvm_kpit_state *ps;
	228	int restart_timer = 0;
	229
	230	ps = container_of(data, struct kvm_kpit_state, pit_timer.timer);
	231
	232	restart_timer = __pit_timer_fn(ps);
	233
	234	if (restart_timer)
	235	return HRTIMER_RESTART;
	236	else
	237	return HRTIMER_NORESTART;
	238	}
	239
	240	static void destroy_pit_timer(struct kvm_kpit_timer *pt)
	241	{
	242	pr_debug("pit: execute del timer!\n");
	243	hrtimer_cancel(&pt->timer);
	244	}
	245
	246	static void create_pit_timer(struct kvm_kpit_timer *pt, u32 val, int is_period)
	247	{
	248	s64 interval;
	249
	250	interval = muldiv64(val, NSEC_PER_SEC, KVM_PIT_FREQ);
	251
	252	pr_debug("pit: create pit timer, interval is %llu nsec\n", interval);
	253
	254	/* TODO The new value only affected after the retriggered */
	255	hrtimer_cancel(&pt->timer);
	256	pt->period = (is_period == 0) ? 0 : interval;
	257	pt->timer.function = pit_timer_fn;
	258	atomic_set(&pt->pending, 0);
	259
	260	hrtimer_start(&pt->timer, ktime_add_ns(ktime_get(), interval),
	261	HRTIMER_MODE_ABS);
	262	}
	263
	264	static void pit_load_count(struct kvm *kvm, int channel, u32 val)
	265	{
	266	struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state;
	267
	268	WARN_ON(!mutex_is_locked(&ps->lock));
	269
	270	pr_debug("pit: load_count val is %d, channel is %d\n", val, channel);
	271
	272	/*
	273	* Though spec said the state of 8254 is undefined after power-up,
	274	* seems some tricky OS like Windows XP depends on IRQ0 interrupt
	275	* when booting up.
	276	* So here setting initialize rate for it, and not a specific number
	277	*/
	278	if (val == 0)
	279	val = 0x10000;
	280
	281	ps->channels[channel].count_load_time = ktime_get();
	282	ps->channels[channel].count = val;
	283
	284	if (channel != 0)
	285	return;
	286
	287	/* Two types of timer
	288	* mode 1 is one shot, mode 2 is period, otherwise del timer */
289	switch (ps->channels[0].mode) {
290	case 1:
ece15bab MT	291	/* FIXME: enhance mode 4 precision */
ece15bab MT	292	case 4:
7837699f SY	293	create_pit_timer(&ps->pit_timer, val, 0);
	294	break;
	295	case 2:
	296	create_pit_timer(&ps->pit_timer, val, 1);
	297	break;
	298	default:
	299	destroy_pit_timer(&ps->pit_timer);
	300	}
	301	}
	302
e0f63cb9 SY	303	void kvm_pit_load_count(struct kvm *kvm, int channel, u32 val)
	304	{
	305	mutex_lock(&kvm->arch.vpit->pit_state.lock);
	306	pit_load_count(kvm, channel, val);
	307	mutex_unlock(&kvm->arch.vpit->pit_state.lock);
	308	}
	309
7837699f SY	310	static void pit_ioport_write(struct kvm_io_device *this,
	311	gpa_t addr, int len, const void *data)
	312	{
	313	struct kvm_pit pit = (struct kvm_pit )this->private;
	314	struct kvm_kpit_state *pit_state = &pit->pit_state;
	315	struct kvm *kvm = pit->kvm;
	316	int channel, access;
	317	struct kvm_kpit_channel_state *s;
	318	u32 val = (u32 ) data;
	319
	320	val &= 0xff;
	321	addr &= KVM_PIT_CHANNEL_MASK;
	322
	323	mutex_lock(&pit_state->lock);
	324
	325	if (val != 0)
	326	pr_debug("pit: write addr is 0x%x, len is %d, val is 0x%x\n",
	327	(unsigned int)addr, len, val);
	328
	329	if (addr == 3) {
	330	channel = val >> 6;
	331	if (channel == 3) {
	332	/* Read-Back Command. */
	333	for (channel = 0; channel < 3; channel++) {
	334	s = &pit_state->channels[channel];
	335	if (val & (2 << channel)) {
	336	if (!(val & 0x20))
	337	pit_latch_count(kvm, channel);
	338	if (!(val & 0x10))
	339	pit_latch_status(kvm, channel);
	340	}
	341	}
	342	} else {
	343	/* Select Counter <channel>. */
	344	s = &pit_state->channels[channel];
	345	access = (val >> 4) & KVM_PIT_CHANNEL_MASK;
	346	if (access == 0) {
	347	pit_latch_count(kvm, channel);
	348	} else {
	349	s->rw_mode = access;
	350	s->read_state = access;
	351	s->write_state = access;
	352	s->mode = (val >> 1) & 7;
	353	if (s->mode > 5)
	354	s->mode -= 4;
	355	s->bcd = val & 1;
	356	}
	357	}
	358	} else {
	359	/* Write Count. */
	360	s = &pit_state->channels[addr];
	361	switch (s->write_state) {
	362	default:
	363	case RW_STATE_LSB:
	364	pit_load_count(kvm, addr, val);
	365	break;
	366	case RW_STATE_MSB:
	367	pit_load_count(kvm, addr, val << 8);
	368	break;
	369	case RW_STATE_WORD0:
	370	s->write_latch = val;
	371	s->write_state = RW_STATE_WORD1;
	372	break;
	373	case RW_STATE_WORD1:
374	pit_load_count(kvm, addr, s->write_latch \| (val << 8));
375	s->write_state = RW_STATE_WORD0;
376	break;
377	}
378	}
379
380	mutex_unlock(&pit_state->lock);
381	}
382
383	static void pit_ioport_read(struct kvm_io_device *this,
384	gpa_t addr, int len, void *data)
385	{
386	struct kvm_pit pit = (struct kvm_pit )this->private;
387	struct kvm_kpit_state *pit_state = &pit->pit_state;
388	struct kvm *kvm = pit->kvm;
389	int ret, count;
390	struct kvm_kpit_channel_state *s;
391
392	addr &= KVM_PIT_CHANNEL_MASK;
393	s = &pit_state->channels[addr];
394
395	mutex_lock(&pit_state->lock);
396
397	if (s->status_latched) {
398	s->status_latched = 0;
399	ret = s->status;
400	} else if (s->count_latched) {
401	switch (s->count_latched) {
402	default:
403	case RW_STATE_LSB:
404	ret = s->latched_count & 0xff;
405	s->count_latched = 0;
406	break;
407	case RW_STATE_MSB:
408	ret = s->latched_count >> 8;
409	s->count_latched = 0;
410	break;
411	case RW_STATE_WORD0:
412	ret = s->latched_count & 0xff;
413	s->count_latched = RW_STATE_MSB;
414	break;
415	}
416	} else {
417	switch (s->read_state) {
418	default:
419	case RW_STATE_LSB:
420	count = pit_get_count(kvm, addr);
421	ret = count & 0xff;
422	break;
423	case RW_STATE_MSB:
424	count = pit_get_count(kvm, addr);
425	ret = (count >> 8) & 0xff;
426	break;
427	case RW_STATE_WORD0:
428	count = pit_get_count(kvm, addr);
429	ret = count & 0xff;
430	s->read_state = RW_STATE_WORD1;
431	break;
432	case RW_STATE_WORD1:
433	count = pit_get_count(kvm, addr);
434	ret = (count >> 8) & 0xff;
435	s->read_state = RW_STATE_WORD0;
436	break;
437	}
438	}
439
440	if (len > sizeof(ret))
441	len = sizeof(ret);
442	memcpy(data, (char *)&ret, len);
443
444	mutex_unlock(&pit_state->lock);
445	}
446
447	static int pit_in_range(struct kvm_io_device *this, gpa_t addr)
448	{
449	return ((addr >= KVM_PIT_BASE_ADDRESS) &&
450	(addr < KVM_PIT_BASE_ADDRESS + KVM_PIT_MEM_LENGTH));
451	}
452
453	static void speaker_ioport_write(struct kvm_io_device *this,
454	gpa_t addr, int len, const void *data)
455	{
456	struct kvm_pit pit = (struct kvm_pit )this->private;
457	struct kvm_kpit_state *pit_state = &pit->pit_state;
458	struct kvm *kvm = pit->kvm;
459	u32 val = (u32 ) data;
460
461	mutex_lock(&pit_state->lock);
462	pit_state->speaker_data_on = (val >> 1) & 1;
463	pit_set_gate(kvm, 2, val & 1);
464	mutex_unlock(&pit_state->lock);
465	}
466
467	static void speaker_ioport_read(struct kvm_io_device *this,
468	gpa_t addr, int len, void *data)
469	{
470	struct kvm_pit pit = (struct kvm_pit )this->private;
471	struct kvm_kpit_state *pit_state = &pit->pit_state;
472	struct kvm *kvm = pit->kvm;
473	unsigned int refresh_clock;
474	int ret;
475
476	/* Refresh clock toggles at about 15us. We approximate as 2^14ns. */
477	refresh_clock = ((unsigned int)ktime_to_ns(ktime_get()) >> 14) & 1;
478
479	mutex_lock(&pit_state->lock);
480	ret = ((pit_state->speaker_data_on << 1) \| pit_get_gate(kvm, 2) \|
481	(pit_get_out(kvm, 2) << 5) \| (refresh_clock << 4));
482	if (len > sizeof(ret))
483	len = sizeof(ret);
484	memcpy(data, (char *)&ret, len);
485	mutex_unlock(&pit_state->lock);
486	}
487
488	static int speaker_in_range(struct kvm_io_device *this, gpa_t addr)
489	{
490	return (addr == KVM_SPEAKER_BASE_ADDRESS);
491	}
492
308b0f23	493	void kvm_pit_reset(struct kvm_pit *pit)
7837699f SY	494	{
7837699f SY	495	int i;
308b0f23 SY	496	struct kvm_kpit_channel_state *c;
	497
	498	mutex_lock(&pit->pit_state.lock);
	499	for (i = 0; i < 3; i++) {
	500	c = &pit->pit_state.channels[i];
	501	c->mode = 0xff;
	502	c->gate = (i != 2);
	503	pit_load_count(pit->kvm, i, 0);
	504	}
	505	mutex_unlock(&pit->pit_state.lock);
	506
	507	atomic_set(&pit->pit_state.pit_timer.pending, 0);
	508	pit->pit_state.inject_pending = 1;
	509	}
	510
	511	struct kvm_pit kvm_create_pit(struct kvm kvm)
	512	{
7837699f SY	513	struct kvm_pit *pit;
7837699f SY	514	struct kvm_kpit_state *pit_state;
7837699f SY	515
	516	pit = kzalloc(sizeof(struct kvm_pit), GFP_KERNEL);
	517	if (!pit)
	518	return NULL;
	519
	520	mutex_init(&pit->pit_state.lock);
	521	mutex_lock(&pit->pit_state.lock);
	522
	523	/* Initialize PIO device */
	524	pit->dev.read = pit_ioport_read;
	525	pit->dev.write = pit_ioport_write;
	526	pit->dev.in_range = pit_in_range;
	527	pit->dev.private = pit;
	528	kvm_io_bus_register_dev(&kvm->pio_bus, &pit->dev);
	529
	530	pit->speaker_dev.read = speaker_ioport_read;
	531	pit->speaker_dev.write = speaker_ioport_write;
	532	pit->speaker_dev.in_range = speaker_in_range;
	533	pit->speaker_dev.private = pit;
	534	kvm_io_bus_register_dev(&kvm->pio_bus, &pit->speaker_dev);
	535
	536	kvm->arch.vpit = pit;
	537	pit->kvm = kvm;
	538
	539	pit_state = &pit->pit_state;
	540	pit_state->pit = pit;
	541	hrtimer_init(&pit_state->pit_timer.timer,
	542	CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
7837699f SY	543	mutex_unlock(&pit->pit_state.lock);
7837699f SY	544
308b0f23	545	kvm_pit_reset(pit);
7837699f SY	546
	547	return pit;
	548	}
	549
	550	void kvm_free_pit(struct kvm *kvm)
	551	{
	552	struct hrtimer *timer;
	553
	554	if (kvm->arch.vpit) {
	555	mutex_lock(&kvm->arch.vpit->pit_state.lock);
	556	timer = &kvm->arch.vpit->pit_state.pit_timer.timer;
	557	hrtimer_cancel(timer);
	558	mutex_unlock(&kvm->arch.vpit->pit_state.lock);
	559	kfree(kvm->arch.vpit);
	560	}
	561	}
	562
	563	void __inject_pit_timer_intr(struct kvm *kvm)
	564	{
	565	mutex_lock(&kvm->lock);
	566	kvm_ioapic_set_irq(kvm->arch.vioapic, 0, 1);
	567	kvm_ioapic_set_irq(kvm->arch.vioapic, 0, 0);
	568	kvm_pic_set_irq(pic_irqchip(kvm), 0, 1);
	569	kvm_pic_set_irq(pic_irqchip(kvm), 0, 0);
	570	mutex_unlock(&kvm->lock);
	571	}
	572
	573	void kvm_inject_pit_timer_irqs(struct kvm_vcpu *vcpu)
	574	{
	575	struct kvm_pit *pit = vcpu->kvm->arch.vpit;
	576	struct kvm *kvm = vcpu->kvm;
	577	struct kvm_kpit_state *ps;
	578
	579	if (vcpu && pit) {
	580	ps = &pit->pit_state;
	581
	582	/* Try to inject pending interrupts when:
	583	* 1. Pending exists
	584	* 2. Last interrupt was accepted or waited for too long time*/
	585	if (atomic_read(&ps->pit_timer.pending) &&
	586	(ps->inject_pending \|\|
	587	(jiffies - ps->last_injected_time
	588	>= KVM_MAX_PIT_INTR_INTERVAL))) {
	589	ps->inject_pending = 0;
	590	__inject_pit_timer_intr(kvm);
	591	ps->last_injected_time = jiffies;
	592	}
	593	}
	594	}
	595
	596	void kvm_pit_timer_intr_post(struct kvm_vcpu *vcpu, int vec)
	597	{
	598	struct kvm_arch *arch = &vcpu->kvm->arch;
	599	struct kvm_kpit_state *ps;
	600
	601	if (vcpu && arch->vpit) {
	602	ps = &arch->vpit->pit_state;
	603	if (atomic_read(&ps->pit_timer.pending) &&
	604	(((arch->vpic->pics[0].imr & 1) == 0 &&
	605	arch->vpic->pics[0].irq_base == vec) \|\|
	606	(arch->vioapic->redirtbl[0].fields.vector == vec &&
	607	arch->vioapic->redirtbl[0].fields.mask != 1))) {
	608	ps->inject_pending = 1;
	609	atomic_dec(&ps->pit_timer.pending);
610	ps->channels[0].count_load_time = ktime_get();
611	}
612	}
613	}