Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 1991, 1992 Linus Torvalds |
a8c1be9d | 3 | * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs |
1da177e4 LT |
4 | * |
5 | * Pentium III FXSR, SSE support | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
8 | ||
9 | /* | |
c1d518c8 | 10 | * Handle hardware traps and faults. |
1da177e4 | 11 | */ |
b5964405 IM |
12 | #include <linux/interrupt.h> |
13 | #include <linux/kallsyms.h> | |
14 | #include <linux/spinlock.h> | |
b5964405 IM |
15 | #include <linux/kprobes.h> |
16 | #include <linux/uaccess.h> | |
17 | #include <linux/utsname.h> | |
18 | #include <linux/kdebug.h> | |
1da177e4 | 19 | #include <linux/kernel.h> |
b5964405 IM |
20 | #include <linux/module.h> |
21 | #include <linux/ptrace.h> | |
1da177e4 | 22 | #include <linux/string.h> |
b5964405 | 23 | #include <linux/delay.h> |
1da177e4 | 24 | #include <linux/errno.h> |
b5964405 IM |
25 | #include <linux/kexec.h> |
26 | #include <linux/sched.h> | |
1da177e4 | 27 | #include <linux/timer.h> |
1da177e4 | 28 | #include <linux/init.h> |
91768d6c | 29 | #include <linux/bug.h> |
b5964405 IM |
30 | #include <linux/nmi.h> |
31 | #include <linux/mm.h> | |
c1d518c8 AH |
32 | #include <linux/smp.h> |
33 | #include <linux/io.h> | |
1da177e4 LT |
34 | |
35 | #ifdef CONFIG_EISA | |
36 | #include <linux/ioport.h> | |
37 | #include <linux/eisa.h> | |
38 | #endif | |
39 | ||
40 | #ifdef CONFIG_MCA | |
41 | #include <linux/mca.h> | |
42 | #endif | |
43 | ||
c0d12172 DJ |
44 | #if defined(CONFIG_EDAC) |
45 | #include <linux/edac.h> | |
46 | #endif | |
47 | ||
b5964405 | 48 | #include <asm/stacktrace.h> |
1da177e4 | 49 | #include <asm/processor.h> |
1da177e4 | 50 | #include <asm/debugreg.h> |
b5964405 IM |
51 | #include <asm/atomic.h> |
52 | #include <asm/system.h> | |
c1d518c8 | 53 | #include <asm/traps.h> |
1da177e4 LT |
54 | #include <asm/desc.h> |
55 | #include <asm/i387.h> | |
c1d518c8 | 56 | |
1164dd00 | 57 | #include <asm/mach_traps.h> |
c1d518c8 | 58 | |
081f75bb AH |
59 | #ifdef CONFIG_X86_64 |
60 | #include <asm/pgalloc.h> | |
61 | #include <asm/proto.h> | |
081f75bb | 62 | #else |
c1d518c8 | 63 | #include <asm/processor-flags.h> |
8e6dafd6 | 64 | #include <asm/setup.h> |
6ac8d51f | 65 | #include <asm/traps.h> |
1da177e4 | 66 | |
eb642f62 | 67 | #include "cpu/mcheck/mce.h" |
1da177e4 LT |
68 | |
69 | asmlinkage int system_call(void); | |
70 | ||
1da177e4 | 71 | /* Do we ignore FPU interrupts ? */ |
b5964405 | 72 | char ignore_fpu_irq; |
1da177e4 LT |
73 | |
74 | /* | |
75 | * The IDT has to be page-aligned to simplify the Pentium | |
76 | * F0 0F bug workaround.. We have a special link segment | |
77 | * for this. | |
78 | */ | |
010d4f82 | 79 | gate_desc idt_table[256] |
6842ef0e | 80 | __attribute__((__section__(".data.idt"))) = { { { { 0, 0 } } }, }; |
081f75bb | 81 | #endif |
1da177e4 | 82 | |
b77b881f YL |
83 | DECLARE_BITMAP(used_vectors, NR_VECTORS); |
84 | EXPORT_SYMBOL_GPL(used_vectors); | |
85 | ||
badc7652 | 86 | static int ignore_nmis; |
e041c683 | 87 | |
762db434 AH |
88 | static inline void conditional_sti(struct pt_regs *regs) |
89 | { | |
90 | if (regs->flags & X86_EFLAGS_IF) | |
91 | local_irq_enable(); | |
92 | } | |
93 | ||
3d2a71a5 AH |
94 | static inline void preempt_conditional_sti(struct pt_regs *regs) |
95 | { | |
96 | inc_preempt_count(); | |
97 | if (regs->flags & X86_EFLAGS_IF) | |
98 | local_irq_enable(); | |
99 | } | |
100 | ||
be716615 TG |
101 | static inline void conditional_cli(struct pt_regs *regs) |
102 | { | |
103 | if (regs->flags & X86_EFLAGS_IF) | |
104 | local_irq_disable(); | |
105 | } | |
106 | ||
3d2a71a5 AH |
107 | static inline void preempt_conditional_cli(struct pt_regs *regs) |
108 | { | |
109 | if (regs->flags & X86_EFLAGS_IF) | |
110 | local_irq_disable(); | |
111 | dec_preempt_count(); | |
112 | } | |
113 | ||
081f75bb | 114 | #ifdef CONFIG_X86_32 |
b5964405 IM |
115 | static inline void |
116 | die_if_kernel(const char *str, struct pt_regs *regs, long err) | |
1da177e4 | 117 | { |
717b594a | 118 | if (!user_mode_vm(regs)) |
1da177e4 LT |
119 | die(str, regs, err); |
120 | } | |
081f75bb | 121 | #endif |
ae82157b | 122 | |
b5964405 | 123 | static void __kprobes |
3c1326f8 | 124 | do_trap(int trapnr, int signr, char *str, struct pt_regs *regs, |
b5964405 | 125 | long error_code, siginfo_t *info) |
1da177e4 | 126 | { |
4f339ecb | 127 | struct task_struct *tsk = current; |
4f339ecb | 128 | |
081f75bb | 129 | #ifdef CONFIG_X86_32 |
6b6891f9 | 130 | if (regs->flags & X86_VM_MASK) { |
3c1326f8 AH |
131 | /* |
132 | * traps 0, 1, 3, 4, and 5 should be forwarded to vm86. | |
133 | * On nmi (interrupt 2), do_trap should not be called. | |
134 | */ | |
135 | if (trapnr < 6) | |
1da177e4 LT |
136 | goto vm86_trap; |
137 | goto trap_signal; | |
138 | } | |
081f75bb | 139 | #endif |
1da177e4 | 140 | |
717b594a | 141 | if (!user_mode(regs)) |
1da177e4 LT |
142 | goto kernel_trap; |
143 | ||
081f75bb | 144 | #ifdef CONFIG_X86_32 |
b5964405 | 145 | trap_signal: |
081f75bb | 146 | #endif |
b5964405 IM |
147 | /* |
148 | * We want error_code and trap_no set for userspace faults and | |
149 | * kernelspace faults which result in die(), but not | |
150 | * kernelspace faults which are fixed up. die() gives the | |
151 | * process no chance to handle the signal and notice the | |
152 | * kernel fault information, so that won't result in polluting | |
153 | * the information about previously queued, but not yet | |
154 | * delivered, faults. See also do_general_protection below. | |
155 | */ | |
156 | tsk->thread.error_code = error_code; | |
157 | tsk->thread.trap_no = trapnr; | |
d1895183 | 158 | |
081f75bb AH |
159 | #ifdef CONFIG_X86_64 |
160 | if (show_unhandled_signals && unhandled_signal(tsk, signr) && | |
161 | printk_ratelimit()) { | |
162 | printk(KERN_INFO | |
163 | "%s[%d] trap %s ip:%lx sp:%lx error:%lx", | |
164 | tsk->comm, tsk->pid, str, | |
165 | regs->ip, regs->sp, error_code); | |
166 | print_vma_addr(" in ", regs->ip); | |
167 | printk("\n"); | |
168 | } | |
169 | #endif | |
170 | ||
b5964405 IM |
171 | if (info) |
172 | force_sig_info(signr, info, tsk); | |
173 | else | |
174 | force_sig(signr, tsk); | |
175 | return; | |
1da177e4 | 176 | |
b5964405 IM |
177 | kernel_trap: |
178 | if (!fixup_exception(regs)) { | |
179 | tsk->thread.error_code = error_code; | |
180 | tsk->thread.trap_no = trapnr; | |
181 | die(str, regs, error_code); | |
1da177e4 | 182 | } |
b5964405 | 183 | return; |
1da177e4 | 184 | |
081f75bb | 185 | #ifdef CONFIG_X86_32 |
b5964405 IM |
186 | vm86_trap: |
187 | if (handle_vm86_trap((struct kernel_vm86_regs *) regs, | |
188 | error_code, trapnr)) | |
189 | goto trap_signal; | |
190 | return; | |
081f75bb | 191 | #endif |
1da177e4 LT |
192 | } |
193 | ||
b5964405 | 194 | #define DO_ERROR(trapnr, signr, str, name) \ |
e407d620 | 195 | dotraplinkage void do_##name(struct pt_regs *regs, long error_code) \ |
b5964405 IM |
196 | { \ |
197 | if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) \ | |
a8c1be9d | 198 | == NOTIFY_STOP) \ |
b5964405 | 199 | return; \ |
61aef7d2 | 200 | conditional_sti(regs); \ |
3c1326f8 | 201 | do_trap(trapnr, signr, str, regs, error_code, NULL); \ |
1da177e4 LT |
202 | } |
203 | ||
3c1326f8 | 204 | #define DO_ERROR_INFO(trapnr, signr, str, name, sicode, siaddr) \ |
e407d620 | 205 | dotraplinkage void do_##name(struct pt_regs *regs, long error_code) \ |
b5964405 IM |
206 | { \ |
207 | siginfo_t info; \ | |
208 | info.si_signo = signr; \ | |
209 | info.si_errno = 0; \ | |
210 | info.si_code = sicode; \ | |
211 | info.si_addr = (void __user *)siaddr; \ | |
b5964405 | 212 | if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) \ |
a8c1be9d | 213 | == NOTIFY_STOP) \ |
b5964405 | 214 | return; \ |
61aef7d2 | 215 | conditional_sti(regs); \ |
3c1326f8 | 216 | do_trap(trapnr, signr, str, regs, error_code, &info); \ |
1da177e4 LT |
217 | } |
218 | ||
3c1326f8 AH |
219 | DO_ERROR_INFO(0, SIGFPE, "divide error", divide_error, FPE_INTDIV, regs->ip) |
220 | DO_ERROR(4, SIGSEGV, "overflow", overflow) | |
221 | DO_ERROR(5, SIGSEGV, "bounds", bounds) | |
222 | DO_ERROR_INFO(6, SIGILL, "invalid opcode", invalid_op, ILL_ILLOPN, regs->ip) | |
51bc1ed6 | 223 | DO_ERROR(9, SIGFPE, "coprocessor segment overrun", coprocessor_segment_overrun) |
6bf77bf9 | 224 | DO_ERROR(10, SIGSEGV, "invalid TSS", invalid_TSS) |
36d936c7 | 225 | DO_ERROR(11, SIGBUS, "segment not present", segment_not_present) |
081f75bb | 226 | #ifdef CONFIG_X86_32 |
f5ca8187 | 227 | DO_ERROR(12, SIGBUS, "stack segment", stack_segment) |
081f75bb | 228 | #endif |
3c1326f8 | 229 | DO_ERROR_INFO(17, SIGBUS, "alignment check", alignment_check, BUS_ADRALN, 0) |
1da177e4 | 230 | |
081f75bb AH |
231 | #ifdef CONFIG_X86_64 |
232 | /* Runs on IST stack */ | |
233 | dotraplinkage void do_stack_segment(struct pt_regs *regs, long error_code) | |
234 | { | |
235 | if (notify_die(DIE_TRAP, "stack segment", regs, error_code, | |
236 | 12, SIGBUS) == NOTIFY_STOP) | |
237 | return; | |
238 | preempt_conditional_sti(regs); | |
239 | do_trap(12, SIGBUS, "stack segment", regs, error_code, NULL); | |
240 | preempt_conditional_cli(regs); | |
241 | } | |
242 | ||
243 | dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code) | |
244 | { | |
245 | static const char str[] = "double fault"; | |
246 | struct task_struct *tsk = current; | |
247 | ||
248 | /* Return not checked because double check cannot be ignored */ | |
249 | notify_die(DIE_TRAP, str, regs, error_code, 8, SIGSEGV); | |
250 | ||
251 | tsk->thread.error_code = error_code; | |
252 | tsk->thread.trap_no = 8; | |
253 | ||
bd8b96df IM |
254 | /* |
255 | * This is always a kernel trap and never fixable (and thus must | |
256 | * never return). | |
257 | */ | |
081f75bb AH |
258 | for (;;) |
259 | die(str, regs, error_code); | |
260 | } | |
261 | #endif | |
262 | ||
e407d620 | 263 | dotraplinkage void __kprobes |
13485ab5 | 264 | do_general_protection(struct pt_regs *regs, long error_code) |
1da177e4 | 265 | { |
13485ab5 | 266 | struct task_struct *tsk; |
b5964405 | 267 | |
c6df0d71 AH |
268 | conditional_sti(regs); |
269 | ||
081f75bb | 270 | #ifdef CONFIG_X86_32 |
6b6891f9 | 271 | if (regs->flags & X86_VM_MASK) |
1da177e4 | 272 | goto gp_in_vm86; |
081f75bb | 273 | #endif |
1da177e4 | 274 | |
13485ab5 | 275 | tsk = current; |
717b594a | 276 | if (!user_mode(regs)) |
1da177e4 LT |
277 | goto gp_in_kernel; |
278 | ||
13485ab5 AH |
279 | tsk->thread.error_code = error_code; |
280 | tsk->thread.trap_no = 13; | |
b5964405 | 281 | |
13485ab5 AH |
282 | if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) && |
283 | printk_ratelimit()) { | |
abd4f750 | 284 | printk(KERN_INFO |
13485ab5 AH |
285 | "%s[%d] general protection ip:%lx sp:%lx error:%lx", |
286 | tsk->comm, task_pid_nr(tsk), | |
287 | regs->ip, regs->sp, error_code); | |
03252919 AK |
288 | print_vma_addr(" in ", regs->ip); |
289 | printk("\n"); | |
290 | } | |
abd4f750 | 291 | |
13485ab5 | 292 | force_sig(SIGSEGV, tsk); |
1da177e4 LT |
293 | return; |
294 | ||
081f75bb | 295 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
296 | gp_in_vm86: |
297 | local_irq_enable(); | |
298 | handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code); | |
299 | return; | |
081f75bb | 300 | #endif |
1da177e4 LT |
301 | |
302 | gp_in_kernel: | |
13485ab5 AH |
303 | if (fixup_exception(regs)) |
304 | return; | |
305 | ||
306 | tsk->thread.error_code = error_code; | |
307 | tsk->thread.trap_no = 13; | |
308 | if (notify_die(DIE_GPF, "general protection fault", regs, | |
1da177e4 | 309 | error_code, 13, SIGSEGV) == NOTIFY_STOP) |
13485ab5 AH |
310 | return; |
311 | die("general protection fault", regs, error_code); | |
1da177e4 LT |
312 | } |
313 | ||
5deb45e3 | 314 | static notrace __kprobes void |
b5964405 | 315 | mem_parity_error(unsigned char reason, struct pt_regs *regs) |
1da177e4 | 316 | { |
b5964405 IM |
317 | printk(KERN_EMERG |
318 | "Uhhuh. NMI received for unknown reason %02x on CPU %d.\n", | |
319 | reason, smp_processor_id()); | |
320 | ||
321 | printk(KERN_EMERG | |
322 | "You have some hardware problem, likely on the PCI bus.\n"); | |
c0d12172 DJ |
323 | |
324 | #if defined(CONFIG_EDAC) | |
b5964405 | 325 | if (edac_handler_set()) { |
c0d12172 DJ |
326 | edac_atomic_assert_error(); |
327 | return; | |
328 | } | |
329 | #endif | |
330 | ||
8da5adda | 331 | if (panic_on_unrecovered_nmi) |
b5964405 | 332 | panic("NMI: Not continuing"); |
1da177e4 | 333 | |
c41c5cd3 | 334 | printk(KERN_EMERG "Dazed and confused, but trying to continue\n"); |
1da177e4 LT |
335 | |
336 | /* Clear and disable the memory parity error line. */ | |
7970479c AH |
337 | reason = (reason & 0xf) | 4; |
338 | outb(reason, 0x61); | |
1da177e4 LT |
339 | } |
340 | ||
5deb45e3 | 341 | static notrace __kprobes void |
b5964405 | 342 | io_check_error(unsigned char reason, struct pt_regs *regs) |
1da177e4 LT |
343 | { |
344 | unsigned long i; | |
345 | ||
9c107805 | 346 | printk(KERN_EMERG "NMI: IOCK error (debug interrupt?)\n"); |
1da177e4 LT |
347 | show_registers(regs); |
348 | ||
349 | /* Re-enable the IOCK line, wait for a few seconds */ | |
350 | reason = (reason & 0xf) | 8; | |
351 | outb(reason, 0x61); | |
b5964405 | 352 | |
1da177e4 | 353 | i = 2000; |
b5964405 IM |
354 | while (--i) |
355 | udelay(1000); | |
356 | ||
1da177e4 LT |
357 | reason &= ~8; |
358 | outb(reason, 0x61); | |
359 | } | |
360 | ||
5deb45e3 | 361 | static notrace __kprobes void |
b5964405 | 362 | unknown_nmi_error(unsigned char reason, struct pt_regs *regs) |
1da177e4 | 363 | { |
c1d518c8 AH |
364 | if (notify_die(DIE_NMIUNKNOWN, "nmi", regs, reason, 2, SIGINT) == |
365 | NOTIFY_STOP) | |
d3597524 | 366 | return; |
1da177e4 | 367 | #ifdef CONFIG_MCA |
b5964405 IM |
368 | /* |
369 | * Might actually be able to figure out what the guilty party | |
370 | * is: | |
371 | */ | |
372 | if (MCA_bus) { | |
1da177e4 LT |
373 | mca_handle_nmi(); |
374 | return; | |
375 | } | |
376 | #endif | |
b5964405 IM |
377 | printk(KERN_EMERG |
378 | "Uhhuh. NMI received for unknown reason %02x on CPU %d.\n", | |
379 | reason, smp_processor_id()); | |
380 | ||
c41c5cd3 | 381 | printk(KERN_EMERG "Do you have a strange power saving mode enabled?\n"); |
8da5adda | 382 | if (panic_on_unrecovered_nmi) |
b5964405 | 383 | panic("NMI: Not continuing"); |
8da5adda | 384 | |
c41c5cd3 | 385 | printk(KERN_EMERG "Dazed and confused, but trying to continue\n"); |
1da177e4 LT |
386 | } |
387 | ||
5deb45e3 | 388 | static notrace __kprobes void default_do_nmi(struct pt_regs *regs) |
1da177e4 LT |
389 | { |
390 | unsigned char reason = 0; | |
abd34807 AH |
391 | int cpu; |
392 | ||
393 | cpu = smp_processor_id(); | |
1da177e4 | 394 | |
abd34807 AH |
395 | /* Only the BSP gets external NMIs from the system. */ |
396 | if (!cpu) | |
1da177e4 | 397 | reason = get_nmi_reason(); |
b5964405 | 398 | |
1da177e4 | 399 | if (!(reason & 0xc0)) { |
20c0d2d4 | 400 | if (notify_die(DIE_NMI_IPI, "nmi_ipi", regs, reason, 2, SIGINT) |
a8c1be9d | 401 | == NOTIFY_STOP) |
1da177e4 LT |
402 | return; |
403 | #ifdef CONFIG_X86_LOCAL_APIC | |
404 | /* | |
405 | * Ok, so this is none of the documented NMI sources, | |
406 | * so it must be the NMI watchdog. | |
407 | */ | |
3adbbcce | 408 | if (nmi_watchdog_tick(regs, reason)) |
1da177e4 | 409 | return; |
abd34807 | 410 | if (!do_nmi_callback(regs, cpu)) |
3adbbcce | 411 | unknown_nmi_error(reason, regs); |
b5964405 IM |
412 | #else |
413 | unknown_nmi_error(reason, regs); | |
414 | #endif | |
2fbe7b25 | 415 | |
1da177e4 LT |
416 | return; |
417 | } | |
20c0d2d4 | 418 | if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT) == NOTIFY_STOP) |
1da177e4 | 419 | return; |
a8c1be9d AH |
420 | |
421 | /* AK: following checks seem to be broken on modern chipsets. FIXME */ | |
1da177e4 LT |
422 | if (reason & 0x80) |
423 | mem_parity_error(reason, regs); | |
424 | if (reason & 0x40) | |
425 | io_check_error(reason, regs); | |
081f75bb | 426 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
427 | /* |
428 | * Reassert NMI in case it became active meanwhile | |
b5964405 | 429 | * as it's edge-triggered: |
1da177e4 LT |
430 | */ |
431 | reassert_nmi(); | |
081f75bb | 432 | #endif |
1da177e4 LT |
433 | } |
434 | ||
e407d620 AH |
435 | dotraplinkage notrace __kprobes void |
436 | do_nmi(struct pt_regs *regs, long error_code) | |
1da177e4 | 437 | { |
1da177e4 LT |
438 | nmi_enter(); |
439 | ||
915b0d01 | 440 | inc_irq_stat(__nmi_count); |
1da177e4 | 441 | |
8f4e956b AK |
442 | if (!ignore_nmis) |
443 | default_do_nmi(regs); | |
1da177e4 LT |
444 | |
445 | nmi_exit(); | |
446 | } | |
447 | ||
8f4e956b AK |
448 | void stop_nmi(void) |
449 | { | |
450 | acpi_nmi_disable(); | |
451 | ignore_nmis++; | |
452 | } | |
453 | ||
454 | void restart_nmi(void) | |
455 | { | |
456 | ignore_nmis--; | |
457 | acpi_nmi_enable(); | |
458 | } | |
459 | ||
c1d518c8 | 460 | /* May run on IST stack. */ |
e407d620 | 461 | dotraplinkage void __kprobes do_int3(struct pt_regs *regs, long error_code) |
1da177e4 | 462 | { |
b94da1e4 | 463 | #ifdef CONFIG_KPROBES |
1da177e4 LT |
464 | if (notify_die(DIE_INT3, "int3", regs, error_code, 3, SIGTRAP) |
465 | == NOTIFY_STOP) | |
48c88211 | 466 | return; |
b94da1e4 AH |
467 | #else |
468 | if (notify_die(DIE_TRAP, "int3", regs, error_code, 3, SIGTRAP) | |
469 | == NOTIFY_STOP) | |
470 | return; | |
471 | #endif | |
b5964405 | 472 | |
4915a35e | 473 | preempt_conditional_sti(regs); |
3c1326f8 | 474 | do_trap(3, SIGTRAP, "int3", regs, error_code, NULL); |
4915a35e | 475 | preempt_conditional_cli(regs); |
1da177e4 | 476 | } |
1da177e4 | 477 | |
081f75bb | 478 | #ifdef CONFIG_X86_64 |
bd8b96df IM |
479 | /* |
480 | * Help handler running on IST stack to switch back to user stack | |
481 | * for scheduling or signal handling. The actual stack switch is done in | |
482 | * entry.S | |
483 | */ | |
081f75bb AH |
484 | asmlinkage __kprobes struct pt_regs *sync_regs(struct pt_regs *eregs) |
485 | { | |
486 | struct pt_regs *regs = eregs; | |
487 | /* Did already sync */ | |
488 | if (eregs == (struct pt_regs *)eregs->sp) | |
489 | ; | |
490 | /* Exception from user space */ | |
491 | else if (user_mode(eregs)) | |
492 | regs = task_pt_regs(current); | |
bd8b96df IM |
493 | /* |
494 | * Exception from kernel and interrupts are enabled. Move to | |
495 | * kernel process stack. | |
496 | */ | |
081f75bb AH |
497 | else if (eregs->flags & X86_EFLAGS_IF) |
498 | regs = (struct pt_regs *)(eregs->sp -= sizeof(struct pt_regs)); | |
499 | if (eregs != regs) | |
500 | *regs = *eregs; | |
501 | return regs; | |
502 | } | |
503 | #endif | |
504 | ||
1da177e4 LT |
505 | /* |
506 | * Our handling of the processor debug registers is non-trivial. | |
507 | * We do not clear them on entry and exit from the kernel. Therefore | |
508 | * it is possible to get a watchpoint trap here from inside the kernel. | |
509 | * However, the code in ./ptrace.c has ensured that the user can | |
510 | * only set watchpoints on userspace addresses. Therefore the in-kernel | |
511 | * watchpoint trap can only occur in code which is reading/writing | |
512 | * from user space. Such code must not hold kernel locks (since it | |
513 | * can equally take a page fault), therefore it is safe to call | |
514 | * force_sig_info even though that claims and releases locks. | |
b5964405 | 515 | * |
1da177e4 LT |
516 | * Code in ./signal.c ensures that the debug control register |
517 | * is restored before we deliver any signal, and therefore that | |
518 | * user code runs with the correct debug control register even though | |
519 | * we clear it here. | |
520 | * | |
521 | * Being careful here means that we don't have to be as careful in a | |
522 | * lot of more complicated places (task switching can be a bit lazy | |
523 | * about restoring all the debug state, and ptrace doesn't have to | |
524 | * find every occurrence of the TF bit that could be saved away even | |
525 | * by user code) | |
c1d518c8 AH |
526 | * |
527 | * May run on IST stack. | |
1da177e4 | 528 | */ |
e407d620 | 529 | dotraplinkage void __kprobes do_debug(struct pt_regs *regs, long error_code) |
1da177e4 | 530 | { |
1da177e4 | 531 | struct task_struct *tsk = current; |
08d68323 | 532 | unsigned long dr6; |
da654b74 | 533 | int si_code; |
1da177e4 | 534 | |
08d68323 | 535 | get_debugreg(dr6, 6); |
1da177e4 | 536 | |
08d68323 P |
537 | /* DR6 may or may not be cleared by the CPU */ |
538 | set_debugreg(0, 6); | |
10faa81e RM |
539 | /* |
540 | * The processor cleared BTF, so don't mark that we need it set. | |
541 | */ | |
542 | clear_tsk_thread_flag(tsk, TIF_DEBUGCTLMSR); | |
543 | tsk->thread.debugctlmsr = 0; | |
544 | ||
08d68323 P |
545 | /* Store the virtualized DR6 value */ |
546 | tsk->thread.debugreg6 = dr6; | |
547 | ||
62edab90 P |
548 | if (notify_die(DIE_DEBUG, "debug", regs, PTR_ERR(&dr6), error_code, |
549 | SIGTRAP) == NOTIFY_STOP) | |
1da177e4 | 550 | return; |
3d2a71a5 | 551 | |
1da177e4 | 552 | /* It's safe to allow irq's after DR6 has been saved */ |
3d2a71a5 | 553 | preempt_conditional_sti(regs); |
1da177e4 | 554 | |
08d68323 P |
555 | if (regs->flags & X86_VM_MASK) { |
556 | handle_vm86_trap((struct kernel_vm86_regs *) regs, | |
557 | error_code, 1); | |
558 | return; | |
1da177e4 LT |
559 | } |
560 | ||
1da177e4 | 561 | /* |
08d68323 P |
562 | * Single-stepping through system calls: ignore any exceptions in |
563 | * kernel space, but re-enable TF when returning to user mode. | |
564 | * | |
565 | * We already checked v86 mode above, so we can check for kernel mode | |
566 | * by just checking the CPL of CS. | |
1da177e4 | 567 | */ |
08d68323 P |
568 | if ((dr6 & DR_STEP) && !user_mode(regs)) { |
569 | tsk->thread.debugreg6 &= ~DR_STEP; | |
570 | set_tsk_thread_flag(tsk, TIF_SINGLESTEP); | |
571 | regs->flags &= ~X86_EFLAGS_TF; | |
1da177e4 | 572 | } |
08d68323 P |
573 | si_code = get_si_code(tsk->thread.debugreg6); |
574 | if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS)) | |
575 | send_sigtrap(tsk, regs, error_code, si_code); | |
3d2a71a5 | 576 | preempt_conditional_cli(regs); |
1da177e4 | 577 | |
1da177e4 LT |
578 | return; |
579 | } | |
580 | ||
081f75bb AH |
581 | #ifdef CONFIG_X86_64 |
582 | static int kernel_math_error(struct pt_regs *regs, const char *str, int trapnr) | |
583 | { | |
584 | if (fixup_exception(regs)) | |
585 | return 1; | |
586 | ||
587 | notify_die(DIE_GPF, str, regs, 0, trapnr, SIGFPE); | |
588 | /* Illegal floating point operation in the kernel */ | |
589 | current->thread.trap_no = trapnr; | |
590 | die(str, regs, 0); | |
591 | return 0; | |
592 | } | |
593 | #endif | |
594 | ||
1da177e4 LT |
595 | /* |
596 | * Note that we play around with the 'TS' bit in an attempt to get | |
597 | * the correct behaviour even in the presence of the asynchronous | |
598 | * IRQ13 behaviour | |
599 | */ | |
65ea5b03 | 600 | void math_error(void __user *ip) |
1da177e4 | 601 | { |
b5964405 | 602 | struct task_struct *task; |
1da177e4 | 603 | siginfo_t info; |
adf77bac | 604 | unsigned short cwd, swd, err; |
1da177e4 LT |
605 | |
606 | /* | |
607 | * Save the info for the exception handler and clear the error. | |
608 | */ | |
609 | task = current; | |
610 | save_init_fpu(task); | |
611 | task->thread.trap_no = 16; | |
612 | task->thread.error_code = 0; | |
613 | info.si_signo = SIGFPE; | |
614 | info.si_errno = 0; | |
65ea5b03 | 615 | info.si_addr = ip; |
1da177e4 LT |
616 | /* |
617 | * (~cwd & swd) will mask out exceptions that are not set to unmasked | |
618 | * status. 0x3f is the exception bits in these regs, 0x200 is the | |
619 | * C1 reg you need in case of a stack fault, 0x040 is the stack | |
620 | * fault bit. We should only be taking one exception at a time, | |
621 | * so if this combination doesn't produce any single exception, | |
a8c1be9d | 622 | * then we have a bad program that isn't synchronizing its FPU usage |
1da177e4 LT |
623 | * and it will suffer the consequences since we won't be able to |
624 | * fully reproduce the context of the exception | |
625 | */ | |
626 | cwd = get_fpu_cwd(task); | |
627 | swd = get_fpu_swd(task); | |
adf77bac | 628 | |
a73ad333 | 629 | err = swd & ~cwd; |
adf77bac PA |
630 | |
631 | if (err & 0x001) { /* Invalid op */ | |
b5964405 IM |
632 | /* |
633 | * swd & 0x240 == 0x040: Stack Underflow | |
634 | * swd & 0x240 == 0x240: Stack Overflow | |
635 | * User must clear the SF bit (0x40) if set | |
636 | */ | |
637 | info.si_code = FPE_FLTINV; | |
adf77bac | 638 | } else if (err & 0x004) { /* Divide by Zero */ |
b5964405 | 639 | info.si_code = FPE_FLTDIV; |
adf77bac | 640 | } else if (err & 0x008) { /* Overflow */ |
b5964405 | 641 | info.si_code = FPE_FLTOVF; |
adf77bac PA |
642 | } else if (err & 0x012) { /* Denormal, Underflow */ |
643 | info.si_code = FPE_FLTUND; | |
644 | } else if (err & 0x020) { /* Precision */ | |
b5964405 | 645 | info.si_code = FPE_FLTRES; |
adf77bac | 646 | } else { |
bd8b96df IM |
647 | /* |
648 | * If we're using IRQ 13, or supposedly even some trap 16 | |
649 | * implementations, it's possible we get a spurious trap... | |
650 | */ | |
a73ad333 | 651 | return; /* Spurious trap, no error */ |
1da177e4 LT |
652 | } |
653 | force_sig_info(SIGFPE, &info, task); | |
654 | } | |
655 | ||
e407d620 | 656 | dotraplinkage void do_coprocessor_error(struct pt_regs *regs, long error_code) |
1da177e4 | 657 | { |
252d28fe | 658 | conditional_sti(regs); |
081f75bb AH |
659 | |
660 | #ifdef CONFIG_X86_32 | |
1da177e4 | 661 | ignore_fpu_irq = 1; |
081f75bb AH |
662 | #else |
663 | if (!user_mode(regs) && | |
664 | kernel_math_error(regs, "kernel x87 math error", 16)) | |
665 | return; | |
666 | #endif | |
667 | ||
65ea5b03 | 668 | math_error((void __user *)regs->ip); |
1da177e4 LT |
669 | } |
670 | ||
65ea5b03 | 671 | static void simd_math_error(void __user *ip) |
1da177e4 | 672 | { |
b5964405 | 673 | struct task_struct *task; |
b5964405 | 674 | siginfo_t info; |
7b4fd4bb | 675 | unsigned short mxcsr; |
1da177e4 LT |
676 | |
677 | /* | |
678 | * Save the info for the exception handler and clear the error. | |
679 | */ | |
680 | task = current; | |
681 | save_init_fpu(task); | |
682 | task->thread.trap_no = 19; | |
683 | task->thread.error_code = 0; | |
684 | info.si_signo = SIGFPE; | |
685 | info.si_errno = 0; | |
686 | info.si_code = __SI_FAULT; | |
65ea5b03 | 687 | info.si_addr = ip; |
1da177e4 LT |
688 | /* |
689 | * The SIMD FPU exceptions are handled a little differently, as there | |
690 | * is only a single status/control register. Thus, to determine which | |
691 | * unmasked exception was caught we must mask the exception mask bits | |
692 | * at 0x1f80, and then use these to mask the exception bits at 0x3f. | |
693 | */ | |
694 | mxcsr = get_fpu_mxcsr(task); | |
695 | switch (~((mxcsr & 0x1f80) >> 7) & (mxcsr & 0x3f)) { | |
b5964405 IM |
696 | case 0x000: |
697 | default: | |
698 | break; | |
699 | case 0x001: /* Invalid Op */ | |
700 | info.si_code = FPE_FLTINV; | |
701 | break; | |
702 | case 0x002: /* Denormalize */ | |
703 | case 0x010: /* Underflow */ | |
704 | info.si_code = FPE_FLTUND; | |
705 | break; | |
706 | case 0x004: /* Zero Divide */ | |
707 | info.si_code = FPE_FLTDIV; | |
708 | break; | |
709 | case 0x008: /* Overflow */ | |
710 | info.si_code = FPE_FLTOVF; | |
711 | break; | |
712 | case 0x020: /* Precision */ | |
713 | info.si_code = FPE_FLTRES; | |
714 | break; | |
1da177e4 LT |
715 | } |
716 | force_sig_info(SIGFPE, &info, task); | |
717 | } | |
718 | ||
e407d620 AH |
719 | dotraplinkage void |
720 | do_simd_coprocessor_error(struct pt_regs *regs, long error_code) | |
1da177e4 | 721 | { |
b939bde2 AH |
722 | conditional_sti(regs); |
723 | ||
081f75bb | 724 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
725 | if (cpu_has_xmm) { |
726 | /* Handle SIMD FPU exceptions on PIII+ processors. */ | |
727 | ignore_fpu_irq = 1; | |
65ea5b03 | 728 | simd_math_error((void __user *)regs->ip); |
b5964405 IM |
729 | return; |
730 | } | |
731 | /* | |
732 | * Handle strange cache flush from user space exception | |
733 | * in all other cases. This is undocumented behaviour. | |
734 | */ | |
6b6891f9 | 735 | if (regs->flags & X86_VM_MASK) { |
b5964405 IM |
736 | handle_vm86_fault((struct kernel_vm86_regs *)regs, error_code); |
737 | return; | |
1da177e4 | 738 | } |
b5964405 IM |
739 | current->thread.trap_no = 19; |
740 | current->thread.error_code = error_code; | |
741 | die_if_kernel("cache flush denied", regs, error_code); | |
742 | force_sig(SIGSEGV, current); | |
081f75bb AH |
743 | #else |
744 | if (!user_mode(regs) && | |
745 | kernel_math_error(regs, "kernel simd math error", 19)) | |
746 | return; | |
747 | simd_math_error((void __user *)regs->ip); | |
748 | #endif | |
1da177e4 LT |
749 | } |
750 | ||
e407d620 AH |
751 | dotraplinkage void |
752 | do_spurious_interrupt_bug(struct pt_regs *regs, long error_code) | |
1da177e4 | 753 | { |
cf81978d | 754 | conditional_sti(regs); |
1da177e4 LT |
755 | #if 0 |
756 | /* No need to warn about this any longer. */ | |
b5964405 | 757 | printk(KERN_INFO "Ignoring P6 Local APIC Spurious Interrupt Bug...\n"); |
1da177e4 LT |
758 | #endif |
759 | } | |
760 | ||
081f75bb | 761 | #ifdef CONFIG_X86_32 |
b5964405 | 762 | unsigned long patch_espfix_desc(unsigned long uesp, unsigned long kesp) |
1da177e4 | 763 | { |
736f12bf | 764 | struct desc_struct *gdt = get_cpu_gdt_table(smp_processor_id()); |
be44d2aa SS |
765 | unsigned long base = (kesp - uesp) & -THREAD_SIZE; |
766 | unsigned long new_kesp = kesp - base; | |
767 | unsigned long lim_pages = (new_kesp | (THREAD_SIZE - 1)) >> PAGE_SHIFT; | |
768 | __u64 desc = *(__u64 *)&gdt[GDT_ENTRY_ESPFIX_SS]; | |
b5964405 | 769 | |
be44d2aa | 770 | /* Set up base for espfix segment */ |
b5964405 IM |
771 | desc &= 0x00f0ff0000000000ULL; |
772 | desc |= ((((__u64)base) << 16) & 0x000000ffffff0000ULL) | | |
be44d2aa SS |
773 | ((((__u64)base) << 32) & 0xff00000000000000ULL) | |
774 | ((((__u64)lim_pages) << 32) & 0x000f000000000000ULL) | | |
775 | (lim_pages & 0xffff); | |
776 | *(__u64 *)&gdt[GDT_ENTRY_ESPFIX_SS] = desc; | |
b5964405 | 777 | |
be44d2aa | 778 | return new_kesp; |
1da177e4 | 779 | } |
081f75bb AH |
780 | #else |
781 | asmlinkage void __attribute__((weak)) smp_thermal_interrupt(void) | |
782 | { | |
783 | } | |
784 | ||
785 | asmlinkage void __attribute__((weak)) mce_threshold_interrupt(void) | |
786 | { | |
787 | } | |
788 | #endif | |
1da177e4 LT |
789 | |
790 | /* | |
b5964405 | 791 | * 'math_state_restore()' saves the current math information in the |
1da177e4 LT |
792 | * old math state array, and gets the new ones from the current task |
793 | * | |
794 | * Careful.. There are problems with IBM-designed IRQ13 behaviour. | |
795 | * Don't touch unless you *really* know how it works. | |
796 | * | |
797 | * Must be called with kernel preemption disabled (in this case, | |
798 | * local interrupts are disabled at the call-site in entry.S). | |
799 | */ | |
acc20761 | 800 | asmlinkage void math_state_restore(void) |
1da177e4 LT |
801 | { |
802 | struct thread_info *thread = current_thread_info(); | |
803 | struct task_struct *tsk = thread->task; | |
804 | ||
aa283f49 SS |
805 | if (!tsk_used_math(tsk)) { |
806 | local_irq_enable(); | |
807 | /* | |
808 | * does a slab alloc which can sleep | |
809 | */ | |
810 | if (init_fpu(tsk)) { | |
811 | /* | |
812 | * ran out of memory! | |
813 | */ | |
814 | do_group_exit(SIGKILL); | |
815 | return; | |
816 | } | |
817 | local_irq_disable(); | |
818 | } | |
819 | ||
b5964405 | 820 | clts(); /* Allow maths ops (or we recurse) */ |
081f75bb | 821 | #ifdef CONFIG_X86_32 |
1da177e4 | 822 | restore_fpu(tsk); |
081f75bb AH |
823 | #else |
824 | /* | |
825 | * Paranoid restore. send a SIGSEGV if we fail to restore the state. | |
826 | */ | |
827 | if (unlikely(restore_fpu_checking(tsk))) { | |
828 | stts(); | |
829 | force_sig(SIGSEGV, tsk); | |
830 | return; | |
831 | } | |
832 | #endif | |
1da177e4 | 833 | thread->status |= TS_USEDFPU; /* So we fnsave on switch_to() */ |
acc20761 | 834 | tsk->fpu_counter++; |
1da177e4 | 835 | } |
5992b6da | 836 | EXPORT_SYMBOL_GPL(math_state_restore); |
1da177e4 LT |
837 | |
838 | #ifndef CONFIG_MATH_EMULATION | |
d315760f | 839 | void math_emulate(struct math_emu_info *info) |
1da177e4 | 840 | { |
b5964405 IM |
841 | printk(KERN_EMERG |
842 | "math-emulation not enabled and no coprocessor found.\n"); | |
843 | printk(KERN_EMERG "killing %s.\n", current->comm); | |
844 | force_sig(SIGFPE, current); | |
1da177e4 LT |
845 | schedule(); |
846 | } | |
1da177e4 LT |
847 | #endif /* CONFIG_MATH_EMULATION */ |
848 | ||
e407d620 | 849 | dotraplinkage void __kprobes |
aa78bcfa | 850 | do_device_not_available(struct pt_regs *regs, long error_code) |
7643e9b9 | 851 | { |
081f75bb | 852 | #ifdef CONFIG_X86_32 |
7643e9b9 | 853 | if (read_cr0() & X86_CR0_EM) { |
d315760f TH |
854 | struct math_emu_info info = { }; |
855 | ||
7643e9b9 | 856 | conditional_sti(regs); |
d315760f | 857 | |
aa78bcfa | 858 | info.regs = regs; |
d315760f | 859 | math_emulate(&info); |
7643e9b9 AH |
860 | } else { |
861 | math_state_restore(); /* interrupts still off */ | |
862 | conditional_sti(regs); | |
863 | } | |
081f75bb AH |
864 | #else |
865 | math_state_restore(); | |
866 | #endif | |
7643e9b9 AH |
867 | } |
868 | ||
081f75bb | 869 | #ifdef CONFIG_X86_32 |
e407d620 | 870 | dotraplinkage void do_iret_error(struct pt_regs *regs, long error_code) |
f8e0870f AH |
871 | { |
872 | siginfo_t info; | |
873 | local_irq_enable(); | |
874 | ||
875 | info.si_signo = SIGILL; | |
876 | info.si_errno = 0; | |
877 | info.si_code = ILL_BADSTK; | |
fc6fcdfb | 878 | info.si_addr = NULL; |
f8e0870f AH |
879 | if (notify_die(DIE_TRAP, "iret exception", |
880 | regs, error_code, 32, SIGILL) == NOTIFY_STOP) | |
881 | return; | |
3c1326f8 | 882 | do_trap(32, SIGILL, "iret exception", regs, error_code, &info); |
f8e0870f | 883 | } |
081f75bb | 884 | #endif |
f8e0870f | 885 | |
1da177e4 LT |
886 | void __init trap_init(void) |
887 | { | |
dbeb2be2 RR |
888 | int i; |
889 | ||
1da177e4 | 890 | #ifdef CONFIG_EISA |
927222b1 | 891 | void __iomem *p = early_ioremap(0x0FFFD9, 4); |
b5964405 IM |
892 | |
893 | if (readl(p) == 'E' + ('I'<<8) + ('S'<<16) + ('A'<<24)) | |
1da177e4 | 894 | EISA_bus = 1; |
927222b1 | 895 | early_iounmap(p, 4); |
1da177e4 LT |
896 | #endif |
897 | ||
976382dc | 898 | set_intr_gate(0, ÷_error); |
699d2937 AH |
899 | set_intr_gate_ist(1, &debug, DEBUG_STACK); |
900 | set_intr_gate_ist(2, &nmi, NMI_STACK); | |
901 | /* int3 can be called from all */ | |
902 | set_system_intr_gate_ist(3, &int3, DEBUG_STACK); | |
903 | /* int4 can be called from all */ | |
904 | set_system_intr_gate(4, &overflow); | |
64f644c0 | 905 | set_intr_gate(5, &bounds); |
12394cf5 | 906 | set_intr_gate(6, &invalid_op); |
7643e9b9 | 907 | set_intr_gate(7, &device_not_available); |
081f75bb | 908 | #ifdef CONFIG_X86_32 |
a8c1be9d | 909 | set_task_gate(8, GDT_ENTRY_DOUBLEFAULT_TSS); |
081f75bb AH |
910 | #else |
911 | set_intr_gate_ist(8, &double_fault, DOUBLEFAULT_STACK); | |
912 | #endif | |
51bc1ed6 | 913 | set_intr_gate(9, &coprocessor_segment_overrun); |
6bf77bf9 | 914 | set_intr_gate(10, &invalid_TSS); |
36d936c7 | 915 | set_intr_gate(11, &segment_not_present); |
699d2937 | 916 | set_intr_gate_ist(12, &stack_segment, STACKFAULT_STACK); |
c6df0d71 | 917 | set_intr_gate(13, &general_protection); |
b5964405 | 918 | set_intr_gate(14, &page_fault); |
cf81978d | 919 | set_intr_gate(15, &spurious_interrupt_bug); |
252d28fe | 920 | set_intr_gate(16, &coprocessor_error); |
5feedfd4 | 921 | set_intr_gate(17, &alignment_check); |
1da177e4 | 922 | #ifdef CONFIG_X86_MCE |
699d2937 | 923 | set_intr_gate_ist(18, &machine_check, MCE_STACK); |
1da177e4 | 924 | #endif |
b939bde2 | 925 | set_intr_gate(19, &simd_coprocessor_error); |
1da177e4 | 926 | |
081f75bb AH |
927 | #ifdef CONFIG_IA32_EMULATION |
928 | set_system_intr_gate(IA32_SYSCALL_VECTOR, ia32_syscall); | |
929 | #endif | |
930 | ||
931 | #ifdef CONFIG_X86_32 | |
d43c6e80 | 932 | if (cpu_has_fxsr) { |
d43c6e80 JB |
933 | printk(KERN_INFO "Enabling fast FPU save and restore... "); |
934 | set_in_cr4(X86_CR4_OSFXSR); | |
935 | printk("done.\n"); | |
936 | } | |
937 | if (cpu_has_xmm) { | |
b5964405 IM |
938 | printk(KERN_INFO |
939 | "Enabling unmasked SIMD FPU exception support... "); | |
d43c6e80 JB |
940 | set_in_cr4(X86_CR4_OSXMMEXCPT); |
941 | printk("done.\n"); | |
942 | } | |
943 | ||
699d2937 | 944 | set_system_trap_gate(SYSCALL_VECTOR, &system_call); |
b77b881f | 945 | #endif |
1da177e4 | 946 | |
b5964405 | 947 | /* Reserve all the builtin and the syscall vector: */ |
dbeb2be2 RR |
948 | for (i = 0; i < FIRST_EXTERNAL_VECTOR; i++) |
949 | set_bit(i, used_vectors); | |
b5964405 | 950 | |
b77b881f YL |
951 | #ifdef CONFIG_X86_64 |
952 | set_bit(IA32_SYSCALL_VECTOR, used_vectors); | |
953 | #else | |
dbeb2be2 | 954 | set_bit(SYSCALL_VECTOR, used_vectors); |
081f75bb | 955 | #endif |
1da177e4 | 956 | /* |
b5964405 | 957 | * Should be a barrier for any external CPU state: |
1da177e4 LT |
958 | */ |
959 | cpu_init(); | |
960 | ||
081f75bb | 961 | #ifdef CONFIG_X86_32 |
8e6dafd6 | 962 | x86_quirk_trap_init(); |
081f75bb | 963 | #endif |
1da177e4 | 964 | } |