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Use extended crashkernel command line on i386
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kernel / setup_64.c
CommitLineData
1da177e4 1/*
1da177e4 2 * Copyright (C) 1995 Linus Torvalds
1da177e4
LT		 3 */
4
5/*
6 * This file handles the architecture-dependent parts of initialization
7 */
8
9#include <linux/errno.h>
10#include <linux/sched.h>
11#include <linux/kernel.h>
12#include <linux/mm.h>
13#include <linux/stddef.h>
14#include <linux/unistd.h>
15#include <linux/ptrace.h>
16#include <linux/slab.h>
17#include <linux/user.h>
18#include <linux/a.out.h>
894673ee 19#include <linux/screen_info.h>
1da177e4
LT		 20#include <linux/ioport.h>
21#include <linux/delay.h>
1da177e4
LT		 22#include <linux/init.h>
23#include <linux/initrd.h>
24#include <linux/highmem.h>
25#include <linux/bootmem.h>
26#include <linux/module.h>
27#include <asm/processor.h>
28#include <linux/console.h>
29#include <linux/seq_file.h>
aac04b32 30#include <linux/crash_dump.h>
1da177e4
LT		 31#include <linux/root_dev.h>
32#include <linux/pci.h>
33#include <linux/acpi.h>
34#include <linux/kallsyms.h>
35#include <linux/edd.h>
bbfceef4 36#include <linux/mmzone.h>
5f5609df 37#include <linux/kexec.h>
95235ca2 38#include <linux/cpufreq.h>
e9928674 39#include <linux/dmi.h>
17a941d8 40#include <linux/dma-mapping.h>
681558fd 41#include <linux/ctype.h>
bbfceef4 42
1da177e4
LT		 43#include <asm/mtrr.h>
44#include <asm/uaccess.h>
45#include <asm/system.h>
46#include <asm/io.h>
47#include <asm/smp.h>
48#include <asm/msr.h>
49#include <asm/desc.h>
50#include <video/edid.h>
51#include <asm/e820.h>
52#include <asm/dma.h>
53#include <asm/mpspec.h>
54#include <asm/mmu_context.h>
1da177e4
LT		 55#include <asm/proto.h>
56#include <asm/setup.h>
57#include <asm/mach_apic.h>
58#include <asm/numa.h>
2bc0414e 59#include <asm/sections.h>
f2d3efed 60#include <asm/dmi.h>
1da177e4
LT		 61
62/*
63 * Machine setup..
64 */
65
6c231b7b 66struct cpuinfo_x86 boot_cpu_data __read_mostly;
2ee60e17 67EXPORT_SYMBOL(boot_cpu_data);
1da177e4
LT		 68
69unsigned long mmu_cr4_features;
70
1da177e4
LT		 71/* Boot loader ID as an integer, for the benefit of proc_dointvec */
72int bootloader_type;
73
74unsigned long saved_video_mode;
75
f039b754
AK		 76int force_mwait __cpuinitdata;
77
f2d3efed
AK		 78/*
79 * Early DMI memory
80 */
81int dmi_alloc_index;
82char dmi_alloc_data[DMI_MAX_DATA];
83
1da177e4
LT		 84/*
85 * Setup options
86 */
1da177e4 87struct screen_info screen_info;
2ee60e17 88EXPORT_SYMBOL(screen_info);
1da177e4
LT		 89struct sys_desc_table_struct {
90 unsigned short length;
91 unsigned char table[0];
92};
93
94struct edid_info edid_info;
ba70710e 95EXPORT_SYMBOL_GPL(edid_info);
1da177e4
LT		 96
97extern int root_mountflags;
1da177e4 98
adf48856 99char __initdata command_line[COMMAND_LINE_SIZE];
1da177e4
LT		 100
101struct resource standard_io_resources[] = {
102 { .name = "dma1", .start = 0x00, .end = 0x1f,
103 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
104 { .name = "pic1", .start = 0x20, .end = 0x21,
105 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
106 { .name = "timer0", .start = 0x40, .end = 0x43,
107 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
108 { .name = "timer1", .start = 0x50, .end = 0x53,
109 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
110 { .name = "keyboard", .start = 0x60, .end = 0x6f,
111 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
112 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
113 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
114 { .name = "pic2", .start = 0xa0, .end = 0xa1,
115 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
116 { .name = "dma2", .start = 0xc0, .end = 0xdf,
117 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
118 { .name = "fpu", .start = 0xf0, .end = 0xff,
119 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
120};
121
1da177e4
LT		 122#define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
123
124struct resource data_resource = {
125 .name = "Kernel data",
126 .start = 0,
127 .end = 0,
128 .flags = IORESOURCE_RAM,
129};
130struct resource code_resource = {
131 .name = "Kernel code",
132 .start = 0,
133 .end = 0,
134 .flags = IORESOURCE_RAM,
135};
136
2c8c0e6b
AK		 137#ifdef CONFIG_PROC_VMCORE
138/* elfcorehdr= specifies the location of elf core header
139 * stored by the crashed kernel. This option will be passed
140 * by kexec loader to the capture kernel.
141 */
142static int __init setup_elfcorehdr(char *arg)
681558fd 143{
2c8c0e6b
AK		 144 char *end;
145 if (!arg)
146 return -EINVAL;
147 elfcorehdr_addr = memparse(arg, &end);
148 return end > arg ? 0 : -EINVAL;
681558fd 149}
2c8c0e6b 150early_param("elfcorehdr", setup_elfcorehdr);
e2c03888
AK		 151#endif
152
2b97690f 153#ifndef CONFIG_NUMA
bbfceef4
MT		 154static void __init
155contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
1da177e4 156{
bbfceef4
MT		 157 unsigned long bootmap_size, bootmap;
158
bbfceef4
MT		 159 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
160 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
161 if (bootmap == -1L)
162 panic("Cannot find bootmem map of size %ld\n",bootmap_size);
163 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
5cb248ab
MG		 164 e820_register_active_regions(0, start_pfn, end_pfn);
165 free_bootmem_with_active_regions(0, end_pfn);
bbfceef4 166 reserve_bootmem(bootmap, bootmap_size);
1da177e4
LT		 167}
168#endif
169
1da177e4
LT		 170#if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
171struct edd edd;
172#ifdef CONFIG_EDD_MODULE
173EXPORT_SYMBOL(edd);
174#endif
175/**
176 * copy_edd() - Copy the BIOS EDD information
177 * from boot_params into a safe place.
178 *
179 */
180static inline void copy_edd(void)
181{
30c82645
PA		 182 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
183 sizeof(edd.mbr_signature));
184 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
185 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
186 edd.edd_info_nr = boot_params.eddbuf_entries;
1da177e4
LT		 187}
188#else
189static inline void copy_edd(void)
190{
191}
192#endif
193
194#define EBDA_ADDR_POINTER 0x40E
ac71d12c
AK		 195
196unsigned __initdata ebda_addr;
197unsigned __initdata ebda_size;
198
199static void discover_ebda(void)
1da177e4 200{
ac71d12c 201 /*
1da177e4
LT		 202 * there is a real-mode segmented pointer pointing to the
203 * 4K EBDA area at 0x40E
204 */
bdb96a66 205 ebda_addr = *(unsigned short *)__va(EBDA_ADDR_POINTER);
ac71d12c
AK		 206 ebda_addr <<= 4;
207
bdb96a66 208 ebda_size = *(unsigned short *)__va(ebda_addr);
ac71d12c
AK		 209
210 /* Round EBDA up to pages */
211 if (ebda_size == 0)
212 ebda_size = 1;
213 ebda_size <<= 10;
214 ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
215 if (ebda_size > 64*1024)
216 ebda_size = 64*1024;
1da177e4
LT		 217}
218
219void __init setup_arch(char **cmdline_p)
220{
adf48856 221 printk(KERN_INFO "Command line: %s\n", boot_command_line);
43c85c9c 222
30c82645
PA		 223 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
224 screen_info = boot_params.screen_info;
225 edid_info = boot_params.edid_info;
226 saved_video_mode = boot_params.hdr.vid_mode;
227 bootloader_type = boot_params.hdr.type_of_loader;
1da177e4
LT		 228
229#ifdef CONFIG_BLK_DEV_RAM
30c82645
PA		 230 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
231 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
232 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
1da177e4
LT		 233#endif
234 setup_memory_region();
235 copy_edd();
236
30c82645 237 if (!boot_params.hdr.root_flags)
1da177e4
LT		 238 root_mountflags &= ~MS_RDONLY;
239 init_mm.start_code = (unsigned long) &_text;
240 init_mm.end_code = (unsigned long) &_etext;
241 init_mm.end_data = (unsigned long) &_edata;
242 init_mm.brk = (unsigned long) &_end;
243
e3ebadd9
LT		 244 code_resource.start = virt_to_phys(&_text);
245 code_resource.end = virt_to_phys(&_etext)-1;
246 data_resource.start = virt_to_phys(&_etext);
247 data_resource.end = virt_to_phys(&_edata)-1;
1da177e4 248
1da177e4
LT		 249 early_identify_cpu(&boot_cpu_data);
250
adf48856 251 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
2c8c0e6b
AK		 252 *cmdline_p = command_line;
253
254 parse_early_param();
255
256 finish_e820_parsing();
9ca33eb6 257
5cb248ab 258 e820_register_active_regions(0, 0, -1UL);
1da177e4
LT		 259 /*
260 * partially used pages are not usable - thus
261 * we are rounding upwards:
262 */
263 end_pfn = e820_end_of_ram();
caff0710 264 num_physpages = end_pfn;
1da177e4
LT		 265
266 check_efer();
267
ac71d12c
AK		 268 discover_ebda();
269
1da177e4
LT		 270 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
271
f2d3efed
AK		 272 dmi_scan_machine();
273
888ba6c6 274#ifdef CONFIG_ACPI
1da177e4
LT		 275 /*
276 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
277 * Call this early for SRAT node setup.
278 */
279 acpi_boot_table_init();
280#endif
281
caff0710
JB		 282 /* How many end-of-memory variables you have, grandma! */
283 max_low_pfn = end_pfn;
284 max_pfn = end_pfn;
285 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
286
5cb248ab
MG		 287 /* Remove active ranges so rediscovery with NUMA-awareness happens */
288 remove_all_active_ranges();
289
1da177e4
LT		 290#ifdef CONFIG_ACPI_NUMA
291 /*
292 * Parse SRAT to discover nodes.
293 */
294 acpi_numa_init();
295#endif
296
2b97690f 297#ifdef CONFIG_NUMA
1da177e4
LT		 298 numa_initmem_init(0, end_pfn);
299#else
bbfceef4 300 contig_initmem_init(0, end_pfn);
1da177e4
LT		 301#endif
302
303 /* Reserve direct mapping */
304 reserve_bootmem_generic(table_start << PAGE_SHIFT,
305 (table_end - table_start) << PAGE_SHIFT);
306
307 /* reserve kernel */
ceee8822
AK		 308 reserve_bootmem_generic(__pa_symbol(&_text),
309 __pa_symbol(&_end) - __pa_symbol(&_text));
1da177e4
LT		 310
311 /*
312 * reserve physical page 0 - it's a special BIOS page on many boxes,
313 * enabling clean reboots, SMP operation, laptop functions.
314 */
315 reserve_bootmem_generic(0, PAGE_SIZE);
316
317 /* reserve ebda region */
ac71d12c
AK		 318 if (ebda_addr)
319 reserve_bootmem_generic(ebda_addr, ebda_size);
076422d2
AS		 320#ifdef CONFIG_NUMA
321 /* reserve nodemap region */
322 if (nodemap_addr)
323 reserve_bootmem_generic(nodemap_addr, nodemap_size);
324#endif
1da177e4
LT		 325
326#ifdef CONFIG_SMP
1da177e4 327 /* Reserve SMP trampoline */
90b1c208 328 reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, 2*PAGE_SIZE);
1da177e4
LT		 329#endif
330
673d5b43 331#ifdef CONFIG_ACPI_SLEEP
1da177e4
LT		 332 /*
333 * Reserve low memory region for sleep support.
334 */
335 acpi_reserve_bootmem();
336#endif
1da177e4
LT		 337 /*
338 * Find and reserve possible boot-time SMP configuration:
339 */
340 find_smp_config();
1da177e4 341#ifdef CONFIG_BLK_DEV_INITRD
30c82645
PA		 342 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
343 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
344 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
345 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
346 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
347
348 if (ramdisk_end <= end_of_mem) {
349 reserve_bootmem_generic(ramdisk_image, ramdisk_size);
350 initrd_start = ramdisk_image + PAGE_OFFSET;
351 initrd_end = initrd_start+ramdisk_size;
352 } else {
1da177e4 353 printk(KERN_ERR "initrd extends beyond end of memory "
30c82645
PA		 354 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
355 ramdisk_end, end_of_mem);
1da177e4
LT		 356 initrd_start = 0;
357 }
358 }
359#endif
5f5609df
EB		 360#ifdef CONFIG_KEXEC
361 if (crashk_res.start != crashk_res.end) {
00212fef 362 reserve_bootmem_generic(crashk_res.start,
5f5609df
EB		 363 crashk_res.end - crashk_res.start + 1);
364 }
365#endif
0d317fb7 366
1da177e4
LT		 367 paging_init();
368
f157cbb1 369#ifdef CONFIG_PCI
dfa4698c 370 early_quirks();
f157cbb1 371#endif
1da177e4 372
51f62e18
AR		 373 /*
374 * set this early, so we dont allocate cpu0
375 * if MADT list doesnt list BSP first
376 * mpparse.c/MP_processor_info() allocates logical cpu numbers.
377 */
378 cpu_set(0, cpu_present_map);
888ba6c6 379#ifdef CONFIG_ACPI
1da177e4
LT		 380 /*
381 * Read APIC and some other early information from ACPI tables.
382 */
383 acpi_boot_init();
384#endif
385
05b3cbd8
RT		 386 init_cpu_to_node();
387
1da177e4
LT		 388 /*
389 * get boot-time SMP configuration:
390 */
391 if (smp_found_config)
392 get_smp_config();
393 init_apic_mappings();
1da177e4
LT		 394
395 /*
fc986db4
AK		 396 * We trust e820 completely. No explicit ROM probing in memory.
397 */
1da177e4 398 e820_reserve_resources();
e8eff5ac 399 e820_mark_nosave_regions();
1da177e4 400
1da177e4
LT		 401 {
402 unsigned i;
403 /* request I/O space for devices used on all i[345]86 PCs */
9d0ef4fd 404 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
1da177e4
LT		 405 request_resource(&ioport_resource, &standard_io_resources[i]);
406 }
407
a1e97782 408 e820_setup_gap();
1da177e4 409
1da177e4
LT		 410#ifdef CONFIG_VT
411#if defined(CONFIG_VGA_CONSOLE)
412 conswitchp = &vga_con;
413#elif defined(CONFIG_DUMMY_CONSOLE)
414 conswitchp = &dummy_con;
415#endif
416#endif
417}
418
e6982c67 419static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
1da177e4
LT		 420{
421 unsigned int *v;
422
ebfcaa96 423 if (c->extended_cpuid_level < 0x80000004)
1da177e4
LT		 424 return 0;
425
426 v = (unsigned int *) c->x86_model_id;
427 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
428 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
429 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
430 c->x86_model_id[48] = 0;
431 return 1;
432}
433
434
e6982c67 435static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
1da177e4
LT		 436{
437 unsigned int n, dummy, eax, ebx, ecx, edx;
438
ebfcaa96 439 n = c->extended_cpuid_level;
1da177e4
LT		 440
441 if (n >= 0x80000005) {
442 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
443 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
444 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
445 c->x86_cache_size=(ecx>>24)+(edx>>24);
446 /* On K8 L1 TLB is inclusive, so don't count it */
447 c->x86_tlbsize = 0;
448 }
449
450 if (n >= 0x80000006) {
451 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
452 ecx = cpuid_ecx(0x80000006);
453 c->x86_cache_size = ecx >> 16;
454 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
455
456 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
457 c->x86_cache_size, ecx & 0xFF);
458 }
459
460 if (n >= 0x80000007)
461 cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
462 if (n >= 0x80000008) {
463 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
464 c->x86_virt_bits = (eax >> 8) & 0xff;
465 c->x86_phys_bits = eax & 0xff;
466 }
467}
468
3f098c26
AK		 469#ifdef CONFIG_NUMA
470static int nearby_node(int apicid)
471{
472 int i;
473 for (i = apicid - 1; i >= 0; i--) {
474 int node = apicid_to_node[i];
475 if (node != NUMA_NO_NODE && node_online(node))
476 return node;
477 }
478 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
479 int node = apicid_to_node[i];
480 if (node != NUMA_NO_NODE && node_online(node))
481 return node;
482 }
483 return first_node(node_online_map); /* Shouldn't happen */
484}
485#endif
486
63518644
AK		 487/*
488 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
489 * Assumes number of cores is a power of two.
490 */
491static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
492{
493#ifdef CONFIG_SMP
b41e2939 494 unsigned bits;
3f098c26 495#ifdef CONFIG_NUMA
f3fa8ebc 496 int cpu = smp_processor_id();
3f098c26 497 int node = 0;
60c1bc82 498 unsigned apicid = hard_smp_processor_id();
3f098c26 499#endif
faee9a5d 500 unsigned ecx = cpuid_ecx(0x80000008);
b41e2939 501
faee9a5d 502 c->x86_max_cores = (ecx & 0xff) + 1;
b41e2939 503
faee9a5d
AK		 504 /* CPU telling us the core id bits shift? */
505 bits = (ecx >> 12) & 0xF;
506
507 /* Otherwise recompute */
508 if (bits == 0) {
509 while ((1 << bits) < c->x86_max_cores)
510 bits++;
511 }
b41e2939
AK		 512
513 /* Low order bits define the core id (index of core in socket) */
f3fa8ebc 514 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
b41e2939 515 /* Convert the APIC ID into the socket ID */
f3fa8ebc 516 c->phys_proc_id = phys_pkg_id(bits);
63518644
AK		 517
518#ifdef CONFIG_NUMA
f3fa8ebc 519 node = c->phys_proc_id;
3f098c26
AK		 520 if (apicid_to_node[apicid] != NUMA_NO_NODE)
521 node = apicid_to_node[apicid];
522 if (!node_online(node)) {
523 /* Two possibilities here:
524 - The CPU is missing memory and no node was created.
525 In that case try picking one from a nearby CPU
526 - The APIC IDs differ from the HyperTransport node IDs
527 which the K8 northbridge parsing fills in.
528 Assume they are all increased by a constant offset,
529 but in the same order as the HT nodeids.
530 If that doesn't result in a usable node fall back to the
531 path for the previous case. */
f3fa8ebc 532 int ht_nodeid = apicid - (cpu_data[0].phys_proc_id << bits);
3f098c26
AK		 533 if (ht_nodeid >= 0 &&
534 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
535 node = apicid_to_node[ht_nodeid];
536 /* Pick a nearby node */
537 if (!node_online(node))
538 node = nearby_node(apicid);
539 }
69d81fcd 540 numa_set_node(cpu, node);
3f098c26 541
e42f9437 542 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
63518644 543#endif
63518644
AK		 544#endif
545}
1da177e4 546
fb79d22e
TG		 547#define ENABLE_C1E_MASK 0x18000000
548#define CPUID_PROCESSOR_SIGNATURE 1
549#define CPUID_XFAM 0x0ff00000
550#define CPUID_XFAM_K8 0x00000000
551#define CPUID_XFAM_10H 0x00100000
552#define CPUID_XFAM_11H 0x00200000
553#define CPUID_XMOD 0x000f0000
554#define CPUID_XMOD_REV_F 0x00040000
555
556/* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
557static __cpuinit int amd_apic_timer_broken(void)
558{
559 u32 lo, hi;
560 u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
561 switch (eax & CPUID_XFAM) {
562 case CPUID_XFAM_K8:
563 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
564 break;
565 case CPUID_XFAM_10H:
566 case CPUID_XFAM_11H:
567 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
568 if (lo & ENABLE_C1E_MASK)
569 return 1;
570 break;
571 default:
572 /* err on the side of caution */
573 return 1;
574 }
575 return 0;
576}
577
ed77504b 578static void __cpuinit init_amd(struct cpuinfo_x86 *c)
1da177e4 579{
7bcd3f34 580 unsigned level;
1da177e4 581
bc5e8fdf
LT		 582#ifdef CONFIG_SMP
583 unsigned long value;
584
7d318d77
AK		 585 /*
586 * Disable TLB flush filter by setting HWCR.FFDIS on K8
587 * bit 6 of msr C001_0015
588 *
589 * Errata 63 for SH-B3 steppings
590 * Errata 122 for all steppings (F+ have it disabled by default)
591 */
592 if (c->x86 == 15) {
593 rdmsrl(MSR_K8_HWCR, value);
594 value |= 1 << 6;
595 wrmsrl(MSR_K8_HWCR, value);
596 }
bc5e8fdf
LT		 597#endif
598
1da177e4
LT		 599 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
600 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
601 clear_bit(0*32+31, &c->x86_capability);
602
7bcd3f34
AK		 603 /* On C+ stepping K8 rep microcode works well for copy/memset */
604 level = cpuid_eax(1);
605 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58))
606 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
99741faa 607 if (c->x86 == 0x10 || c->x86 == 0x11)
5b74e3ab 608 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
7bcd3f34 609
18bd057b
AK		 610 /* Enable workaround for FXSAVE leak */
611 if (c->x86 >= 6)
612 set_bit(X86_FEATURE_FXSAVE_LEAK, &c->x86_capability);
613
e42f9437
RS		 614 level = get_model_name(c);
615 if (!level) {
1da177e4
LT		 616 switch (c->x86) {
617 case 15:
618 /* Should distinguish Models here, but this is only
619 a fallback anyways. */
620 strcpy(c->x86_model_id, "Hammer");
621 break;
622 }
623 }
624 display_cacheinfo(c);
625
130951cc
AK		 626 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
627 if (c->x86_power & (1<<8))
628 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
629
faee9a5d
AK		 630 /* Multi core CPU? */
631 if (c->extended_cpuid_level >= 0x80000008)
63518644 632 amd_detect_cmp(c);
1da177e4 633
67cddd94
AK		 634 if (c->extended_cpuid_level >= 0x80000006 &&
635 (cpuid_edx(0x80000006) & 0xf000))
636 num_cache_leaves = 4;
637 else
638 num_cache_leaves = 3;
2049336f 639
0bd8acd1
AK		 640 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
641 set_bit(X86_FEATURE_K8, &c->x86_capability);
642
61677965
AK		 643 /* RDTSC can be speculated around */
644 clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
f039b754
AK		 645
646 /* Family 10 doesn't support C states in MWAIT so don't use it */
647 if (c->x86 == 0x10 && !force_mwait)
648 clear_bit(X86_FEATURE_MWAIT, &c->x86_capability);
fb79d22e
TG		 649
650 if (amd_apic_timer_broken())
651 disable_apic_timer = 1;
1da177e4
LT		 652}
653
e6982c67 654static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
1da177e4
LT		 655{
656#ifdef CONFIG_SMP
657 u32 eax, ebx, ecx, edx;
94605eff 658 int index_msb, core_bits;
94605eff
SS		 659
660 cpuid(1, &eax, &ebx, &ecx, &edx);
661
94605eff 662
e42f9437 663 if (!cpu_has(c, X86_FEATURE_HT))
1da177e4 664 return;
e42f9437
RS		 665 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
666 goto out;
1da177e4 667
1da177e4 668 smp_num_siblings = (ebx & 0xff0000) >> 16;
94605eff 669
1da177e4
LT		 670 if (smp_num_siblings == 1) {
671 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
94605eff
SS		 672 } else if (smp_num_siblings > 1 ) {
673
1da177e4
LT		 674 if (smp_num_siblings > NR_CPUS) {
675 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
676 smp_num_siblings = 1;
677 return;
678 }
94605eff
SS		 679
680 index_msb = get_count_order(smp_num_siblings);
f3fa8ebc 681 c->phys_proc_id = phys_pkg_id(index_msb);
3dd9d514 682
94605eff 683 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
3dd9d514 684
94605eff
SS		 685 index_msb = get_count_order(smp_num_siblings) ;
686
687 core_bits = get_count_order(c->x86_max_cores);
3dd9d514 688
f3fa8ebc 689 c->cpu_core_id = phys_pkg_id(index_msb) &
94605eff 690 ((1 << core_bits) - 1);
1da177e4 691 }
e42f9437
RS		 692out:
693 if ((c->x86_max_cores * smp_num_siblings) > 1) {
694 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", c->phys_proc_id);
695 printk(KERN_INFO "CPU: Processor Core ID: %d\n", c->cpu_core_id);
696 }
697
1da177e4
LT		 698#endif
699}
700
3dd9d514
AK		 701/*
702 * find out the number of processor cores on the die
703 */
e6982c67 704static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
3dd9d514 705{
2bbc419f 706 unsigned int eax, t;
3dd9d514
AK		 707
708 if (c->cpuid_level < 4)
709 return 1;
710
2bbc419f 711 cpuid_count(4, 0, &eax, &t, &t, &t);
3dd9d514
AK		 712
713 if (eax & 0x1f)
714 return ((eax >> 26) + 1);
715 else
716 return 1;
717}
718
df0cc26b
AK		 719static void srat_detect_node(void)
720{
721#ifdef CONFIG_NUMA
ddea7be0 722 unsigned node;
df0cc26b 723 int cpu = smp_processor_id();
e42f9437 724 int apicid = hard_smp_processor_id();
df0cc26b
AK		 725
726 /* Don't do the funky fallback heuristics the AMD version employs
727 for now. */
e42f9437 728 node = apicid_to_node[apicid];
df0cc26b 729 if (node == NUMA_NO_NODE)
0d015324 730 node = first_node(node_online_map);
69d81fcd 731 numa_set_node(cpu, node);
df0cc26b 732
c31fbb1a 733 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
df0cc26b
AK		 734#endif
735}
736
e6982c67 737static void __cpuinit init_intel(struct cpuinfo_x86 *c)
1da177e4
LT		 738{
739 /* Cache sizes */
740 unsigned n;
741
742 init_intel_cacheinfo(c);
0080e667
VP		 743 if (c->cpuid_level > 9 ) {
744 unsigned eax = cpuid_eax(10);
745 /* Check for version and the number of counters */
746 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
747 set_bit(X86_FEATURE_ARCH_PERFMON, &c->x86_capability);
748 }
749
36b2a8d5
SE		 750 if (cpu_has_ds) {
751 unsigned int l1, l2;
752 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
ee58fad5
SE		 753 if (!(l1 & (1<<11)))
754 set_bit(X86_FEATURE_BTS, c->x86_capability);
36b2a8d5
SE		 755 if (!(l1 & (1<<12)))
756 set_bit(X86_FEATURE_PEBS, c->x86_capability);
757 }
758
ebfcaa96 759 n = c->extended_cpuid_level;
1da177e4
LT		 760 if (n >= 0x80000008) {
761 unsigned eax = cpuid_eax(0x80000008);
762 c->x86_virt_bits = (eax >> 8) & 0xff;
763 c->x86_phys_bits = eax & 0xff;
af9c142d
SL		 764 /* CPUID workaround for Intel 0F34 CPU */
765 if (c->x86_vendor == X86_VENDOR_INTEL &&
766 c->x86 == 0xF && c->x86_model == 0x3 &&
767 c->x86_mask == 0x4)
768 c->x86_phys_bits = 36;
1da177e4
LT		 769 }
770
771 if (c->x86 == 15)
772 c->x86_cache_alignment = c->x86_clflush_size * 2;
39b3a791
AK		 773 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
774 (c->x86 == 0x6 && c->x86_model >= 0x0e))
c29601e9 775 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
27fbe5b2
AK		 776 if (c->x86 == 6)
777 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
f3d73707
AV		 778 if (c->x86 == 15)
779 set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
780 else
781 clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
94605eff 782 c->x86_max_cores = intel_num_cpu_cores(c);
df0cc26b
AK		 783
784 srat_detect_node();
1da177e4
LT		 785}
786
672289e9 787static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
1da177e4
LT		 788{
789 char *v = c->x86_vendor_id;
790
791 if (!strcmp(v, "AuthenticAMD"))
792 c->x86_vendor = X86_VENDOR_AMD;
793 else if (!strcmp(v, "GenuineIntel"))
794 c->x86_vendor = X86_VENDOR_INTEL;
795 else
796 c->x86_vendor = X86_VENDOR_UNKNOWN;
797}
798
799struct cpu_model_info {
800 int vendor;
801 int family;
802 char *model_names[16];
803};
804
805/* Do some early cpuid on the boot CPU to get some parameter that are
806 needed before check_bugs. Everything advanced is in identify_cpu
807 below. */
e6982c67 808void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
1da177e4
LT		 809{
810 u32 tfms;
811
812 c->loops_per_jiffy = loops_per_jiffy;
813 c->x86_cache_size = -1;
814 c->x86_vendor = X86_VENDOR_UNKNOWN;
815 c->x86_model = c->x86_mask = 0; /* So far unknown... */
816 c->x86_vendor_id[0] = '\0'; /* Unset */
817 c->x86_model_id[0] = '\0'; /* Unset */
818 c->x86_clflush_size = 64;
819 c->x86_cache_alignment = c->x86_clflush_size;
94605eff 820 c->x86_max_cores = 1;
ebfcaa96 821 c->extended_cpuid_level = 0;
1da177e4
LT		 822 memset(&c->x86_capability, 0, sizeof c->x86_capability);
823
824 /* Get vendor name */
825 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
826 (unsigned int *)&c->x86_vendor_id[0],
827 (unsigned int *)&c->x86_vendor_id[8],
828 (unsigned int *)&c->x86_vendor_id[4]);
829
830 get_cpu_vendor(c);
831
832 /* Initialize the standard set of capabilities */
833 /* Note that the vendor-specific code below might override */
834
835 /* Intel-defined flags: level 0x00000001 */
836 if (c->cpuid_level >= 0x00000001) {
837 __u32 misc;
838 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
839 &c->x86_capability[0]);
840 c->x86 = (tfms >> 8) & 0xf;
841 c->x86_model = (tfms >> 4) & 0xf;
842 c->x86_mask = tfms & 0xf;
f5f786d0 843 if (c->x86 == 0xf)
1da177e4 844 c->x86 += (tfms >> 20) & 0xff;
f5f786d0 845 if (c->x86 >= 0x6)
1da177e4 846 c->x86_model += ((tfms >> 16) & 0xF) << 4;
1da177e4
LT		 847 if (c->x86_capability[0] & (1<<19))
848 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
1da177e4
LT		 849 } else {
850 /* Have CPUID level 0 only - unheard of */
851 c->x86 = 4;
852 }
a158608b
AK		 853
854#ifdef CONFIG_SMP
f3fa8ebc 855 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
a158608b 856#endif
1da177e4
LT		 857}
858
859/*
860 * This does the hard work of actually picking apart the CPU stuff...
861 */
e6982c67 862void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1da177e4
LT		 863{
864 int i;
865 u32 xlvl;
866
867 early_identify_cpu(c);
868
869 /* AMD-defined flags: level 0x80000001 */
870 xlvl = cpuid_eax(0x80000000);
ebfcaa96 871 c->extended_cpuid_level = xlvl;
1da177e4
LT		 872 if ((xlvl & 0xffff0000) == 0x80000000) {
873 if (xlvl >= 0x80000001) {
874 c->x86_capability[1] = cpuid_edx(0x80000001);
5b7abc6f 875 c->x86_capability[6] = cpuid_ecx(0x80000001);
1da177e4
LT		 876 }
877 if (xlvl >= 0x80000004)
878 get_model_name(c); /* Default name */
879 }
880
881 /* Transmeta-defined flags: level 0x80860001 */
882 xlvl = cpuid_eax(0x80860000);
883 if ((xlvl & 0xffff0000) == 0x80860000) {
884 /* Don't set x86_cpuid_level here for now to not confuse. */
885 if (xlvl >= 0x80860001)
886 c->x86_capability[2] = cpuid_edx(0x80860001);
887 }
888
1d67953f
VP		 889 init_scattered_cpuid_features(c);
890
1e9f28fa
SS		 891 c->apicid = phys_pkg_id(0);
892
1da177e4
LT		 893 /*
894 * Vendor-specific initialization. In this section we
895 * canonicalize the feature flags, meaning if there are
896 * features a certain CPU supports which CPUID doesn't
897 * tell us, CPUID claiming incorrect flags, or other bugs,
898 * we handle them here.
899 *
900 * At the end of this section, c->x86_capability better
901 * indicate the features this CPU genuinely supports!
902 */
903 switch (c->x86_vendor) {
904 case X86_VENDOR_AMD:
905 init_amd(c);
906 break;
907
908 case X86_VENDOR_INTEL:
909 init_intel(c);
910 break;
911
912 case X86_VENDOR_UNKNOWN:
913 default:
914 display_cacheinfo(c);
915 break;
916 }
917
918 select_idle_routine(c);
919 detect_ht(c);
1da177e4
LT		 920
921 /*
922 * On SMP, boot_cpu_data holds the common feature set between
923 * all CPUs; so make sure that we indicate which features are
924 * common between the CPUs. The first time this routine gets
925 * executed, c == &boot_cpu_data.
926 */
927 if (c != &boot_cpu_data) {
928 /* AND the already accumulated flags with these */
929 for (i = 0 ; i < NCAPINTS ; i++)
930 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
931 }
932
933#ifdef CONFIG_X86_MCE
934 mcheck_init(c);
935#endif
8bd99481 936 if (c != &boot_cpu_data)
3b520b23 937 mtrr_ap_init();
1da177e4 938#ifdef CONFIG_NUMA
3019e8eb 939 numa_add_cpu(smp_processor_id());
1da177e4
LT		 940#endif
941}
942
943
e6982c67 944void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1da177e4
LT		 945{
946 if (c->x86_model_id[0])
947 printk("%s", c->x86_model_id);
948
949 if (c->x86_mask || c->cpuid_level >= 0)
950 printk(" stepping %02x\n", c->x86_mask);
951 else
952 printk("\n");
953}
954
955/*
956 * Get CPU information for use by the procfs.
957 */
958
959static int show_cpuinfo(struct seq_file *m, void *v)
960{
961 struct cpuinfo_x86 *c = v;
962
963 /*
964 * These flag bits must match the definitions in <asm/cpufeature.h>.
965 * NULL means this bit is undefined or reserved; either way it doesn't
966 * have meaning as far as Linux is concerned. Note that it's important
967 * to realize there is a difference between this table and CPUID -- if
968 * applications want to get the raw CPUID data, they should access
969 * /dev/cpu/<cpu_nr>/cpuid instead.
970 */
121d7bf5 971 static const char *const x86_cap_flags[] = {
1da177e4
LT		 972 /* Intel-defined */
973 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
974 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
975 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
ec481536 976 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
1da177e4
LT		 977
978 /* AMD-defined */
3c3b73b6 979 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4
LT		 980 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
981 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
f790cd30
AK		 982 NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
983 "3dnowext", "3dnow",
1da177e4
LT		 984
985 /* Transmeta-defined */
986 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
987 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
988 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
989 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
990
991 /* Other (Linux-defined) */
ec481536
PA		 992 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
993 NULL, NULL, NULL, NULL,
994 "constant_tsc", "up", NULL, "arch_perfmon",
995 "pebs", "bts", NULL, "sync_rdtsc",
996 "rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4
LT		 997 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
998
999 /* Intel-defined (#2) */
9d95dd84 1000 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
dcf10307 1001 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
f790cd30 1002 NULL, NULL, "dca", NULL, NULL, NULL, NULL, "popcnt",
1da177e4
LT		 1003 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1004
5b7abc6f
PA		 1005 /* VIA/Cyrix/Centaur-defined */
1006 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
ec481536 1007 "ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
5b7abc6f
PA		 1008 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1009 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1010
1da177e4 1011 /* AMD-defined (#2) */
f790cd30
AK		 1012 "lahf_lm", "cmp_legacy", "svm", "extapic", "cr8_legacy",
1013 "altmovcr8", "abm", "sse4a",
1014 "misalignsse", "3dnowprefetch",
1015 "osvw", "ibs", NULL, NULL, NULL, NULL,
1da177e4 1016 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
5b7abc6f 1017 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1d67953f
VP		 1018
1019 /* Auxiliary (Linux-defined) */
1020 "ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1021 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1022 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1023 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4 1024 };
121d7bf5 1025 static const char *const x86_power_flags[] = {
1da177e4
LT		 1026 "ts", /* temperature sensor */
1027 "fid", /* frequency id control */
1028 "vid", /* voltage id control */
1029 "ttp", /* thermal trip */
1030 "tm",
3f98bc49 1031 "stc",
f790cd30
AK		 1032 "100mhzsteps",
1033 "hwpstate",
d824395c
JR		 1034 "", /* tsc invariant mapped to constant_tsc */
1035 /* nothing */
1da177e4
LT		 1036 };
1037
1038
1039#ifdef CONFIG_SMP
1040 if (!cpu_online(c-cpu_data))
1041 return 0;
1042#endif
1043
1044 seq_printf(m,"processor\t: %u\n"
1045 "vendor_id\t: %s\n"
1046 "cpu family\t: %d\n"
1047 "model\t\t: %d\n"
1048 "model name\t: %s\n",
1049 (unsigned)(c-cpu_data),
1050 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1051 c->x86,
1052 (int)c->x86_model,
1053 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1054
1055 if (c->x86_mask || c->cpuid_level >= 0)
1056 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1057 else
1058 seq_printf(m, "stepping\t: unknown\n");
1059
1060 if (cpu_has(c,X86_FEATURE_TSC)) {
95235ca2
VP		 1061 unsigned int freq = cpufreq_quick_get((unsigned)(c-cpu_data));
1062 if (!freq)
1063 freq = cpu_khz;
1da177e4 1064 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
95235ca2 1065 freq / 1000, (freq % 1000));
1da177e4
LT		 1066 }
1067
1068 /* Cache size */
1069 if (c->x86_cache_size >= 0)
1070 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1071
1072#ifdef CONFIG_SMP
94605eff 1073 if (smp_num_siblings * c->x86_max_cores > 1) {
db468681 1074 int cpu = c - cpu_data;
f3fa8ebc 1075 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
08357611
MT		 1076 seq_printf(m, "siblings\t: %d\n",
1077 cpus_weight(per_cpu(cpu_core_map, cpu)));
f3fa8ebc 1078 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
94605eff 1079 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
db468681 1080 }
1da177e4
LT		 1081#endif
1082
1083 seq_printf(m,
1084 "fpu\t\t: yes\n"
1085 "fpu_exception\t: yes\n"
1086 "cpuid level\t: %d\n"
1087 "wp\t\t: yes\n"
1088 "flags\t\t:",
1089 c->cpuid_level);
1090
1091 {
1092 int i;
1093 for ( i = 0 ; i < 32*NCAPINTS ; i++ )
3d1712c9 1094 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
1da177e4
LT		 1095 seq_printf(m, " %s", x86_cap_flags[i]);
1096 }
1097
1098 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1099 c->loops_per_jiffy/(500000/HZ),
1100 (c->loops_per_jiffy/(5000/HZ)) % 100);
1101
1102 if (c->x86_tlbsize > 0)
1103 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1104 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1105 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1106
1107 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1108 c->x86_phys_bits, c->x86_virt_bits);
1109
1110 seq_printf(m, "power management:");
1111 {
1112 unsigned i;
1113 for (i = 0; i < 32; i++)
1114 if (c->x86_power & (1 << i)) {
3f98bc49
AK		 1115 if (i < ARRAY_SIZE(x86_power_flags) &&
1116 x86_power_flags[i])
1117 seq_printf(m, "%s%s",
1118 x86_power_flags[i][0]?" ":"",
1119 x86_power_flags[i]);
1da177e4
LT		 1120 else
1121 seq_printf(m, " [%d]", i);
1122 }
1123 }
1da177e4 1124
d31ddaa1 1125 seq_printf(m, "\n\n");
1da177e4
LT		 1126
1127 return 0;
1128}
1129
1130static void *c_start(struct seq_file *m, loff_t *pos)
1131{
1132 return *pos < NR_CPUS ? cpu_data + *pos : NULL;
1133}
1134
1135static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1136{
1137 ++*pos;
1138 return c_start(m, pos);
1139}
1140
1141static void c_stop(struct seq_file *m, void *v)
1142{
1143}
1144
1145struct seq_operations cpuinfo_op = {
1146 .start =c_start,
1147 .next = c_next,
1148 .stop = c_stop,
1149 .show = show_cpuinfo,
1150};
kernel source for telekom puls (alcatel/mediatek)