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x86: move debug related declarations to kdebug.h
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kernel / setup_64.c
CommitLineData
1da177e4 1/*
1da177e4 2 * Copyright (C) 1995 Linus Torvalds
1da177e4
LT		 3 */
4
5/*
6 * This file handles the architecture-dependent parts of initialization
7 */
8
9#include <linux/errno.h>
10#include <linux/sched.h>
11#include <linux/kernel.h>
12#include <linux/mm.h>
13#include <linux/stddef.h>
14#include <linux/unistd.h>
15#include <linux/ptrace.h>
16#include <linux/slab.h>
17#include <linux/user.h>
18#include <linux/a.out.h>
894673ee 19#include <linux/screen_info.h>
1da177e4
LT		 20#include <linux/ioport.h>
21#include <linux/delay.h>
1da177e4
LT		 22#include <linux/init.h>
23#include <linux/initrd.h>
24#include <linux/highmem.h>
25#include <linux/bootmem.h>
26#include <linux/module.h>
27#include <asm/processor.h>
28#include <linux/console.h>
29#include <linux/seq_file.h>
aac04b32 30#include <linux/crash_dump.h>
1da177e4
LT		 31#include <linux/root_dev.h>
32#include <linux/pci.h>
33#include <linux/acpi.h>
34#include <linux/kallsyms.h>
35#include <linux/edd.h>
bbfceef4 36#include <linux/mmzone.h>
5f5609df 37#include <linux/kexec.h>
95235ca2 38#include <linux/cpufreq.h>
e9928674 39#include <linux/dmi.h>
17a941d8 40#include <linux/dma-mapping.h>
681558fd 41#include <linux/ctype.h>
bbfceef4 42
1da177e4
LT		 43#include <asm/mtrr.h>
44#include <asm/uaccess.h>
45#include <asm/system.h>
46#include <asm/io.h>
47#include <asm/smp.h>
48#include <asm/msr.h>
49#include <asm/desc.h>
50#include <video/edid.h>
51#include <asm/e820.h>
52#include <asm/dma.h>
53#include <asm/mpspec.h>
54#include <asm/mmu_context.h>
1da177e4
LT		 55#include <asm/proto.h>
56#include <asm/setup.h>
57#include <asm/mach_apic.h>
58#include <asm/numa.h>
2bc0414e 59#include <asm/sections.h>
f2d3efed 60#include <asm/dmi.h>
00bf4098 61#include <asm/cacheflush.h>
1da177e4
LT		 62
63/*
64 * Machine setup..
65 */
66
6c231b7b 67struct cpuinfo_x86 boot_cpu_data __read_mostly;
2ee60e17 68EXPORT_SYMBOL(boot_cpu_data);
1da177e4
LT		 69
70unsigned long mmu_cr4_features;
71
1da177e4
LT		 72/* Boot loader ID as an integer, for the benefit of proc_dointvec */
73int bootloader_type;
74
75unsigned long saved_video_mode;
76
f039b754
AK		 77int force_mwait __cpuinitdata;
78
f2d3efed
AK		 79/*
80 * Early DMI memory
81 */
82int dmi_alloc_index;
83char dmi_alloc_data[DMI_MAX_DATA];
84
1da177e4
LT		 85/*
86 * Setup options
87 */
1da177e4 88struct screen_info screen_info;
2ee60e17 89EXPORT_SYMBOL(screen_info);
1da177e4
LT		 90struct sys_desc_table_struct {
91 unsigned short length;
92 unsigned char table[0];
93};
94
95struct edid_info edid_info;
ba70710e 96EXPORT_SYMBOL_GPL(edid_info);
1da177e4
LT		 97
98extern int root_mountflags;
1da177e4 99
adf48856 100char __initdata command_line[COMMAND_LINE_SIZE];
1da177e4
LT		 101
102struct resource standard_io_resources[] = {
103 { .name = "dma1", .start = 0x00, .end = 0x1f,
104 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
105 { .name = "pic1", .start = 0x20, .end = 0x21,
106 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
107 { .name = "timer0", .start = 0x40, .end = 0x43,
108 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
109 { .name = "timer1", .start = 0x50, .end = 0x53,
110 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
111 { .name = "keyboard", .start = 0x60, .end = 0x6f,
112 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
113 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
114 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
115 { .name = "pic2", .start = 0xa0, .end = 0xa1,
116 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
117 { .name = "dma2", .start = 0xc0, .end = 0xdf,
118 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
119 { .name = "fpu", .start = 0xf0, .end = 0xff,
120 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
121};
122
1da177e4
LT		 123#define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
124
125struct resource data_resource = {
126 .name = "Kernel data",
127 .start = 0,
128 .end = 0,
129 .flags = IORESOURCE_RAM,
130};
131struct resource code_resource = {
132 .name = "Kernel code",
133 .start = 0,
134 .end = 0,
135 .flags = IORESOURCE_RAM,
136};
00bf4098
BW		 137struct resource bss_resource = {
138 .name = "Kernel bss",
139 .start = 0,
140 .end = 0,
141 .flags = IORESOURCE_RAM,
142};
1da177e4 143
8c61b900
TG		 144static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
145
2c8c0e6b
AK		 146#ifdef CONFIG_PROC_VMCORE
147/* elfcorehdr= specifies the location of elf core header
148 * stored by the crashed kernel. This option will be passed
149 * by kexec loader to the capture kernel.
150 */
151static int __init setup_elfcorehdr(char *arg)
681558fd 152{
2c8c0e6b
AK		 153 char *end;
154 if (!arg)
155 return -EINVAL;
156 elfcorehdr_addr = memparse(arg, &end);
157 return end > arg ? 0 : -EINVAL;
681558fd 158}
2c8c0e6b 159early_param("elfcorehdr", setup_elfcorehdr);
e2c03888
AK		 160#endif
161
2b97690f 162#ifndef CONFIG_NUMA
bbfceef4
MT		 163static void __init
164contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
1da177e4 165{
bbfceef4
MT		 166 unsigned long bootmap_size, bootmap;
167
bbfceef4
MT		 168 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
169 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
170 if (bootmap == -1L)
171 panic("Cannot find bootmem map of size %ld\n",bootmap_size);
172 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
5cb248ab
MG		 173 e820_register_active_regions(0, start_pfn, end_pfn);
174 free_bootmem_with_active_regions(0, end_pfn);
bbfceef4 175 reserve_bootmem(bootmap, bootmap_size);
1da177e4
LT		 176}
177#endif
178
1da177e4
LT		 179#if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
180struct edd edd;
181#ifdef CONFIG_EDD_MODULE
182EXPORT_SYMBOL(edd);
183#endif
184/**
185 * copy_edd() - Copy the BIOS EDD information
186 * from boot_params into a safe place.
187 *
188 */
189static inline void copy_edd(void)
190{
30c82645
PA		 191 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
192 sizeof(edd.mbr_signature));
193 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
194 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
195 edd.edd_info_nr = boot_params.eddbuf_entries;
1da177e4
LT		 196}
197#else
198static inline void copy_edd(void)
199{
200}
201#endif
202
5c3391f9
BW		 203#ifdef CONFIG_KEXEC
204static void __init reserve_crashkernel(void)
205{
206 unsigned long long free_mem;
207 unsigned long long crash_size, crash_base;
208 int ret;
209
210 free_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
211
212 ret = parse_crashkernel(boot_command_line, free_mem,
213 &crash_size, &crash_base);
214 if (ret == 0 && crash_size) {
215 if (crash_base > 0) {
216 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
217 "for crashkernel (System RAM: %ldMB)\n",
218 (unsigned long)(crash_size >> 20),
219 (unsigned long)(crash_base >> 20),
220 (unsigned long)(free_mem >> 20));
221 crashk_res.start = crash_base;
222 crashk_res.end = crash_base + crash_size - 1;
223 reserve_bootmem(crash_base, crash_size);
224 } else
225 printk(KERN_INFO "crashkernel reservation failed - "
226 "you have to specify a base address\n");
227 }
228}
229#else
230static inline void __init reserve_crashkernel(void)
231{}
232#endif
233
1da177e4 234#define EBDA_ADDR_POINTER 0x40E
ac71d12c
AK		 235
236unsigned __initdata ebda_addr;
237unsigned __initdata ebda_size;
238
239static void discover_ebda(void)
1da177e4 240{
ac71d12c 241 /*
1da177e4
LT		 242 * there is a real-mode segmented pointer pointing to the
243 * 4K EBDA area at 0x40E
244 */
bdb96a66 245 ebda_addr = *(unsigned short *)__va(EBDA_ADDR_POINTER);
ac71d12c
AK		 246 ebda_addr <<= 4;
247
bdb96a66 248 ebda_size = *(unsigned short *)__va(ebda_addr);
ac71d12c
AK		 249
250 /* Round EBDA up to pages */
251 if (ebda_size == 0)
252 ebda_size = 1;
253 ebda_size <<= 10;
254 ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
255 if (ebda_size > 64*1024)
256 ebda_size = 64*1024;
1da177e4
LT		 257}
258
259void __init setup_arch(char **cmdline_p)
260{
adf48856 261 printk(KERN_INFO "Command line: %s\n", boot_command_line);
43c85c9c 262
30c82645
PA		 263 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
264 screen_info = boot_params.screen_info;
265 edid_info = boot_params.edid_info;
266 saved_video_mode = boot_params.hdr.vid_mode;
267 bootloader_type = boot_params.hdr.type_of_loader;
1da177e4
LT		 268
269#ifdef CONFIG_BLK_DEV_RAM
30c82645
PA		 270 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
271 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
272 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
1da177e4
LT		 273#endif
274 setup_memory_region();
275 copy_edd();
276
30c82645 277 if (!boot_params.hdr.root_flags)
1da177e4
LT		 278 root_mountflags &= ~MS_RDONLY;
279 init_mm.start_code = (unsigned long) &_text;
280 init_mm.end_code = (unsigned long) &_etext;
281 init_mm.end_data = (unsigned long) &_edata;
282 init_mm.brk = (unsigned long) &_end;
283
e3ebadd9
LT		 284 code_resource.start = virt_to_phys(&_text);
285 code_resource.end = virt_to_phys(&_etext)-1;
286 data_resource.start = virt_to_phys(&_etext);
287 data_resource.end = virt_to_phys(&_edata)-1;
00bf4098
BW		 288 bss_resource.start = virt_to_phys(&__bss_start);
289 bss_resource.end = virt_to_phys(&__bss_stop)-1;
1da177e4 290
1da177e4
LT		 291 early_identify_cpu(&boot_cpu_data);
292
adf48856 293 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
2c8c0e6b
AK		 294 *cmdline_p = command_line;
295
296 parse_early_param();
297
298 finish_e820_parsing();
9ca33eb6 299
5cb248ab 300 e820_register_active_regions(0, 0, -1UL);
1da177e4
LT		 301 /*
302 * partially used pages are not usable - thus
303 * we are rounding upwards:
304 */
305 end_pfn = e820_end_of_ram();
caff0710 306 num_physpages = end_pfn;
1da177e4
LT		 307
308 check_efer();
309
ac71d12c
AK		 310 discover_ebda();
311
1da177e4
LT		 312 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
313
f2d3efed
AK		 314 dmi_scan_machine();
315
b02aae9c
RH		 316 io_delay_init();
317
71fff5e6
MT		 318#ifdef CONFIG_SMP
319 /* setup to use the static apicid table during kernel startup */
320 x86_cpu_to_apicid_ptr = (void *)&x86_cpu_to_apicid_init;
321#endif
322
888ba6c6 323#ifdef CONFIG_ACPI
1da177e4
LT		 324 /*
325 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
326 * Call this early for SRAT node setup.
327 */
328 acpi_boot_table_init();
329#endif
330
caff0710
JB		 331 /* How many end-of-memory variables you have, grandma! */
332 max_low_pfn = end_pfn;
333 max_pfn = end_pfn;
334 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
335
5cb248ab
MG		 336 /* Remove active ranges so rediscovery with NUMA-awareness happens */
337 remove_all_active_ranges();
338
1da177e4
LT		 339#ifdef CONFIG_ACPI_NUMA
340 /*
341 * Parse SRAT to discover nodes.
342 */
343 acpi_numa_init();
344#endif
345
2b97690f 346#ifdef CONFIG_NUMA
1da177e4
LT		 347 numa_initmem_init(0, end_pfn);
348#else
bbfceef4 349 contig_initmem_init(0, end_pfn);
1da177e4
LT		 350#endif
351
352 /* Reserve direct mapping */
353 reserve_bootmem_generic(table_start << PAGE_SHIFT,
354 (table_end - table_start) << PAGE_SHIFT);
355
356 /* reserve kernel */
ceee8822
AK		 357 reserve_bootmem_generic(__pa_symbol(&_text),
358 __pa_symbol(&_end) - __pa_symbol(&_text));
1da177e4
LT		 359
360 /*
361 * reserve physical page 0 - it's a special BIOS page on many boxes,
362 * enabling clean reboots, SMP operation, laptop functions.
363 */
364 reserve_bootmem_generic(0, PAGE_SIZE);
365
366 /* reserve ebda region */
ac71d12c
AK		 367 if (ebda_addr)
368 reserve_bootmem_generic(ebda_addr, ebda_size);
076422d2
AS		 369#ifdef CONFIG_NUMA
370 /* reserve nodemap region */
371 if (nodemap_addr)
372 reserve_bootmem_generic(nodemap_addr, nodemap_size);
373#endif
1da177e4
LT		 374
375#ifdef CONFIG_SMP
1da177e4 376 /* Reserve SMP trampoline */
90b1c208 377 reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, 2*PAGE_SIZE);
1da177e4
LT		 378#endif
379
673d5b43 380#ifdef CONFIG_ACPI_SLEEP
1da177e4
LT		 381 /*
382 * Reserve low memory region for sleep support.
383 */
384 acpi_reserve_bootmem();
385#endif
1da177e4
LT		 386 /*
387 * Find and reserve possible boot-time SMP configuration:
388 */
389 find_smp_config();
1da177e4 390#ifdef CONFIG_BLK_DEV_INITRD
30c82645
PA		 391 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
392 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
393 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
394 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
395 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
396
397 if (ramdisk_end <= end_of_mem) {
398 reserve_bootmem_generic(ramdisk_image, ramdisk_size);
399 initrd_start = ramdisk_image + PAGE_OFFSET;
400 initrd_end = initrd_start+ramdisk_size;
401 } else {
1da177e4 402 printk(KERN_ERR "initrd extends beyond end of memory "
30c82645
PA		 403 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
404 ramdisk_end, end_of_mem);
1da177e4
LT		 405 initrd_start = 0;
406 }
407 }
408#endif
5c3391f9 409 reserve_crashkernel();
1da177e4
LT		 410 paging_init();
411
dfa4698c 412 early_quirks();
1da177e4 413
51f62e18
AR		 414 /*
415 * set this early, so we dont allocate cpu0
416 * if MADT list doesnt list BSP first
417 * mpparse.c/MP_processor_info() allocates logical cpu numbers.
418 */
419 cpu_set(0, cpu_present_map);
888ba6c6 420#ifdef CONFIG_ACPI
1da177e4
LT		 421 /*
422 * Read APIC and some other early information from ACPI tables.
423 */
424 acpi_boot_init();
425#endif
426
05b3cbd8
RT		 427 init_cpu_to_node();
428
1da177e4
LT		 429 /*
430 * get boot-time SMP configuration:
431 */
432 if (smp_found_config)
433 get_smp_config();
434 init_apic_mappings();
1da177e4
LT		 435
436 /*
fc986db4
AK		 437 * We trust e820 completely. No explicit ROM probing in memory.
438 */
1da177e4 439 e820_reserve_resources();
e8eff5ac 440 e820_mark_nosave_regions();
1da177e4 441
1da177e4
LT		 442 {
443 unsigned i;
444 /* request I/O space for devices used on all i[345]86 PCs */
9d0ef4fd 445 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
1da177e4
LT		 446 request_resource(&ioport_resource, &standard_io_resources[i]);
447 }
448
a1e97782 449 e820_setup_gap();
1da177e4 450
1da177e4
LT		 451#ifdef CONFIG_VT
452#if defined(CONFIG_VGA_CONSOLE)
453 conswitchp = &vga_con;
454#elif defined(CONFIG_DUMMY_CONSOLE)
455 conswitchp = &dummy_con;
456#endif
457#endif
458}
459
e6982c67 460static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
1da177e4
LT		 461{
462 unsigned int *v;
463
ebfcaa96 464 if (c->extended_cpuid_level < 0x80000004)
1da177e4
LT		 465 return 0;
466
467 v = (unsigned int *) c->x86_model_id;
468 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
469 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
470 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
471 c->x86_model_id[48] = 0;
472 return 1;
473}
474
475
e6982c67 476static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
1da177e4
LT		 477{
478 unsigned int n, dummy, eax, ebx, ecx, edx;
479
ebfcaa96 480 n = c->extended_cpuid_level;
1da177e4
LT		 481
482 if (n >= 0x80000005) {
483 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
484 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
485 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
486 c->x86_cache_size=(ecx>>24)+(edx>>24);
487 /* On K8 L1 TLB is inclusive, so don't count it */
488 c->x86_tlbsize = 0;
489 }
490
491 if (n >= 0x80000006) {
492 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
493 ecx = cpuid_ecx(0x80000006);
494 c->x86_cache_size = ecx >> 16;
495 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
496
497 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
498 c->x86_cache_size, ecx & 0xFF);
499 }
500
501 if (n >= 0x80000007)
502 cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
503 if (n >= 0x80000008) {
504 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
505 c->x86_virt_bits = (eax >> 8) & 0xff;
506 c->x86_phys_bits = eax & 0xff;
507 }
508}
509
3f098c26
AK		 510#ifdef CONFIG_NUMA
511static int nearby_node(int apicid)
512{
513 int i;
514 for (i = apicid - 1; i >= 0; i--) {
515 int node = apicid_to_node[i];
516 if (node != NUMA_NO_NODE && node_online(node))
517 return node;
518 }
519 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
520 int node = apicid_to_node[i];
521 if (node != NUMA_NO_NODE && node_online(node))
522 return node;
523 }
524 return first_node(node_online_map); /* Shouldn't happen */
525}
526#endif
527
63518644
AK		 528/*
529 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
530 * Assumes number of cores is a power of two.
531 */
532static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
533{
534#ifdef CONFIG_SMP
b41e2939 535 unsigned bits;
3f098c26 536#ifdef CONFIG_NUMA
f3fa8ebc 537 int cpu = smp_processor_id();
3f098c26 538 int node = 0;
60c1bc82 539 unsigned apicid = hard_smp_processor_id();
3f098c26 540#endif
faee9a5d 541 unsigned ecx = cpuid_ecx(0x80000008);
b41e2939 542
faee9a5d 543 c->x86_max_cores = (ecx & 0xff) + 1;
b41e2939 544
faee9a5d
AK		 545 /* CPU telling us the core id bits shift? */
546 bits = (ecx >> 12) & 0xF;
547
548 /* Otherwise recompute */
549 if (bits == 0) {
550 while ((1 << bits) < c->x86_max_cores)
551 bits++;
552 }
b41e2939
AK		 553
554 /* Low order bits define the core id (index of core in socket) */
f3fa8ebc 555 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
b41e2939 556 /* Convert the APIC ID into the socket ID */
f3fa8ebc 557 c->phys_proc_id = phys_pkg_id(bits);
63518644
AK		 558
559#ifdef CONFIG_NUMA
f3fa8ebc 560 node = c->phys_proc_id;
3f098c26
AK		 561 if (apicid_to_node[apicid] != NUMA_NO_NODE)
562 node = apicid_to_node[apicid];
563 if (!node_online(node)) {
564 /* Two possibilities here:
565 - The CPU is missing memory and no node was created.
566 In that case try picking one from a nearby CPU
567 - The APIC IDs differ from the HyperTransport node IDs
568 which the K8 northbridge parsing fills in.
569 Assume they are all increased by a constant offset,
570 but in the same order as the HT nodeids.
571 If that doesn't result in a usable node fall back to the
572 path for the previous case. */
92cb7612 573 int ht_nodeid = apicid - (cpu_data(0).phys_proc_id << bits);
3f098c26
AK		 574 if (ht_nodeid >= 0 &&
575 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
576 node = apicid_to_node[ht_nodeid];
577 /* Pick a nearby node */
578 if (!node_online(node))
579 node = nearby_node(apicid);
580 }
69d81fcd 581 numa_set_node(cpu, node);
3f098c26 582
e42f9437 583 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
63518644 584#endif
63518644
AK		 585#endif
586}
1da177e4 587
fb79d22e
TG		 588#define ENABLE_C1E_MASK 0x18000000
589#define CPUID_PROCESSOR_SIGNATURE 1
590#define CPUID_XFAM 0x0ff00000
591#define CPUID_XFAM_K8 0x00000000
592#define CPUID_XFAM_10H 0x00100000
593#define CPUID_XFAM_11H 0x00200000
594#define CPUID_XMOD 0x000f0000
595#define CPUID_XMOD_REV_F 0x00040000
596
597/* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
598static __cpuinit int amd_apic_timer_broken(void)
599{
600 u32 lo, hi;
601 u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
602 switch (eax & CPUID_XFAM) {
603 case CPUID_XFAM_K8:
604 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
605 break;
606 case CPUID_XFAM_10H:
607 case CPUID_XFAM_11H:
608 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
609 if (lo & ENABLE_C1E_MASK)
610 return 1;
611 break;
612 default:
613 /* err on the side of caution */
614 return 1;
615 }
616 return 0;
617}
618
ed77504b 619static void __cpuinit init_amd(struct cpuinfo_x86 *c)
1da177e4 620{
7bcd3f34 621 unsigned level;
1da177e4 622
bc5e8fdf
LT		 623#ifdef CONFIG_SMP
624 unsigned long value;
625
7d318d77
AK		 626 /*
627 * Disable TLB flush filter by setting HWCR.FFDIS on K8
628 * bit 6 of msr C001_0015
629 *
630 * Errata 63 for SH-B3 steppings
631 * Errata 122 for all steppings (F+ have it disabled by default)
632 */
633 if (c->x86 == 15) {
634 rdmsrl(MSR_K8_HWCR, value);
635 value |= 1 << 6;
636 wrmsrl(MSR_K8_HWCR, value);
637 }
bc5e8fdf
LT		 638#endif
639
1da177e4
LT		 640 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
641 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
642 clear_bit(0*32+31, &c->x86_capability);
643
7bcd3f34
AK		 644 /* On C+ stepping K8 rep microcode works well for copy/memset */
645 level = cpuid_eax(1);
646 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58))
647 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
99741faa 648 if (c->x86 == 0x10 || c->x86 == 0x11)
5b74e3ab 649 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
7bcd3f34 650
18bd057b
AK		 651 /* Enable workaround for FXSAVE leak */
652 if (c->x86 >= 6)
653 set_bit(X86_FEATURE_FXSAVE_LEAK, &c->x86_capability);
654
e42f9437
RS		 655 level = get_model_name(c);
656 if (!level) {
1da177e4
LT		 657 switch (c->x86) {
658 case 15:
659 /* Should distinguish Models here, but this is only
660 a fallback anyways. */
661 strcpy(c->x86_model_id, "Hammer");
662 break;
663 }
664 }
665 display_cacheinfo(c);
666
130951cc
AK		 667 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
668 if (c->x86_power & (1<<8))
669 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
670
faee9a5d
AK		 671 /* Multi core CPU? */
672 if (c->extended_cpuid_level >= 0x80000008)
63518644 673 amd_detect_cmp(c);
1da177e4 674
67cddd94
AK		 675 if (c->extended_cpuid_level >= 0x80000006 &&
676 (cpuid_edx(0x80000006) & 0xf000))
677 num_cache_leaves = 4;
678 else
679 num_cache_leaves = 3;
2049336f 680
0bd8acd1
AK		 681 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
682 set_bit(X86_FEATURE_K8, &c->x86_capability);
683
61677965
AK		 684 /* RDTSC can be speculated around */
685 clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
f039b754
AK		 686
687 /* Family 10 doesn't support C states in MWAIT so don't use it */
688 if (c->x86 == 0x10 && !force_mwait)
689 clear_bit(X86_FEATURE_MWAIT, &c->x86_capability);
fb79d22e
TG		 690
691 if (amd_apic_timer_broken())
692 disable_apic_timer = 1;
1da177e4
LT		 693}
694
e6982c67 695static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
1da177e4
LT		 696{
697#ifdef CONFIG_SMP
698 u32 eax, ebx, ecx, edx;
94605eff 699 int index_msb, core_bits;
94605eff
SS		 700
701 cpuid(1, &eax, &ebx, &ecx, &edx);
702
94605eff 703
e42f9437 704 if (!cpu_has(c, X86_FEATURE_HT))
1da177e4 705 return;
e42f9437
RS		 706 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
707 goto out;
1da177e4 708
1da177e4 709 smp_num_siblings = (ebx & 0xff0000) >> 16;
94605eff 710
1da177e4
LT		 711 if (smp_num_siblings == 1) {
712 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
94605eff
SS		 713 } else if (smp_num_siblings > 1 ) {
714
1da177e4
LT		 715 if (smp_num_siblings > NR_CPUS) {
716 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
717 smp_num_siblings = 1;
718 return;
719 }
94605eff
SS		 720
721 index_msb = get_count_order(smp_num_siblings);
f3fa8ebc 722 c->phys_proc_id = phys_pkg_id(index_msb);
3dd9d514 723
94605eff 724 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
3dd9d514 725
94605eff
SS		 726 index_msb = get_count_order(smp_num_siblings) ;
727
728 core_bits = get_count_order(c->x86_max_cores);
3dd9d514 729
f3fa8ebc 730 c->cpu_core_id = phys_pkg_id(index_msb) &
94605eff 731 ((1 << core_bits) - 1);
1da177e4 732 }
e42f9437
RS		 733out:
734 if ((c->x86_max_cores * smp_num_siblings) > 1) {
735 printk(KERN_INFO "CPU: Physical Processor ID: %d\n", c->phys_proc_id);
736 printk(KERN_INFO "CPU: Processor Core ID: %d\n", c->cpu_core_id);
737 }
738
1da177e4
LT		 739#endif
740}
741
3dd9d514
AK		 742/*
743 * find out the number of processor cores on the die
744 */
e6982c67 745static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
3dd9d514 746{
2bbc419f 747 unsigned int eax, t;
3dd9d514
AK		 748
749 if (c->cpuid_level < 4)
750 return 1;
751
2bbc419f 752 cpuid_count(4, 0, &eax, &t, &t, &t);
3dd9d514
AK		 753
754 if (eax & 0x1f)
755 return ((eax >> 26) + 1);
756 else
757 return 1;
758}
759
df0cc26b
AK		 760static void srat_detect_node(void)
761{
762#ifdef CONFIG_NUMA
ddea7be0 763 unsigned node;
df0cc26b 764 int cpu = smp_processor_id();
e42f9437 765 int apicid = hard_smp_processor_id();
df0cc26b
AK		 766
767 /* Don't do the funky fallback heuristics the AMD version employs
768 for now. */
e42f9437 769 node = apicid_to_node[apicid];
df0cc26b 770 if (node == NUMA_NO_NODE)
0d015324 771 node = first_node(node_online_map);
69d81fcd 772 numa_set_node(cpu, node);
df0cc26b 773
c31fbb1a 774 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
df0cc26b
AK		 775#endif
776}
777
e6982c67 778static void __cpuinit init_intel(struct cpuinfo_x86 *c)
1da177e4
LT		 779{
780 /* Cache sizes */
781 unsigned n;
782
783 init_intel_cacheinfo(c);
0080e667
VP		 784 if (c->cpuid_level > 9 ) {
785 unsigned eax = cpuid_eax(10);
786 /* Check for version and the number of counters */
787 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
788 set_bit(X86_FEATURE_ARCH_PERFMON, &c->x86_capability);
789 }
790
36b2a8d5
SE		 791 if (cpu_has_ds) {
792 unsigned int l1, l2;
793 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
ee58fad5
SE		 794 if (!(l1 & (1<<11)))
795 set_bit(X86_FEATURE_BTS, c->x86_capability);
36b2a8d5
SE		 796 if (!(l1 & (1<<12)))
797 set_bit(X86_FEATURE_PEBS, c->x86_capability);
798 }
799
ebfcaa96 800 n = c->extended_cpuid_level;
1da177e4
LT		 801 if (n >= 0x80000008) {
802 unsigned eax = cpuid_eax(0x80000008);
803 c->x86_virt_bits = (eax >> 8) & 0xff;
804 c->x86_phys_bits = eax & 0xff;
af9c142d
SL		 805 /* CPUID workaround for Intel 0F34 CPU */
806 if (c->x86_vendor == X86_VENDOR_INTEL &&
807 c->x86 == 0xF && c->x86_model == 0x3 &&
808 c->x86_mask == 0x4)
809 c->x86_phys_bits = 36;
1da177e4
LT		 810 }
811
812 if (c->x86 == 15)
813 c->x86_cache_alignment = c->x86_clflush_size * 2;
39b3a791
AK		 814 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
815 (c->x86 == 0x6 && c->x86_model >= 0x0e))
c29601e9 816 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
27fbe5b2
AK		 817 if (c->x86 == 6)
818 set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
f3d73707
AV		 819 if (c->x86 == 15)
820 set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
821 else
822 clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
94605eff 823 c->x86_max_cores = intel_num_cpu_cores(c);
df0cc26b
AK		 824
825 srat_detect_node();
1da177e4
LT		 826}
827
672289e9 828static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
1da177e4
LT		 829{
830 char *v = c->x86_vendor_id;
831
832 if (!strcmp(v, "AuthenticAMD"))
833 c->x86_vendor = X86_VENDOR_AMD;
834 else if (!strcmp(v, "GenuineIntel"))
835 c->x86_vendor = X86_VENDOR_INTEL;
836 else
837 c->x86_vendor = X86_VENDOR_UNKNOWN;
838}
839
840struct cpu_model_info {
841 int vendor;
842 int family;
843 char *model_names[16];
844};
845
846/* Do some early cpuid on the boot CPU to get some parameter that are
847 needed before check_bugs. Everything advanced is in identify_cpu
848 below. */
8c61b900 849static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
1da177e4
LT		 850{
851 u32 tfms;
852
853 c->loops_per_jiffy = loops_per_jiffy;
854 c->x86_cache_size = -1;
855 c->x86_vendor = X86_VENDOR_UNKNOWN;
856 c->x86_model = c->x86_mask = 0; /* So far unknown... */
857 c->x86_vendor_id[0] = '\0'; /* Unset */
858 c->x86_model_id[0] = '\0'; /* Unset */
859 c->x86_clflush_size = 64;
860 c->x86_cache_alignment = c->x86_clflush_size;
94605eff 861 c->x86_max_cores = 1;
ebfcaa96 862 c->extended_cpuid_level = 0;
1da177e4
LT		 863 memset(&c->x86_capability, 0, sizeof c->x86_capability);
864
865 /* Get vendor name */
866 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
867 (unsigned int *)&c->x86_vendor_id[0],
868 (unsigned int *)&c->x86_vendor_id[8],
869 (unsigned int *)&c->x86_vendor_id[4]);
870
871 get_cpu_vendor(c);
872
873 /* Initialize the standard set of capabilities */
874 /* Note that the vendor-specific code below might override */
875
876 /* Intel-defined flags: level 0x00000001 */
877 if (c->cpuid_level >= 0x00000001) {
878 __u32 misc;
879 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
880 &c->x86_capability[0]);
881 c->x86 = (tfms >> 8) & 0xf;
882 c->x86_model = (tfms >> 4) & 0xf;
883 c->x86_mask = tfms & 0xf;
f5f786d0 884 if (c->x86 == 0xf)
1da177e4 885 c->x86 += (tfms >> 20) & 0xff;
f5f786d0 886 if (c->x86 >= 0x6)
1da177e4 887 c->x86_model += ((tfms >> 16) & 0xF) << 4;
1da177e4
LT		 888 if (c->x86_capability[0] & (1<<19))
889 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
1da177e4
LT		 890 } else {
891 /* Have CPUID level 0 only - unheard of */
892 c->x86 = 4;
893 }
a158608b
AK		 894
895#ifdef CONFIG_SMP
f3fa8ebc 896 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
a158608b 897#endif
1da177e4
LT		 898}
899
900/*
901 * This does the hard work of actually picking apart the CPU stuff...
902 */
e6982c67 903void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1da177e4
LT		 904{
905 int i;
906 u32 xlvl;
907
908 early_identify_cpu(c);
909
910 /* AMD-defined flags: level 0x80000001 */
911 xlvl = cpuid_eax(0x80000000);
ebfcaa96 912 c->extended_cpuid_level = xlvl;
1da177e4
LT		 913 if ((xlvl & 0xffff0000) == 0x80000000) {
914 if (xlvl >= 0x80000001) {
915 c->x86_capability[1] = cpuid_edx(0x80000001);
5b7abc6f 916 c->x86_capability[6] = cpuid_ecx(0x80000001);
1da177e4
LT		 917 }
918 if (xlvl >= 0x80000004)
919 get_model_name(c); /* Default name */
920 }
921
922 /* Transmeta-defined flags: level 0x80860001 */
923 xlvl = cpuid_eax(0x80860000);
924 if ((xlvl & 0xffff0000) == 0x80860000) {
925 /* Don't set x86_cpuid_level here for now to not confuse. */
926 if (xlvl >= 0x80860001)
927 c->x86_capability[2] = cpuid_edx(0x80860001);
928 }
929
1d67953f
VP		 930 init_scattered_cpuid_features(c);
931
1e9f28fa
SS		 932 c->apicid = phys_pkg_id(0);
933
1da177e4
LT		 934 /*
935 * Vendor-specific initialization. In this section we
936 * canonicalize the feature flags, meaning if there are
937 * features a certain CPU supports which CPUID doesn't
938 * tell us, CPUID claiming incorrect flags, or other bugs,
939 * we handle them here.
940 *
941 * At the end of this section, c->x86_capability better
942 * indicate the features this CPU genuinely supports!
943 */
944 switch (c->x86_vendor) {
945 case X86_VENDOR_AMD:
946 init_amd(c);
947 break;
948
949 case X86_VENDOR_INTEL:
950 init_intel(c);
951 break;
952
953 case X86_VENDOR_UNKNOWN:
954 default:
955 display_cacheinfo(c);
956 break;
957 }
958
959 select_idle_routine(c);
960 detect_ht(c);
1da177e4
LT		 961
962 /*
963 * On SMP, boot_cpu_data holds the common feature set between
964 * all CPUs; so make sure that we indicate which features are
965 * common between the CPUs. The first time this routine gets
966 * executed, c == &boot_cpu_data.
967 */
968 if (c != &boot_cpu_data) {
969 /* AND the already accumulated flags with these */
970 for (i = 0 ; i < NCAPINTS ; i++)
971 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
972 }
973
974#ifdef CONFIG_X86_MCE
975 mcheck_init(c);
976#endif
8bd99481 977 if (c != &boot_cpu_data)
3b520b23 978 mtrr_ap_init();
1da177e4 979#ifdef CONFIG_NUMA
3019e8eb 980 numa_add_cpu(smp_processor_id());
1da177e4
LT		 981#endif
982}
983
984
e6982c67 985void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1da177e4
LT		 986{
987 if (c->x86_model_id[0])
988 printk("%s", c->x86_model_id);
989
990 if (c->x86_mask || c->cpuid_level >= 0)
991 printk(" stepping %02x\n", c->x86_mask);
992 else
993 printk("\n");
994}
995
996/*
997 * Get CPU information for use by the procfs.
998 */
999
1000static int show_cpuinfo(struct seq_file *m, void *v)
1001{
1002 struct cpuinfo_x86 *c = v;
92cb7612 1003 int cpu = 0;
1da177e4
LT		 1004
1005 /*
1006 * These flag bits must match the definitions in <asm/cpufeature.h>.
1007 * NULL means this bit is undefined or reserved; either way it doesn't
1008 * have meaning as far as Linux is concerned. Note that it's important
1009 * to realize there is a difference between this table and CPUID -- if
1010 * applications want to get the raw CPUID data, they should access
1011 * /dev/cpu/<cpu_nr>/cpuid instead.
1012 */
121d7bf5 1013 static const char *const x86_cap_flags[] = {
1da177e4
LT		 1014 /* Intel-defined */
1015 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
1016 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
1017 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
ec481536 1018 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
1da177e4
LT		 1019
1020 /* AMD-defined */
3c3b73b6 1021 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4
LT		 1022 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
1023 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
f790cd30
AK		 1024 NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
1025 "3dnowext", "3dnow",
1da177e4
LT		 1026
1027 /* Transmeta-defined */
1028 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
1029 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1030 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1031 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1032
1033 /* Other (Linux-defined) */
ec481536
PA		 1034 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
1035 NULL, NULL, NULL, NULL,
1036 "constant_tsc", "up", NULL, "arch_perfmon",
1037 "pebs", "bts", NULL, "sync_rdtsc",
1038 "rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4
LT		 1039 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1040
1041 /* Intel-defined (#2) */
9d95dd84 1042 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
dcf10307 1043 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
e1054b39 1044 NULL, NULL, "dca", "sse4_1", "sse4_2", NULL, NULL, "popcnt",
1da177e4
LT		 1045 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1046
5b7abc6f
PA		 1047 /* VIA/Cyrix/Centaur-defined */
1048 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
ec481536 1049 "ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
5b7abc6f
PA		 1050 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1051 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1052
1da177e4 1053 /* AMD-defined (#2) */
e1054b39
PA		 1054 "lahf_lm", "cmp_legacy", "svm", "extapic",
1055 "cr8_legacy", "abm", "sse4a", "misalignsse",
1056 "3dnowprefetch", "osvw", "ibs", "sse5",
1057 "skinit", "wdt", NULL, NULL,
1da177e4 1058 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
5b7abc6f 1059 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1d67953f
VP		 1060
1061 /* Auxiliary (Linux-defined) */
1062 "ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1063 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1064 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1065 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4 1066 };
121d7bf5 1067 static const char *const x86_power_flags[] = {
1da177e4
LT		 1068 "ts", /* temperature sensor */
1069 "fid", /* frequency id control */
1070 "vid", /* voltage id control */
1071 "ttp", /* thermal trip */
1072 "tm",
3f98bc49 1073 "stc",
f790cd30
AK		 1074 "100mhzsteps",
1075 "hwpstate",
d824395c
JR		 1076 "", /* tsc invariant mapped to constant_tsc */
1077 /* nothing */
1da177e4
LT		 1078 };
1079
1080
1081#ifdef CONFIG_SMP
92cb7612 1082 cpu = c->cpu_index;
1da177e4
LT		 1083#endif
1084
1085 seq_printf(m,"processor\t: %u\n"
1086 "vendor_id\t: %s\n"
1087 "cpu family\t: %d\n"
1088 "model\t\t: %d\n"
1089 "model name\t: %s\n",
92cb7612 1090 (unsigned)cpu,
1da177e4
LT		 1091 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1092 c->x86,
1093 (int)c->x86_model,
1094 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1095
1096 if (c->x86_mask || c->cpuid_level >= 0)
1097 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1098 else
1099 seq_printf(m, "stepping\t: unknown\n");
1100
1101 if (cpu_has(c,X86_FEATURE_TSC)) {
92cb7612 1102 unsigned int freq = cpufreq_quick_get((unsigned)cpu);
95235ca2
VP		 1103 if (!freq)
1104 freq = cpu_khz;
1da177e4 1105 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
95235ca2 1106 freq / 1000, (freq % 1000));
1da177e4
LT		 1107 }
1108
1109 /* Cache size */
1110 if (c->x86_cache_size >= 0)
1111 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1112
1113#ifdef CONFIG_SMP
94605eff 1114 if (smp_num_siblings * c->x86_max_cores > 1) {
f3fa8ebc 1115 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
08357611
MT		 1116 seq_printf(m, "siblings\t: %d\n",
1117 cpus_weight(per_cpu(cpu_core_map, cpu)));
f3fa8ebc 1118 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
94605eff 1119 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
db468681 1120 }
1da177e4
LT		 1121#endif
1122
1123 seq_printf(m,
1124 "fpu\t\t: yes\n"
1125 "fpu_exception\t: yes\n"
1126 "cpuid level\t: %d\n"
1127 "wp\t\t: yes\n"
1128 "flags\t\t:",
1129 c->cpuid_level);
1130
1131 {
1132 int i;
1133 for ( i = 0 ; i < 32*NCAPINTS ; i++ )
3d1712c9 1134 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
1da177e4
LT		 1135 seq_printf(m, " %s", x86_cap_flags[i]);
1136 }
1137
1138 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1139 c->loops_per_jiffy/(500000/HZ),
1140 (c->loops_per_jiffy/(5000/HZ)) % 100);
1141
1142 if (c->x86_tlbsize > 0)
1143 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1144 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1145 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1146
1147 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1148 c->x86_phys_bits, c->x86_virt_bits);
1149
1150 seq_printf(m, "power management:");
1151 {
1152 unsigned i;
1153 for (i = 0; i < 32; i++)
1154 if (c->x86_power & (1 << i)) {
3f98bc49
AK		 1155 if (i < ARRAY_SIZE(x86_power_flags) &&
1156 x86_power_flags[i])
1157 seq_printf(m, "%s%s",
1158 x86_power_flags[i][0]?" ":"",
1159 x86_power_flags[i]);
1da177e4
LT		 1160 else
1161 seq_printf(m, " [%d]", i);
1162 }
1163 }
1da177e4 1164
d31ddaa1 1165 seq_printf(m, "\n\n");
1da177e4
LT		 1166
1167 return 0;
1168}
1169
1170static void *c_start(struct seq_file *m, loff_t *pos)
1171{
92cb7612 1172 if (*pos == 0) /* just in case, cpu 0 is not the first */
c0c52d28
AH		 1173 *pos = first_cpu(cpu_online_map);
1174 if ((*pos) < NR_CPUS && cpu_online(*pos))
92cb7612
MT		 1175 return &cpu_data(*pos);
1176 return NULL;
1da177e4
LT		 1177}
1178
1179static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1180{
c0c52d28 1181 *pos = next_cpu(*pos, cpu_online_map);
1da177e4
LT		 1182 return c_start(m, pos);
1183}
1184
1185static void c_stop(struct seq_file *m, void *v)
1186{
1187}
1188
1189struct seq_operations cpuinfo_op = {
1190 .start =c_start,
1191 .next = c_next,
1192 .stop = c_stop,
1193 .show = show_cpuinfo,
1194};
kernel source for telekom puls (alcatel/mediatek)