Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 1995 Linus Torvalds |
1da177e4 LT |
3 | */ |
4 | ||
5 | /* | |
6 | * This file handles the architecture-dependent parts of initialization | |
7 | */ | |
8 | ||
9 | #include <linux/errno.h> | |
10 | #include <linux/sched.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/mm.h> | |
13 | #include <linux/stddef.h> | |
14 | #include <linux/unistd.h> | |
15 | #include <linux/ptrace.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/user.h> | |
894673ee | 18 | #include <linux/screen_info.h> |
1da177e4 LT |
19 | #include <linux/ioport.h> |
20 | #include <linux/delay.h> | |
1da177e4 LT |
21 | #include <linux/init.h> |
22 | #include <linux/initrd.h> | |
23 | #include <linux/highmem.h> | |
24 | #include <linux/bootmem.h> | |
25 | #include <linux/module.h> | |
26 | #include <asm/processor.h> | |
27 | #include <linux/console.h> | |
28 | #include <linux/seq_file.h> | |
aac04b32 | 29 | #include <linux/crash_dump.h> |
1da177e4 LT |
30 | #include <linux/root_dev.h> |
31 | #include <linux/pci.h> | |
5b83683f | 32 | #include <linux/efi.h> |
1da177e4 LT |
33 | #include <linux/acpi.h> |
34 | #include <linux/kallsyms.h> | |
35 | #include <linux/edd.h> | |
bbfceef4 | 36 | #include <linux/mmzone.h> |
5f5609df | 37 | #include <linux/kexec.h> |
95235ca2 | 38 | #include <linux/cpufreq.h> |
e9928674 | 39 | #include <linux/dmi.h> |
17a941d8 | 40 | #include <linux/dma-mapping.h> |
681558fd | 41 | #include <linux/ctype.h> |
746ef0cd | 42 | #include <linux/uaccess.h> |
f212ec4b | 43 | #include <linux/init_ohci1394_dma.h> |
bbfceef4 | 44 | |
1da177e4 LT |
45 | #include <asm/mtrr.h> |
46 | #include <asm/uaccess.h> | |
47 | #include <asm/system.h> | |
e4026440 | 48 | #include <asm/vsyscall.h> |
1da177e4 LT |
49 | #include <asm/io.h> |
50 | #include <asm/smp.h> | |
51 | #include <asm/msr.h> | |
52 | #include <asm/desc.h> | |
53 | #include <video/edid.h> | |
54 | #include <asm/e820.h> | |
55 | #include <asm/dma.h> | |
aaf23042 | 56 | #include <asm/gart.h> |
1da177e4 LT |
57 | #include <asm/mpspec.h> |
58 | #include <asm/mmu_context.h> | |
1da177e4 LT |
59 | #include <asm/proto.h> |
60 | #include <asm/setup.h> | |
61 | #include <asm/mach_apic.h> | |
62 | #include <asm/numa.h> | |
2bc0414e | 63 | #include <asm/sections.h> |
f2d3efed | 64 | #include <asm/dmi.h> |
00bf4098 | 65 | #include <asm/cacheflush.h> |
af7a78e9 | 66 | #include <asm/mce.h> |
eee3af4a | 67 | #include <asm/ds.h> |
df3825c5 | 68 | #include <asm/topology.h> |
1da177e4 | 69 | |
746ef0cd GOC |
70 | #ifdef CONFIG_PARAVIRT |
71 | #include <asm/paravirt.h> | |
72 | #else | |
73 | #define ARCH_SETUP | |
74 | #endif | |
75 | ||
1da177e4 LT |
76 | /* |
77 | * Machine setup.. | |
78 | */ | |
79 | ||
6c231b7b | 80 | struct cpuinfo_x86 boot_cpu_data __read_mostly; |
2ee60e17 | 81 | EXPORT_SYMBOL(boot_cpu_data); |
1da177e4 | 82 | |
7d851c8d AK |
83 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
84 | ||
1da177e4 LT |
85 | unsigned long mmu_cr4_features; |
86 | ||
1da177e4 LT |
87 | /* Boot loader ID as an integer, for the benefit of proc_dointvec */ |
88 | int bootloader_type; | |
89 | ||
90 | unsigned long saved_video_mode; | |
91 | ||
f039b754 AK |
92 | int force_mwait __cpuinitdata; |
93 | ||
04e1ba85 | 94 | /* |
f2d3efed AK |
95 | * Early DMI memory |
96 | */ | |
97 | int dmi_alloc_index; | |
98 | char dmi_alloc_data[DMI_MAX_DATA]; | |
99 | ||
1da177e4 LT |
100 | /* |
101 | * Setup options | |
102 | */ | |
1da177e4 | 103 | struct screen_info screen_info; |
2ee60e17 | 104 | EXPORT_SYMBOL(screen_info); |
1da177e4 LT |
105 | struct sys_desc_table_struct { |
106 | unsigned short length; | |
107 | unsigned char table[0]; | |
108 | }; | |
109 | ||
110 | struct edid_info edid_info; | |
ba70710e | 111 | EXPORT_SYMBOL_GPL(edid_info); |
1da177e4 LT |
112 | |
113 | extern int root_mountflags; | |
1da177e4 | 114 | |
adf48856 | 115 | char __initdata command_line[COMMAND_LINE_SIZE]; |
1da177e4 LT |
116 | |
117 | struct resource standard_io_resources[] = { | |
118 | { .name = "dma1", .start = 0x00, .end = 0x1f, | |
119 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
120 | { .name = "pic1", .start = 0x20, .end = 0x21, | |
121 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
122 | { .name = "timer0", .start = 0x40, .end = 0x43, | |
123 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
124 | { .name = "timer1", .start = 0x50, .end = 0x53, | |
125 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
126 | { .name = "keyboard", .start = 0x60, .end = 0x6f, | |
127 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
128 | { .name = "dma page reg", .start = 0x80, .end = 0x8f, | |
129 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
130 | { .name = "pic2", .start = 0xa0, .end = 0xa1, | |
131 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
132 | { .name = "dma2", .start = 0xc0, .end = 0xdf, | |
133 | .flags = IORESOURCE_BUSY | IORESOURCE_IO }, | |
134 | { .name = "fpu", .start = 0xf0, .end = 0xff, | |
135 | .flags = IORESOURCE_BUSY | IORESOURCE_IO } | |
136 | }; | |
137 | ||
1da177e4 LT |
138 | #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM) |
139 | ||
c9cce83d | 140 | static struct resource data_resource = { |
1da177e4 LT |
141 | .name = "Kernel data", |
142 | .start = 0, | |
143 | .end = 0, | |
144 | .flags = IORESOURCE_RAM, | |
145 | }; | |
c9cce83d | 146 | static struct resource code_resource = { |
1da177e4 LT |
147 | .name = "Kernel code", |
148 | .start = 0, | |
149 | .end = 0, | |
150 | .flags = IORESOURCE_RAM, | |
151 | }; | |
c9cce83d | 152 | static struct resource bss_resource = { |
00bf4098 BW |
153 | .name = "Kernel bss", |
154 | .start = 0, | |
155 | .end = 0, | |
156 | .flags = IORESOURCE_RAM, | |
157 | }; | |
1da177e4 | 158 | |
8c61b900 TG |
159 | static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c); |
160 | ||
2c8c0e6b AK |
161 | #ifdef CONFIG_PROC_VMCORE |
162 | /* elfcorehdr= specifies the location of elf core header | |
163 | * stored by the crashed kernel. This option will be passed | |
164 | * by kexec loader to the capture kernel. | |
165 | */ | |
166 | static int __init setup_elfcorehdr(char *arg) | |
681558fd | 167 | { |
2c8c0e6b AK |
168 | char *end; |
169 | if (!arg) | |
170 | return -EINVAL; | |
171 | elfcorehdr_addr = memparse(arg, &end); | |
172 | return end > arg ? 0 : -EINVAL; | |
681558fd | 173 | } |
2c8c0e6b | 174 | early_param("elfcorehdr", setup_elfcorehdr); |
e2c03888 AK |
175 | #endif |
176 | ||
2b97690f | 177 | #ifndef CONFIG_NUMA |
bbfceef4 MT |
178 | static void __init |
179 | contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn) | |
1da177e4 | 180 | { |
bbfceef4 MT |
181 | unsigned long bootmap_size, bootmap; |
182 | ||
bbfceef4 | 183 | bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT; |
24a5da73 YL |
184 | bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size, |
185 | PAGE_SIZE); | |
bbfceef4 | 186 | if (bootmap == -1L) |
04e1ba85 | 187 | panic("Cannot find bootmem map of size %ld\n", bootmap_size); |
bbfceef4 | 188 | bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn); |
5cb248ab MG |
189 | e820_register_active_regions(0, start_pfn, end_pfn); |
190 | free_bootmem_with_active_regions(0, end_pfn); | |
72a7fe39 | 191 | reserve_bootmem(bootmap, bootmap_size, BOOTMEM_DEFAULT); |
04e1ba85 | 192 | } |
1da177e4 LT |
193 | #endif |
194 | ||
1da177e4 LT |
195 | #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE) |
196 | struct edd edd; | |
197 | #ifdef CONFIG_EDD_MODULE | |
198 | EXPORT_SYMBOL(edd); | |
199 | #endif | |
200 | /** | |
201 | * copy_edd() - Copy the BIOS EDD information | |
202 | * from boot_params into a safe place. | |
203 | * | |
204 | */ | |
205 | static inline void copy_edd(void) | |
206 | { | |
30c82645 PA |
207 | memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer, |
208 | sizeof(edd.mbr_signature)); | |
209 | memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info)); | |
210 | edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries; | |
211 | edd.edd_info_nr = boot_params.eddbuf_entries; | |
1da177e4 LT |
212 | } |
213 | #else | |
214 | static inline void copy_edd(void) | |
215 | { | |
216 | } | |
217 | #endif | |
218 | ||
5c3391f9 BW |
219 | #ifdef CONFIG_KEXEC |
220 | static void __init reserve_crashkernel(void) | |
221 | { | |
18a01a3b | 222 | unsigned long long total_mem; |
5c3391f9 BW |
223 | unsigned long long crash_size, crash_base; |
224 | int ret; | |
225 | ||
18a01a3b | 226 | total_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT; |
5c3391f9 | 227 | |
18a01a3b | 228 | ret = parse_crashkernel(boot_command_line, total_mem, |
5c3391f9 BW |
229 | &crash_size, &crash_base); |
230 | if (ret == 0 && crash_size) { | |
18a01a3b | 231 | if (crash_base <= 0) { |
5c3391f9 BW |
232 | printk(KERN_INFO "crashkernel reservation failed - " |
233 | "you have to specify a base address\n"); | |
18a01a3b BW |
234 | return; |
235 | } | |
236 | ||
237 | if (reserve_bootmem(crash_base, crash_size, | |
238 | BOOTMEM_EXCLUSIVE) < 0) { | |
239 | printk(KERN_INFO "crashkernel reservation failed - " | |
240 | "memory is in use\n"); | |
241 | return; | |
242 | } | |
243 | ||
244 | printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " | |
245 | "for crashkernel (System RAM: %ldMB)\n", | |
246 | (unsigned long)(crash_size >> 20), | |
247 | (unsigned long)(crash_base >> 20), | |
248 | (unsigned long)(total_mem >> 20)); | |
249 | crashk_res.start = crash_base; | |
250 | crashk_res.end = crash_base + crash_size - 1; | |
5c3391f9 BW |
251 | } |
252 | } | |
253 | #else | |
254 | static inline void __init reserve_crashkernel(void) | |
255 | {} | |
256 | #endif | |
257 | ||
746ef0cd | 258 | /* Overridden in paravirt.c if CONFIG_PARAVIRT */ |
e3cfac84 | 259 | void __attribute__((weak)) __init memory_setup(void) |
746ef0cd GOC |
260 | { |
261 | machine_specific_memory_setup(); | |
262 | } | |
263 | ||
f212ec4b BK |
264 | /* |
265 | * setup_arch - architecture-specific boot-time initializations | |
266 | * | |
267 | * Note: On x86_64, fixmaps are ready for use even before this is called. | |
268 | */ | |
1da177e4 LT |
269 | void __init setup_arch(char **cmdline_p) |
270 | { | |
04e1ba85 TG |
271 | unsigned i; |
272 | ||
adf48856 | 273 | printk(KERN_INFO "Command line: %s\n", boot_command_line); |
43c85c9c | 274 | |
30c82645 PA |
275 | ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev); |
276 | screen_info = boot_params.screen_info; | |
277 | edid_info = boot_params.edid_info; | |
278 | saved_video_mode = boot_params.hdr.vid_mode; | |
279 | bootloader_type = boot_params.hdr.type_of_loader; | |
1da177e4 LT |
280 | |
281 | #ifdef CONFIG_BLK_DEV_RAM | |
30c82645 PA |
282 | rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK; |
283 | rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0); | |
284 | rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0); | |
1da177e4 | 285 | #endif |
5b83683f HY |
286 | #ifdef CONFIG_EFI |
287 | if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature, | |
288 | "EL64", 4)) | |
289 | efi_enabled = 1; | |
290 | #endif | |
746ef0cd GOC |
291 | |
292 | ARCH_SETUP | |
293 | ||
294 | memory_setup(); | |
1da177e4 LT |
295 | copy_edd(); |
296 | ||
30c82645 | 297 | if (!boot_params.hdr.root_flags) |
1da177e4 LT |
298 | root_mountflags &= ~MS_RDONLY; |
299 | init_mm.start_code = (unsigned long) &_text; | |
300 | init_mm.end_code = (unsigned long) &_etext; | |
301 | init_mm.end_data = (unsigned long) &_edata; | |
302 | init_mm.brk = (unsigned long) &_end; | |
303 | ||
e3ebadd9 LT |
304 | code_resource.start = virt_to_phys(&_text); |
305 | code_resource.end = virt_to_phys(&_etext)-1; | |
306 | data_resource.start = virt_to_phys(&_etext); | |
307 | data_resource.end = virt_to_phys(&_edata)-1; | |
00bf4098 BW |
308 | bss_resource.start = virt_to_phys(&__bss_start); |
309 | bss_resource.end = virt_to_phys(&__bss_stop)-1; | |
1da177e4 | 310 | |
1da177e4 LT |
311 | early_identify_cpu(&boot_cpu_data); |
312 | ||
adf48856 | 313 | strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE); |
2c8c0e6b AK |
314 | *cmdline_p = command_line; |
315 | ||
316 | parse_early_param(); | |
317 | ||
f212ec4b BK |
318 | #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT |
319 | if (init_ohci1394_dma_early) | |
320 | init_ohci1394_dma_on_all_controllers(); | |
321 | #endif | |
322 | ||
2c8c0e6b | 323 | finish_e820_parsing(); |
9ca33eb6 | 324 | |
aaf23042 YL |
325 | early_gart_iommu_check(); |
326 | ||
5cb248ab | 327 | e820_register_active_regions(0, 0, -1UL); |
1da177e4 LT |
328 | /* |
329 | * partially used pages are not usable - thus | |
330 | * we are rounding upwards: | |
331 | */ | |
332 | end_pfn = e820_end_of_ram(); | |
99fc8d42 JB |
333 | /* update e820 for memory not covered by WB MTRRs */ |
334 | mtrr_bp_init(); | |
335 | if (mtrr_trim_uncached_memory(end_pfn)) { | |
336 | e820_register_active_regions(0, 0, -1UL); | |
337 | end_pfn = e820_end_of_ram(); | |
338 | } | |
339 | ||
caff0710 | 340 | num_physpages = end_pfn; |
1da177e4 LT |
341 | |
342 | check_efer(); | |
343 | ||
344 | init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT)); | |
5b83683f HY |
345 | if (efi_enabled) |
346 | efi_init(); | |
1da177e4 | 347 | |
2785c8d0 GC |
348 | #ifdef CONFIG_PARAVIRT |
349 | vsmp_init(); | |
350 | #endif | |
351 | ||
f2d3efed AK |
352 | dmi_scan_machine(); |
353 | ||
b02aae9c RH |
354 | io_delay_init(); |
355 | ||
71fff5e6 | 356 | #ifdef CONFIG_SMP |
df3825c5 | 357 | /* setup to use the early static init tables during kernel startup */ |
3effef1f YL |
358 | x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init; |
359 | x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init; | |
e8c10ef9 | 360 | #ifdef CONFIG_NUMA |
3effef1f | 361 | x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init; |
71fff5e6 | 362 | #endif |
e8c10ef9 | 363 | #endif |
71fff5e6 | 364 | |
888ba6c6 | 365 | #ifdef CONFIG_ACPI |
1da177e4 LT |
366 | /* |
367 | * Initialize the ACPI boot-time table parser (gets the RSDP and SDT). | |
368 | * Call this early for SRAT node setup. | |
369 | */ | |
370 | acpi_boot_table_init(); | |
371 | #endif | |
372 | ||
caff0710 JB |
373 | /* How many end-of-memory variables you have, grandma! */ |
374 | max_low_pfn = end_pfn; | |
375 | max_pfn = end_pfn; | |
376 | high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1; | |
377 | ||
5cb248ab MG |
378 | /* Remove active ranges so rediscovery with NUMA-awareness happens */ |
379 | remove_all_active_ranges(); | |
380 | ||
1da177e4 LT |
381 | #ifdef CONFIG_ACPI_NUMA |
382 | /* | |
383 | * Parse SRAT to discover nodes. | |
384 | */ | |
385 | acpi_numa_init(); | |
386 | #endif | |
387 | ||
2b97690f | 388 | #ifdef CONFIG_NUMA |
04e1ba85 | 389 | numa_initmem_init(0, end_pfn); |
1da177e4 | 390 | #else |
bbfceef4 | 391 | contig_initmem_init(0, end_pfn); |
1da177e4 LT |
392 | #endif |
393 | ||
75175278 | 394 | early_res_to_bootmem(); |
1da177e4 | 395 | |
673d5b43 | 396 | #ifdef CONFIG_ACPI_SLEEP |
1da177e4 | 397 | /* |
04e1ba85 | 398 | * Reserve low memory region for sleep support. |
1da177e4 | 399 | */ |
04e1ba85 TG |
400 | acpi_reserve_bootmem(); |
401 | #endif | |
5b83683f | 402 | |
a3828064 | 403 | if (efi_enabled) |
5b83683f | 404 | efi_reserve_bootmem(); |
5b83683f | 405 | |
04e1ba85 TG |
406 | /* |
407 | * Find and reserve possible boot-time SMP configuration: | |
408 | */ | |
1da177e4 | 409 | find_smp_config(); |
1da177e4 | 410 | #ifdef CONFIG_BLK_DEV_INITRD |
30c82645 PA |
411 | if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) { |
412 | unsigned long ramdisk_image = boot_params.hdr.ramdisk_image; | |
413 | unsigned long ramdisk_size = boot_params.hdr.ramdisk_size; | |
414 | unsigned long ramdisk_end = ramdisk_image + ramdisk_size; | |
415 | unsigned long end_of_mem = end_pfn << PAGE_SHIFT; | |
416 | ||
417 | if (ramdisk_end <= end_of_mem) { | |
418 | reserve_bootmem_generic(ramdisk_image, ramdisk_size); | |
419 | initrd_start = ramdisk_image + PAGE_OFFSET; | |
420 | initrd_end = initrd_start+ramdisk_size; | |
421 | } else { | |
75175278 AK |
422 | /* Assumes everything on node 0 */ |
423 | free_bootmem(ramdisk_image, ramdisk_size); | |
1da177e4 | 424 | printk(KERN_ERR "initrd extends beyond end of memory " |
30c82645 PA |
425 | "(0x%08lx > 0x%08lx)\ndisabling initrd\n", |
426 | ramdisk_end, end_of_mem); | |
1da177e4 LT |
427 | initrd_start = 0; |
428 | } | |
429 | } | |
430 | #endif | |
5c3391f9 | 431 | reserve_crashkernel(); |
1da177e4 | 432 | paging_init(); |
e4026440 | 433 | map_vsyscall(); |
1da177e4 | 434 | |
dfa4698c | 435 | early_quirks(); |
1da177e4 | 436 | |
888ba6c6 | 437 | #ifdef CONFIG_ACPI |
1da177e4 LT |
438 | /* |
439 | * Read APIC and some other early information from ACPI tables. | |
440 | */ | |
441 | acpi_boot_init(); | |
442 | #endif | |
443 | ||
05b3cbd8 RT |
444 | init_cpu_to_node(); |
445 | ||
1da177e4 LT |
446 | /* |
447 | * get boot-time SMP configuration: | |
448 | */ | |
449 | if (smp_found_config) | |
450 | get_smp_config(); | |
451 | init_apic_mappings(); | |
3e35a0e5 | 452 | ioapic_init_mappings(); |
1da177e4 LT |
453 | |
454 | /* | |
fc986db4 | 455 | * We trust e820 completely. No explicit ROM probing in memory. |
04e1ba85 | 456 | */ |
c9cce83d | 457 | e820_reserve_resources(&code_resource, &data_resource, &bss_resource); |
e8eff5ac | 458 | e820_mark_nosave_regions(); |
1da177e4 | 459 | |
1da177e4 | 460 | /* request I/O space for devices used on all i[345]86 PCs */ |
9d0ef4fd | 461 | for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++) |
1da177e4 | 462 | request_resource(&ioport_resource, &standard_io_resources[i]); |
1da177e4 | 463 | |
a1e97782 | 464 | e820_setup_gap(); |
1da177e4 | 465 | |
1da177e4 LT |
466 | #ifdef CONFIG_VT |
467 | #if defined(CONFIG_VGA_CONSOLE) | |
5b83683f HY |
468 | if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY)) |
469 | conswitchp = &vga_con; | |
1da177e4 LT |
470 | #elif defined(CONFIG_DUMMY_CONSOLE) |
471 | conswitchp = &dummy_con; | |
472 | #endif | |
473 | #endif | |
474 | } | |
475 | ||
e6982c67 | 476 | static int __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
477 | { |
478 | unsigned int *v; | |
479 | ||
ebfcaa96 | 480 | if (c->extended_cpuid_level < 0x80000004) |
1da177e4 LT |
481 | return 0; |
482 | ||
483 | v = (unsigned int *) c->x86_model_id; | |
484 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
485 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
486 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
487 | c->x86_model_id[48] = 0; | |
488 | return 1; | |
489 | } | |
490 | ||
491 | ||
e6982c67 | 492 | static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 LT |
493 | { |
494 | unsigned int n, dummy, eax, ebx, ecx, edx; | |
495 | ||
ebfcaa96 | 496 | n = c->extended_cpuid_level; |
1da177e4 LT |
497 | |
498 | if (n >= 0x80000005) { | |
499 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); | |
04e1ba85 TG |
500 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), " |
501 | "D cache %dK (%d bytes/line)\n", | |
502 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); | |
503 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
1da177e4 LT |
504 | /* On K8 L1 TLB is inclusive, so don't count it */ |
505 | c->x86_tlbsize = 0; | |
506 | } | |
507 | ||
508 | if (n >= 0x80000006) { | |
509 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); | |
510 | ecx = cpuid_ecx(0x80000006); | |
511 | c->x86_cache_size = ecx >> 16; | |
512 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
513 | ||
514 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
515 | c->x86_cache_size, ecx & 0xFF); | |
516 | } | |
1da177e4 | 517 | if (n >= 0x80000008) { |
04e1ba85 | 518 | cpuid(0x80000008, &eax, &dummy, &dummy, &dummy); |
1da177e4 LT |
519 | c->x86_virt_bits = (eax >> 8) & 0xff; |
520 | c->x86_phys_bits = eax & 0xff; | |
521 | } | |
522 | } | |
523 | ||
3f098c26 | 524 | #ifdef CONFIG_NUMA |
08acb672 | 525 | static int __cpuinit nearby_node(int apicid) |
3f098c26 | 526 | { |
04e1ba85 TG |
527 | int i, node; |
528 | ||
3f098c26 | 529 | for (i = apicid - 1; i >= 0; i--) { |
04e1ba85 | 530 | node = apicid_to_node[i]; |
3f098c26 AK |
531 | if (node != NUMA_NO_NODE && node_online(node)) |
532 | return node; | |
533 | } | |
534 | for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { | |
04e1ba85 | 535 | node = apicid_to_node[i]; |
3f098c26 AK |
536 | if (node != NUMA_NO_NODE && node_online(node)) |
537 | return node; | |
538 | } | |
539 | return first_node(node_online_map); /* Shouldn't happen */ | |
540 | } | |
541 | #endif | |
542 | ||
63518644 AK |
543 | /* |
544 | * On a AMD dual core setup the lower bits of the APIC id distingush the cores. | |
545 | * Assumes number of cores is a power of two. | |
546 | */ | |
adb8daed | 547 | static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c) |
63518644 AK |
548 | { |
549 | #ifdef CONFIG_SMP | |
b41e2939 | 550 | unsigned bits; |
3f098c26 | 551 | #ifdef CONFIG_NUMA |
f3fa8ebc | 552 | int cpu = smp_processor_id(); |
3f098c26 | 553 | int node = 0; |
60c1bc82 | 554 | unsigned apicid = hard_smp_processor_id(); |
3f098c26 | 555 | #endif |
a860b63c | 556 | bits = c->x86_coreid_bits; |
b41e2939 AK |
557 | |
558 | /* Low order bits define the core id (index of core in socket) */ | |
f3fa8ebc | 559 | c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1); |
b41e2939 | 560 | /* Convert the APIC ID into the socket ID */ |
f3fa8ebc | 561 | c->phys_proc_id = phys_pkg_id(bits); |
63518644 AK |
562 | |
563 | #ifdef CONFIG_NUMA | |
04e1ba85 TG |
564 | node = c->phys_proc_id; |
565 | if (apicid_to_node[apicid] != NUMA_NO_NODE) | |
566 | node = apicid_to_node[apicid]; | |
567 | if (!node_online(node)) { | |
568 | /* Two possibilities here: | |
569 | - The CPU is missing memory and no node was created. | |
570 | In that case try picking one from a nearby CPU | |
571 | - The APIC IDs differ from the HyperTransport node IDs | |
572 | which the K8 northbridge parsing fills in. | |
573 | Assume they are all increased by a constant offset, | |
574 | but in the same order as the HT nodeids. | |
575 | If that doesn't result in a usable node fall back to the | |
576 | path for the previous case. */ | |
577 | ||
92cb7612 | 578 | int ht_nodeid = apicid - (cpu_data(0).phys_proc_id << bits); |
04e1ba85 TG |
579 | |
580 | if (ht_nodeid >= 0 && | |
581 | apicid_to_node[ht_nodeid] != NUMA_NO_NODE) | |
582 | node = apicid_to_node[ht_nodeid]; | |
583 | /* Pick a nearby node */ | |
584 | if (!node_online(node)) | |
585 | node = nearby_node(apicid); | |
586 | } | |
69d81fcd | 587 | numa_set_node(cpu, node); |
3f098c26 | 588 | |
e42f9437 | 589 | printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node); |
63518644 | 590 | #endif |
63518644 AK |
591 | #endif |
592 | } | |
1da177e4 | 593 | |
2b16a235 | 594 | static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c) |
a860b63c YL |
595 | { |
596 | #ifdef CONFIG_SMP | |
597 | unsigned bits, ecx; | |
598 | ||
599 | /* Multi core CPU? */ | |
600 | if (c->extended_cpuid_level < 0x80000008) | |
601 | return; | |
602 | ||
603 | ecx = cpuid_ecx(0x80000008); | |
604 | ||
605 | c->x86_max_cores = (ecx & 0xff) + 1; | |
606 | ||
607 | /* CPU telling us the core id bits shift? */ | |
608 | bits = (ecx >> 12) & 0xF; | |
609 | ||
610 | /* Otherwise recompute */ | |
611 | if (bits == 0) { | |
612 | while ((1 << bits) < c->x86_max_cores) | |
613 | bits++; | |
614 | } | |
615 | ||
616 | c->x86_coreid_bits = bits; | |
617 | ||
618 | #endif | |
619 | } | |
620 | ||
fb79d22e TG |
621 | #define ENABLE_C1E_MASK 0x18000000 |
622 | #define CPUID_PROCESSOR_SIGNATURE 1 | |
623 | #define CPUID_XFAM 0x0ff00000 | |
624 | #define CPUID_XFAM_K8 0x00000000 | |
625 | #define CPUID_XFAM_10H 0x00100000 | |
626 | #define CPUID_XFAM_11H 0x00200000 | |
627 | #define CPUID_XMOD 0x000f0000 | |
628 | #define CPUID_XMOD_REV_F 0x00040000 | |
629 | ||
630 | /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */ | |
631 | static __cpuinit int amd_apic_timer_broken(void) | |
632 | { | |
04e1ba85 TG |
633 | u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); |
634 | ||
fb79d22e TG |
635 | switch (eax & CPUID_XFAM) { |
636 | case CPUID_XFAM_K8: | |
637 | if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F) | |
638 | break; | |
639 | case CPUID_XFAM_10H: | |
640 | case CPUID_XFAM_11H: | |
641 | rdmsr(MSR_K8_ENABLE_C1E, lo, hi); | |
642 | if (lo & ENABLE_C1E_MASK) | |
643 | return 1; | |
644 | break; | |
645 | default: | |
646 | /* err on the side of caution */ | |
647 | return 1; | |
648 | } | |
649 | return 0; | |
650 | } | |
651 | ||
2b16a235 AK |
652 | static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) |
653 | { | |
654 | early_init_amd_mc(c); | |
655 | ||
656 | /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */ | |
657 | if (c->x86_power & (1<<8)) | |
658 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | |
659 | } | |
660 | ||
ed77504b | 661 | static void __cpuinit init_amd(struct cpuinfo_x86 *c) |
1da177e4 | 662 | { |
7bcd3f34 | 663 | unsigned level; |
1da177e4 | 664 | |
bc5e8fdf LT |
665 | #ifdef CONFIG_SMP |
666 | unsigned long value; | |
667 | ||
7d318d77 AK |
668 | /* |
669 | * Disable TLB flush filter by setting HWCR.FFDIS on K8 | |
670 | * bit 6 of msr C001_0015 | |
04e1ba85 | 671 | * |
7d318d77 AK |
672 | * Errata 63 for SH-B3 steppings |
673 | * Errata 122 for all steppings (F+ have it disabled by default) | |
674 | */ | |
675 | if (c->x86 == 15) { | |
676 | rdmsrl(MSR_K8_HWCR, value); | |
677 | value |= 1 << 6; | |
678 | wrmsrl(MSR_K8_HWCR, value); | |
679 | } | |
bc5e8fdf LT |
680 | #endif |
681 | ||
1da177e4 LT |
682 | /* Bit 31 in normal CPUID used for nonstandard 3DNow ID; |
683 | 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */ | |
5548fecd | 684 | clear_bit(0*32+31, (unsigned long *)&c->x86_capability); |
04e1ba85 | 685 | |
7bcd3f34 AK |
686 | /* On C+ stepping K8 rep microcode works well for copy/memset */ |
687 | level = cpuid_eax(1); | |
04e1ba85 TG |
688 | if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) || |
689 | level >= 0x0f58)) | |
53756d37 | 690 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
99741faa | 691 | if (c->x86 == 0x10 || c->x86 == 0x11) |
53756d37 | 692 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
7bcd3f34 | 693 | |
18bd057b AK |
694 | /* Enable workaround for FXSAVE leak */ |
695 | if (c->x86 >= 6) | |
53756d37 | 696 | set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK); |
18bd057b | 697 | |
e42f9437 RS |
698 | level = get_model_name(c); |
699 | if (!level) { | |
04e1ba85 | 700 | switch (c->x86) { |
1da177e4 LT |
701 | case 15: |
702 | /* Should distinguish Models here, but this is only | |
703 | a fallback anyways. */ | |
704 | strcpy(c->x86_model_id, "Hammer"); | |
04e1ba85 TG |
705 | break; |
706 | } | |
707 | } | |
1da177e4 LT |
708 | display_cacheinfo(c); |
709 | ||
faee9a5d AK |
710 | /* Multi core CPU? */ |
711 | if (c->extended_cpuid_level >= 0x80000008) | |
63518644 | 712 | amd_detect_cmp(c); |
1da177e4 | 713 | |
67cddd94 AK |
714 | if (c->extended_cpuid_level >= 0x80000006 && |
715 | (cpuid_edx(0x80000006) & 0xf000)) | |
716 | num_cache_leaves = 4; | |
717 | else | |
718 | num_cache_leaves = 3; | |
2049336f | 719 | |
0bd8acd1 | 720 | if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11) |
53756d37 | 721 | set_cpu_cap(c, X86_FEATURE_K8); |
0bd8acd1 | 722 | |
de421863 AK |
723 | /* MFENCE stops RDTSC speculation */ |
724 | set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); | |
f039b754 | 725 | |
fb79d22e TG |
726 | if (amd_apic_timer_broken()) |
727 | disable_apic_timer = 1; | |
1da177e4 LT |
728 | } |
729 | ||
1a53905a | 730 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 LT |
731 | { |
732 | #ifdef CONFIG_SMP | |
04e1ba85 TG |
733 | u32 eax, ebx, ecx, edx; |
734 | int index_msb, core_bits; | |
94605eff SS |
735 | |
736 | cpuid(1, &eax, &ebx, &ecx, &edx); | |
737 | ||
94605eff | 738 | |
e42f9437 | 739 | if (!cpu_has(c, X86_FEATURE_HT)) |
1da177e4 | 740 | return; |
04e1ba85 | 741 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
e42f9437 | 742 | goto out; |
1da177e4 | 743 | |
1da177e4 | 744 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
94605eff | 745 | |
1da177e4 LT |
746 | if (smp_num_siblings == 1) { |
747 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
04e1ba85 | 748 | } else if (smp_num_siblings > 1) { |
94605eff | 749 | |
1da177e4 | 750 | if (smp_num_siblings > NR_CPUS) { |
04e1ba85 TG |
751 | printk(KERN_WARNING "CPU: Unsupported number of " |
752 | "siblings %d", smp_num_siblings); | |
1da177e4 LT |
753 | smp_num_siblings = 1; |
754 | return; | |
755 | } | |
94605eff SS |
756 | |
757 | index_msb = get_count_order(smp_num_siblings); | |
f3fa8ebc | 758 | c->phys_proc_id = phys_pkg_id(index_msb); |
3dd9d514 | 759 | |
94605eff | 760 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
3dd9d514 | 761 | |
04e1ba85 | 762 | index_msb = get_count_order(smp_num_siblings); |
94605eff SS |
763 | |
764 | core_bits = get_count_order(c->x86_max_cores); | |
3dd9d514 | 765 | |
f3fa8ebc | 766 | c->cpu_core_id = phys_pkg_id(index_msb) & |
94605eff | 767 | ((1 << core_bits) - 1); |
1da177e4 | 768 | } |
e42f9437 RS |
769 | out: |
770 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
04e1ba85 TG |
771 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", |
772 | c->phys_proc_id); | |
773 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
774 | c->cpu_core_id); | |
e42f9437 RS |
775 | } |
776 | ||
1da177e4 LT |
777 | #endif |
778 | } | |
779 | ||
3dd9d514 AK |
780 | /* |
781 | * find out the number of processor cores on the die | |
782 | */ | |
e6982c67 | 783 | static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c) |
3dd9d514 | 784 | { |
2bbc419f | 785 | unsigned int eax, t; |
3dd9d514 AK |
786 | |
787 | if (c->cpuid_level < 4) | |
788 | return 1; | |
789 | ||
2bbc419f | 790 | cpuid_count(4, 0, &eax, &t, &t, &t); |
3dd9d514 AK |
791 | |
792 | if (eax & 0x1f) | |
793 | return ((eax >> 26) + 1); | |
794 | else | |
795 | return 1; | |
796 | } | |
797 | ||
04d733bd | 798 | static void __cpuinit srat_detect_node(void) |
df0cc26b AK |
799 | { |
800 | #ifdef CONFIG_NUMA | |
ddea7be0 | 801 | unsigned node; |
df0cc26b | 802 | int cpu = smp_processor_id(); |
e42f9437 | 803 | int apicid = hard_smp_processor_id(); |
df0cc26b AK |
804 | |
805 | /* Don't do the funky fallback heuristics the AMD version employs | |
806 | for now. */ | |
e42f9437 | 807 | node = apicid_to_node[apicid]; |
475613b9 | 808 | if (node == NUMA_NO_NODE || !node_online(node)) |
0d015324 | 809 | node = first_node(node_online_map); |
69d81fcd | 810 | numa_set_node(cpu, node); |
df0cc26b | 811 | |
c31fbb1a | 812 | printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node); |
df0cc26b AK |
813 | #endif |
814 | } | |
815 | ||
2b16a235 AK |
816 | static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) |
817 | { | |
818 | if ((c->x86 == 0xf && c->x86_model >= 0x03) || | |
819 | (c->x86 == 0x6 && c->x86_model >= 0x0e)) | |
820 | set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability); | |
821 | } | |
822 | ||
e6982c67 | 823 | static void __cpuinit init_intel(struct cpuinfo_x86 *c) |
1da177e4 LT |
824 | { |
825 | /* Cache sizes */ | |
826 | unsigned n; | |
827 | ||
828 | init_intel_cacheinfo(c); | |
04e1ba85 | 829 | if (c->cpuid_level > 9) { |
0080e667 VP |
830 | unsigned eax = cpuid_eax(10); |
831 | /* Check for version and the number of counters */ | |
832 | if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) | |
53756d37 | 833 | set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); |
0080e667 VP |
834 | } |
835 | ||
36b2a8d5 SE |
836 | if (cpu_has_ds) { |
837 | unsigned int l1, l2; | |
838 | rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); | |
ee58fad5 | 839 | if (!(l1 & (1<<11))) |
53756d37 | 840 | set_cpu_cap(c, X86_FEATURE_BTS); |
36b2a8d5 | 841 | if (!(l1 & (1<<12))) |
53756d37 | 842 | set_cpu_cap(c, X86_FEATURE_PEBS); |
36b2a8d5 SE |
843 | } |
844 | ||
eee3af4a MM |
845 | |
846 | if (cpu_has_bts) | |
847 | ds_init_intel(c); | |
848 | ||
ebfcaa96 | 849 | n = c->extended_cpuid_level; |
1da177e4 LT |
850 | if (n >= 0x80000008) { |
851 | unsigned eax = cpuid_eax(0x80000008); | |
852 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
853 | c->x86_phys_bits = eax & 0xff; | |
af9c142d SL |
854 | /* CPUID workaround for Intel 0F34 CPU */ |
855 | if (c->x86_vendor == X86_VENDOR_INTEL && | |
856 | c->x86 == 0xF && c->x86_model == 0x3 && | |
857 | c->x86_mask == 0x4) | |
858 | c->x86_phys_bits = 36; | |
1da177e4 LT |
859 | } |
860 | ||
861 | if (c->x86 == 15) | |
862 | c->x86_cache_alignment = c->x86_clflush_size * 2; | |
39b3a791 AK |
863 | if ((c->x86 == 0xf && c->x86_model >= 0x03) || |
864 | (c->x86 == 0x6 && c->x86_model >= 0x0e)) | |
53756d37 | 865 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); |
27fbe5b2 | 866 | if (c->x86 == 6) |
53756d37 | 867 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
707fa8ed | 868 | set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); |
04e1ba85 | 869 | c->x86_max_cores = intel_num_cpu_cores(c); |
df0cc26b AK |
870 | |
871 | srat_detect_node(); | |
1da177e4 LT |
872 | } |
873 | ||
672289e9 | 874 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
875 | { |
876 | char *v = c->x86_vendor_id; | |
877 | ||
878 | if (!strcmp(v, "AuthenticAMD")) | |
879 | c->x86_vendor = X86_VENDOR_AMD; | |
880 | else if (!strcmp(v, "GenuineIntel")) | |
881 | c->x86_vendor = X86_VENDOR_INTEL; | |
882 | else | |
883 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
884 | } | |
885 | ||
1da177e4 LT |
886 | /* Do some early cpuid on the boot CPU to get some parameter that are |
887 | needed before check_bugs. Everything advanced is in identify_cpu | |
888 | below. */ | |
8c61b900 | 889 | static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 | 890 | { |
a860b63c | 891 | u32 tfms, xlvl; |
1da177e4 LT |
892 | |
893 | c->loops_per_jiffy = loops_per_jiffy; | |
894 | c->x86_cache_size = -1; | |
895 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
896 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
897 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
898 | c->x86_model_id[0] = '\0'; /* Unset */ | |
899 | c->x86_clflush_size = 64; | |
900 | c->x86_cache_alignment = c->x86_clflush_size; | |
94605eff | 901 | c->x86_max_cores = 1; |
a860b63c | 902 | c->x86_coreid_bits = 0; |
ebfcaa96 | 903 | c->extended_cpuid_level = 0; |
1da177e4 LT |
904 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
905 | ||
906 | /* Get vendor name */ | |
907 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, | |
908 | (unsigned int *)&c->x86_vendor_id[0], | |
909 | (unsigned int *)&c->x86_vendor_id[8], | |
910 | (unsigned int *)&c->x86_vendor_id[4]); | |
04e1ba85 | 911 | |
1da177e4 LT |
912 | get_cpu_vendor(c); |
913 | ||
914 | /* Initialize the standard set of capabilities */ | |
915 | /* Note that the vendor-specific code below might override */ | |
916 | ||
917 | /* Intel-defined flags: level 0x00000001 */ | |
918 | if (c->cpuid_level >= 0x00000001) { | |
919 | __u32 misc; | |
920 | cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4], | |
921 | &c->x86_capability[0]); | |
922 | c->x86 = (tfms >> 8) & 0xf; | |
923 | c->x86_model = (tfms >> 4) & 0xf; | |
924 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 925 | if (c->x86 == 0xf) |
1da177e4 | 926 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 927 | if (c->x86 >= 0x6) |
1da177e4 | 928 | c->x86_model += ((tfms >> 16) & 0xF) << 4; |
04e1ba85 | 929 | if (c->x86_capability[0] & (1<<19)) |
1da177e4 | 930 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
1da177e4 LT |
931 | } else { |
932 | /* Have CPUID level 0 only - unheard of */ | |
933 | c->x86 = 4; | |
934 | } | |
a158608b AK |
935 | |
936 | #ifdef CONFIG_SMP | |
f3fa8ebc | 937 | c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff; |
a158608b | 938 | #endif |
1da177e4 LT |
939 | /* AMD-defined flags: level 0x80000001 */ |
940 | xlvl = cpuid_eax(0x80000000); | |
ebfcaa96 | 941 | c->extended_cpuid_level = xlvl; |
1da177e4 LT |
942 | if ((xlvl & 0xffff0000) == 0x80000000) { |
943 | if (xlvl >= 0x80000001) { | |
944 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
5b7abc6f | 945 | c->x86_capability[6] = cpuid_ecx(0x80000001); |
1da177e4 LT |
946 | } |
947 | if (xlvl >= 0x80000004) | |
948 | get_model_name(c); /* Default name */ | |
949 | } | |
950 | ||
951 | /* Transmeta-defined flags: level 0x80860001 */ | |
952 | xlvl = cpuid_eax(0x80860000); | |
953 | if ((xlvl & 0xffff0000) == 0x80860000) { | |
954 | /* Don't set x86_cpuid_level here for now to not confuse. */ | |
955 | if (xlvl >= 0x80860001) | |
956 | c->x86_capability[2] = cpuid_edx(0x80860001); | |
957 | } | |
958 | ||
9566e91d AH |
959 | c->extended_cpuid_level = cpuid_eax(0x80000000); |
960 | if (c->extended_cpuid_level >= 0x80000007) | |
961 | c->x86_power = cpuid_edx(0x80000007); | |
962 | ||
a860b63c YL |
963 | switch (c->x86_vendor) { |
964 | case X86_VENDOR_AMD: | |
965 | early_init_amd(c); | |
966 | break; | |
71617bf1 YL |
967 | case X86_VENDOR_INTEL: |
968 | early_init_intel(c); | |
969 | break; | |
a860b63c YL |
970 | } |
971 | ||
972 | } | |
973 | ||
974 | /* | |
975 | * This does the hard work of actually picking apart the CPU stuff... | |
976 | */ | |
977 | void __cpuinit identify_cpu(struct cpuinfo_x86 *c) | |
978 | { | |
979 | int i; | |
980 | ||
981 | early_identify_cpu(c); | |
982 | ||
1d67953f VP |
983 | init_scattered_cpuid_features(c); |
984 | ||
1e9f28fa SS |
985 | c->apicid = phys_pkg_id(0); |
986 | ||
1da177e4 LT |
987 | /* |
988 | * Vendor-specific initialization. In this section we | |
989 | * canonicalize the feature flags, meaning if there are | |
990 | * features a certain CPU supports which CPUID doesn't | |
991 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
992 | * we handle them here. | |
993 | * | |
994 | * At the end of this section, c->x86_capability better | |
995 | * indicate the features this CPU genuinely supports! | |
996 | */ | |
997 | switch (c->x86_vendor) { | |
998 | case X86_VENDOR_AMD: | |
999 | init_amd(c); | |
1000 | break; | |
1001 | ||
1002 | case X86_VENDOR_INTEL: | |
1003 | init_intel(c); | |
1004 | break; | |
1005 | ||
1006 | case X86_VENDOR_UNKNOWN: | |
1007 | default: | |
1008 | display_cacheinfo(c); | |
1009 | break; | |
1010 | } | |
1011 | ||
04e1ba85 | 1012 | detect_ht(c); |
1da177e4 LT |
1013 | |
1014 | /* | |
1015 | * On SMP, boot_cpu_data holds the common feature set between | |
1016 | * all CPUs; so make sure that we indicate which features are | |
1017 | * common between the CPUs. The first time this routine gets | |
1018 | * executed, c == &boot_cpu_data. | |
1019 | */ | |
1020 | if (c != &boot_cpu_data) { | |
1021 | /* AND the already accumulated flags with these */ | |
04e1ba85 | 1022 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
1023 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
1024 | } | |
1025 | ||
7d851c8d AK |
1026 | /* Clear all flags overriden by options */ |
1027 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 1028 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 1029 | |
1da177e4 LT |
1030 | #ifdef CONFIG_X86_MCE |
1031 | mcheck_init(c); | |
1032 | #endif | |
74ff305b HS |
1033 | select_idle_routine(c); |
1034 | ||
8bd99481 | 1035 | if (c != &boot_cpu_data) |
3b520b23 | 1036 | mtrr_ap_init(); |
1da177e4 | 1037 | #ifdef CONFIG_NUMA |
3019e8eb | 1038 | numa_add_cpu(smp_processor_id()); |
1da177e4 | 1039 | #endif |
2b16a235 | 1040 | |
1da177e4 | 1041 | } |
1da177e4 | 1042 | |
191679fd AK |
1043 | static __init int setup_noclflush(char *arg) |
1044 | { | |
1045 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
1046 | return 1; | |
1047 | } | |
1048 | __setup("noclflush", setup_noclflush); | |
1049 | ||
e6982c67 | 1050 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
1051 | { |
1052 | if (c->x86_model_id[0]) | |
d8ff0bbf | 1053 | printk(KERN_CONT "%s", c->x86_model_id); |
1da177e4 | 1054 | |
04e1ba85 TG |
1055 | if (c->x86_mask || c->cpuid_level >= 0) |
1056 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); | |
1da177e4 | 1057 | else |
04e1ba85 | 1058 | printk(KERN_CONT "\n"); |
1da177e4 LT |
1059 | } |
1060 | ||
ac72e788 AK |
1061 | static __init int setup_disablecpuid(char *arg) |
1062 | { | |
1063 | int bit; | |
1064 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
1065 | setup_clear_cpu_cap(bit); | |
1066 | else | |
1067 | return 0; | |
1068 | return 1; | |
1069 | } | |
1070 | __setup("clearcpuid=", setup_disablecpuid); |