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x86: clean up bitops-related warnings
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kernel / setup_64.c
CommitLineData
1da177e4 1/*
1da177e4 2 * Copyright (C) 1995 Linus Torvalds
1da177e4
LT		 3 */
4
5/*
6 * This file handles the architecture-dependent parts of initialization
7 */
8
9#include <linux/errno.h>
10#include <linux/sched.h>
11#include <linux/kernel.h>
12#include <linux/mm.h>
13#include <linux/stddef.h>
14#include <linux/unistd.h>
15#include <linux/ptrace.h>
16#include <linux/slab.h>
17#include <linux/user.h>
18#include <linux/a.out.h>
894673ee 19#include <linux/screen_info.h>
1da177e4
LT		 20#include <linux/ioport.h>
21#include <linux/delay.h>
1da177e4
LT		 22#include <linux/init.h>
23#include <linux/initrd.h>
24#include <linux/highmem.h>
25#include <linux/bootmem.h>
26#include <linux/module.h>
27#include <asm/processor.h>
28#include <linux/console.h>
29#include <linux/seq_file.h>
aac04b32 30#include <linux/crash_dump.h>
1da177e4
LT		 31#include <linux/root_dev.h>
32#include <linux/pci.h>
33#include <linux/acpi.h>
34#include <linux/kallsyms.h>
35#include <linux/edd.h>
bbfceef4 36#include <linux/mmzone.h>
5f5609df 37#include <linux/kexec.h>
95235ca2 38#include <linux/cpufreq.h>
e9928674 39#include <linux/dmi.h>
17a941d8 40#include <linux/dma-mapping.h>
681558fd 41#include <linux/ctype.h>
bbfceef4 42
1da177e4
LT		 43#include <asm/mtrr.h>
44#include <asm/uaccess.h>
45#include <asm/system.h>
46#include <asm/io.h>
47#include <asm/smp.h>
48#include <asm/msr.h>
49#include <asm/desc.h>
50#include <video/edid.h>
51#include <asm/e820.h>
52#include <asm/dma.h>
53#include <asm/mpspec.h>
54#include <asm/mmu_context.h>
1da177e4
LT		 55#include <asm/proto.h>
56#include <asm/setup.h>
57#include <asm/mach_apic.h>
58#include <asm/numa.h>
2bc0414e 59#include <asm/sections.h>
f2d3efed 60#include <asm/dmi.h>
00bf4098 61#include <asm/cacheflush.h>
af7a78e9 62#include <asm/mce.h>
1da177e4
LT		 63
64/*
65 * Machine setup..
66 */
67
6c231b7b 68struct cpuinfo_x86 boot_cpu_data __read_mostly;
2ee60e17 69EXPORT_SYMBOL(boot_cpu_data);
1da177e4
LT		 70
71unsigned long mmu_cr4_features;
72
1da177e4
LT		 73/* Boot loader ID as an integer, for the benefit of proc_dointvec */
74int bootloader_type;
75
76unsigned long saved_video_mode;
77
f039b754
AK		 78int force_mwait __cpuinitdata;
79
04e1ba85 80/*
f2d3efed
AK		 81 * Early DMI memory
82 */
83int dmi_alloc_index;
84char dmi_alloc_data[DMI_MAX_DATA];
85
1da177e4
LT		 86/*
87 * Setup options
88 */
1da177e4 89struct screen_info screen_info;
2ee60e17 90EXPORT_SYMBOL(screen_info);
1da177e4
LT		 91struct sys_desc_table_struct {
92 unsigned short length;
93 unsigned char table[0];
94};
95
96struct edid_info edid_info;
ba70710e 97EXPORT_SYMBOL_GPL(edid_info);
1da177e4
LT		 98
99extern int root_mountflags;
1da177e4 100
adf48856 101char __initdata command_line[COMMAND_LINE_SIZE];
1da177e4
LT		 102
103struct resource standard_io_resources[] = {
104 { .name = "dma1", .start = 0x00, .end = 0x1f,
105 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
106 { .name = "pic1", .start = 0x20, .end = 0x21,
107 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
108 { .name = "timer0", .start = 0x40, .end = 0x43,
109 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
110 { .name = "timer1", .start = 0x50, .end = 0x53,
111 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
112 { .name = "keyboard", .start = 0x60, .end = 0x6f,
113 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
114 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
115 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
116 { .name = "pic2", .start = 0xa0, .end = 0xa1,
117 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
118 { .name = "dma2", .start = 0xc0, .end = 0xdf,
119 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
120 { .name = "fpu", .start = 0xf0, .end = 0xff,
121 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
122};
123
1da177e4
LT		 124#define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
125
c9cce83d 126static struct resource data_resource = {
1da177e4
LT		 127 .name = "Kernel data",
128 .start = 0,
129 .end = 0,
130 .flags = IORESOURCE_RAM,
131};
c9cce83d 132static struct resource code_resource = {
1da177e4
LT		 133 .name = "Kernel code",
134 .start = 0,
135 .end = 0,
136 .flags = IORESOURCE_RAM,
137};
c9cce83d 138static struct resource bss_resource = {
00bf4098
BW		 139 .name = "Kernel bss",
140 .start = 0,
141 .end = 0,
142 .flags = IORESOURCE_RAM,
143};
1da177e4 144
8c61b900
TG		 145static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
146
2c8c0e6b
AK		 147#ifdef CONFIG_PROC_VMCORE
148/* elfcorehdr= specifies the location of elf core header
149 * stored by the crashed kernel. This option will be passed
150 * by kexec loader to the capture kernel.
151 */
152static int __init setup_elfcorehdr(char *arg)
681558fd 153{
2c8c0e6b
AK		 154 char *end;
155 if (!arg)
156 return -EINVAL;
157 elfcorehdr_addr = memparse(arg, &end);
158 return end > arg ? 0 : -EINVAL;
681558fd 159}
2c8c0e6b 160early_param("elfcorehdr", setup_elfcorehdr);
e2c03888
AK		 161#endif
162
2b97690f 163#ifndef CONFIG_NUMA
bbfceef4
MT		 164static void __init
165contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
1da177e4 166{
bbfceef4
MT		 167 unsigned long bootmap_size, bootmap;
168
bbfceef4
MT		 169 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
170 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
171 if (bootmap == -1L)
04e1ba85 172 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
bbfceef4 173 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
5cb248ab
MG		 174 e820_register_active_regions(0, start_pfn, end_pfn);
175 free_bootmem_with_active_regions(0, end_pfn);
bbfceef4 176 reserve_bootmem(bootmap, bootmap_size);
04e1ba85 177}
1da177e4
LT		 178#endif
179
1da177e4
LT		 180#if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
181struct edd edd;
182#ifdef CONFIG_EDD_MODULE
183EXPORT_SYMBOL(edd);
184#endif
185/**
186 * copy_edd() - Copy the BIOS EDD information
187 * from boot_params into a safe place.
188 *
189 */
190static inline void copy_edd(void)
191{
30c82645
PA		 192 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
193 sizeof(edd.mbr_signature));
194 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
195 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
196 edd.edd_info_nr = boot_params.eddbuf_entries;
1da177e4
LT		 197}
198#else
199static inline void copy_edd(void)
200{
201}
202#endif
203
5c3391f9
BW		 204#ifdef CONFIG_KEXEC
205static void __init reserve_crashkernel(void)
206{
207 unsigned long long free_mem;
208 unsigned long long crash_size, crash_base;
209 int ret;
210
04e1ba85
TG		 211 free_mem =
212 ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
5c3391f9
BW		 213
214 ret = parse_crashkernel(boot_command_line, free_mem,
215 &crash_size, &crash_base);
216 if (ret == 0 && crash_size) {
217 if (crash_base > 0) {
218 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
219 "for crashkernel (System RAM: %ldMB)\n",
220 (unsigned long)(crash_size >> 20),
221 (unsigned long)(crash_base >> 20),
222 (unsigned long)(free_mem >> 20));
223 crashk_res.start = crash_base;
224 crashk_res.end = crash_base + crash_size - 1;
225 reserve_bootmem(crash_base, crash_size);
226 } else
227 printk(KERN_INFO "crashkernel reservation failed - "
228 "you have to specify a base address\n");
229 }
230}
231#else
232static inline void __init reserve_crashkernel(void)
233{}
234#endif
235
1da177e4 236#define EBDA_ADDR_POINTER 0x40E
ac71d12c
AK		 237
238unsigned __initdata ebda_addr;
239unsigned __initdata ebda_size;
240
241static void discover_ebda(void)
1da177e4 242{
ac71d12c 243 /*
04e1ba85 244 * there is a real-mode segmented pointer pointing to the
1da177e4
LT		 245 * 4K EBDA area at 0x40E
246 */
bdb96a66 247 ebda_addr = *(unsigned short *)__va(EBDA_ADDR_POINTER);
ac71d12c
AK		 248 ebda_addr <<= 4;
249
bdb96a66 250 ebda_size = *(unsigned short *)__va(ebda_addr);
ac71d12c
AK		 251
252 /* Round EBDA up to pages */
253 if (ebda_size == 0)
254 ebda_size = 1;
255 ebda_size <<= 10;
256 ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
257 if (ebda_size > 64*1024)
258 ebda_size = 64*1024;
1da177e4
LT		 259}
260
261void __init setup_arch(char **cmdline_p)
262{
04e1ba85
TG		 263 unsigned i;
264
adf48856 265 printk(KERN_INFO "Command line: %s\n", boot_command_line);
43c85c9c 266
30c82645
PA		 267 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
268 screen_info = boot_params.screen_info;
269 edid_info = boot_params.edid_info;
270 saved_video_mode = boot_params.hdr.vid_mode;
271 bootloader_type = boot_params.hdr.type_of_loader;
1da177e4
LT		 272
273#ifdef CONFIG_BLK_DEV_RAM
30c82645
PA		 274 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
275 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
276 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
1da177e4
LT		 277#endif
278 setup_memory_region();
279 copy_edd();
280
30c82645 281 if (!boot_params.hdr.root_flags)
1da177e4
LT		 282 root_mountflags &= ~MS_RDONLY;
283 init_mm.start_code = (unsigned long) &_text;
284 init_mm.end_code = (unsigned long) &_etext;
285 init_mm.end_data = (unsigned long) &_edata;
286 init_mm.brk = (unsigned long) &_end;
287
e3ebadd9
LT		 288 code_resource.start = virt_to_phys(&_text);
289 code_resource.end = virt_to_phys(&_etext)-1;
290 data_resource.start = virt_to_phys(&_etext);
291 data_resource.end = virt_to_phys(&_edata)-1;
00bf4098
BW		 292 bss_resource.start = virt_to_phys(&__bss_start);
293 bss_resource.end = virt_to_phys(&__bss_stop)-1;
1da177e4 294
1da177e4
LT		 295 early_identify_cpu(&boot_cpu_data);
296
adf48856 297 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
2c8c0e6b
AK		 298 *cmdline_p = command_line;
299
300 parse_early_param();
301
302 finish_e820_parsing();
9ca33eb6 303
5cb248ab 304 e820_register_active_regions(0, 0, -1UL);
1da177e4
LT		 305 /*
306 * partially used pages are not usable - thus
307 * we are rounding upwards:
308 */
309 end_pfn = e820_end_of_ram();
caff0710 310 num_physpages = end_pfn;
1da177e4
LT		 311
312 check_efer();
313
ac71d12c
AK		 314 discover_ebda();
315
1da177e4
LT		 316 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
317
f2d3efed
AK		 318 dmi_scan_machine();
319
b02aae9c
RH		 320 io_delay_init();
321
71fff5e6
MT		 322#ifdef CONFIG_SMP
323 /* setup to use the static apicid table during kernel startup */
324 x86_cpu_to_apicid_ptr = (void *)&x86_cpu_to_apicid_init;
325#endif
326
888ba6c6 327#ifdef CONFIG_ACPI
1da177e4
LT		 328 /*
329 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
330 * Call this early for SRAT node setup.
331 */
332 acpi_boot_table_init();
333#endif
334
caff0710
JB		 335 /* How many end-of-memory variables you have, grandma! */
336 max_low_pfn = end_pfn;
337 max_pfn = end_pfn;
338 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
339
5cb248ab
MG		 340 /* Remove active ranges so rediscovery with NUMA-awareness happens */
341 remove_all_active_ranges();
342
1da177e4
LT		 343#ifdef CONFIG_ACPI_NUMA
344 /*
345 * Parse SRAT to discover nodes.
346 */
347 acpi_numa_init();
348#endif
349
2b97690f 350#ifdef CONFIG_NUMA
04e1ba85 351 numa_initmem_init(0, end_pfn);
1da177e4 352#else
bbfceef4 353 contig_initmem_init(0, end_pfn);
1da177e4
LT		 354#endif
355
356 /* Reserve direct mapping */
04e1ba85 357 reserve_bootmem_generic(table_start << PAGE_SHIFT,
1da177e4
LT		 358 (table_end - table_start) << PAGE_SHIFT);
359
360 /* reserve kernel */
ceee8822
AK		 361 reserve_bootmem_generic(__pa_symbol(&_text),
362 __pa_symbol(&_end) - __pa_symbol(&_text));
1da177e4
LT		 363
364 /*
365 * reserve physical page 0 - it's a special BIOS page on many boxes,
366 * enabling clean reboots, SMP operation, laptop functions.
367 */
368 reserve_bootmem_generic(0, PAGE_SIZE);
369
370 /* reserve ebda region */
ac71d12c
AK		 371 if (ebda_addr)
372 reserve_bootmem_generic(ebda_addr, ebda_size);
076422d2
AS		 373#ifdef CONFIG_NUMA
374 /* reserve nodemap region */
375 if (nodemap_addr)
376 reserve_bootmem_generic(nodemap_addr, nodemap_size);
377#endif
1da177e4
LT		 378
379#ifdef CONFIG_SMP
1da177e4 380 /* Reserve SMP trampoline */
90b1c208 381 reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, 2*PAGE_SIZE);
1da177e4
LT		 382#endif
383
673d5b43 384#ifdef CONFIG_ACPI_SLEEP
1da177e4 385 /*
04e1ba85 386 * Reserve low memory region for sleep support.
1da177e4 387 */
04e1ba85
TG		 388 acpi_reserve_bootmem();
389#endif
390 /*
391 * Find and reserve possible boot-time SMP configuration:
392 */
1da177e4 393 find_smp_config();
1da177e4 394#ifdef CONFIG_BLK_DEV_INITRD
30c82645
PA		 395 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
396 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
397 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
398 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
399 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
400
401 if (ramdisk_end <= end_of_mem) {
402 reserve_bootmem_generic(ramdisk_image, ramdisk_size);
403 initrd_start = ramdisk_image + PAGE_OFFSET;
404 initrd_end = initrd_start+ramdisk_size;
405 } else {
1da177e4 406 printk(KERN_ERR "initrd extends beyond end of memory "
30c82645
PA		 407 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
408 ramdisk_end, end_of_mem);
1da177e4
LT		 409 initrd_start = 0;
410 }
411 }
412#endif
5c3391f9 413 reserve_crashkernel();
1da177e4
LT		 414 paging_init();
415
dfa4698c 416 early_quirks();
1da177e4 417
51f62e18
AR		 418 /*
419 * set this early, so we dont allocate cpu0
420 * if MADT list doesnt list BSP first
421 * mpparse.c/MP_processor_info() allocates logical cpu numbers.
422 */
423 cpu_set(0, cpu_present_map);
888ba6c6 424#ifdef CONFIG_ACPI
1da177e4
LT		 425 /*
426 * Read APIC and some other early information from ACPI tables.
427 */
428 acpi_boot_init();
429#endif
430
05b3cbd8
RT		 431 init_cpu_to_node();
432
1da177e4
LT		 433 /*
434 * get boot-time SMP configuration:
435 */
436 if (smp_found_config)
437 get_smp_config();
438 init_apic_mappings();
3e35a0e5 439 ioapic_init_mappings();
1da177e4
LT		 440
441 /*
fc986db4 442 * We trust e820 completely. No explicit ROM probing in memory.
04e1ba85 443 */
c9cce83d 444 e820_reserve_resources(&code_resource, &data_resource, &bss_resource);
e8eff5ac 445 e820_mark_nosave_regions();
1da177e4 446
1da177e4 447 /* request I/O space for devices used on all i[345]86 PCs */
9d0ef4fd 448 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
1da177e4 449 request_resource(&ioport_resource, &standard_io_resources[i]);
1da177e4 450
a1e97782 451 e820_setup_gap();
1da177e4 452
1da177e4
LT		 453#ifdef CONFIG_VT
454#if defined(CONFIG_VGA_CONSOLE)
455 conswitchp = &vga_con;
456#elif defined(CONFIG_DUMMY_CONSOLE)
457 conswitchp = &dummy_con;
458#endif
459#endif
460}
461
e6982c67 462static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
1da177e4
LT		 463{
464 unsigned int *v;
465
ebfcaa96 466 if (c->extended_cpuid_level < 0x80000004)
1da177e4
LT		 467 return 0;
468
469 v = (unsigned int *) c->x86_model_id;
470 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
471 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
472 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
473 c->x86_model_id[48] = 0;
474 return 1;
475}
476
477
e6982c67 478static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
1da177e4
LT		 479{
480 unsigned int n, dummy, eax, ebx, ecx, edx;
481
ebfcaa96 482 n = c->extended_cpuid_level;
1da177e4
LT		 483
484 if (n >= 0x80000005) {
485 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
04e1ba85
TG		 486 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
487 "D cache %dK (%d bytes/line)\n",
488 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
489 c->x86_cache_size = (ecx>>24) + (edx>>24);
1da177e4
LT		 490 /* On K8 L1 TLB is inclusive, so don't count it */
491 c->x86_tlbsize = 0;
492 }
493
494 if (n >= 0x80000006) {
495 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
496 ecx = cpuid_ecx(0x80000006);
497 c->x86_cache_size = ecx >> 16;
498 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
499
500 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
501 c->x86_cache_size, ecx & 0xFF);
502 }
503
504 if (n >= 0x80000007)
04e1ba85 505 cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
1da177e4 506 if (n >= 0x80000008) {
04e1ba85 507 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
1da177e4
LT		 508 c->x86_virt_bits = (eax >> 8) & 0xff;
509 c->x86_phys_bits = eax & 0xff;
510 }
511}
512
3f098c26
AK		 513#ifdef CONFIG_NUMA
514static int nearby_node(int apicid)
515{
04e1ba85
TG		 516 int i, node;
517
3f098c26 518 for (i = apicid - 1; i >= 0; i--) {
04e1ba85 519 node = apicid_to_node[i];
3f098c26
AK		 520 if (node != NUMA_NO_NODE && node_online(node))
521 return node;
522 }
523 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
04e1ba85 524 node = apicid_to_node[i];
3f098c26
AK		 525 if (node != NUMA_NO_NODE && node_online(node))
526 return node;
527 }
528 return first_node(node_online_map); /* Shouldn't happen */
529}
530#endif
531
63518644
AK		 532/*
533 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
534 * Assumes number of cores is a power of two.
535 */
536static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
537{
538#ifdef CONFIG_SMP
b41e2939 539 unsigned bits;
3f098c26 540#ifdef CONFIG_NUMA
f3fa8ebc 541 int cpu = smp_processor_id();
3f098c26 542 int node = 0;
60c1bc82 543 unsigned apicid = hard_smp_processor_id();
3f098c26 544#endif
a860b63c 545 bits = c->x86_coreid_bits;
b41e2939
AK		 546
547 /* Low order bits define the core id (index of core in socket) */
f3fa8ebc 548 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
b41e2939 549 /* Convert the APIC ID into the socket ID */
f3fa8ebc 550 c->phys_proc_id = phys_pkg_id(bits);
63518644
AK		 551
552#ifdef CONFIG_NUMA
04e1ba85
TG		 553 node = c->phys_proc_id;
554 if (apicid_to_node[apicid] != NUMA_NO_NODE)
555 node = apicid_to_node[apicid];
556 if (!node_online(node)) {
557 /* Two possibilities here:
558 - The CPU is missing memory and no node was created.
559 In that case try picking one from a nearby CPU
560 - The APIC IDs differ from the HyperTransport node IDs
561 which the K8 northbridge parsing fills in.
562 Assume they are all increased by a constant offset,
563 but in the same order as the HT nodeids.
564 If that doesn't result in a usable node fall back to the
565 path for the previous case. */
566
92cb7612 567 int ht_nodeid = apicid - (cpu_data(0).phys_proc_id << bits);
04e1ba85
TG		 568
569 if (ht_nodeid >= 0 &&
570 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
571 node = apicid_to_node[ht_nodeid];
572 /* Pick a nearby node */
573 if (!node_online(node))
574 node = nearby_node(apicid);
575 }
69d81fcd 576 numa_set_node(cpu, node);
3f098c26 577
e42f9437 578 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
63518644 579#endif
63518644
AK		 580#endif
581}
1da177e4 582
a860b63c
YL		 583static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
584{
585#ifdef CONFIG_SMP
586 unsigned bits, ecx;
587
588 /* Multi core CPU? */
589 if (c->extended_cpuid_level < 0x80000008)
590 return;
591
592 ecx = cpuid_ecx(0x80000008);
593
594 c->x86_max_cores = (ecx & 0xff) + 1;
595
596 /* CPU telling us the core id bits shift? */
597 bits = (ecx >> 12) & 0xF;
598
599 /* Otherwise recompute */
600 if (bits == 0) {
601 while ((1 << bits) < c->x86_max_cores)
602 bits++;
603 }
604
605 c->x86_coreid_bits = bits;
606
607#endif
608}
609
fb79d22e
TG		 610#define ENABLE_C1E_MASK 0x18000000
611#define CPUID_PROCESSOR_SIGNATURE 1
612#define CPUID_XFAM 0x0ff00000
613#define CPUID_XFAM_K8 0x00000000
614#define CPUID_XFAM_10H 0x00100000
615#define CPUID_XFAM_11H 0x00200000
616#define CPUID_XMOD 0x000f0000
617#define CPUID_XMOD_REV_F 0x00040000
618
619/* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
620static __cpuinit int amd_apic_timer_broken(void)
621{
04e1ba85
TG		 622 u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
623
fb79d22e
TG		 624 switch (eax & CPUID_XFAM) {
625 case CPUID_XFAM_K8:
626 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
627 break;
628 case CPUID_XFAM_10H:
629 case CPUID_XFAM_11H:
630 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
631 if (lo & ENABLE_C1E_MASK)
632 return 1;
633 break;
634 default:
635 /* err on the side of caution */
636 return 1;
637 }
638 return 0;
639}
640
ed77504b 641static void __cpuinit init_amd(struct cpuinfo_x86 *c)
1da177e4 642{
7bcd3f34 643 unsigned level;
1da177e4 644
bc5e8fdf
LT		 645#ifdef CONFIG_SMP
646 unsigned long value;
647
7d318d77
AK		 648 /*
649 * Disable TLB flush filter by setting HWCR.FFDIS on K8
650 * bit 6 of msr C001_0015
04e1ba85 651 *
7d318d77
AK		 652 * Errata 63 for SH-B3 steppings
653 * Errata 122 for all steppings (F+ have it disabled by default)
654 */
655 if (c->x86 == 15) {
656 rdmsrl(MSR_K8_HWCR, value);
657 value |= 1 << 6;
658 wrmsrl(MSR_K8_HWCR, value);
659 }
bc5e8fdf
LT		 660#endif
661
1da177e4
LT		 662 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
663 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
5548fecd 664 clear_bit(0*32+31, (unsigned long *)&c->x86_capability);
04e1ba85 665
7bcd3f34
AK		 666 /* On C+ stepping K8 rep microcode works well for copy/memset */
667 level = cpuid_eax(1);
04e1ba85
TG		 668 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
669 level >= 0x0f58))
5548fecd 670 set_bit(X86_FEATURE_REP_GOOD, (unsigned long *)&c->x86_capability);
99741faa 671 if (c->x86 == 0x10 || c->x86 == 0x11)
5548fecd 672 set_bit(X86_FEATURE_REP_GOOD, (unsigned long *)&c->x86_capability);
7bcd3f34 673
18bd057b
AK		 674 /* Enable workaround for FXSAVE leak */
675 if (c->x86 >= 6)
5548fecd 676 set_bit(X86_FEATURE_FXSAVE_LEAK, (unsigned long *)&c->x86_capability);
18bd057b 677
e42f9437
RS		 678 level = get_model_name(c);
679 if (!level) {
04e1ba85 680 switch (c->x86) {
1da177e4
LT		 681 case 15:
682 /* Should distinguish Models here, but this is only
683 a fallback anyways. */
684 strcpy(c->x86_model_id, "Hammer");
04e1ba85
TG		 685 break;
686 }
687 }
1da177e4
LT		 688 display_cacheinfo(c);
689
130951cc
AK		 690 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
691 if (c->x86_power & (1<<8))
5548fecd 692 set_bit(X86_FEATURE_CONSTANT_TSC, (unsigned long *)&c->x86_capability);
130951cc 693
faee9a5d
AK		 694 /* Multi core CPU? */
695 if (c->extended_cpuid_level >= 0x80000008)
63518644 696 amd_detect_cmp(c);
1da177e4 697
67cddd94
AK		 698 if (c->extended_cpuid_level >= 0x80000006 &&
699 (cpuid_edx(0x80000006) & 0xf000))
700 num_cache_leaves = 4;
701 else
702 num_cache_leaves = 3;
2049336f 703
0bd8acd1 704 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
5548fecd 705 set_bit(X86_FEATURE_K8, (unsigned long *)&c->x86_capability);
0bd8acd1 706
61677965 707 /* RDTSC can be speculated around */
5548fecd 708 clear_bit(X86_FEATURE_SYNC_RDTSC, (unsigned long *)&c->x86_capability);
f039b754
AK		 709
710 /* Family 10 doesn't support C states in MWAIT so don't use it */
711 if (c->x86 == 0x10 && !force_mwait)
5548fecd 712 clear_bit(X86_FEATURE_MWAIT, (unsigned long *)&c->x86_capability);
fb79d22e
TG		 713
714 if (amd_apic_timer_broken())
715 disable_apic_timer = 1;
1da177e4
LT		 716}
717
e6982c67 718static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
1da177e4
LT		 719{
720#ifdef CONFIG_SMP
04e1ba85
TG		 721 u32 eax, ebx, ecx, edx;
722 int index_msb, core_bits;
94605eff
SS		 723
724 cpuid(1, &eax, &ebx, &ecx, &edx);
725
94605eff 726
e42f9437 727 if (!cpu_has(c, X86_FEATURE_HT))
1da177e4 728 return;
04e1ba85 729 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
e42f9437 730 goto out;
1da177e4 731
1da177e4 732 smp_num_siblings = (ebx & 0xff0000) >> 16;
94605eff 733
1da177e4
LT		 734 if (smp_num_siblings == 1) {
735 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
04e1ba85 736 } else if (smp_num_siblings > 1) {
94605eff 737
1da177e4 738 if (smp_num_siblings > NR_CPUS) {
04e1ba85
TG		 739 printk(KERN_WARNING "CPU: Unsupported number of "
740 "siblings %d", smp_num_siblings);
1da177e4
LT		 741 smp_num_siblings = 1;
742 return;
743 }
94605eff
SS		 744
745 index_msb = get_count_order(smp_num_siblings);
f3fa8ebc 746 c->phys_proc_id = phys_pkg_id(index_msb);
3dd9d514 747
94605eff 748 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
3dd9d514 749
04e1ba85 750 index_msb = get_count_order(smp_num_siblings);
94605eff
SS		 751
752 core_bits = get_count_order(c->x86_max_cores);
3dd9d514 753
f3fa8ebc 754 c->cpu_core_id = phys_pkg_id(index_msb) &
94605eff 755 ((1 << core_bits) - 1);
1da177e4 756 }
e42f9437
RS		 757out:
758 if ((c->x86_max_cores * smp_num_siblings) > 1) {
04e1ba85
TG		 759 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
760 c->phys_proc_id);
761 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
762 c->cpu_core_id);
e42f9437
RS		 763 }
764
1da177e4
LT		 765#endif
766}
767
3dd9d514
AK		 768/*
769 * find out the number of processor cores on the die
770 */
e6982c67 771static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
3dd9d514 772{
2bbc419f 773 unsigned int eax, t;
3dd9d514
AK		 774
775 if (c->cpuid_level < 4)
776 return 1;
777
2bbc419f 778 cpuid_count(4, 0, &eax, &t, &t, &t);
3dd9d514
AK		 779
780 if (eax & 0x1f)
781 return ((eax >> 26) + 1);
782 else
783 return 1;
784}
785
df0cc26b
AK		 786static void srat_detect_node(void)
787{
788#ifdef CONFIG_NUMA
ddea7be0 789 unsigned node;
df0cc26b 790 int cpu = smp_processor_id();
e42f9437 791 int apicid = hard_smp_processor_id();
df0cc26b
AK		 792
793 /* Don't do the funky fallback heuristics the AMD version employs
794 for now. */
e42f9437 795 node = apicid_to_node[apicid];
df0cc26b 796 if (node == NUMA_NO_NODE)
0d015324 797 node = first_node(node_online_map);
69d81fcd 798 numa_set_node(cpu, node);
df0cc26b 799
c31fbb1a 800 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
df0cc26b
AK		 801#endif
802}
803
e6982c67 804static void __cpuinit init_intel(struct cpuinfo_x86 *c)
1da177e4
LT		 805{
806 /* Cache sizes */
807 unsigned n;
808
809 init_intel_cacheinfo(c);
04e1ba85 810 if (c->cpuid_level > 9) {
0080e667
VP		 811 unsigned eax = cpuid_eax(10);
812 /* Check for version and the number of counters */
813 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
5548fecd
JF		 814 set_bit(X86_FEATURE_ARCH_PERFMON,
815 (unsigned long *)&c->x86_capability);
0080e667
VP		 816 }
817
36b2a8d5
SE		 818 if (cpu_has_ds) {
819 unsigned int l1, l2;
820 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
ee58fad5 821 if (!(l1 & (1<<11)))
5548fecd 822 set_bit(X86_FEATURE_BTS, (unsigned long *)c->x86_capability);
36b2a8d5 823 if (!(l1 & (1<<12)))
5548fecd 824 set_bit(X86_FEATURE_PEBS, (unsigned long *)c->x86_capability);
36b2a8d5
SE		 825 }
826
ebfcaa96 827 n = c->extended_cpuid_level;
1da177e4
LT		 828 if (n >= 0x80000008) {
829 unsigned eax = cpuid_eax(0x80000008);
830 c->x86_virt_bits = (eax >> 8) & 0xff;
831 c->x86_phys_bits = eax & 0xff;
af9c142d
SL		 832 /* CPUID workaround for Intel 0F34 CPU */
833 if (c->x86_vendor == X86_VENDOR_INTEL &&
834 c->x86 == 0xF && c->x86_model == 0x3 &&
835 c->x86_mask == 0x4)
836 c->x86_phys_bits = 36;
1da177e4
LT		 837 }
838
839 if (c->x86 == 15)
840 c->x86_cache_alignment = c->x86_clflush_size * 2;
39b3a791
AK		 841 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
842 (c->x86 == 0x6 && c->x86_model >= 0x0e))
5548fecd 843 set_bit(X86_FEATURE_CONSTANT_TSC, (unsigned long *)&c->x86_capability);
27fbe5b2 844 if (c->x86 == 6)
5548fecd 845 set_bit(X86_FEATURE_REP_GOOD, (unsigned long *)&c->x86_capability);
f3d73707 846 if (c->x86 == 15)
5548fecd 847 set_bit(X86_FEATURE_SYNC_RDTSC, (unsigned long *)&c->x86_capability);
f3d73707 848 else
5548fecd 849 clear_bit(X86_FEATURE_SYNC_RDTSC, (unsigned long *)&c->x86_capability);
04e1ba85 850 c->x86_max_cores = intel_num_cpu_cores(c);
df0cc26b
AK		 851
852 srat_detect_node();
1da177e4
LT		 853}
854
672289e9 855static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
1da177e4
LT		 856{
857 char *v = c->x86_vendor_id;
858
859 if (!strcmp(v, "AuthenticAMD"))
860 c->x86_vendor = X86_VENDOR_AMD;
861 else if (!strcmp(v, "GenuineIntel"))
862 c->x86_vendor = X86_VENDOR_INTEL;
863 else
864 c->x86_vendor = X86_VENDOR_UNKNOWN;
865}
866
867struct cpu_model_info {
868 int vendor;
869 int family;
870 char *model_names[16];
871};
872
873/* Do some early cpuid on the boot CPU to get some parameter that are
874 needed before check_bugs. Everything advanced is in identify_cpu
875 below. */
8c61b900 876static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
1da177e4 877{
a860b63c 878 u32 tfms, xlvl;
1da177e4
LT		 879
880 c->loops_per_jiffy = loops_per_jiffy;
881 c->x86_cache_size = -1;
882 c->x86_vendor = X86_VENDOR_UNKNOWN;
883 c->x86_model = c->x86_mask = 0; /* So far unknown... */
884 c->x86_vendor_id[0] = '\0'; /* Unset */
885 c->x86_model_id[0] = '\0'; /* Unset */
886 c->x86_clflush_size = 64;
887 c->x86_cache_alignment = c->x86_clflush_size;
94605eff 888 c->x86_max_cores = 1;
a860b63c 889 c->x86_coreid_bits = 0;
ebfcaa96 890 c->extended_cpuid_level = 0;
1da177e4
LT		 891 memset(&c->x86_capability, 0, sizeof c->x86_capability);
892
893 /* Get vendor name */
894 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
895 (unsigned int *)&c->x86_vendor_id[0],
896 (unsigned int *)&c->x86_vendor_id[8],
897 (unsigned int *)&c->x86_vendor_id[4]);
04e1ba85 898
1da177e4
LT		 899 get_cpu_vendor(c);
900
901 /* Initialize the standard set of capabilities */
902 /* Note that the vendor-specific code below might override */
903
904 /* Intel-defined flags: level 0x00000001 */
905 if (c->cpuid_level >= 0x00000001) {
906 __u32 misc;
907 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
908 &c->x86_capability[0]);
909 c->x86 = (tfms >> 8) & 0xf;
910 c->x86_model = (tfms >> 4) & 0xf;
911 c->x86_mask = tfms & 0xf;
f5f786d0 912 if (c->x86 == 0xf)
1da177e4 913 c->x86 += (tfms >> 20) & 0xff;
f5f786d0 914 if (c->x86 >= 0x6)
1da177e4 915 c->x86_model += ((tfms >> 16) & 0xF) << 4;
04e1ba85 916 if (c->x86_capability[0] & (1<<19))
1da177e4 917 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
1da177e4
LT		 918 } else {
919 /* Have CPUID level 0 only - unheard of */
920 c->x86 = 4;
921 }
a158608b
AK		 922
923#ifdef CONFIG_SMP
f3fa8ebc 924 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
a158608b 925#endif
1da177e4
LT		 926 /* AMD-defined flags: level 0x80000001 */
927 xlvl = cpuid_eax(0x80000000);
ebfcaa96 928 c->extended_cpuid_level = xlvl;
1da177e4
LT		 929 if ((xlvl & 0xffff0000) == 0x80000000) {
930 if (xlvl >= 0x80000001) {
931 c->x86_capability[1] = cpuid_edx(0x80000001);
5b7abc6f 932 c->x86_capability[6] = cpuid_ecx(0x80000001);
1da177e4
LT		 933 }
934 if (xlvl >= 0x80000004)
935 get_model_name(c); /* Default name */
936 }
937
938 /* Transmeta-defined flags: level 0x80860001 */
939 xlvl = cpuid_eax(0x80860000);
940 if ((xlvl & 0xffff0000) == 0x80860000) {
941 /* Don't set x86_cpuid_level here for now to not confuse. */
942 if (xlvl >= 0x80860001)
943 c->x86_capability[2] = cpuid_edx(0x80860001);
944 }
945
a860b63c
YL		 946 switch (c->x86_vendor) {
947 case X86_VENDOR_AMD:
948 early_init_amd(c);
949 break;
950 }
951
952}
953
954/*
955 * This does the hard work of actually picking apart the CPU stuff...
956 */
957void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
958{
959 int i;
960
961 early_identify_cpu(c);
962
1d67953f
VP		 963 init_scattered_cpuid_features(c);
964
1e9f28fa
SS		 965 c->apicid = phys_pkg_id(0);
966
1da177e4
LT		 967 /*
968 * Vendor-specific initialization. In this section we
969 * canonicalize the feature flags, meaning if there are
970 * features a certain CPU supports which CPUID doesn't
971 * tell us, CPUID claiming incorrect flags, or other bugs,
972 * we handle them here.
973 *
974 * At the end of this section, c->x86_capability better
975 * indicate the features this CPU genuinely supports!
976 */
977 switch (c->x86_vendor) {
978 case X86_VENDOR_AMD:
979 init_amd(c);
980 break;
981
982 case X86_VENDOR_INTEL:
983 init_intel(c);
984 break;
985
986 case X86_VENDOR_UNKNOWN:
987 default:
988 display_cacheinfo(c);
989 break;
990 }
991
992 select_idle_routine(c);
04e1ba85 993 detect_ht(c);
1da177e4
LT		 994
995 /*
996 * On SMP, boot_cpu_data holds the common feature set between
997 * all CPUs; so make sure that we indicate which features are
998 * common between the CPUs. The first time this routine gets
999 * executed, c == &boot_cpu_data.
1000 */
1001 if (c != &boot_cpu_data) {
1002 /* AND the already accumulated flags with these */
04e1ba85 1003 for (i = 0; i < NCAPINTS; i++)
1da177e4
LT		 1004 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1005 }
1006
1007#ifdef CONFIG_X86_MCE
1008 mcheck_init(c);
1009#endif
8bd99481 1010 if (c != &boot_cpu_data)
3b520b23 1011 mtrr_ap_init();
1da177e4 1012#ifdef CONFIG_NUMA
3019e8eb 1013 numa_add_cpu(smp_processor_id());
1da177e4
LT		 1014#endif
1015}
1da177e4 1016
e6982c67 1017void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1da177e4
LT		 1018{
1019 if (c->x86_model_id[0])
04e1ba85 1020 printk(KERN_INFO "%s", c->x86_model_id);
1da177e4 1021
04e1ba85
TG		 1022 if (c->x86_mask || c->cpuid_level >= 0)
1023 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1da177e4 1024 else
04e1ba85 1025 printk(KERN_CONT "\n");
1da177e4
LT		 1026}
1027
1028/*
1029 * Get CPU information for use by the procfs.
1030 */
1031
1032static int show_cpuinfo(struct seq_file *m, void *v)
1033{
1034 struct cpuinfo_x86 *c = v;
04e1ba85 1035 int cpu = 0, i;
1da177e4 1036
04e1ba85 1037 /*
1da177e4
LT		 1038 * These flag bits must match the definitions in <asm/cpufeature.h>.
1039 * NULL means this bit is undefined or reserved; either way it doesn't
1040 * have meaning as far as Linux is concerned. Note that it's important
1041 * to realize there is a difference between this table and CPUID -- if
1042 * applications want to get the raw CPUID data, they should access
1043 * /dev/cpu/<cpu_nr>/cpuid instead.
1044 */
121d7bf5 1045 static const char *const x86_cap_flags[] = {
1da177e4 1046 /* Intel-defined */
04e1ba85
TG		 1047 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
1048 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
1049 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
1050 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
1da177e4
LT		 1051
1052 /* AMD-defined */
3c3b73b6 1053 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4
LT		 1054 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
1055 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
f790cd30
AK		 1056 NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
1057 "3dnowext", "3dnow",
1da177e4
LT		 1058
1059 /* Transmeta-defined */
1060 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
1061 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1062 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1063 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1064
1065 /* Other (Linux-defined) */
ec481536
PA		 1066 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
1067 NULL, NULL, NULL, NULL,
1068 "constant_tsc", "up", NULL, "arch_perfmon",
1069 "pebs", "bts", NULL, "sync_rdtsc",
1070 "rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4
LT		 1071 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1072
1073 /* Intel-defined (#2) */
9d95dd84 1074 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
dcf10307 1075 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
e1054b39 1076 NULL, NULL, "dca", "sse4_1", "sse4_2", NULL, NULL, "popcnt",
1da177e4
LT		 1077 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1078
5b7abc6f
PA		 1079 /* VIA/Cyrix/Centaur-defined */
1080 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
ec481536 1081 "ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
5b7abc6f
PA		 1082 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1083 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1084
1da177e4 1085 /* AMD-defined (#2) */
e1054b39
PA		 1086 "lahf_lm", "cmp_legacy", "svm", "extapic",
1087 "cr8_legacy", "abm", "sse4a", "misalignsse",
1088 "3dnowprefetch", "osvw", "ibs", "sse5",
1089 "skinit", "wdt", NULL, NULL,
1da177e4 1090 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
5b7abc6f 1091 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1d67953f
VP		 1092
1093 /* Auxiliary (Linux-defined) */
1094 "ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1095 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1096 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1097 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1da177e4 1098 };
121d7bf5 1099 static const char *const x86_power_flags[] = {
1da177e4
LT		 1100 "ts", /* temperature sensor */
1101 "fid", /* frequency id control */
1102 "vid", /* voltage id control */
1103 "ttp", /* thermal trip */
1104 "tm",
3f98bc49 1105 "stc",
f790cd30
AK		 1106 "100mhzsteps",
1107 "hwpstate",
d824395c
JR		 1108 "", /* tsc invariant mapped to constant_tsc */
1109 /* nothing */
1da177e4
LT		 1110 };
1111
1112
1113#ifdef CONFIG_SMP
92cb7612 1114 cpu = c->cpu_index;
1da177e4
LT		 1115#endif
1116
04e1ba85
TG		 1117 seq_printf(m, "processor\t: %u\n"
1118 "vendor_id\t: %s\n"
1119 "cpu family\t: %d\n"
1120 "model\t\t: %d\n"
1121 "model name\t: %s\n",
1122 (unsigned)cpu,
1123 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1124 c->x86,
1125 (int)c->x86_model,
1126 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1127
1da177e4
LT		 1128 if (c->x86_mask || c->cpuid_level >= 0)
1129 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1130 else
1131 seq_printf(m, "stepping\t: unknown\n");
04e1ba85
TG		 1132
1133 if (cpu_has(c, X86_FEATURE_TSC)) {
92cb7612 1134 unsigned int freq = cpufreq_quick_get((unsigned)cpu);
04e1ba85 1135
95235ca2
VP		 1136 if (!freq)
1137 freq = cpu_khz;
1da177e4 1138 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
04e1ba85 1139 freq / 1000, (freq % 1000));
1da177e4
LT		 1140 }
1141
1142 /* Cache size */
04e1ba85 1143 if (c->x86_cache_size >= 0)
1da177e4 1144 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
04e1ba85 1145
1da177e4 1146#ifdef CONFIG_SMP
94605eff 1147 if (smp_num_siblings * c->x86_max_cores > 1) {
f3fa8ebc 1148 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
08357611
MT		 1149 seq_printf(m, "siblings\t: %d\n",
1150 cpus_weight(per_cpu(cpu_core_map, cpu)));
f3fa8ebc 1151 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
94605eff 1152 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
db468681 1153 }
04e1ba85 1154#endif
1da177e4
LT		 1155
1156 seq_printf(m,
04e1ba85
TG		 1157 "fpu\t\t: yes\n"
1158 "fpu_exception\t: yes\n"
1159 "cpuid level\t: %d\n"
1160 "wp\t\t: yes\n"
1161 "flags\t\t:",
1da177e4
LT		 1162 c->cpuid_level);
1163
04e1ba85
TG		 1164 for (i = 0; i < 32*NCAPINTS; i++)
1165 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
1166 seq_printf(m, " %s", x86_cap_flags[i]);
1167
1da177e4
LT		 1168 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1169 c->loops_per_jiffy/(500000/HZ),
1170 (c->loops_per_jiffy/(5000/HZ)) % 100);
1171
04e1ba85 1172 if (c->x86_tlbsize > 0)
1da177e4
LT		 1173 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1174 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1175 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1176
04e1ba85 1177 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1da177e4
LT		 1178 c->x86_phys_bits, c->x86_virt_bits);
1179
1180 seq_printf(m, "power management:");
04e1ba85
TG		 1181 for (i = 0; i < 32; i++) {
1182 if (c->x86_power & (1 << i)) {
1183 if (i < ARRAY_SIZE(x86_power_flags) &&
1184 x86_power_flags[i])
1185 seq_printf(m, "%s%s",
1186 x86_power_flags[i][0]?" ":"",
1187 x86_power_flags[i]);
1188 else
1189 seq_printf(m, " [%d]", i);
1190 }
1da177e4 1191 }
1da177e4 1192
d31ddaa1 1193 seq_printf(m, "\n\n");
1da177e4
LT		 1194
1195 return 0;
1196}
1197
1198static void *c_start(struct seq_file *m, loff_t *pos)
1199{
92cb7612 1200 if (*pos == 0) /* just in case, cpu 0 is not the first */
c0c52d28
AH		 1201 *pos = first_cpu(cpu_online_map);
1202 if ((*pos) < NR_CPUS && cpu_online(*pos))
92cb7612
MT		 1203 return &cpu_data(*pos);
1204 return NULL;
1da177e4
LT		 1205}
1206
1207static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1208{
c0c52d28 1209 *pos = next_cpu(*pos, cpu_online_map);
1da177e4
LT		 1210 return c_start(m, pos);
1211}
1212
1213static void c_stop(struct seq_file *m, void *v)
1214{
1215}
1216
1217struct seq_operations cpuinfo_op = {
04e1ba85 1218 .start = c_start,
1da177e4
LT		 1219 .next = c_next,
1220 .stop = c_stop,
1221 .show = show_cpuinfo,
1222};
kernel source for telekom puls (alcatel/mediatek)