x86, apic: remove genapic.h
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kernel / probe_32.c
CommitLineData
9b0c5028 1/*
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2 * Default generic APIC driver. This handles up to 8 CPUs.
3 *
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4 * Copyright 2003 Andi Kleen, SuSE Labs.
5 * Subject to the GNU Public License, v.2
6 *
1da177e4 7 * Generic x86 APIC driver probe layer.
9b0c5028 8 */
1da177e4
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9#include <linux/threads.h>
10#include <linux/cpumask.h>
7d01d32d 11#include <linux/module.h>
1da177e4
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12#include <linux/string.h>
13#include <linux/kernel.h>
14#include <linux/ctype.h>
15#include <linux/init.h>
1a3f239d 16#include <linux/errno.h>
1da177e4
LT
17#include <asm/fixmap.h>
18#include <asm/mpspec.h>
19#include <asm/apicdef.h>
7b6aa335 20#include <asm/apic.h>
54ac14a8 21#include <asm/setup.h>
1da177e4 22
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23#include <linux/threads.h>
24#include <linux/cpumask.h>
25#include <asm/mpspec.h>
7b6aa335 26#include <asm/apic.h>
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27#include <asm/fixmap.h>
28#include <asm/apicdef.h>
29#include <linux/kernel.h>
30#include <linux/string.h>
31#include <linux/smp.h>
32#include <linux/init.h>
7b6aa335 33#include <asm/apic.h>
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34#include <asm/ipi.h>
35
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36#include <linux/smp.h>
37#include <linux/init.h>
38#include <linux/interrupt.h>
39#include <asm/acpi.h>
40#include <asm/arch_hooks.h>
41#include <asm/e820.h>
42#include <asm/setup.h>
43
7b6aa335 44#include <asm/apic.h>
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45
46#ifdef CONFIG_HOTPLUG_CPU
47#define DEFAULT_SEND_IPI (1)
48#else
49#define DEFAULT_SEND_IPI (0)
50#endif
51
52int no_broadcast = DEFAULT_SEND_IPI;
53
54#ifdef CONFIG_X86_LOCAL_APIC
55
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56void default_setup_apic_routing(void)
57{
58#ifdef CONFIG_X86_IO_APIC
59 printk(KERN_INFO
60 "Enabling APIC mode: Flat. Using %d I/O APICs\n",
61 nr_ioapics);
62#endif
63}
64
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65static void default_vector_allocation_domain(int cpu, struct cpumask *retmask)
66{
67 /*
68 * Careful. Some cpus do not strictly honor the set of cpus
69 * specified in the interrupt destination when using lowest
70 * priority interrupt delivery mode.
71 *
72 * In particular there was a hyperthreading cpu observed to
73 * deliver interrupts to the wrong hyperthread when only one
74 * hyperthread was specified in the interrupt desitination.
75 */
76 *retmask = (cpumask_t) { { [0] = APIC_ALL_CPUS } };
77}
78
79/* should be called last. */
80static int probe_default(void)
81{
82 return 1;
83}
84
85struct genapic apic_default = {
86
87 .name = "default",
88 .probe = probe_default,
89 .acpi_madt_oem_check = NULL,
90 .apic_id_registered = default_apic_id_registered,
91
92 .irq_delivery_mode = dest_LowestPrio,
93 /* logical delivery broadcast to all CPUs: */
94 .irq_dest_mode = 1,
95
96 .target_cpus = default_target_cpus,
97 .disable_esr = 0,
98 .dest_logical = APIC_DEST_LOGICAL,
99 .check_apicid_used = default_check_apicid_used,
100 .check_apicid_present = default_check_apicid_present,
101
102 .vector_allocation_domain = default_vector_allocation_domain,
103 .init_apic_ldr = default_init_apic_ldr,
104
105 .ioapic_phys_id_map = default_ioapic_phys_id_map,
106 .setup_apic_routing = default_setup_apic_routing,
107 .multi_timer_check = NULL,
108 .apicid_to_node = default_apicid_to_node,
109 .cpu_to_logical_apicid = default_cpu_to_logical_apicid,
110 .cpu_present_to_apicid = default_cpu_present_to_apicid,
111 .apicid_to_cpu_present = default_apicid_to_cpu_present,
112 .setup_portio_remap = NULL,
113 .check_phys_apicid_present = default_check_phys_apicid_present,
114 .enable_apic_mode = NULL,
115 .phys_pkg_id = default_phys_pkg_id,
116 .mps_oem_check = NULL,
117
118 .get_apic_id = default_get_apic_id,
119 .set_apic_id = NULL,
120 .apic_id_mask = 0x0F << 24,
121
122 .cpu_mask_to_apicid = default_cpu_mask_to_apicid,
123 .cpu_mask_to_apicid_and = default_cpu_mask_to_apicid_and,
124
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125 .send_IPI_mask = default_send_IPI_mask_logical,
126 .send_IPI_mask_allbutself = default_send_IPI_mask_allbutself_logical,
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127 .send_IPI_allbutself = default_send_IPI_allbutself,
128 .send_IPI_all = default_send_IPI_all,
6b64ee02 129 .send_IPI_self = default_send_IPI_self,
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130
131 .wakeup_cpu = NULL,
132 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
133 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
134
135 .wait_for_init_deassert = default_wait_for_init_deassert,
136
137 .smp_callin_clear_local_apic = NULL,
138 .store_NMI_vector = NULL,
139 .inquire_remote_apic = default_inquire_remote_apic,
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140
141 .read = native_apic_mem_read,
142 .write = native_apic_mem_write,
143 .icr_read = native_apic_icr_read,
144 .icr_write = native_apic_icr_write,
145 .wait_icr_idle = native_apic_wait_icr_idle,
146 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
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147};
148
d49c4288 149extern struct genapic apic_numaq;
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150extern struct genapic apic_summit;
151extern struct genapic apic_bigsmp;
152extern struct genapic apic_es7000;
153extern struct genapic apic_default;
154
c8d46cf0 155struct genapic *apic = &apic_default;
7d01d32d 156EXPORT_SYMBOL_GPL(apic);
1da177e4 157
96d55358 158static struct genapic *apic_probe[] __initdata = {
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159#ifdef CONFIG_X86_NUMAQ
160 &apic_numaq,
161#endif
162#ifdef CONFIG_X86_SUMMIT
1da177e4 163 &apic_summit,
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164#endif
165#ifdef CONFIG_X86_BIGSMP
9b0c5028 166 &apic_bigsmp,
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167#endif
168#ifdef CONFIG_X86_ES7000
1da177e4 169 &apic_es7000,
d49c4288 170#endif
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171 &apic_default, /* must be last */
172 NULL,
173};
174
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175static int cmdline_apic __initdata;
176static int __init parse_apic(char *arg)
177{
178 int i;
179
180 if (!arg)
181 return -EINVAL;
182
183 for (i = 0; apic_probe[i]; i++) {
184 if (!strcmp(apic_probe[i]->name, arg)) {
c8d46cf0 185 apic = apic_probe[i];
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186 cmdline_apic = 1;
187 return 0;
188 }
189 }
9a8cb626 190
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191 if (x86_quirks->update_genapic)
192 x86_quirks->update_genapic();
193
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194 /* Parsed again by __setup for debug/verbose */
195 return 0;
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196}
197early_param("apic", parse_apic);
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198
199void __init generic_bigsmp_probe(void)
200{
b20d70b7 201#ifdef CONFIG_X86_BIGSMP
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202 /*
203 * This routine is used to switch to bigsmp mode when
204 * - There is no apic= option specified by the user
27b46d76 205 * - generic_apic_probe() has chosen apic_default as the sub_arch
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206 * - we find more than 8 CPUs in acpi LAPIC listing with xAPIC support
207 */
208
c8d46cf0 209 if (!cmdline_apic && apic == &apic_default) {
911a62d4 210 if (apic_bigsmp.probe()) {
c8d46cf0 211 apic = &apic_bigsmp;
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212 if (x86_quirks->update_genapic)
213 x86_quirks->update_genapic();
911a62d4 214 printk(KERN_INFO "Overriding APIC driver with %s\n",
c8d46cf0 215 apic->name);
911a62d4 216 }
87f76065 217 }
d49c4288 218#endif
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219}
220
1a3f239d 221void __init generic_apic_probe(void)
9b0c5028 222{
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223 if (!cmdline_apic) {
224 int i;
225 for (i = 0; apic_probe[i]; i++) {
226 if (apic_probe[i]->probe()) {
c8d46cf0 227 apic = apic_probe[i];
1a3f239d 228 break;
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229 }
230 }
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231 /* Not visible without early console */
232 if (!apic_probe[i])
233 panic("Didn't find an APIC driver");
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234
235 if (x86_quirks->update_genapic)
236 x86_quirks->update_genapic();
1da177e4 237 }
c8d46cf0 238 printk(KERN_INFO "Using APIC driver %s\n", apic->name);
9b0c5028 239}
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240
241/* These functions can switch the APIC even after the initial ->probe() */
242
9c764247
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243int __init
244generic_mps_oem_check(struct mpc_table *mpc, char *oem, char *productid)
9b0c5028 245{
1da177e4 246 int i;
5f836405 247
9b0c5028 248 for (i = 0; apic_probe[i]; ++i) {
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249 if (!apic_probe[i]->mps_oem_check)
250 continue;
251 if (!apic_probe[i]->mps_oem_check(mpc, oem, productid))
252 continue;
253
254 if (!cmdline_apic) {
255 apic = apic_probe[i];
256 if (x86_quirks->update_genapic)
257 x86_quirks->update_genapic();
258 printk(KERN_INFO "Switched to APIC driver `%s'.\n",
259 apic->name);
9b0c5028 260 }
5f836405 261 return 1;
9b0c5028 262 }
1da177e4 263 return 0;
9b0c5028 264}
1da177e4 265
306db03b 266int __init default_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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LT
267{
268 int i;
306db03b 269
9b0c5028 270 for (i = 0; apic_probe[i]; ++i) {
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271 if (!apic_probe[i]->acpi_madt_oem_check)
272 continue;
273 if (!apic_probe[i]->acpi_madt_oem_check(oem_id, oem_table_id))
274 continue;
275
276 if (!cmdline_apic) {
277 apic = apic_probe[i];
278 if (x86_quirks->update_genapic)
279 x86_quirks->update_genapic();
280 printk(KERN_INFO "Switched to APIC driver `%s'.\n",
281 apic->name);
9b0c5028 282 }
306db03b 283 return 1;
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284 }
285 return 0;
1da177e4 286}
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287
288#endif /* CONFIG_X86_LOCAL_APIC */
289
290/**
291 * pre_intr_init_hook - initialisation prior to setting up interrupt vectors
292 *
293 * Description:
294 * Perform any necessary interrupt initialisation prior to setting up
295 * the "ordinary" interrupt call gates. For legacy reasons, the ISA
296 * interrupts should be initialised here if the machine emulates a PC
297 * in any way.
298 **/
299void __init pre_intr_init_hook(void)
300{
301 if (x86_quirks->arch_pre_intr_init) {
302 if (x86_quirks->arch_pre_intr_init())
303 return;
304 }
305 init_ISA_irqs();
306}
307
308/**
309 * intr_init_hook - post gate setup interrupt initialisation
310 *
311 * Description:
312 * Fill in any interrupts that may have been left out by the general
313 * init_IRQ() routine. interrupts having to do with the machine rather
314 * than the devices on the I/O bus (like APIC interrupts in intel MP
315 * systems) are started here.
316 **/
317void __init intr_init_hook(void)
318{
319 if (x86_quirks->arch_intr_init) {
320 if (x86_quirks->arch_intr_init())
321 return;
322 }
323}
324
325/**
326 * pre_setup_arch_hook - hook called prior to any setup_arch() execution
327 *
328 * Description:
329 * generally used to activate any machine specific identification
330 * routines that may be needed before setup_arch() runs. On Voyager
331 * this is used to get the board revision and type.
332 **/
333void __init pre_setup_arch_hook(void)
334{
335}
336
337/**
338 * trap_init_hook - initialise system specific traps
339 *
340 * Description:
341 * Called as the final act of trap_init(). Used in VISWS to initialise
342 * the various board specific APIC traps.
343 **/
344void __init trap_init_hook(void)
345{
346 if (x86_quirks->arch_trap_init) {
347 if (x86_quirks->arch_trap_init())
348 return;
349 }
350}
351
352static struct irqaction irq0 = {
353 .handler = timer_interrupt,
354 .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_IRQPOLL,
355 .mask = CPU_MASK_NONE,
356 .name = "timer"
357};
358
359/**
360 * pre_time_init_hook - do any specific initialisations before.
361 *
362 **/
363void __init pre_time_init_hook(void)
364{
365 if (x86_quirks->arch_pre_time_init)
366 x86_quirks->arch_pre_time_init();
367}
368
369/**
370 * time_init_hook - do any specific initialisations for the system timer.
371 *
372 * Description:
373 * Must plug the system timer interrupt source at HZ into the IRQ listed
374 * in irq_vectors.h:TIMER_IRQ
375 **/
376void __init time_init_hook(void)
377{
378 if (x86_quirks->arch_time_init) {
379 /*
380 * A nonzero return code does not mean failure, it means
381 * that the architecture quirk does not want any
382 * generic (timer) setup to be performed after this:
383 */
384 if (x86_quirks->arch_time_init())
385 return;
386 }
387
388 irq0.mask = cpumask_of_cpu(0);
389 setup_irq(0, &irq0);
390}
391
392#ifdef CONFIG_MCA
393/**
394 * mca_nmi_hook - hook into MCA specific NMI chain
395 *
396 * Description:
397 * The MCA (Microchannel Architecture) has an NMI chain for NMI sources
398 * along the MCA bus. Use this to hook into that chain if you will need
399 * it.
400 **/
401void mca_nmi_hook(void)
402{
403 /*
404 * If I recall correctly, there's a whole bunch of other things that
405 * we can do to check for NMI problems, but that's all I know about
406 * at the moment.
407 */
408 pr_warning("NMI generated from unknown source!\n");
409}
410#endif
411
412static __init int no_ipi_broadcast(char *str)
413{
414 get_option(&str, &no_broadcast);
415 pr_info("Using %s mode\n",
416 no_broadcast ? "No IPI Broadcast" : "IPI Broadcast");
417 return 1;
418}
419__setup("no_ipi_broadcast=", no_ipi_broadcast);
420
421static int __init print_ipi_mode(void)
422{
423 pr_info("Using IPI %s mode\n",
424 no_broadcast ? "No-Shortcut" : "Shortcut");
425 return 0;
426}
427
428late_initcall(print_ipi_mode);
429