x86: irq.c - tiny cleanup
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kernel / irq.c
CommitLineData
6b39ba77
TG
1/*
2 * Common interrupt code for 32 and 64 bit
3 */
4#include <linux/cpu.h>
5#include <linux/interrupt.h>
6#include <linux/kernel_stat.h>
7#include <linux/seq_file.h>
6a02e710 8#include <linux/smp.h>
7c1d7cdc 9#include <linux/ftrace.h>
6b39ba77 10
7b6aa335 11#include <asm/apic.h>
6b39ba77 12#include <asm/io_apic.h>
c3d80000 13#include <asm/irq.h>
7c1d7cdc 14#include <asm/idle.h>
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TG
15
16atomic_t irq_err_count;
17
acaabe79
DS
18/* Function pointer for generic interrupt vector handling */
19void (*generic_interrupt_extension)(void) = NULL;
20
249f6d9e
TG
21/*
22 * 'what should we do if we get a hw irq event on an illegal vector'.
23 * each architecture has to answer this themselves.
24 */
25void ack_bad_irq(unsigned int irq)
26{
edea7148
CG
27 if (printk_ratelimit())
28 pr_err("unexpected IRQ trap at vector %02x\n", irq);
249f6d9e
TG
29
30#ifdef CONFIG_X86_LOCAL_APIC
31 /*
32 * Currently unexpected vectors happen only on SMP and APIC.
33 * We _must_ ack these because every local APIC has only N
34 * irq slots per priority level, and a 'hanging, unacked' IRQ
35 * holds up an irq slot - in excessive cases (when multiple
36 * unexpected vectors occur) that might lock up the APIC
37 * completely.
38 * But only ack when the APIC is enabled -AK
39 */
40 if (cpu_has_apic)
41 ack_APIC_irq();
42#endif
43}
44
1b437c8c 45#define irq_stats(x) (&per_cpu(irq_stat, x))
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46/*
47 * /proc/interrupts printing:
48 */
7a81d9a7 49static int show_other_interrupts(struct seq_file *p, int prec)
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TG
50{
51 int j;
52
7a81d9a7 53 seq_printf(p, "%*s: ", prec, "NMI");
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54 for_each_online_cpu(j)
55 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
56 seq_printf(p, " Non-maskable interrupts\n");
57#ifdef CONFIG_X86_LOCAL_APIC
7a81d9a7 58 seq_printf(p, "%*s: ", prec, "LOC");
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TG
59 for_each_online_cpu(j)
60 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
61 seq_printf(p, " Local timer interrupts\n");
474e56b8
JSR
62
63 seq_printf(p, "%*s: ", prec, "SPU");
64 for_each_online_cpu(j)
65 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
66 seq_printf(p, " Spurious interrupts\n");
6b39ba77 67#endif
acaabe79
DS
68 if (generic_interrupt_extension) {
69 seq_printf(p, "PLT: ");
70 for_each_online_cpu(j)
71 seq_printf(p, "%10u ", irq_stats(j)->generic_irqs);
72 seq_printf(p, " Platform interrupts\n");
73 }
6b39ba77 74#ifdef CONFIG_SMP
7a81d9a7 75 seq_printf(p, "%*s: ", prec, "RES");
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TG
76 for_each_online_cpu(j)
77 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
78 seq_printf(p, " Rescheduling interrupts\n");
7a81d9a7 79 seq_printf(p, "%*s: ", prec, "CAL");
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TG
80 for_each_online_cpu(j)
81 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
82 seq_printf(p, " Function call interrupts\n");
7a81d9a7 83 seq_printf(p, "%*s: ", prec, "TLB");
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TG
84 for_each_online_cpu(j)
85 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
86 seq_printf(p, " TLB shootdowns\n");
87#endif
88#ifdef CONFIG_X86_MCE
7a81d9a7 89 seq_printf(p, "%*s: ", prec, "TRM");
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90 for_each_online_cpu(j)
91 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
92 seq_printf(p, " Thermal event interrupts\n");
93# ifdef CONFIG_X86_64
7a81d9a7 94 seq_printf(p, "%*s: ", prec, "THR");
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95 for_each_online_cpu(j)
96 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
97 seq_printf(p, " Threshold APIC interrupts\n");
98# endif
6b39ba77 99#endif
7a81d9a7 100 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
6b39ba77 101#if defined(CONFIG_X86_IO_APIC)
7a81d9a7 102 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
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103#endif
104 return 0;
105}
106
107int show_interrupts(struct seq_file *p, void *v)
108{
109 unsigned long flags, any_count = 0;
7a81d9a7 110 int i = *(loff_t *) v, j, prec;
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TG
111 struct irqaction *action;
112 struct irq_desc *desc;
113
114 if (i > nr_irqs)
115 return 0;
116
7a81d9a7
JB
117 for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec)
118 j *= 10;
119
6b39ba77 120 if (i == nr_irqs)
7a81d9a7 121 return show_other_interrupts(p, prec);
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TG
122
123 /* print header */
124 if (i == 0) {
7a81d9a7 125 seq_printf(p, "%*s", prec + 8, "");
6b39ba77 126 for_each_online_cpu(j)
e9f95e63 127 seq_printf(p, "CPU%-8d", j);
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TG
128 seq_putc(p, '\n');
129 }
130
131 desc = irq_to_desc(i);
0b8f1efa
YL
132 if (!desc)
133 return 0;
134
6b39ba77 135 spin_lock_irqsave(&desc->lock, flags);
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136 for_each_online_cpu(j)
137 any_count |= kstat_irqs_cpu(i, j);
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138 action = desc->action;
139 if (!action && !any_count)
140 goto out;
141
7a81d9a7 142 seq_printf(p, "%*d: ", prec, i);
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143 for_each_online_cpu(j)
144 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
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145 seq_printf(p, " %8s", desc->chip->name);
146 seq_printf(p, "-%-8s", desc->name);
147
148 if (action) {
149 seq_printf(p, " %s", action->name);
150 while ((action = action->next) != NULL)
151 seq_printf(p, ", %s", action->name);
152 }
153
154 seq_putc(p, '\n');
155out:
156 spin_unlock_irqrestore(&desc->lock, flags);
157 return 0;
158}
159
160/*
161 * /proc/stat helpers
162 */
163u64 arch_irq_stat_cpu(unsigned int cpu)
164{
165 u64 sum = irq_stats(cpu)->__nmi_count;
166
167#ifdef CONFIG_X86_LOCAL_APIC
168 sum += irq_stats(cpu)->apic_timer_irqs;
474e56b8 169 sum += irq_stats(cpu)->irq_spurious_count;
6b39ba77 170#endif
acaabe79
DS
171 if (generic_interrupt_extension)
172 sum += irq_stats(cpu)->generic_irqs;
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173#ifdef CONFIG_SMP
174 sum += irq_stats(cpu)->irq_resched_count;
175 sum += irq_stats(cpu)->irq_call_count;
176 sum += irq_stats(cpu)->irq_tlb_count;
177#endif
178#ifdef CONFIG_X86_MCE
179 sum += irq_stats(cpu)->irq_thermal_count;
180# ifdef CONFIG_X86_64
181 sum += irq_stats(cpu)->irq_threshold_count;
edea7148 182# endif
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183#endif
184 return sum;
185}
186
187u64 arch_irq_stat(void)
188{
189 u64 sum = atomic_read(&irq_err_count);
190
191#ifdef CONFIG_X86_IO_APIC
192 sum += atomic_read(&irq_mis_count);
193#endif
194 return sum;
195}
c3d80000 196
7c1d7cdc
JF
197
198/*
199 * do_IRQ handles all normal device IRQ's (the special
200 * SMP cross-CPU interrupts have their own specific
201 * handlers).
202 */
203unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
204{
205 struct pt_regs *old_regs = set_irq_regs(regs);
206
207 /* high bit used in ret_from_ code */
208 unsigned vector = ~regs->orig_ax;
209 unsigned irq;
210
211 exit_idle();
212 irq_enter();
213
214 irq = __get_cpu_var(vector_irq)[vector];
215
216 if (!handle_irq(irq, regs)) {
217#ifdef CONFIG_X86_64
218 if (!disable_apic)
219 ack_APIC_irq();
220#endif
221
222 if (printk_ratelimit())
edea7148
CG
223 pr_emerg("%s: %d.%d No irq handler for vector (irq %d)\n",
224 __func__, smp_processor_id(), vector, irq);
7c1d7cdc
JF
225 }
226
227 irq_exit();
228
229 set_irq_regs(old_regs);
230 return 1;
231}
232
acaabe79
DS
233/*
234 * Handler for GENERIC_INTERRUPT_VECTOR.
235 */
236void smp_generic_interrupt(struct pt_regs *regs)
237{
238 struct pt_regs *old_regs = set_irq_regs(regs);
239
240 ack_APIC_irq();
241
242 exit_idle();
243
244 irq_enter();
245
246 inc_irq_stat(generic_irqs);
247
248 if (generic_interrupt_extension)
249 generic_interrupt_extension();
250
251 irq_exit();
252
253 set_irq_regs(old_regs);
254}
255
c3d80000 256EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);