[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kernel / i8259.c

#include <linux/linkage.h>
#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/timex.h>
#include <linux/random.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/syscore_ops.h>
#include <linux/bitops.h>
#include <linux/acpi.h>
#include <linux/io.h>
#include <linux/delay.h>

#include <linux/atomic.h>
#include <asm/system.h>
#include <asm/timer.h>
#include <asm/hw_irq.h>
#include <asm/pgtable.h>
#include <asm/desc.h>
#include <asm/apic.h>
#include <asm/i8259.h>

/*
 * This is the 'legacy' 8259A Programmable Interrupt Controller,
 * present in the majority of PC/AT boxes.
 * plus some generic x86 specific things if generic specifics makes
 * any sense at all.
 */
static void init_8259A(int auto_eoi);

static int i8259A_auto_eoi;
DEFINE_RAW_SPINLOCK(i8259A_lock);

/*
 * 8259A PIC functions to handle ISA devices:
 */

/*
 * This contains the irq mask for both 8259A irq controllers,
 */
unsigned int cached_irq_mask = 0xffff;

/*
 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
 * boards the timer interrupt is not really connected to any IO-APIC pin,
 * it's fed to the master 8259A's IR0 line only.
 *
 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
 * this 'mixed mode' IRQ handling costs nothing because it's only used
 * at IRQ setup time.
 */
unsigned long io_apic_irqs;

static void mask_8259A_irq(unsigned int irq)
{
	unsigned int mask = 1 << irq;
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);
	cached_irq_mask |= mask;
	if (irq & 8)
		outb(cached_slave_mask, PIC_SLAVE_IMR);
	else
		outb(cached_master_mask, PIC_MASTER_IMR);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

static void disable_8259A_irq(struct irq_data *data)
{
	mask_8259A_irq(data->irq);
}

static void unmask_8259A_irq(unsigned int irq)
{
	unsigned int mask = ~(1 << irq);
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);
	cached_irq_mask &= mask;
	if (irq & 8)
		outb(cached_slave_mask, PIC_SLAVE_IMR);
	else
		outb(cached_master_mask, PIC_MASTER_IMR);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

static void enable_8259A_irq(struct irq_data *data)
{
	unmask_8259A_irq(data->irq);
}

static int i8259A_irq_pending(unsigned int irq)
{
	unsigned int mask = 1<<irq;
	unsigned long flags;
	int ret;

	raw_spin_lock_irqsave(&i8259A_lock, flags);
	if (irq < 8)
		ret = inb(PIC_MASTER_CMD) & mask;
	else
		ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);

	return ret;
}

static void make_8259A_irq(unsigned int irq)
{
	disable_irq_nosync(irq);
	io_apic_irqs &= ~(1<<irq);
	irq_set_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
				      i8259A_chip.name);
	enable_irq(irq);
}

/*
 * This function assumes to be called rarely. Switching between
 * 8259A registers is slow.
 * This has to be protected by the irq controller spinlock
 * before being called.
 */
static inline int i8259A_irq_real(unsigned int irq)
{
	int value;
	int irqmask = 1<<irq;

	if (irq < 8) {
		outb(0x0B, PIC_MASTER_CMD);	/* ISR register */
		value = inb(PIC_MASTER_CMD) & irqmask;
		outb(0x0A, PIC_MASTER_CMD);	/* back to the IRR register */
		return value;
	}
	outb(0x0B, PIC_SLAVE_CMD);	/* ISR register */
	value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
	outb(0x0A, PIC_SLAVE_CMD);	/* back to the IRR register */
	return value;
}

/*
 * Careful! The 8259A is a fragile beast, it pretty
 * much _has_ to be done exactly like this (mask it
 * first, _then_ send the EOI, and the order of EOI
 * to the two 8259s is important!
 */
static void mask_and_ack_8259A(struct irq_data *data)
{
	unsigned int irq = data->irq;
	unsigned int irqmask = 1 << irq;
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);
	/*
	 * Lightweight spurious IRQ detection. We do not want
	 * to overdo spurious IRQ handling - it's usually a sign
	 * of hardware problems, so we only do the checks we can
	 * do without slowing down good hardware unnecessarily.
	 *
	 * Note that IRQ7 and IRQ15 (the two spurious IRQs
	 * usually resulting from the 8259A-1|2 PICs) occur
	 * even if the IRQ is masked in the 8259A. Thus we
	 * can check spurious 8259A IRQs without doing the
	 * quite slow i8259A_irq_real() call for every IRQ.
	 * This does not cover 100% of spurious interrupts,
	 * but should be enough to warn the user that there
	 * is something bad going on ...
	 */
	if (cached_irq_mask & irqmask)
		goto spurious_8259A_irq;
	cached_irq_mask |= irqmask;

handle_real_irq:
	if (irq & 8) {
		inb(PIC_SLAVE_IMR);	/* DUMMY - (do we need this?) */
		outb(cached_slave_mask, PIC_SLAVE_IMR);
		/* 'Specific EOI' to slave */
		outb(0x60+(irq&7), PIC_SLAVE_CMD);
		 /* 'Specific EOI' to master-IRQ2 */
		outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD);
	} else {
		inb(PIC_MASTER_IMR);	/* DUMMY - (do we need this?) */
		outb(cached_master_mask, PIC_MASTER_IMR);
		outb(0x60+irq, PIC_MASTER_CMD);	/* 'Specific EOI to master */
	}
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
	return;

spurious_8259A_irq:
	/*
	 * this is the slow path - should happen rarely.
	 */
	if (i8259A_irq_real(irq))
		/*
		 * oops, the IRQ _is_ in service according to the
		 * 8259A - not spurious, go handle it.
		 */
		goto handle_real_irq;

	{
		static int spurious_irq_mask;
		/*
		 * At this point we can be sure the IRQ is spurious,
		 * lets ACK and report it. [once per IRQ]
		 */
		if (!(spurious_irq_mask & irqmask)) {
			printk(KERN_DEBUG
			       "spurious 8259A interrupt: IRQ%d.\n", irq);
			spurious_irq_mask |= irqmask;
		}
		atomic_inc(&irq_err_count);
		/*
		 * Theoretically we do not have to handle this IRQ,
		 * but in Linux this does not cause problems and is
		 * simpler for us.
		 */
		goto handle_real_irq;
	}
}

struct irq_chip i8259A_chip = {
	.name		= "XT-PIC",
	.irq_mask	= disable_8259A_irq,
	.irq_disable	= disable_8259A_irq,
	.irq_unmask	= enable_8259A_irq,
	.irq_mask_ack	= mask_and_ack_8259A,
};

static char irq_trigger[2];
/**
 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
 */
static void restore_ELCR(char *trigger)
{
	outb(trigger[0], 0x4d0);
	outb(trigger[1], 0x4d1);
}

static void save_ELCR(char *trigger)
{
	/* IRQ 0,1,2,8,13 are marked as reserved */
	trigger[0] = inb(0x4d0) & 0xF8;
	trigger[1] = inb(0x4d1) & 0xDE;
}

static void i8259A_resume(void)
{
	init_8259A(i8259A_auto_eoi);
	restore_ELCR(irq_trigger);
}

static int i8259A_suspend(void)
{
	save_ELCR(irq_trigger);
	return 0;
}

static void i8259A_shutdown(void)
{
	/* Put the i8259A into a quiescent state that
	 * the kernel initialization code can get it
	 * out of.
	 */
	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-1 */
}

static struct syscore_ops i8259_syscore_ops = {
	.suspend = i8259A_suspend,
	.resume = i8259A_resume,
	.shutdown = i8259A_shutdown,
};

static void mask_8259A(void)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);

	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

static void unmask_8259A(void)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);

	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	outb(cached_slave_mask, PIC_SLAVE_IMR);	  /* restore slave IRQ mask */

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

static void init_8259A(int auto_eoi)
{
	unsigned long flags;

	i8259A_auto_eoi = auto_eoi;

	raw_spin_lock_irqsave(&i8259A_lock, flags);

	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */

	/*
	 * outb_pic - this has to work on a wide range of PC hardware.
	 */
	outb_pic(0x11, PIC_MASTER_CMD);	/* ICW1: select 8259A-1 init */

	/* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 on x86-64,
	   to 0x20-0x27 on i386 */
	outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);

	/* 8259A-1 (the master) has a slave on IR2 */
	outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);

	if (auto_eoi)	/* master does Auto EOI */
		outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
	else		/* master expects normal EOI */
		outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);

	outb_pic(0x11, PIC_SLAVE_CMD);	/* ICW1: select 8259A-2 init */

	/* ICW2: 8259A-2 IR0-7 mapped to IRQ8_VECTOR */
	outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR);
	/* 8259A-2 is a slave on master's IR2 */
	outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
	/* (slave's support for AEOI in flat mode is to be investigated) */
	outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);

	if (auto_eoi)
		/*
		 * In AEOI mode we just have to mask the interrupt
		 * when acking.
		 */
		i8259A_chip.irq_mask_ack = disable_8259A_irq;
	else
		i8259A_chip.irq_mask_ack = mask_and_ack_8259A;

	udelay(100);		/* wait for 8259A to initialize */

	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	outb(cached_slave_mask, PIC_SLAVE_IMR);	  /* restore slave IRQ mask */

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

/*
 * make i8259 a driver so that we can select pic functions at run time. the goal
 * is to make x86 binary compatible among pc compatible and non-pc compatible
 * platforms, such as x86 MID.
 */

static void legacy_pic_noop(void) { };
static void legacy_pic_uint_noop(unsigned int unused) { };
static void legacy_pic_int_noop(int unused) { };
static int legacy_pic_irq_pending_noop(unsigned int irq)
{
	return 0;
}

struct legacy_pic null_legacy_pic = {
	.nr_legacy_irqs = 0,
	.chip = &dummy_irq_chip,
	.mask = legacy_pic_uint_noop,
	.unmask = legacy_pic_uint_noop,
	.mask_all = legacy_pic_noop,
	.restore_mask = legacy_pic_noop,
	.init = legacy_pic_int_noop,
	.irq_pending = legacy_pic_irq_pending_noop,
	.make_irq = legacy_pic_uint_noop,
};

struct legacy_pic default_legacy_pic = {
	.nr_legacy_irqs = NR_IRQS_LEGACY,
	.chip  = &i8259A_chip,
	.mask = mask_8259A_irq,
	.unmask = unmask_8259A_irq,
	.mask_all = mask_8259A,
	.restore_mask = unmask_8259A,
	.init = init_8259A,
	.irq_pending = i8259A_irq_pending,
	.make_irq = make_8259A_irq,
};

struct legacy_pic *legacy_pic = &default_legacy_pic;

static int __init i8259A_init_ops(void)
{
	if (legacy_pic == &default_legacy_pic)
		register_syscore_ops(&i8259_syscore_ops);

	return 0;
}

device_initcall(i8259A_init_ops);
Commit	Line	Data
21fd5132	1	#include <linux/linkage.h>
21fd5132 PM	2	#include <linux/errno.h>
	3	#include <linux/signal.h>
	4	#include <linux/sched.h>
	5	#include <linux/ioport.h>
	6	#include <linux/interrupt.h>
21fd5132	7	#include <linux/timex.h>
21fd5132 PM	8	#include <linux/random.h>
	9	#include <linux/init.h>
	10	#include <linux/kernel_stat.h>
f3c6ea1b	11	#include <linux/syscore_ops.h>
21fd5132	12	#include <linux/bitops.h>
7bafaf30 JSR	13	#include <linux/acpi.h>
	14	#include <linux/io.h>
	15	#include <linux/delay.h>
21fd5132	16
60063497	17	#include <linux/atomic.h>
21fd5132	18	#include <asm/system.h>
21fd5132	19	#include <asm/timer.h>
21fd5132	20	#include <asm/hw_irq.h>
21fd5132	21	#include <asm/pgtable.h>
21fd5132 PM	22	#include <asm/desc.h>
21fd5132 PM	23	#include <asm/apic.h>
21fd5132 PM	24	#include <asm/i8259.h>
	25
	26	/*
	27	* This is the 'legacy' 8259A Programmable Interrupt Controller,
	28	* present in the majority of PC/AT boxes.
	29	* plus some generic x86 specific things if generic specifics makes
	30	* any sense at all.
	31	*/
4305df94	32	static void init_8259A(int auto_eoi);
21fd5132 PM	33
21fd5132 PM	34	static int i8259A_auto_eoi;
5619c280	35	DEFINE_RAW_SPINLOCK(i8259A_lock);
21fd5132 PM	36
	37	/*
	38	* 8259A PIC functions to handle ISA devices:
	39	*/
	40
	41	/*
	42	* This contains the irq mask for both 8259A irq controllers,
	43	*/
	44	unsigned int cached_irq_mask = 0xffff;
	45
	46	/*
	47	* Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
	48	* boards the timer interrupt is not really connected to any IO-APIC pin,
	49	* it's fed to the master 8259A's IR0 line only.
	50	*
	51	* Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
	52	* this 'mixed mode' IRQ handling costs nothing because it's only used
	53	* at IRQ setup time.
	54	*/
	55	unsigned long io_apic_irqs;
	56
4305df94	57	static void mask_8259A_irq(unsigned int irq)
21fd5132 PM	58	{
	59	unsigned int mask = 1 << irq;
	60	unsigned long flags;
	61
5619c280	62	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	63	cached_irq_mask \|= mask;
	64	if (irq & 8)
	65	outb(cached_slave_mask, PIC_SLAVE_IMR);
	66	else
	67	outb(cached_master_mask, PIC_MASTER_IMR);
5619c280	68	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132 PM	69	}
21fd5132 PM	70
4305df94 TG	71	static void disable_8259A_irq(struct irq_data *data)
	72	{
	73	mask_8259A_irq(data->irq);
	74	}
	75
	76	static void unmask_8259A_irq(unsigned int irq)
21fd5132 PM	77	{
	78	unsigned int mask = ~(1 << irq);
	79	unsigned long flags;
	80
5619c280	81	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	82	cached_irq_mask &= mask;
	83	if (irq & 8)
	84	outb(cached_slave_mask, PIC_SLAVE_IMR);
	85	else
	86	outb(cached_master_mask, PIC_MASTER_IMR);
5619c280	87	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132 PM	88	}
21fd5132 PM	89
4305df94 TG	90	static void enable_8259A_irq(struct irq_data *data)
	91	{
	92	unmask_8259A_irq(data->irq);
	93	}
	94
b81bb373	95	static int i8259A_irq_pending(unsigned int irq)
21fd5132 PM	96	{
	97	unsigned int mask = 1<<irq;
	98	unsigned long flags;
	99	int ret;
	100
5619c280	101	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	102	if (irq < 8)
	103	ret = inb(PIC_MASTER_CMD) & mask;
	104	else
	105	ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
5619c280	106	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132 PM	107
	108	return ret;
	109	}
	110
b81bb373	111	static void make_8259A_irq(unsigned int irq)
21fd5132 PM	112	{
	113	disable_irq_nosync(irq);
	114	io_apic_irqs &= ~(1<<irq);
2c778651	115	irq_set_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
4305df94	116	i8259A_chip.name);
21fd5132 PM	117	enable_irq(irq);
	118	}
	119
	120	/*
	121	* This function assumes to be called rarely. Switching between
	122	* 8259A registers is slow.
	123	* This has to be protected by the irq controller spinlock
	124	* before being called.
	125	*/
	126	static inline int i8259A_irq_real(unsigned int irq)
	127	{
	128	int value;
	129	int irqmask = 1<<irq;
	130
	131	if (irq < 8) {
680afbf9	132	outb(0x0B, PIC_MASTER_CMD); /* ISR register */
21fd5132	133	value = inb(PIC_MASTER_CMD) & irqmask;
680afbf9	134	outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */
21fd5132 PM	135	return value;
21fd5132 PM	136	}
680afbf9	137	outb(0x0B, PIC_SLAVE_CMD); /* ISR register */
21fd5132	138	value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
680afbf9	139	outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */
21fd5132 PM	140	return value;
	141	}
	142
	143	/*
	144	* Careful! The 8259A is a fragile beast, it pretty
	145	* much _has_ to be done exactly like this (mask it
	146	* first, _then_ send the EOI, and the order of EOI
	147	* to the two 8259s is important!
	148	*/
4305df94	149	static void mask_and_ack_8259A(struct irq_data *data)
21fd5132	150	{
4305df94	151	unsigned int irq = data->irq;
21fd5132 PM	152	unsigned int irqmask = 1 << irq;
	153	unsigned long flags;
	154
5619c280	155	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	156	/*
	157	* Lightweight spurious IRQ detection. We do not want
	158	* to overdo spurious IRQ handling - it's usually a sign
	159	* of hardware problems, so we only do the checks we can
	160	* do without slowing down good hardware unnecessarily.
	161	*
	162	* Note that IRQ7 and IRQ15 (the two spurious IRQs
	163	* usually resulting from the 8259A-1\|2 PICs) occur
	164	* even if the IRQ is masked in the 8259A. Thus we
	165	* can check spurious 8259A IRQs without doing the
	166	* quite slow i8259A_irq_real() call for every IRQ.
	167	* This does not cover 100% of spurious interrupts,
	168	* but should be enough to warn the user that there
	169	* is something bad going on ...
	170	*/
	171	if (cached_irq_mask & irqmask)
	172	goto spurious_8259A_irq;
	173	cached_irq_mask \|= irqmask;
	174
	175	handle_real_irq:
	176	if (irq & 8) {
	177	inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
	178	outb(cached_slave_mask, PIC_SLAVE_IMR);
21fd5132	179	/* 'Specific EOI' to slave */
3e8631d2	180	outb(0x60+(irq&7), PIC_SLAVE_CMD);
21fd5132	181	/* 'Specific EOI' to master-IRQ2 */
3e8631d2	182	outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD);
21fd5132 PM	183	} else {
	184	inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
	185	outb(cached_master_mask, PIC_MASTER_IMR);
3e8631d2	186	outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
21fd5132	187	}
5619c280	188	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132 PM	189	return;
	190
	191	spurious_8259A_irq:
	192	/*
	193	* this is the slow path - should happen rarely.
	194	*/
	195	if (i8259A_irq_real(irq))
	196	/*
	197	* oops, the IRQ _is_ in service according to the
	198	* 8259A - not spurious, go handle it.
	199	*/
	200	goto handle_real_irq;
	201
	202	{
	203	static int spurious_irq_mask;
	204	/*
	205	* At this point we can be sure the IRQ is spurious,
	206	* lets ACK and report it. [once per IRQ]
	207	*/
	208	if (!(spurious_irq_mask & irqmask)) {
21fd5132 PM	209	printk(KERN_DEBUG
21fd5132 PM	210	"spurious 8259A interrupt: IRQ%d.\n", irq);
21fd5132 PM	211	spurious_irq_mask \|= irqmask;
	212	}
	213	atomic_inc(&irq_err_count);
	214	/*
	215	* Theoretically we do not have to handle this IRQ,
	216	* but in Linux this does not cause problems and is
	217	* simpler for us.
	218	*/
	219	goto handle_real_irq;
	220	}
	221	}
	222
4305df94 TG	223	struct irq_chip i8259A_chip = {
	224	.name = "XT-PIC",
	225	.irq_mask = disable_8259A_irq,
	226	.irq_disable = disable_8259A_irq,
	227	.irq_unmask = enable_8259A_irq,
	228	.irq_mask_ack = mask_and_ack_8259A,
	229	};
	230
21fd5132 PM	231	static char irq_trigger[2];
	232	/**
	233	* ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
	234	*/
	235	static void restore_ELCR(char *trigger)
	236	{
	237	outb(trigger[0], 0x4d0);
	238	outb(trigger[1], 0x4d1);
	239	}
	240
	241	static void save_ELCR(char *trigger)
	242	{
	243	/* IRQ 0,1,2,8,13 are marked as reserved */
	244	trigger[0] = inb(0x4d0) & 0xF8;
	245	trigger[1] = inb(0x4d1) & 0xDE;
	246	}
	247
f3c6ea1b	248	static void i8259A_resume(void)
21fd5132 PM	249	{
	250	init_8259A(i8259A_auto_eoi);
	251	restore_ELCR(irq_trigger);
21fd5132 PM	252	}
21fd5132 PM	253
f3c6ea1b	254	static int i8259A_suspend(void)
21fd5132 PM	255	{
	256	save_ELCR(irq_trigger);
	257	return 0;
	258	}
	259
f3c6ea1b	260	static void i8259A_shutdown(void)
21fd5132 PM	261	{
	262	/* Put the i8259A into a quiescent state that
	263	* the kernel initialization code can get it
	264	* out of.
	265	*/
	266	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
	267	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
21fd5132 PM	268	}
21fd5132 PM	269
f3c6ea1b	270	static struct syscore_ops i8259_syscore_ops = {
21fd5132 PM	271	.suspend = i8259A_suspend,
	272	.resume = i8259A_resume,
	273	.shutdown = i8259A_shutdown,
	274	};
	275
b81bb373	276	static void mask_8259A(void)
d94d93ca SS	277	{
	278	unsigned long flags;
	279
5619c280	280	raw_spin_lock_irqsave(&i8259A_lock, flags);
d94d93ca SS	281
	282	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
	283	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
	284
5619c280	285	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
d94d93ca SS	286	}
d94d93ca SS	287
b81bb373	288	static void unmask_8259A(void)
d94d93ca SS	289	{
	290	unsigned long flags;
	291
5619c280	292	raw_spin_lock_irqsave(&i8259A_lock, flags);
d94d93ca SS	293
	294	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	295	outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
	296
5619c280	297	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
d94d93ca SS	298	}
d94d93ca SS	299
b81bb373	300	static void init_8259A(int auto_eoi)
21fd5132 PM	301	{
	302	unsigned long flags;
	303
	304	i8259A_auto_eoi = auto_eoi;
	305
5619c280	306	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	307
	308	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
	309	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
	310
	311	/*
	312	* outb_pic - this has to work on a wide range of PC hardware.
	313	*/
	314	outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
c46e62f7 PM	315
c46e62f7 PM	316	/* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 on x86-64,
7bafaf30	317	to 0x20-0x27 on i386 */
21fd5132	318	outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);
c46e62f7	319
21fd5132	320	/* 8259A-1 (the master) has a slave on IR2 */
c46e62f7 PM	321	outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);
c46e62f7 PM	322
21fd5132 PM	323	if (auto_eoi) /* master does Auto EOI */
	324	outb_pic(MASTER_ICW4_DEFAULT \| PIC_ICW4_AEOI, PIC_MASTER_IMR);
	325	else /* master expects normal EOI */
	326	outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
	327
	328	outb_pic(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
c46e62f7 PM	329
c46e62f7 PM	330	/* ICW2: 8259A-2 IR0-7 mapped to IRQ8_VECTOR */
21fd5132 PM	331	outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR);
	332	/* 8259A-2 is a slave on master's IR2 */
	333	outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
	334	/* (slave's support for AEOI in flat mode is to be investigated) */
	335	outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
	336
21fd5132 PM	337	if (auto_eoi)
	338	/*
	339	* In AEOI mode we just have to mask the interrupt
	340	* when acking.
	341	*/
4305df94	342	i8259A_chip.irq_mask_ack = disable_8259A_irq;
21fd5132	343	else
4305df94	344	i8259A_chip.irq_mask_ack = mask_and_ack_8259A;
21fd5132 PM	345
	346	udelay(100); /* wait for 8259A to initialize */
	347
	348	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	349	outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
	350
5619c280	351	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132	352	}
b81bb373	353
ef354866 JP	354	/*
	355	* make i8259 a driver so that we can select pic functions at run time. the goal
	356	* is to make x86 binary compatible among pc compatible and non-pc compatible
	357	* platforms, such as x86 MID.
	358	*/
	359
28a3c93d JP	360	static void legacy_pic_noop(void) { };
	361	static void legacy_pic_uint_noop(unsigned int unused) { };
	362	static void legacy_pic_int_noop(int unused) { };
ef354866 JP	363	static int legacy_pic_irq_pending_noop(unsigned int irq)
	364	{
	365	return 0;
	366	}
	367
	368	struct legacy_pic null_legacy_pic = {
	369	.nr_legacy_irqs = 0,
4305df94 TG	370	.chip = &dummy_irq_chip,
	371	.mask = legacy_pic_uint_noop,
	372	.unmask = legacy_pic_uint_noop,
ef354866 JP	373	.mask_all = legacy_pic_noop,
	374	.restore_mask = legacy_pic_noop,
	375	.init = legacy_pic_int_noop,
	376	.irq_pending = legacy_pic_irq_pending_noop,
	377	.make_irq = legacy_pic_uint_noop,
	378	};
	379
	380	struct legacy_pic default_legacy_pic = {
	381	.nr_legacy_irqs = NR_IRQS_LEGACY,
	382	.chip = &i8259A_chip,
4305df94 TG	383	.mask = mask_8259A_irq,
	384	.unmask = unmask_8259A_irq,
	385	.mask_all = mask_8259A,
ef354866 JP	386	.restore_mask = unmask_8259A,
	387	.init = init_8259A,
	388	.irq_pending = i8259A_irq_pending,
	389	.make_irq = make_8259A_irq,
	390	};
	391
	392	struct legacy_pic *legacy_pic = &default_legacy_pic;
087b255a	393
f3c6ea1b	394	static int __init i8259A_init_ops(void)
087b255a	395	{
f3c6ea1b RW	396	if (legacy_pic == &default_legacy_pic)
f3c6ea1b RW	397	register_syscore_ops(&i8259_syscore_ops);
087b255a	398
f3c6ea1b	399	return 0;
087b255a AL	400	}
087b255a AL	401
f3c6ea1b	402	device_initcall(i8259A_init_ops);