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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kernel / hpet.c
CommitLineData
5d0cf410 1#include <linux/clocksource.h>
e9e2cdb4 2#include <linux/clockchips.h>
4588c1f0
IM		 3#include <linux/interrupt.h>
4#include <linux/sysdev.h>
28769149 5#include <linux/delay.h>
5d0cf410 6#include <linux/errno.h>
5a0e3ad6 7#include <linux/slab.h>
5d0cf410
JS		 8#include <linux/hpet.h>
9#include <linux/init.h>
58ac1e76 10#include <linux/cpu.h>
4588c1f0
IM		 11#include <linux/pm.h>
12#include <linux/io.h>
5d0cf410 13
28769149 14#include <asm/fixmap.h>
06a24dec 15#include <asm/i8253.h>
4588c1f0 16#include <asm/hpet.h>
5d0cf410 17
4588c1f0 18#define HPET_MASK CLOCKSOURCE_MASK(32)
5d0cf410 19
b10db7f0
PM		 20/* FSEC = 10^-15
21 NSEC = 10^-9 */
4588c1f0 22#define FSEC_PER_NSEC 1000000L
5d0cf410 23
26afe5f2 24#define HPET_DEV_USED_BIT 2
25#define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
26#define HPET_DEV_VALID 0x8
27#define HPET_DEV_FSB_CAP 0x1000
28#define HPET_DEV_PERI_CAP 0x2000
29
30#define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
31
e9e2cdb4
TG		 32/*
33 * HPET address is set in acpi/boot.c, when an ACPI entry exists
34 */
4588c1f0 35unsigned long hpet_address;
c8bc6f3c 36u8 hpet_blockid; /* OS timer block num */
73472a46
PV		 37u8 hpet_msi_disable;
38
e951e4af 39#ifdef CONFIG_PCI_MSI
3b71e9e3 40static unsigned long hpet_num_timers;
e951e4af 41#endif
4588c1f0 42static void __iomem *hpet_virt_address;
e9e2cdb4 43
58ac1e76 44struct hpet_dev {
4588c1f0
IM		 45 struct clock_event_device evt;
46 unsigned int num;
47 int cpu;
48 unsigned int irq;
49 unsigned int flags;
50 char name[10];
58ac1e76 51};
52
5946fa3d 53inline unsigned int hpet_readl(unsigned int a)
e9e2cdb4
TG		 54{
55 return readl(hpet_virt_address + a);
56}
57
5946fa3d 58static inline void hpet_writel(unsigned int d, unsigned int a)
e9e2cdb4
TG		 59{
60 writel(d, hpet_virt_address + a);
61}
62
28769149 63#ifdef CONFIG_X86_64
28769149 64#include <asm/pgtable.h>
2387ce57 65#endif
28769149 66
06a24dec
TG		 67static inline void hpet_set_mapping(void)
68{
69 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
2387ce57
YL		 70#ifdef CONFIG_X86_64
71 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
72#endif
06a24dec
TG		 73}
74
75static inline void hpet_clear_mapping(void)
76{
77 iounmap(hpet_virt_address);
78 hpet_virt_address = NULL;
79}
80
e9e2cdb4
TG		 81/*
82 * HPET command line enable / disable
83 */
84static int boot_hpet_disable;
b17530bd 85int hpet_force_user;
b98103a5 86static int hpet_verbose;
e9e2cdb4 87
4588c1f0 88static int __init hpet_setup(char *str)
e9e2cdb4
TG		 89{
90 if (str) {
91 if (!strncmp("disable", str, 7))
92 boot_hpet_disable = 1;
b17530bd
TG		 93 if (!strncmp("force", str, 5))
94 hpet_force_user = 1;
b98103a5
AH		 95 if (!strncmp("verbose", str, 7))
96 hpet_verbose = 1;
e9e2cdb4
TG		 97 }
98 return 1;
99}
100__setup("hpet=", hpet_setup);
101
28769149
TG		 102static int __init disable_hpet(char *str)
103{
104 boot_hpet_disable = 1;
105 return 1;
106}
107__setup("nohpet", disable_hpet);
108
e9e2cdb4
TG		 109static inline int is_hpet_capable(void)
110{
4588c1f0 111 return !boot_hpet_disable && hpet_address;
e9e2cdb4
TG		 112}
113
114/*
115 * HPET timer interrupt enable / disable
116 */
117static int hpet_legacy_int_enabled;
118
119/**
120 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
121 */
122int is_hpet_enabled(void)
123{
124 return is_hpet_capable() && hpet_legacy_int_enabled;
125}
1bdbdaac 126EXPORT_SYMBOL_GPL(is_hpet_enabled);
e9e2cdb4 127
b98103a5
AH		 128static void _hpet_print_config(const char *function, int line)
129{
130 u32 i, timers, l, h;
131 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
132 l = hpet_readl(HPET_ID);
133 h = hpet_readl(HPET_PERIOD);
134 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
135 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
136 l = hpet_readl(HPET_CFG);
137 h = hpet_readl(HPET_STATUS);
138 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
139 l = hpet_readl(HPET_COUNTER);
140 h = hpet_readl(HPET_COUNTER+4);
141 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
142
143 for (i = 0; i < timers; i++) {
144 l = hpet_readl(HPET_Tn_CFG(i));
145 h = hpet_readl(HPET_Tn_CFG(i)+4);
146 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
147 i, l, h);
148 l = hpet_readl(HPET_Tn_CMP(i));
149 h = hpet_readl(HPET_Tn_CMP(i)+4);
150 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
151 i, l, h);
152 l = hpet_readl(HPET_Tn_ROUTE(i));
153 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
154 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
155 i, l, h);
156 }
157}
158
159#define hpet_print_config() \
160do { \
161 if (hpet_verbose) \
162 _hpet_print_config(__FUNCTION__, __LINE__); \
163} while (0)
164
e9e2cdb4
TG		 165/*
166 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
167 * timer 0 and timer 1 in case of RTC emulation.
168 */
169#ifdef CONFIG_HPET
f0ed4e69 170
5f79f2f2 171static void hpet_reserve_msi_timers(struct hpet_data *hd);
f0ed4e69 172
5946fa3d 173static void hpet_reserve_platform_timers(unsigned int id)
e9e2cdb4
TG		 174{
175 struct hpet __iomem *hpet = hpet_virt_address;
37a47db8
BR		 176 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
177 unsigned int nrtimers, i;
e9e2cdb4
TG		 178 struct hpet_data hd;
179
180 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
181
4588c1f0
IM		 182 memset(&hd, 0, sizeof(hd));
183 hd.hd_phys_address = hpet_address;
184 hd.hd_address = hpet;
185 hd.hd_nirqs = nrtimers;
e9e2cdb4
TG		 186 hpet_reserve_timer(&hd, 0);
187
188#ifdef CONFIG_HPET_EMULATE_RTC
189 hpet_reserve_timer(&hd, 1);
190#endif
5761d64b 191
64a76f66
DB		 192 /*
193 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
194 * is wrong for i8259!) not the output IRQ. Many BIOS writers
195 * don't bother configuring *any* comparator interrupts.
196 */
e9e2cdb4
TG		 197 hd.hd_irq[0] = HPET_LEGACY_8254;
198 hd.hd_irq[1] = HPET_LEGACY_RTC;
199
fc3fbc45 200 for (i = 2; i < nrtimers; timer++, i++) {
4588c1f0
IM		 201 hd.hd_irq[i] = (readl(&timer->hpet_config) &
202 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
fc3fbc45 203 }
5761d64b 204
f0ed4e69 205 hpet_reserve_msi_timers(&hd);
26afe5f2 206
e9e2cdb4 207 hpet_alloc(&hd);
5761d64b 208
e9e2cdb4
TG		 209}
210#else
5946fa3d 211static void hpet_reserve_platform_timers(unsigned int id) { }
e9e2cdb4
TG		 212#endif
213
214/*
215 * Common hpet info
216 */
217static unsigned long hpet_period;
218
610bf2f1 219static void hpet_legacy_set_mode(enum clock_event_mode mode,
e9e2cdb4 220 struct clock_event_device *evt);
610bf2f1 221static int hpet_legacy_next_event(unsigned long delta,
e9e2cdb4
TG		 222 struct clock_event_device *evt);
223
224/*
225 * The hpet clock event device
226 */
227static struct clock_event_device hpet_clockevent = {
228 .name = "hpet",
229 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
610bf2f1
VP		 230 .set_mode = hpet_legacy_set_mode,
231 .set_next_event = hpet_legacy_next_event,
e9e2cdb4
TG		 232 .shift = 32,
233 .irq = 0,
59c69f2a 234 .rating = 50,
e9e2cdb4
TG		 235};
236
8d6f0c82 237static void hpet_stop_counter(void)
e9e2cdb4
TG		 238{
239 unsigned long cfg = hpet_readl(HPET_CFG);
e9e2cdb4
TG		 240 cfg &= ~HPET_CFG_ENABLE;
241 hpet_writel(cfg, HPET_CFG);
7a6f9cbb
AH		 242}
243
244static void hpet_reset_counter(void)
245{
e9e2cdb4
TG		 246 hpet_writel(0, HPET_COUNTER);
247 hpet_writel(0, HPET_COUNTER + 4);
8d6f0c82
AH		 248}
249
250static void hpet_start_counter(void)
251{
5946fa3d 252 unsigned int cfg = hpet_readl(HPET_CFG);
e9e2cdb4
TG		 253 cfg |= HPET_CFG_ENABLE;
254 hpet_writel(cfg, HPET_CFG);
255}
256
8d6f0c82
AH		 257static void hpet_restart_counter(void)
258{
259 hpet_stop_counter();
7a6f9cbb 260 hpet_reset_counter();
8d6f0c82
AH		 261 hpet_start_counter();
262}
263
59c69f2a
VP		 264static void hpet_resume_device(void)
265{
bfe0c1cc 266 force_hpet_resume();
59c69f2a
VP		 267}
268
17622339 269static void hpet_resume_counter(struct clocksource *cs)
59c69f2a
VP		 270{
271 hpet_resume_device();
8d6f0c82 272 hpet_restart_counter();
59c69f2a
VP		 273}
274
610bf2f1 275static void hpet_enable_legacy_int(void)
e9e2cdb4 276{
5946fa3d 277 unsigned int cfg = hpet_readl(HPET_CFG);
e9e2cdb4
TG		 278
279 cfg |= HPET_CFG_LEGACY;
280 hpet_writel(cfg, HPET_CFG);
281 hpet_legacy_int_enabled = 1;
282}
283
610bf2f1
VP		 284static void hpet_legacy_clockevent_register(void)
285{
610bf2f1
VP		 286 /* Start HPET legacy interrupts */
287 hpet_enable_legacy_int();
288
289 /*
6fd592da
CM		 290 * The mult factor is defined as (include/linux/clockchips.h)
291 * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
292 * hpet_period is in units of femtoseconds (per cycle), so
293 * mult/2^shift = cyc/ns = 10^6/hpet_period
294 * mult = (10^6 * 2^shift)/hpet_period
295 * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
610bf2f1 296 */
6fd592da
CM		 297 hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC,
298 hpet_period, hpet_clockevent.shift);
610bf2f1
VP		 299 /* Calculate the min / max delta */
300 hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
301 &hpet_clockevent);
7cfb0435
TG		 302 /* 5 usec minimum reprogramming delta. */
303 hpet_clockevent.min_delta_ns = 5000;
610bf2f1
VP		 304
305 /*
306 * Start hpet with the boot cpu mask and make it
307 * global after the IO_APIC has been initialized.
308 */
320ab2b0 309 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
610bf2f1
VP		 310 clockevents_register_device(&hpet_clockevent);
311 global_clock_event = &hpet_clockevent;
312 printk(KERN_DEBUG "hpet clockevent registered\n");
313}
314
26afe5f2 315static int hpet_setup_msi_irq(unsigned int irq);
316
b40d575b 317static void hpet_set_mode(enum clock_event_mode mode,
318 struct clock_event_device *evt, int timer)
e9e2cdb4 319{
5946fa3d 320 unsigned int cfg, cmp, now;
e9e2cdb4
TG		 321 uint64_t delta;
322
4588c1f0 323 switch (mode) {
e9e2cdb4 324 case CLOCK_EVT_MODE_PERIODIC:
c23e253e 325 hpet_stop_counter();
b40d575b 326 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
327 delta >>= evt->shift;
7a6f9cbb 328 now = hpet_readl(HPET_COUNTER);
5946fa3d 329 cmp = now + (unsigned int) delta;
b40d575b 330 cfg = hpet_readl(HPET_Tn_CFG(timer));
b13e2464
JS		 331 /* Make sure we use edge triggered interrupts */
332 cfg &= ~HPET_TN_LEVEL;
e9e2cdb4
TG		 333 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
334 HPET_TN_SETVAL | HPET_TN_32BIT;
b40d575b 335 hpet_writel(cfg, HPET_Tn_CFG(timer));
7a6f9cbb
AH		 336 hpet_writel(cmp, HPET_Tn_CMP(timer));
337 udelay(1);
338 /*
339 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
340 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
341 * bit is automatically cleared after the first write.
342 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
343 * Publication # 24674)
344 */
5946fa3d 345 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
c23e253e 346 hpet_start_counter();
b98103a5 347 hpet_print_config();
e9e2cdb4
TG		 348 break;
349
350 case CLOCK_EVT_MODE_ONESHOT:
b40d575b 351 cfg = hpet_readl(HPET_Tn_CFG(timer));
e9e2cdb4
TG		 352 cfg &= ~HPET_TN_PERIODIC;
353 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
b40d575b 354 hpet_writel(cfg, HPET_Tn_CFG(timer));
e9e2cdb4
TG		 355 break;
356
357 case CLOCK_EVT_MODE_UNUSED:
358 case CLOCK_EVT_MODE_SHUTDOWN:
b40d575b 359 cfg = hpet_readl(HPET_Tn_CFG(timer));
e9e2cdb4 360 cfg &= ~HPET_TN_ENABLE;
b40d575b 361 hpet_writel(cfg, HPET_Tn_CFG(timer));
e9e2cdb4 362 break;
18de5bc4
TG		 363
364 case CLOCK_EVT_MODE_RESUME:
26afe5f2 365 if (timer == 0) {
366 hpet_enable_legacy_int();
367 } else {
368 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
369 hpet_setup_msi_irq(hdev->irq);
370 disable_irq(hdev->irq);
0de26520 371 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
26afe5f2 372 enable_irq(hdev->irq);
373 }
b98103a5 374 hpet_print_config();
18de5bc4 375 break;
e9e2cdb4
TG		 376 }
377}
378
b40d575b 379static int hpet_next_event(unsigned long delta,
380 struct clock_event_device *evt, int timer)
e9e2cdb4 381{
f7676254 382 u32 cnt;
995bd3bb 383 s32 res;
e9e2cdb4
TG		 384
385 cnt = hpet_readl(HPET_COUNTER);
f7676254 386 cnt += (u32) delta;
b40d575b 387 hpet_writel(cnt, HPET_Tn_CMP(timer));
e9e2cdb4 388
72d43d9b 389 /*
995bd3bb
TG		 390 * HPETs are a complete disaster. The compare register is
391 * based on a equal comparison and neither provides a less
392 * than or equal functionality (which would require to take
393 * the wraparound into account) nor a simple count down event
394 * mode. Further the write to the comparator register is
395 * delayed internally up to two HPET clock cycles in certain
396 * chipsets (ATI, ICH9,10). We worked around that by reading
397 * back the compare register, but that required another
398 * workaround for ICH9,10 chips where the first readout after
399 * write can return the old stale value. We already have a
400 * minimum delta of 5us enforced, but a NMI or SMI hitting
401 * between the counter readout and the comparator write can
402 * move us behind that point easily. Now instead of reading
403 * the compare register back several times, we make the ETIME
404 * decision based on the following: Return ETIME if the
405 * counter value after the write is less than 8 HPET cycles
406 * away from the event or if the counter is already ahead of
407 * the event.
72d43d9b 408 */
995bd3bb 409 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
72d43d9b 410
995bd3bb 411 return res < 8 ? -ETIME : 0;
e9e2cdb4
TG		 412}
413
b40d575b 414static void hpet_legacy_set_mode(enum clock_event_mode mode,
415 struct clock_event_device *evt)
416{
417 hpet_set_mode(mode, evt, 0);
418}
419
420static int hpet_legacy_next_event(unsigned long delta,
421 struct clock_event_device *evt)
422{
423 return hpet_next_event(delta, evt, 0);
424}
425
58ac1e76 426/*
427 * HPET MSI Support
428 */
26afe5f2 429#ifdef CONFIG_PCI_MSI
5f79f2f2
VP		 430
431static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
432static struct hpet_dev *hpet_devs;
433
d0fbca8f 434void hpet_msi_unmask(struct irq_data *data)
58ac1e76 435{
d0fbca8f 436 struct hpet_dev *hdev = data->handler_data;
5946fa3d 437 unsigned int cfg;
58ac1e76 438
439 /* unmask it */
440 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
441 cfg |= HPET_TN_FSB;
442 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
443}
444
d0fbca8f 445void hpet_msi_mask(struct irq_data *data)
58ac1e76 446{
d0fbca8f 447 struct hpet_dev *hdev = data->handler_data;
5946fa3d 448 unsigned int cfg;
58ac1e76 449
450 /* mask it */
451 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
452 cfg &= ~HPET_TN_FSB;
453 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
454}
455
d0fbca8f 456void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
58ac1e76 457{
58ac1e76 458 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
459 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
460}
461
d0fbca8f 462void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
58ac1e76 463{
58ac1e76 464 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
465 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
466 msg->address_hi = 0;
467}
468
26afe5f2 469static void hpet_msi_set_mode(enum clock_event_mode mode,
470 struct clock_event_device *evt)
471{
472 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
473 hpet_set_mode(mode, evt, hdev->num);
474}
475
476static int hpet_msi_next_event(unsigned long delta,
477 struct clock_event_device *evt)
478{
479 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
480 return hpet_next_event(delta, evt, hdev->num);
481}
482
483static int hpet_setup_msi_irq(unsigned int irq)
484{
c8bc6f3c 485 if (arch_setup_hpet_msi(irq, hpet_blockid)) {
26afe5f2 486 destroy_irq(irq);
487 return -EINVAL;
488 }
489 return 0;
490}
491
492static int hpet_assign_irq(struct hpet_dev *dev)
493{
494 unsigned int irq;
495
02198962 496 irq = create_irq_nr(0, -1);
26afe5f2 497 if (!irq)
498 return -EINVAL;
499
500 set_irq_data(irq, dev);
501
502 if (hpet_setup_msi_irq(irq))
503 return -EINVAL;
504
505 dev->irq = irq;
506 return 0;
507}
508
509static irqreturn_t hpet_interrupt_handler(int irq, void *data)
510{
511 struct hpet_dev *dev = (struct hpet_dev *)data;
512 struct clock_event_device *hevt = &dev->evt;
513
514 if (!hevt->event_handler) {
515 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
516 dev->num);
517 return IRQ_HANDLED;
518 }
519
520 hevt->event_handler(hevt);
521 return IRQ_HANDLED;
522}
523
524static int hpet_setup_irq(struct hpet_dev *dev)
525{
526
527 if (request_irq(dev->irq, hpet_interrupt_handler,
507fa3a3
TG		 528 IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
529 dev->name, dev))
26afe5f2 530 return -1;
531
532 disable_irq(dev->irq);
0de26520 533 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
26afe5f2 534 enable_irq(dev->irq);
535
c81bba49
YL		 536 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
537 dev->name, dev->irq);
538
26afe5f2 539 return 0;
540}
541
542/* This should be called in specific @cpu */
543static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
544{
545 struct clock_event_device *evt = &hdev->evt;
546 uint64_t hpet_freq;
547
548 WARN_ON(cpu != smp_processor_id());
549 if (!(hdev->flags & HPET_DEV_VALID))
550 return;
551
552 if (hpet_setup_msi_irq(hdev->irq))
553 return;
554
555 hdev->cpu = cpu;
556 per_cpu(cpu_hpet_dev, cpu) = hdev;
557 evt->name = hdev->name;
558 hpet_setup_irq(hdev);
559 evt->irq = hdev->irq;
560
561 evt->rating = 110;
562 evt->features = CLOCK_EVT_FEAT_ONESHOT;
563 if (hdev->flags & HPET_DEV_PERI_CAP)
564 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
565
566 evt->set_mode = hpet_msi_set_mode;
567 evt->set_next_event = hpet_msi_next_event;
568 evt->shift = 32;
569
570 /*
571 * The period is a femto seconds value. We need to calculate the
572 * scaled math multiplication factor for nanosecond to hpet tick
573 * conversion.
574 */
4936a3b9 575 hpet_freq = FSEC_PER_SEC;
26afe5f2 576 do_div(hpet_freq, hpet_period);
577 evt->mult = div_sc((unsigned long) hpet_freq,
578 NSEC_PER_SEC, evt->shift);
579 /* Calculate the max delta */
580 evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt);
581 /* 5 usec minimum reprogramming delta. */
582 evt->min_delta_ns = 5000;
583
320ab2b0 584 evt->cpumask = cpumask_of(hdev->cpu);
26afe5f2 585 clockevents_register_device(evt);
586}
587
588#ifdef CONFIG_HPET
589/* Reserve at least one timer for userspace (/dev/hpet) */
590#define RESERVE_TIMERS 1
591#else
592#define RESERVE_TIMERS 0
593#endif
5f79f2f2
VP		 594
595static void hpet_msi_capability_lookup(unsigned int start_timer)
26afe5f2 596{
597 unsigned int id;
598 unsigned int num_timers;
599 unsigned int num_timers_used = 0;
600 int i;
601
73472a46
PV		 602 if (hpet_msi_disable)
603 return;
604
39fe05e5
SL		 605 if (boot_cpu_has(X86_FEATURE_ARAT))
606 return;
26afe5f2 607 id = hpet_readl(HPET_ID);
608
609 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
610 num_timers++; /* Value read out starts from 0 */
b98103a5 611 hpet_print_config();
26afe5f2 612
613 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
614 if (!hpet_devs)
615 return;
616
617 hpet_num_timers = num_timers;
618
619 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
620 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
5946fa3d 621 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
26afe5f2 622
623 /* Only consider HPET timer with MSI support */
624 if (!(cfg & HPET_TN_FSB_CAP))
625 continue;
626
627 hdev->flags = 0;
628 if (cfg & HPET_TN_PERIODIC_CAP)
629 hdev->flags |= HPET_DEV_PERI_CAP;
630 hdev->num = i;
631
632 sprintf(hdev->name, "hpet%d", i);
633 if (hpet_assign_irq(hdev))
634 continue;
635
636 hdev->flags |= HPET_DEV_FSB_CAP;
637 hdev->flags |= HPET_DEV_VALID;
638 num_timers_used++;
639 if (num_timers_used == num_possible_cpus())
640 break;
641 }
642
643 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
644 num_timers, num_timers_used);
645}
646
5f79f2f2
VP		 647#ifdef CONFIG_HPET
648static void hpet_reserve_msi_timers(struct hpet_data *hd)
649{
650 int i;
651
652 if (!hpet_devs)
653 return;
654
655 for (i = 0; i < hpet_num_timers; i++) {
656 struct hpet_dev *hdev = &hpet_devs[i];
657
658 if (!(hdev->flags & HPET_DEV_VALID))
659 continue;
660
661 hd->hd_irq[hdev->num] = hdev->irq;
662 hpet_reserve_timer(hd, hdev->num);
663 }
664}
665#endif
666
26afe5f2 667static struct hpet_dev *hpet_get_unused_timer(void)
668{
669 int i;
670
671 if (!hpet_devs)
672 return NULL;
673
674 for (i = 0; i < hpet_num_timers; i++) {
675 struct hpet_dev *hdev = &hpet_devs[i];
676
677 if (!(hdev->flags & HPET_DEV_VALID))
678 continue;
679 if (test_and_set_bit(HPET_DEV_USED_BIT,
680 (unsigned long *)&hdev->flags))
681 continue;
682 return hdev;
683 }
684 return NULL;
685}
686
687struct hpet_work_struct {
688 struct delayed_work work;
689 struct completion complete;
690};
691
692static void hpet_work(struct work_struct *w)
693{
694 struct hpet_dev *hdev;
695 int cpu = smp_processor_id();
696 struct hpet_work_struct *hpet_work;
697
698 hpet_work = container_of(w, struct hpet_work_struct, work.work);
699
700 hdev = hpet_get_unused_timer();
701 if (hdev)
702 init_one_hpet_msi_clockevent(hdev, cpu);
703
704 complete(&hpet_work->complete);
705}
706
707static int hpet_cpuhp_notify(struct notifier_block *n,
708 unsigned long action, void *hcpu)
709{
710 unsigned long cpu = (unsigned long)hcpu;
711 struct hpet_work_struct work;
712 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
713
714 switch (action & 0xf) {
715 case CPU_ONLINE:
ca1cab37 716 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
26afe5f2 717 init_completion(&work.complete);
718 /* FIXME: add schedule_work_on() */
719 schedule_delayed_work_on(cpu, &work.work, 0);
720 wait_for_completion(&work.complete);
336f6c32 721 destroy_timer_on_stack(&work.work.timer);
26afe5f2 722 break;
723 case CPU_DEAD:
724 if (hdev) {
725 free_irq(hdev->irq, hdev);
726 hdev->flags &= ~HPET_DEV_USED;
727 per_cpu(cpu_hpet_dev, cpu) = NULL;
728 }
729 break;
730 }
731 return NOTIFY_OK;
732}
733#else
734
ba374c9b
SN		 735static int hpet_setup_msi_irq(unsigned int irq)
736{
737 return 0;
738}
5f79f2f2
VP		 739static void hpet_msi_capability_lookup(unsigned int start_timer)
740{
741 return;
742}
743
744#ifdef CONFIG_HPET
745static void hpet_reserve_msi_timers(struct hpet_data *hd)
26afe5f2 746{
747 return;
748}
5f79f2f2 749#endif
26afe5f2 750
751static int hpet_cpuhp_notify(struct notifier_block *n,
752 unsigned long action, void *hcpu)
753{
754 return NOTIFY_OK;
755}
756
757#endif
758
6bb74df4
JS		 759/*
760 * Clock source related code
761 */
8e19608e 762static cycle_t read_hpet(struct clocksource *cs)
6bb74df4
JS		 763{
764 return (cycle_t)hpet_readl(HPET_COUNTER);
765}
766
28769149
TG		 767#ifdef CONFIG_X86_64
768static cycle_t __vsyscall_fn vread_hpet(void)
769{
770 return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
771}
772#endif
773
6bb74df4
JS		 774static struct clocksource clocksource_hpet = {
775 .name = "hpet",
776 .rating = 250,
777 .read = read_hpet,
778 .mask = HPET_MASK,
6bb74df4 779 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
8d6f0c82 780 .resume = hpet_resume_counter,
28769149
TG		 781#ifdef CONFIG_X86_64
782 .vread = vread_hpet,
783#endif
6bb74df4
JS		 784};
785
610bf2f1 786static int hpet_clocksource_register(void)
e9e2cdb4 787{
6fd592da 788 u64 start, now;
f12a15be 789 u64 hpet_freq;
075bcd1f 790 cycle_t t1;
e9e2cdb4 791
e9e2cdb4 792 /* Start the counter */
8d6f0c82 793 hpet_restart_counter();
e9e2cdb4 794
075bcd1f 795 /* Verify whether hpet counter works */
8e19608e 796 t1 = hpet_readl(HPET_COUNTER);
075bcd1f
TG		 797 rdtscll(start);
798
799 /*
800 * We don't know the TSC frequency yet, but waiting for
801 * 200000 TSC cycles is safe:
802 * 4 GHz == 50us
803 * 1 GHz == 200us
804 */
805 do {
806 rep_nop();
807 rdtscll(now);
808 } while ((now - start) < 200000UL);
809
8e19608e 810 if (t1 == hpet_readl(HPET_COUNTER)) {
075bcd1f
TG		 811 printk(KERN_WARNING
812 "HPET counter not counting. HPET disabled\n");
610bf2f1 813 return -ENODEV;
075bcd1f
TG		 814 }
815
6fd592da
CM		 816 /*
817 * The definition of mult is (include/linux/clocksource.h)
818 * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
819 * so we first need to convert hpet_period to ns/cyc units:
820 * mult/2^shift = ns/cyc = hpet_period/10^6
821 * mult = (hpet_period * 2^shift)/10^6
822 * mult = (hpet_period << shift)/FSEC_PER_NSEC
6bb74df4 823 */
6bb74df4 824
f12a15be
JS		 825 /* Need to convert hpet_period (fsec/cyc) to cyc/sec:
826 *
827 * cyc/sec = FSEC_PER_SEC/hpet_period(fsec/cyc)
828 * cyc/sec = (FSEC_PER_NSEC * NSEC_PER_SEC)/hpet_period
829 */
4936a3b9 830 hpet_freq = FSEC_PER_SEC;
f12a15be
JS		 831 do_div(hpet_freq, hpet_period);
832 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
6bb74df4 833
610bf2f1
VP		 834 return 0;
835}
836
b02a7f22
PM		 837/**
838 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
610bf2f1
VP		 839 */
840int __init hpet_enable(void)
841{
5946fa3d 842 unsigned int id;
a6825f1c 843 int i;
610bf2f1
VP		 844
845 if (!is_hpet_capable())
846 return 0;
847
848 hpet_set_mapping();
849
850 /*
851 * Read the period and check for a sane value:
852 */
853 hpet_period = hpet_readl(HPET_PERIOD);
a6825f1c
TG		 854
855 /*
856 * AMD SB700 based systems with spread spectrum enabled use a
857 * SMM based HPET emulation to provide proper frequency
858 * setting. The SMM code is initialized with the first HPET
859 * register access and takes some time to complete. During
860 * this time the config register reads 0xffffffff. We check
861 * for max. 1000 loops whether the config register reads a non
862 * 0xffffffff value to make sure that HPET is up and running
863 * before we go further. A counting loop is safe, as the HPET
864 * access takes thousands of CPU cycles. On non SB700 based
865 * machines this check is only done once and has no side
866 * effects.
867 */
868 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
869 if (i == 1000) {
870 printk(KERN_WARNING
871 "HPET config register value = 0xFFFFFFFF. "
872 "Disabling HPET\n");
873 goto out_nohpet;
874 }
875 }
876
610bf2f1
VP		 877 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
878 goto out_nohpet;
879
880 /*
881 * Read the HPET ID register to retrieve the IRQ routing
882 * information and the number of channels
883 */
884 id = hpet_readl(HPET_ID);
b98103a5 885 hpet_print_config();
610bf2f1
VP		 886
887#ifdef CONFIG_HPET_EMULATE_RTC
888 /*
889 * The legacy routing mode needs at least two channels, tick timer
890 * and the rtc emulation channel.
891 */
892 if (!(id & HPET_ID_NUMBER))
893 goto out_nohpet;
894#endif
895
896 if (hpet_clocksource_register())
897 goto out_nohpet;
898
e9e2cdb4 899 if (id & HPET_ID_LEGSUP) {
610bf2f1 900 hpet_legacy_clockevent_register();
e9e2cdb4
TG		 901 return 1;
902 }
903 return 0;
5d0cf410 904
e9e2cdb4 905out_nohpet:
06a24dec 906 hpet_clear_mapping();
bacbe999 907 hpet_address = 0;
e9e2cdb4
TG		 908 return 0;
909}
910
28769149
TG		 911/*
912 * Needs to be late, as the reserve_timer code calls kalloc !
913 *
914 * Not a problem on i386 as hpet_enable is called from late_time_init,
915 * but on x86_64 it is necessary !
916 */
917static __init int hpet_late_init(void)
918{
26afe5f2 919 int cpu;
920
59c69f2a 921 if (boot_hpet_disable)
28769149
TG		 922 return -ENODEV;
923
59c69f2a
VP		 924 if (!hpet_address) {
925 if (!force_hpet_address)
926 return -ENODEV;
927
928 hpet_address = force_hpet_address;
929 hpet_enable();
59c69f2a
VP		 930 }
931
39c04b55
JF		 932 if (!hpet_virt_address)
933 return -ENODEV;
934
39fe05e5
SL		 935 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
936 hpet_msi_capability_lookup(2);
937 else
938 hpet_msi_capability_lookup(0);
939
28769149 940 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
b98103a5 941 hpet_print_config();
59c69f2a 942
73472a46
PV		 943 if (hpet_msi_disable)
944 return 0;
945
39fe05e5
SL		 946 if (boot_cpu_has(X86_FEATURE_ARAT))
947 return 0;
948
26afe5f2 949 for_each_online_cpu(cpu) {
950 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
951 }
952
953 /* This notifier should be called after workqueue is ready */
954 hotcpu_notifier(hpet_cpuhp_notify, -20);
955
28769149
TG		 956 return 0;
957}
958fs_initcall(hpet_late_init);
959
c86c7fbc
OH		 960void hpet_disable(void)
961{
ff487808 962 if (is_hpet_capable() && hpet_virt_address) {
5946fa3d 963 unsigned int cfg = hpet_readl(HPET_CFG);
c86c7fbc
OH		 964
965 if (hpet_legacy_int_enabled) {
966 cfg &= ~HPET_CFG_LEGACY;
967 hpet_legacy_int_enabled = 0;
968 }
969 cfg &= ~HPET_CFG_ENABLE;
970 hpet_writel(cfg, HPET_CFG);
971 }
972}
973
e9e2cdb4
TG		 974#ifdef CONFIG_HPET_EMULATE_RTC
975
976/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
977 * is enabled, we support RTC interrupt functionality in software.
978 * RTC has 3 kinds of interrupts:
979 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
980 * is updated
981 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
982 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
983 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
984 * (1) and (2) above are implemented using polling at a frequency of
985 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
986 * overhead. (DEFAULT_RTC_INT_FREQ)
987 * For (3), we use interrupts at 64Hz or user specified periodic
988 * frequency, whichever is higher.
989 */
990#include <linux/mc146818rtc.h>
991#include <linux/rtc.h>
1bdbdaac 992#include <asm/rtc.h>
e9e2cdb4
TG		 993
994#define DEFAULT_RTC_INT_FREQ 64
995#define DEFAULT_RTC_SHIFT 6
996#define RTC_NUM_INTS 1
997
998static unsigned long hpet_rtc_flags;
7e2a31da 999static int hpet_prev_update_sec;
e9e2cdb4
TG		 1000static struct rtc_time hpet_alarm_time;
1001static unsigned long hpet_pie_count;
ff08f76d 1002static u32 hpet_t1_cmp;
5946fa3d
JB		 1003static u32 hpet_default_delta;
1004static u32 hpet_pie_delta;
e9e2cdb4
TG		 1005static unsigned long hpet_pie_limit;
1006
1bdbdaac
BW		 1007static rtc_irq_handler irq_handler;
1008
ff08f76d
PE		 1009/*
1010 * Check that the hpet counter c1 is ahead of the c2
1011 */
1012static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1013{
1014 return (s32)(c2 - c1) < 0;
1015}
1016
1bdbdaac
BW		 1017/*
1018 * Registers a IRQ handler.
1019 */
1020int hpet_register_irq_handler(rtc_irq_handler handler)
1021{
1022 if (!is_hpet_enabled())
1023 return -ENODEV;
1024 if (irq_handler)
1025 return -EBUSY;
1026
1027 irq_handler = handler;
1028
1029 return 0;
1030}
1031EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1032
1033/*
1034 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1035 * and does cleanup.
1036 */
1037void hpet_unregister_irq_handler(rtc_irq_handler handler)
1038{
1039 if (!is_hpet_enabled())
1040 return;
1041
1042 irq_handler = NULL;
1043 hpet_rtc_flags = 0;
1044}
1045EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1046
e9e2cdb4
TG		 1047/*
1048 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1049 * is not supported by all HPET implementations for timer 1.
1050 *
1051 * hpet_rtc_timer_init() is called when the rtc is initialized.
1052 */
1053int hpet_rtc_timer_init(void)
1054{
5946fa3d
JB		 1055 unsigned int cfg, cnt, delta;
1056 unsigned long flags;
e9e2cdb4
TG		 1057
1058 if (!is_hpet_enabled())
1059 return 0;
1060
1061 if (!hpet_default_delta) {
1062 uint64_t clc;
1063
1064 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1065 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
5946fa3d 1066 hpet_default_delta = clc;
e9e2cdb4
TG		 1067 }
1068
1069 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1070 delta = hpet_default_delta;
1071 else
1072 delta = hpet_pie_delta;
1073
1074 local_irq_save(flags);
1075
1076 cnt = delta + hpet_readl(HPET_COUNTER);
1077 hpet_writel(cnt, HPET_T1_CMP);
1078 hpet_t1_cmp = cnt;
1079
1080 cfg = hpet_readl(HPET_T1_CFG);
1081 cfg &= ~HPET_TN_PERIODIC;
1082 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1083 hpet_writel(cfg, HPET_T1_CFG);
1084
1085 local_irq_restore(flags);
1086
1087 return 1;
1088}
1bdbdaac 1089EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
e9e2cdb4
TG		 1090
1091/*
1092 * The functions below are called from rtc driver.
1093 * Return 0 if HPET is not being used.
1094 * Otherwise do the necessary changes and return 1.
1095 */
1096int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1097{
1098 if (!is_hpet_enabled())
1099 return 0;
1100
1101 hpet_rtc_flags &= ~bit_mask;
1102 return 1;
1103}
1bdbdaac 1104EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
e9e2cdb4
TG		 1105
1106int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1107{
1108 unsigned long oldbits = hpet_rtc_flags;
1109
1110 if (!is_hpet_enabled())
1111 return 0;
1112
1113 hpet_rtc_flags |= bit_mask;
1114
7e2a31da
DB		 1115 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1116 hpet_prev_update_sec = -1;
1117
e9e2cdb4
TG		 1118 if (!oldbits)
1119 hpet_rtc_timer_init();
1120
1121 return 1;
1122}
1bdbdaac 1123EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
e9e2cdb4
TG		 1124
1125int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1126 unsigned char sec)
1127{
1128 if (!is_hpet_enabled())
1129 return 0;
1130
1131 hpet_alarm_time.tm_hour = hrs;
1132 hpet_alarm_time.tm_min = min;
1133 hpet_alarm_time.tm_sec = sec;
1134
1135 return 1;
1136}
1bdbdaac 1137EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
e9e2cdb4
TG		 1138
1139int hpet_set_periodic_freq(unsigned long freq)
1140{
1141 uint64_t clc;
1142
1143 if (!is_hpet_enabled())
1144 return 0;
1145
1146 if (freq <= DEFAULT_RTC_INT_FREQ)
1147 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1148 else {
1149 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1150 do_div(clc, freq);
1151 clc >>= hpet_clockevent.shift;
5946fa3d 1152 hpet_pie_delta = clc;
b4a5e8a1 1153 hpet_pie_limit = 0;
e9e2cdb4
TG		 1154 }
1155 return 1;
1156}
1bdbdaac 1157EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
e9e2cdb4
TG		 1158
1159int hpet_rtc_dropped_irq(void)
1160{
1161 return is_hpet_enabled();
1162}
1bdbdaac 1163EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
e9e2cdb4
TG		 1164
1165static void hpet_rtc_timer_reinit(void)
1166{
5946fa3d 1167 unsigned int cfg, delta;
e9e2cdb4
TG		 1168 int lost_ints = -1;
1169
1170 if (unlikely(!hpet_rtc_flags)) {
1171 cfg = hpet_readl(HPET_T1_CFG);
1172 cfg &= ~HPET_TN_ENABLE;
1173 hpet_writel(cfg, HPET_T1_CFG);
1174 return;
1175 }
1176
1177 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1178 delta = hpet_default_delta;
1179 else
1180 delta = hpet_pie_delta;
1181
1182 /*
1183 * Increment the comparator value until we are ahead of the
1184 * current count.
1185 */
1186 do {
1187 hpet_t1_cmp += delta;
1188 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1189 lost_ints++;
ff08f76d 1190 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
e9e2cdb4
TG		 1191
1192 if (lost_ints) {
1193 if (hpet_rtc_flags & RTC_PIE)
1194 hpet_pie_count += lost_ints;
1195 if (printk_ratelimit())
7e2a31da 1196 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
e9e2cdb4
TG		 1197 lost_ints);
1198 }
1199}
1200
1201irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1202{
1203 struct rtc_time curr_time;
1204 unsigned long rtc_int_flag = 0;
1205
1206 hpet_rtc_timer_reinit();
1bdbdaac 1207 memset(&curr_time, 0, sizeof(struct rtc_time));
e9e2cdb4
TG		 1208
1209 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1bdbdaac 1210 get_rtc_time(&curr_time);
e9e2cdb4
TG		 1211
1212 if (hpet_rtc_flags & RTC_UIE &&
1213 curr_time.tm_sec != hpet_prev_update_sec) {
7e2a31da
DB		 1214 if (hpet_prev_update_sec >= 0)
1215 rtc_int_flag = RTC_UF;
e9e2cdb4
TG		 1216 hpet_prev_update_sec = curr_time.tm_sec;
1217 }
1218
1219 if (hpet_rtc_flags & RTC_PIE &&
1220 ++hpet_pie_count >= hpet_pie_limit) {
1221 rtc_int_flag |= RTC_PF;
1222 hpet_pie_count = 0;
1223 }
1224
8ee291f8 1225 if (hpet_rtc_flags & RTC_AIE &&
e9e2cdb4
TG		 1226 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1227 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1228 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1229 rtc_int_flag |= RTC_AF;
1230
1231 if (rtc_int_flag) {
1232 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1bdbdaac
BW		 1233 if (irq_handler)
1234 irq_handler(rtc_int_flag, dev_id);
e9e2cdb4
TG		 1235 }
1236 return IRQ_HANDLED;
1237}
1bdbdaac 1238EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
e9e2cdb4 1239#endif
kernel source for telekom puls (alcatel/mediatek)