[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kernel / cpu / perf_event.h

/*
 * Performance events x86 architecture header
 *
 *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
 *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
 *  Copyright (C) 2009 Jaswinder Singh Rajput
 *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
 *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
 *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
 *  Copyright (C) 2009 Google, Inc., Stephane Eranian
 *
 *  For licencing details see kernel-base/COPYING
 */

#include <linux/perf_event.h>

/*
 *          |   NHM/WSM    |      SNB     |
 * register -------------------------------
 *          |  HT  | no HT |  HT  | no HT |
 *-----------------------------------------
 * offcore  | core | core  | cpu  | core  |
 * lbr_sel  | core | core  | cpu  | core  |
 * ld_lat   | cpu  | core  | cpu  | core  |
 *-----------------------------------------
 *
 * Given that there is a small number of shared regs,
 * we can pre-allocate their slot in the per-cpu
 * per-core reg tables.
 */
enum extra_reg_type {
	EXTRA_REG_NONE  = -1,	/* not used */

	EXTRA_REG_RSP_0 = 0,	/* offcore_response_0 */
	EXTRA_REG_RSP_1 = 1,	/* offcore_response_1 */

	EXTRA_REG_MAX		/* number of entries needed */
};

struct event_constraint {
	union {
		unsigned long	idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
		u64		idxmsk64;
	};
	u64	code;
	u64	cmask;
	int	weight;
	int	overlap;
};

struct amd_nb {
	int nb_id;  /* NorthBridge id */
	int refcnt; /* reference count */
	struct perf_event *owners[X86_PMC_IDX_MAX];
	struct event_constraint event_constraints[X86_PMC_IDX_MAX];
};

/* The maximal number of PEBS events: */
#define MAX_PEBS_EVENTS		4

/*
 * A debug store configuration.
 *
 * We only support architectures that use 64bit fields.
 */
struct debug_store {
	u64	bts_buffer_base;
	u64	bts_index;
	u64	bts_absolute_maximum;
	u64	bts_interrupt_threshold;
	u64	pebs_buffer_base;
	u64	pebs_index;
	u64	pebs_absolute_maximum;
	u64	pebs_interrupt_threshold;
	u64	pebs_event_reset[MAX_PEBS_EVENTS];
};

/*
 * Per register state.
 */
struct er_account {
	raw_spinlock_t		lock;	/* per-core: protect structure */
	u64                 config;	/* extra MSR config */
	u64                 reg;	/* extra MSR number */
	atomic_t            ref;	/* reference count */
};

/*
 * Per core/cpu state
 *
 * Used to coordinate shared registers between HT threads or
 * among events on a single PMU.
 */
struct intel_shared_regs {
	struct er_account       regs[EXTRA_REG_MAX];
	int                     refcnt;		/* per-core: #HT threads */
	unsigned                core_id;	/* per-core: core id */
};

#define MAX_LBR_ENTRIES		16

struct cpu_hw_events {
	/*
	 * Generic x86 PMC bits
	 */
	struct perf_event	*events[X86_PMC_IDX_MAX]; /* in counter order */
	unsigned long		active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
	unsigned long		running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
	int			enabled;

	int			n_events;
	int			n_added;
	int			n_txn;
	int			assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
	u64			tags[X86_PMC_IDX_MAX];
	struct perf_event	*event_list[X86_PMC_IDX_MAX]; /* in enabled order */

	unsigned int		group_flag;

	/*
	 * Intel DebugStore bits
	 */
	struct debug_store	*ds;
	u64			pebs_enabled;

	/*
	 * Intel LBR bits
	 */
	int				lbr_users;
	void				*lbr_context;
	struct perf_branch_stack	lbr_stack;
	struct perf_branch_entry	lbr_entries[MAX_LBR_ENTRIES];

	/*
	 * Intel host/guest exclude bits
	 */
	u64				intel_ctrl_guest_mask;
	u64				intel_ctrl_host_mask;
	struct perf_guest_switch_msr	guest_switch_msrs[X86_PMC_IDX_MAX];

	/*
	 * manage shared (per-core, per-cpu) registers
	 * used on Intel NHM/WSM/SNB
	 */
	struct intel_shared_regs	*shared_regs;

	/*
	 * AMD specific bits
	 */
	struct amd_nb		*amd_nb;

	void				*kfree_on_online;
};

#define __EVENT_CONSTRAINT(c, n, m, w, o) {\
	{ .idxmsk64 = (n) },		\
	.code = (c),			\
	.cmask = (m),			\
	.weight = (w),			\
	.overlap = (o),			\
}

#define EVENT_CONSTRAINT(c, n, m)	\
	__EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0)

/*
 * The overlap flag marks event constraints with overlapping counter
 * masks. This is the case if the counter mask of such an event is not
 * a subset of any other counter mask of a constraint with an equal or
 * higher weight, e.g.:
 *
 *  c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
 *  c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
 *  c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
 *
 * The event scheduler may not select the correct counter in the first
 * cycle because it needs to know which subsequent events will be
 * scheduled. It may fail to schedule the events then. So we set the
 * overlap flag for such constraints to give the scheduler a hint which
 * events to select for counter rescheduling.
 *
 * Care must be taken as the rescheduling algorithm is O(n!) which
 * will increase scheduling cycles for an over-commited system
 * dramatically.  The number of such EVENT_CONSTRAINT_OVERLAP() macros
 * and its counter masks must be kept at a minimum.
 */
#define EVENT_CONSTRAINT_OVERLAP(c, n, m)	\
	__EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1)

/*
 * Constraint on the Event code.
 */
#define INTEL_EVENT_CONSTRAINT(c, n)	\
	EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)

/*
 * Constraint on the Event code + UMask + fixed-mask
 *
 * filter mask to validate fixed counter events.
 * the following filters disqualify for fixed counters:
 *  - inv
 *  - edge
 *  - cnt-mask
 *  The other filters are supported by fixed counters.
 *  The any-thread option is supported starting with v3.
 */
#define FIXED_EVENT_CONSTRAINT(c, n)	\
	EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)

/*
 * Constraint on the Event code + UMask
 */
#define INTEL_UEVENT_CONSTRAINT(c, n)	\
	EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)

#define EVENT_CONSTRAINT_END		\
	EVENT_CONSTRAINT(0, 0, 0)

#define for_each_event_constraint(e, c)	\
	for ((e) = (c); (e)->weight; (e)++)

/*
 * Extra registers for specific events.
 *
 * Some events need large masks and require external MSRs.
 * Those extra MSRs end up being shared for all events on
 * a PMU and sometimes between PMU of sibling HT threads.
 * In either case, the kernel needs to handle conflicting
 * accesses to those extra, shared, regs. The data structure
 * to manage those registers is stored in cpu_hw_event.
 */
struct extra_reg {
	unsigned int		event;
	unsigned int		msr;
	u64			config_mask;
	u64			valid_mask;
	int			idx;  /* per_xxx->regs[] reg index */
};

#define EVENT_EXTRA_REG(e, ms, m, vm, i) {	\
	.event = (e),		\
	.msr = (ms),		\
	.config_mask = (m),	\
	.valid_mask = (vm),	\
	.idx = EXTRA_REG_##i	\
	}

#define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx)	\
	EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)

#define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)

union perf_capabilities {
	struct {
		u64	lbr_format:6;
		u64	pebs_trap:1;
		u64	pebs_arch_reg:1;
		u64	pebs_format:4;
		u64	smm_freeze:1;
	};
	u64	capabilities;
};

/*
 * struct x86_pmu - generic x86 pmu
 */
struct x86_pmu {
	/*
	 * Generic x86 PMC bits
	 */
	const char	*name;
	int		version;
	int		(*handle_irq)(struct pt_regs *);
	void		(*disable_all)(void);
	void		(*enable_all)(int added);
	void		(*enable)(struct perf_event *);
	void		(*disable)(struct perf_event *);
	int		(*hw_config)(struct perf_event *event);
	int		(*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
	unsigned	eventsel;
	unsigned	perfctr;
	u64		(*event_map)(int);
	int		max_events;
	int		num_counters;
	int		num_counters_fixed;
	int		cntval_bits;
	u64		cntval_mask;
	union {
			unsigned long events_maskl;
			unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
	};
	int		events_mask_len;
	int		apic;
	u64		max_period;
	struct event_constraint *
			(*get_event_constraints)(struct cpu_hw_events *cpuc,
						 struct perf_event *event);

	void		(*put_event_constraints)(struct cpu_hw_events *cpuc,
						 struct perf_event *event);
	struct event_constraint *event_constraints;
	void		(*quirks)(void);
	int		perfctr_second_write;

	int		(*cpu_prepare)(int cpu);
	void		(*cpu_starting)(int cpu);
	void		(*cpu_dying)(int cpu);
	void		(*cpu_dead)(int cpu);

	/*
	 * Intel Arch Perfmon v2+
	 */
	u64			intel_ctrl;
	union perf_capabilities intel_cap;

	/*
	 * Intel DebugStore bits
	 */
	int		bts, pebs;
	int		bts_active, pebs_active;
	int		pebs_record_size;
	void		(*drain_pebs)(struct pt_regs *regs);
	struct event_constraint *pebs_constraints;

	/*
	 * Intel LBR
	 */
	unsigned long	lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
	int		lbr_nr;			   /* hardware stack size */

	/*
	 * Extra registers for events
	 */
	struct extra_reg *extra_regs;
	unsigned int er_flags;

	/*
	 * Intel host/guest support (KVM)
	 */
	struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
};

#define ERF_NO_HT_SHARING	1
#define ERF_HAS_RSP_1		2

extern struct x86_pmu x86_pmu __read_mostly;

DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);

int x86_perf_event_set_period(struct perf_event *event);

/*
 * Generalized hw caching related hw_event table, filled
 * in on a per model basis. A value of 0 means
 * 'not supported', -1 means 'hw_event makes no sense on
 * this CPU', any other value means the raw hw_event
 * ID.
 */

#define C(x) PERF_COUNT_HW_CACHE_##x

extern u64 __read_mostly hw_cache_event_ids
				[PERF_COUNT_HW_CACHE_MAX]
				[PERF_COUNT_HW_CACHE_OP_MAX]
				[PERF_COUNT_HW_CACHE_RESULT_MAX];
extern u64 __read_mostly hw_cache_extra_regs
				[PERF_COUNT_HW_CACHE_MAX]
				[PERF_COUNT_HW_CACHE_OP_MAX]
				[PERF_COUNT_HW_CACHE_RESULT_MAX];

u64 x86_perf_event_update(struct perf_event *event);

static inline int x86_pmu_addr_offset(int index)
{
	int offset;

	/* offset = X86_FEATURE_PERFCTR_CORE ? index << 1 : index */
	alternative_io(ASM_NOP2,
		       "shll $1, %%eax",
		       X86_FEATURE_PERFCTR_CORE,
		       "=a" (offset),
		       "a"  (index));

	return offset;
}

static inline unsigned int x86_pmu_config_addr(int index)
{
	return x86_pmu.eventsel + x86_pmu_addr_offset(index);
}

static inline unsigned int x86_pmu_event_addr(int index)
{
	return x86_pmu.perfctr + x86_pmu_addr_offset(index);
}

int x86_setup_perfctr(struct perf_event *event);

int x86_pmu_hw_config(struct perf_event *event);

void x86_pmu_disable_all(void);

static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
					  u64 enable_mask)
{
	if (hwc->extra_reg.reg)
		wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
	wrmsrl(hwc->config_base, hwc->config | enable_mask);
}

void x86_pmu_enable_all(int added);

int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);

void x86_pmu_stop(struct perf_event *event, int flags);

static inline void x86_pmu_disable_event(struct perf_event *event)
{
	struct hw_perf_event *hwc = &event->hw;

	wrmsrl(hwc->config_base, hwc->config);
}

void x86_pmu_enable_event(struct perf_event *event);

int x86_pmu_handle_irq(struct pt_regs *regs);

extern struct event_constraint emptyconstraint;

extern struct event_constraint unconstrained;

#ifdef CONFIG_CPU_SUP_AMD

int amd_pmu_init(void);

#else /* CONFIG_CPU_SUP_AMD */

static inline int amd_pmu_init(void)
{
	return 0;
}

#endif /* CONFIG_CPU_SUP_AMD */

#ifdef CONFIG_CPU_SUP_INTEL

int intel_pmu_save_and_restart(struct perf_event *event);

struct event_constraint *
x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event);

struct intel_shared_regs *allocate_shared_regs(int cpu);

int intel_pmu_init(void);

void init_debug_store_on_cpu(int cpu);

void fini_debug_store_on_cpu(int cpu);

void release_ds_buffers(void);

void reserve_ds_buffers(void);

extern struct event_constraint bts_constraint;

void intel_pmu_enable_bts(u64 config);

void intel_pmu_disable_bts(void);

int intel_pmu_drain_bts_buffer(void);

extern struct event_constraint intel_core2_pebs_event_constraints[];

extern struct event_constraint intel_atom_pebs_event_constraints[];

extern struct event_constraint intel_nehalem_pebs_event_constraints[];

extern struct event_constraint intel_westmere_pebs_event_constraints[];

extern struct event_constraint intel_snb_pebs_event_constraints[];

struct event_constraint *intel_pebs_constraints(struct perf_event *event);

void intel_pmu_pebs_enable(struct perf_event *event);

void intel_pmu_pebs_disable(struct perf_event *event);

void intel_pmu_pebs_enable_all(void);

void intel_pmu_pebs_disable_all(void);

void intel_ds_init(void);

void intel_pmu_lbr_reset(void);

void intel_pmu_lbr_enable(struct perf_event *event);

void intel_pmu_lbr_disable(struct perf_event *event);

void intel_pmu_lbr_enable_all(void);

void intel_pmu_lbr_disable_all(void);

void intel_pmu_lbr_read(void);

void intel_pmu_lbr_init_core(void);

void intel_pmu_lbr_init_nhm(void);

void intel_pmu_lbr_init_atom(void);

int p4_pmu_init(void);

int p6_pmu_init(void);

#else /* CONFIG_CPU_SUP_INTEL */

static inline void reserve_ds_buffers(void)
{
}

static inline void release_ds_buffers(void)
{
}

static inline int intel_pmu_init(void)
{
	return 0;
}

static inline struct intel_shared_regs *allocate_shared_regs(int cpu)
{
	return NULL;
}

#endif /* CONFIG_CPU_SUP_INTEL */
Commit	Line	Data
de0428a7 KW	1	/*
	2	* Performance events x86 architecture header
	3	*
	4	* Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
	5	* Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
	6	* Copyright (C) 2009 Jaswinder Singh Rajput
	7	* Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
	8	* Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
	9	* Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
	10	* Copyright (C) 2009 Google, Inc., Stephane Eranian
	11	*
	12	* For licencing details see kernel-base/COPYING
	13	*/
	14
	15	#include <linux/perf_event.h>
	16
	17	/*
	18	* \| NHM/WSM \| SNB \|
	19	* register -------------------------------
	20	* \| HT \| no HT \| HT \| no HT \|
	21	*-----------------------------------------
	22	* offcore \| core \| core \| cpu \| core \|
	23	* lbr_sel \| core \| core \| cpu \| core \|
	24	* ld_lat \| cpu \| core \| cpu \| core \|
	25	*-----------------------------------------
	26	*
	27	* Given that there is a small number of shared regs,
	28	* we can pre-allocate their slot in the per-cpu
	29	* per-core reg tables.
	30	*/
	31	enum extra_reg_type {
	32	EXTRA_REG_NONE = -1, /* not used */
	33
	34	EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
	35	EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
	36
	37	EXTRA_REG_MAX /* number of entries needed */
	38	};
	39
	40	struct event_constraint {
	41	union {
	42	unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
	43	u64 idxmsk64;
	44	};
	45	u64 code;
	46	u64 cmask;
	47	int weight;
bc1738f6	48	int overlap;
de0428a7 KW	49	};
	50
	51	struct amd_nb {
	52	int nb_id; /* NorthBridge id */
	53	int refcnt; /* reference count */
	54	struct perf_event *owners[X86_PMC_IDX_MAX];
	55	struct event_constraint event_constraints[X86_PMC_IDX_MAX];
	56	};
	57
	58	/* The maximal number of PEBS events: */
	59	#define MAX_PEBS_EVENTS 4
	60
	61	/*
	62	* A debug store configuration.
	63	*
	64	* We only support architectures that use 64bit fields.
	65	*/
	66	struct debug_store {
	67	u64 bts_buffer_base;
	68	u64 bts_index;
	69	u64 bts_absolute_maximum;
	70	u64 bts_interrupt_threshold;
	71	u64 pebs_buffer_base;
	72	u64 pebs_index;
	73	u64 pebs_absolute_maximum;
	74	u64 pebs_interrupt_threshold;
	75	u64 pebs_event_reset[MAX_PEBS_EVENTS];
	76	};
	77
	78	/*
	79	* Per register state.
	80	*/
	81	struct er_account {
	82	raw_spinlock_t lock; /* per-core: protect structure */
	83	u64 config; /* extra MSR config */
	84	u64 reg; /* extra MSR number */
	85	atomic_t ref; /* reference count */
	86	};
	87
	88	/*
	89	* Per core/cpu state
	90	*
	91	* Used to coordinate shared registers between HT threads or
	92	* among events on a single PMU.
	93	*/
	94	struct intel_shared_regs {
	95	struct er_account regs[EXTRA_REG_MAX];
	96	int refcnt; /* per-core: #HT threads */
	97	unsigned core_id; /* per-core: core id */
	98	};
	99
	100	#define MAX_LBR_ENTRIES 16
	101
	102	struct cpu_hw_events {
	103	/*
	104	* Generic x86 PMC bits
	105	*/
	106	struct perf_event events[X86_PMC_IDX_MAX]; / in counter order */
	107	unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
	108	unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
	109	int enabled;
	110
	111	int n_events;
	112	int n_added;
113	int n_txn;
114	int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
115	u64 tags[X86_PMC_IDX_MAX];
116	struct perf_event event_list[X86_PMC_IDX_MAX]; / in enabled order */
117
118	unsigned int group_flag;
119
120	/*
121	* Intel DebugStore bits
122	*/
123	struct debug_store *ds;
124	u64 pebs_enabled;
125
126	/*
127	* Intel LBR bits
128	*/
129	int lbr_users;
130	void *lbr_context;
131	struct perf_branch_stack lbr_stack;
132	struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
133
144d31e6 GN	134	/*
	135	* Intel host/guest exclude bits
	136	*/
	137	u64 intel_ctrl_guest_mask;
	138	u64 intel_ctrl_host_mask;
	139	struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
	140
de0428a7 KW	141	/*
	142	* manage shared (per-core, per-cpu) registers
	143	* used on Intel NHM/WSM/SNB
	144	*/
	145	struct intel_shared_regs *shared_regs;
	146
	147	/*
	148	* AMD specific bits
	149	*/
	150	struct amd_nb *amd_nb;
	151
	152	void *kfree_on_online;
	153	};
	154
bc1738f6	155	#define __EVENT_CONSTRAINT(c, n, m, w, o) {\
de0428a7 KW	156	{ .idxmsk64 = (n) }, \
	157	.code = (c), \
	158	.cmask = (m), \
	159	.weight = (w), \
bc1738f6	160	.overlap = (o), \
de0428a7 KW	161	}
	162
	163	#define EVENT_CONSTRAINT(c, n, m) \
bc1738f6 RR	164	__EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0)
	165
	166	/*
	167	* The overlap flag marks event constraints with overlapping counter
	168	* masks. This is the case if the counter mask of such an event is not
	169	* a subset of any other counter mask of a constraint with an equal or
	170	* higher weight, e.g.:
	171	*
	172	* c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
	173	* c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
	174	* c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
	175	*
	176	* The event scheduler may not select the correct counter in the first
	177	* cycle because it needs to know which subsequent events will be
	178	* scheduled. It may fail to schedule the events then. So we set the
	179	* overlap flag for such constraints to give the scheduler a hint which
	180	* events to select for counter rescheduling.
	181	*
	182	* Care must be taken as the rescheduling algorithm is O(n!) which
	183	* will increase scheduling cycles for an over-commited system
	184	* dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
	185	* and its counter masks must be kept at a minimum.
	186	*/
	187	#define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
	188	__EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1)
de0428a7 KW	189
	190	/*
	191	* Constraint on the Event code.
	192	*/
	193	#define INTEL_EVENT_CONSTRAINT(c, n) \
	194	EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
	195
	196	/*
	197	* Constraint on the Event code + UMask + fixed-mask
	198	*
	199	* filter mask to validate fixed counter events.
	200	* the following filters disqualify for fixed counters:
	201	* - inv
	202	* - edge
	203	* - cnt-mask
	204	* The other filters are supported by fixed counters.
	205	* The any-thread option is supported starting with v3.
	206	*/
	207	#define FIXED_EVENT_CONSTRAINT(c, n) \
	208	EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
	209
	210	/*
	211	* Constraint on the Event code + UMask
	212	*/
	213	#define INTEL_UEVENT_CONSTRAINT(c, n) \
	214	EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
	215
	216	#define EVENT_CONSTRAINT_END \
	217	EVENT_CONSTRAINT(0, 0, 0)
	218
	219	#define for_each_event_constraint(e, c) \
	220	for ((e) = (c); (e)->weight; (e)++)
	221
	222	/*
	223	* Extra registers for specific events.
	224	*
	225	* Some events need large masks and require external MSRs.
	226	* Those extra MSRs end up being shared for all events on
	227	* a PMU and sometimes between PMU of sibling HT threads.
	228	* In either case, the kernel needs to handle conflicting
	229	* accesses to those extra, shared, regs. The data structure
	230	* to manage those registers is stored in cpu_hw_event.
	231	*/
	232	struct extra_reg {
	233	unsigned int event;
	234	unsigned int msr;
	235	u64 config_mask;
	236	u64 valid_mask;
	237	int idx; /* per_xxx->regs[] reg index */
	238	};
	239
	240	#define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
	241	.event = (e), \
	242	.msr = (ms), \
	243	.config_mask = (m), \
	244	.valid_mask = (vm), \
	245	.idx = EXTRA_REG_##i \
	246	}
	247
	248	#define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
	249	EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
	250
	251	#define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
	252
253	union perf_capabilities {
254	struct {
255	u64 lbr_format:6;
256	u64 pebs_trap:1;
257	u64 pebs_arch_reg:1;
258	u64 pebs_format:4;
259	u64 smm_freeze:1;
260	};
261	u64 capabilities;
262	};
263
264	/*
265	* struct x86_pmu - generic x86 pmu
266	*/
267	struct x86_pmu {
268	/*
269	* Generic x86 PMC bits
270	*/
271	const char *name;
272	int version;
273	int (handle_irq)(struct pt_regs );
274	void (*disable_all)(void);
275	void (*enable_all)(int added);
276	void (enable)(struct perf_event );
277	void (disable)(struct perf_event );
278	int (hw_config)(struct perf_event event);
279	int (schedule_events)(struct cpu_hw_events cpuc, int n, int *assign);
280	unsigned eventsel;
281	unsigned perfctr;
282	u64 (*event_map)(int);
283	int max_events;
284	int num_counters;
285	int num_counters_fixed;
286	int cntval_bits;
287	u64 cntval_mask;
ffb871bc GN	288	union {
	289	unsigned long events_maskl;
	290	unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
	291	};
	292	int events_mask_len;
de0428a7 KW	293	int apic;
	294	u64 max_period;
	295	struct event_constraint *
	296	(get_event_constraints)(struct cpu_hw_events cpuc,
	297	struct perf_event *event);
	298
	299	void (put_event_constraints)(struct cpu_hw_events cpuc,
	300	struct perf_event *event);
	301	struct event_constraint *event_constraints;
	302	void (*quirks)(void);
	303	int perfctr_second_write;
	304
	305	int (*cpu_prepare)(int cpu);
	306	void (*cpu_starting)(int cpu);
	307	void (*cpu_dying)(int cpu);
	308	void (*cpu_dead)(int cpu);
	309
	310	/*
	311	* Intel Arch Perfmon v2+
	312	*/
	313	u64 intel_ctrl;
	314	union perf_capabilities intel_cap;
	315
	316	/*
	317	* Intel DebugStore bits
	318	*/
	319	int bts, pebs;
	320	int bts_active, pebs_active;
	321	int pebs_record_size;
	322	void (drain_pebs)(struct pt_regs regs);
	323	struct event_constraint *pebs_constraints;
	324
	325	/*
	326	* Intel LBR
	327	*/
	328	unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
	329	int lbr_nr; /* hardware stack size */
	330
	331	/*
	332	* Extra registers for events
	333	*/
	334	struct extra_reg *extra_regs;
	335	unsigned int er_flags;
144d31e6 GN	336
	337	/*
	338	* Intel host/guest support (KVM)
	339	*/
	340	struct perf_guest_switch_msr (guest_get_msrs)(int *nr);
de0428a7 KW	341	};
	342
	343	#define ERF_NO_HT_SHARING 1
	344	#define ERF_HAS_RSP_1 2
	345
	346	extern struct x86_pmu x86_pmu __read_mostly;
	347
	348	DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
	349
	350	int x86_perf_event_set_period(struct perf_event *event);
	351
	352	/*
	353	* Generalized hw caching related hw_event table, filled
	354	* in on a per model basis. A value of 0 means
	355	* 'not supported', -1 means 'hw_event makes no sense on
	356	* this CPU', any other value means the raw hw_event
	357	* ID.
	358	*/
	359
	360	#define C(x) PERF_COUNT_HW_CACHE_##x
	361
	362	extern u64 __read_mostly hw_cache_event_ids
	363	[PERF_COUNT_HW_CACHE_MAX]
	364	[PERF_COUNT_HW_CACHE_OP_MAX]
	365	[PERF_COUNT_HW_CACHE_RESULT_MAX];
	366	extern u64 __read_mostly hw_cache_extra_regs
	367	[PERF_COUNT_HW_CACHE_MAX]
	368	[PERF_COUNT_HW_CACHE_OP_MAX]
	369	[PERF_COUNT_HW_CACHE_RESULT_MAX];
	370
	371	u64 x86_perf_event_update(struct perf_event *event);
	372
	373	static inline int x86_pmu_addr_offset(int index)
	374	{
	375	int offset;
	376
	377	/* offset = X86_FEATURE_PERFCTR_CORE ? index << 1 : index */
	378	alternative_io(ASM_NOP2,
	379	"shll $1, %%eax",
	380	X86_FEATURE_PERFCTR_CORE,
	381	"=a" (offset),
	382	"a" (index));
	383
	384	return offset;
	385	}
	386
	387	static inline unsigned int x86_pmu_config_addr(int index)
	388	{
	389	return x86_pmu.eventsel + x86_pmu_addr_offset(index);
	390	}
	391
	392	static inline unsigned int x86_pmu_event_addr(int index)
	393	{
	394	return x86_pmu.perfctr + x86_pmu_addr_offset(index);
	395	}
	396
	397	int x86_setup_perfctr(struct perf_event *event);
	398
	399	int x86_pmu_hw_config(struct perf_event *event);
	400
	401	void x86_pmu_disable_all(void);
	402
	403	static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
	404	u64 enable_mask)
405	{
406	if (hwc->extra_reg.reg)
407	wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
408	wrmsrl(hwc->config_base, hwc->config \| enable_mask);
409	}
410
411	void x86_pmu_enable_all(int added);
412
413	int x86_schedule_events(struct cpu_hw_events cpuc, int n, int assign);
414
415	void x86_pmu_stop(struct perf_event *event, int flags);
416
417	static inline void x86_pmu_disable_event(struct perf_event *event)
418	{
419	struct hw_perf_event *hwc = &event->hw;
420
421	wrmsrl(hwc->config_base, hwc->config);
422	}
423
424	void x86_pmu_enable_event(struct perf_event *event);
425
426	int x86_pmu_handle_irq(struct pt_regs *regs);
427
428	extern struct event_constraint emptyconstraint;
429
430	extern struct event_constraint unconstrained;
431
432	#ifdef CONFIG_CPU_SUP_AMD
433
434	int amd_pmu_init(void);
435
436	#else /* CONFIG_CPU_SUP_AMD */
437
438	static inline int amd_pmu_init(void)
439	{
440	return 0;
441	}
442
443	#endif /* CONFIG_CPU_SUP_AMD */
444
445	#ifdef CONFIG_CPU_SUP_INTEL
446
447	int intel_pmu_save_and_restart(struct perf_event *event);
448
449	struct event_constraint *
450	x86_get_event_constraints(struct cpu_hw_events cpuc, struct perf_event event);
451
452	struct intel_shared_regs *allocate_shared_regs(int cpu);
453
454	int intel_pmu_init(void);
455
456	void init_debug_store_on_cpu(int cpu);
457
458	void fini_debug_store_on_cpu(int cpu);
459
460	void release_ds_buffers(void);
461
462	void reserve_ds_buffers(void);
463
464	extern struct event_constraint bts_constraint;
465
466	void intel_pmu_enable_bts(u64 config);
467
468	void intel_pmu_disable_bts(void);
469
470	int intel_pmu_drain_bts_buffer(void);
471
472	extern struct event_constraint intel_core2_pebs_event_constraints[];
473
474	extern struct event_constraint intel_atom_pebs_event_constraints[];
475
476	extern struct event_constraint intel_nehalem_pebs_event_constraints[];
477
478	extern struct event_constraint intel_westmere_pebs_event_constraints[];
479
480	extern struct event_constraint intel_snb_pebs_event_constraints[];
481
482	struct event_constraint intel_pebs_constraints(struct perf_event event);
483
484	void intel_pmu_pebs_enable(struct perf_event *event);
485
486	void intel_pmu_pebs_disable(struct perf_event *event);
487
488	void intel_pmu_pebs_enable_all(void);
489
490	void intel_pmu_pebs_disable_all(void);
491
492	void intel_ds_init(void);
493
494	void intel_pmu_lbr_reset(void);
495
496	void intel_pmu_lbr_enable(struct perf_event *event);
497
498	void intel_pmu_lbr_disable(struct perf_event *event);
499
500	void intel_pmu_lbr_enable_all(void);
501
502	void intel_pmu_lbr_disable_all(void);
503
504	void intel_pmu_lbr_read(void);
505
506	void intel_pmu_lbr_init_core(void);
507
508	void intel_pmu_lbr_init_nhm(void);
509
510	void intel_pmu_lbr_init_atom(void);
511
512	int p4_pmu_init(void);
513
514	int p6_pmu_init(void);
515
516	#else /* CONFIG_CPU_SUP_INTEL */
517
518	static inline void reserve_ds_buffers(void)
519	{
520	}
521
522	static inline void release_ds_buffers(void)
523	{
524	}
525
526	static inline int intel_pmu_init(void)
527	{
528	return 0;
529	}
530
531	static inline struct intel_shared_regs *allocate_shared_regs(int cpu)
532	{
533	return NULL;
534	}
535
536	#endif /* CONFIG_CPU_SUP_INTEL */