defconfig: exynos9610: Re-add dropped Wi-Fi AP options lost
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / arch / x86 / kernel / cpu / mcheck / mce-severity.c
CommitLineData
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1/*
2 * MCE grading rules.
3 * Copyright 2008, 2009 Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; version 2
8 * of the License.
9 *
10 * Author: Andi Kleen
11 */
12#include <linux/kernel.h>
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13#include <linux/seq_file.h>
14#include <linux/init.h>
15#include <linux/debugfs.h>
817f32d0 16#include <asm/mce.h>
7c0f6ba6 17#include <linux/uaccess.h>
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18
19#include "mce-internal.h"
20
21/*
22 * Grade an mce by severity. In general the most severe ones are processed
23 * first. Since there are quite a lot of combinations test the bits in a
24 * table-driven way. The rules are simply processed in order, first
25 * match wins.
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26 *
27 * Note this is only used for machine check exceptions, the corrected
28 * errors use much simpler rules. The exceptions still check for the corrected
29 * errors, but only to leave them alone for the CMCI handler (except for
30 * panic situations)
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31 */
32
b2f9d678 33enum context { IN_KERNEL = 1, IN_USER = 2, IN_KERNEL_RECOV = 3 };
ed7290d0 34enum ser { SER_REQUIRED = 1, NO_SER = 2 };
e3480271 35enum exception { EXCP_CONTEXT = 1, NO_EXCP = 2 };
ed7290d0 36
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37static struct severity {
38 u64 mask;
39 u64 result;
40 unsigned char sev;
41 unsigned char mcgmask;
42 unsigned char mcgres;
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43 unsigned char ser;
44 unsigned char context;
e3480271 45 unsigned char excp;
4611a6fa 46 unsigned char covered;
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47 char *msg;
48} severities[] = {
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49#define MCESEV(s, m, c...) { .sev = MCE_ ## s ## _SEVERITY, .msg = m, ## c }
50#define KERNEL .context = IN_KERNEL
51#define USER .context = IN_USER
b2f9d678 52#define KERNEL_RECOV .context = IN_KERNEL_RECOV
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53#define SER .ser = SER_REQUIRED
54#define NOSER .ser = NO_SER
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55#define EXCP .excp = EXCP_CONTEXT
56#define NOEXCP .excp = NO_EXCP
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57#define BITCLR(x) .mask = x, .result = 0
58#define BITSET(x) .mask = x, .result = x
59#define MCGMASK(x, y) .mcgmask = x, .mcgres = y
60#define MASK(x, y) .mask = x, .result = y
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61#define MCI_UC_S (MCI_STATUS_UC|MCI_STATUS_S)
62#define MCI_UC_SAR (MCI_STATUS_UC|MCI_STATUS_S|MCI_STATUS_AR)
5f7b88d5 63#define MCI_ADDR (MCI_STATUS_ADDRV|MCI_STATUS_MISCV)
ed7290d0 64
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65 MCESEV(
66 NO, "Invalid",
67 BITCLR(MCI_STATUS_VAL)
901d7691 68 ),
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69 MCESEV(
70 NO, "Not enabled",
e3480271 71 EXCP, BITCLR(MCI_STATUS_EN)
901d7691 72 ),
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73 MCESEV(
74 PANIC, "Processor context corrupt",
75 BITSET(MCI_STATUS_PCC)
901d7691 76 ),
ed7290d0 77 /* When MCIP is not set something is very confused */
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78 MCESEV(
79 PANIC, "MCIP not set in MCA handler",
e3480271 80 EXCP, MCGMASK(MCG_STATUS_MCIP, 0)
901d7691 81 ),
ed7290d0 82 /* Neither return not error IP -- no chance to recover -> PANIC */
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83 MCESEV(
84 PANIC, "Neither restart nor error IP",
e3480271 85 EXCP, MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, 0)
901d7691 86 ),
a17957cd 87 MCESEV(
901d7691 88 PANIC, "In kernel and no restart IP",
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89 EXCP, KERNEL, MCGMASK(MCG_STATUS_RIPV, 0)
90 ),
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91 MCESEV(
92 PANIC, "In kernel and no restart IP",
93 EXCP, KERNEL_RECOV, MCGMASK(MCG_STATUS_RIPV, 0)
94 ),
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95 MCESEV(
96 DEFERRED, "Deferred error",
97 NOSER, MASK(MCI_STATUS_UC|MCI_STATUS_DEFERRED|MCI_STATUS_POISON, MCI_STATUS_DEFERRED)
901d7691 98 ),
a17957cd 99 MCESEV(
901d7691 100 KEEP, "Corrected error",
a17957cd 101 NOSER, BITCLR(MCI_STATUS_UC)
901d7691 102 ),
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103
104 /* ignore OVER for UCNA */
a17957cd 105 MCESEV(
e3480271 106 UCNA, "Uncorrected no action required",
a17957cd 107 SER, MASK(MCI_UC_SAR, MCI_STATUS_UC)
901d7691 108 ),
a17957cd 109 MCESEV(
901d7691 110 PANIC, "Illegal combination (UCNA with AR=1)",
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111 SER,
112 MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_UC|MCI_STATUS_AR)
901d7691 113 ),
a17957cd 114 MCESEV(
901d7691 115 KEEP, "Non signalled machine check",
7639bfc7 116 SER, BITCLR(MCI_STATUS_S)
901d7691 117 ),
ed7290d0 118
a17957cd 119 MCESEV(
901d7691 120 PANIC, "Action required with lost events",
7639bfc7 121 SER, BITSET(MCI_STATUS_OVER|MCI_UC_SAR)
901d7691 122 ),
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123
124 /* known AR MCACODs: */
125#ifdef CONFIG_MEMORY_FAILURE
126 MCESEV(
33d7885b 127 KEEP, "Action required but unaffected thread is continuable",
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128 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR, MCI_UC_SAR|MCI_ADDR),
129 MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, MCG_STATUS_RIPV)
5f7b88d5 130 ),
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131 MCESEV(
132 AR, "Action required: data load in error recoverable area of kernel",
133 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
134 KERNEL_RECOV
135 ),
5f7b88d5 136 MCESEV(
33d7885b 137 AR, "Action required: data load error in a user process",
08dda402 138 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
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139 USER
140 ),
37c3459b 141 MCESEV(
33d7885b 142 AR, "Action required: instruction fetch error in a user process",
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143 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR),
144 USER
145 ),
1d1dd201
TL
146 MCESEV(
147 PANIC, "Data load in unrecoverable area of kernel",
148 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
149 KERNEL
150 ),
5f7b88d5 151#endif
a17957cd 152 MCESEV(
7639bfc7 153 PANIC, "Action required: unknown MCACOD",
a17957cd 154 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_SAR)
901d7691 155 ),
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156
157 /* known AO MCACODs: */
a17957cd 158 MCESEV(
901d7691 159 AO, "Action optional: memory scrubbing error",
08dda402 160 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCACOD_SCRUBMSK, MCI_UC_S|MCACOD_SCRUB)
901d7691 161 ),
a17957cd 162 MCESEV(
901d7691 163 AO, "Action optional: last level cache writeback error",
08dda402 164 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCACOD, MCI_UC_S|MCACOD_L3WB)
901d7691 165 ),
a17957cd 166 MCESEV(
7639bfc7 167 SOME, "Action optional: unknown MCACOD",
a17957cd 168 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_S)
901d7691 169 ),
a17957cd 170 MCESEV(
901d7691 171 SOME, "Action optional with lost events",
7639bfc7 172 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_OVER|MCI_UC_S)
901d7691 173 ),
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174
175 MCESEV(
176 PANIC, "Overflowed uncorrected",
7639bfc7 177 BITSET(MCI_STATUS_OVER|MCI_STATUS_UC)
901d7691 178 ),
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179 MCESEV(
180 UC, "Uncorrected",
181 BITSET(MCI_STATUS_UC)
901d7691 182 ),
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183 MCESEV(
184 SOME, "No match",
185 BITSET(0)
901d7691 186 ) /* always matches. keep at end */
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187};
188
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189#define mc_recoverable(mcg) (((mcg) & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) == \
190 (MCG_STATUS_RIPV|MCG_STATUS_EIPV))
191
ed7290d0 192/*
875e2664
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193 * If mcgstatus indicated that ip/cs on the stack were
194 * no good, then "m->cs" will be zero and we will have
195 * to assume the worst case (IN_KERNEL) as we actually
196 * have no idea what we were executing when the machine
197 * check hit.
198 * If we do have a good "m->cs" (or a faked one in the
199 * case we were executing in VM86 mode) we can use it to
200 * distinguish an exception taken in user from from one
201 * taken in the kernel.
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202 */
203static int error_context(struct mce *m)
204{
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205 if ((m->cs & 3) == 3)
206 return IN_USER;
207 if (mc_recoverable(m->mcgstatus) && ex_has_fault_handler(m->ip))
208 return IN_KERNEL_RECOV;
209 return IN_KERNEL;
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210}
211
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212static int mce_severity_amd_smca(struct mce *m, int err_ctx)
213{
214 u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank);
215 u32 low, high;
216
217 /*
218 * We need to look at the following bits:
219 * - "succor" bit (data poisoning support), and
220 * - TCC bit (Task Context Corrupt)
221 * in MCi_STATUS to determine error severity.
222 */
223 if (!mce_flags.succor)
224 return MCE_PANIC_SEVERITY;
225
226 if (rdmsr_safe(addr, &low, &high))
227 return MCE_PANIC_SEVERITY;
228
229 /* TCC (Task context corrupt). If set and if IN_KERNEL, panic. */
230 if ((low & MCI_CONFIG_MCAX) &&
231 (m->status & MCI_STATUS_TCC) &&
232 (err_ctx == IN_KERNEL))
233 return MCE_PANIC_SEVERITY;
234
235 /* ...otherwise invoke hwpoison handler. */
236 return MCE_AR_SEVERITY;
237}
238
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239/*
240 * See AMD Error Scope Hierarchy table in a newer BKDG. For example
241 * 49125_15h_Models_30h-3Fh_BKDG.pdf, section "RAS Features"
242 */
43eaa2a1 243static int mce_severity_amd(struct mce *m, int tolerant, char **msg, bool is_excp)
bf80bbd7 244{
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245 enum context ctx = error_context(m);
246
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247 /* Processor Context Corrupt, no need to fumble too much, die! */
248 if (m->status & MCI_STATUS_PCC)
249 return MCE_PANIC_SEVERITY;
250
251 if (m->status & MCI_STATUS_UC) {
252
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253 if (ctx == IN_KERNEL)
254 return MCE_PANIC_SEVERITY;
255
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256 /*
257 * On older systems where overflow_recov flag is not present, we
258 * should simply panic if an error overflow occurs. If
259 * overflow_recov flag is present and set, then software can try
260 * to at least kill process to prolong system operation.
261 */
262 if (mce_flags.overflow_recov) {
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263 if (mce_flags.smca)
264 return mce_severity_amd_smca(m, ctx);
265
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266 /* kill current process */
267 return MCE_AR_SEVERITY;
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268 } else {
269 /* at least one error was not logged */
270 if (m->status & MCI_STATUS_OVER)
271 return MCE_PANIC_SEVERITY;
272 }
273
274 /*
275 * For any other case, return MCE_UC_SEVERITY so that we log the
276 * error and exit #MC handler.
277 */
278 return MCE_UC_SEVERITY;
279 }
280
281 /*
282 * deferred error: poll handler catches these and adds to mce_ring so
283 * memory-failure can take recovery actions.
284 */
285 if (m->status & MCI_STATUS_DEFERRED)
286 return MCE_DEFERRED_SEVERITY;
287
288 /*
289 * corrected error: poll handler catches these and passes responsibility
290 * of decoding the error to EDAC
291 */
292 return MCE_KEEP_SEVERITY;
293}
294
43eaa2a1 295static int mce_severity_intel(struct mce *m, int tolerant, char **msg, bool is_excp)
817f32d0 296{
e3480271 297 enum exception excp = (is_excp ? EXCP_CONTEXT : NO_EXCP);
7639bfc7 298 enum context ctx = error_context(m);
817f32d0 299 struct severity *s;
ed7290d0 300
817f32d0 301 for (s = severities;; s++) {
7639bfc7 302 if ((m->status & s->mask) != s->result)
817f32d0 303 continue;
7639bfc7 304 if ((m->mcgstatus & s->mcgmask) != s->mcgres)
817f32d0 305 continue;
1462594b 306 if (s->ser == SER_REQUIRED && !mca_cfg.ser)
ed7290d0 307 continue;
1462594b 308 if (s->ser == NO_SER && mca_cfg.ser)
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309 continue;
310 if (s->context && ctx != s->context)
311 continue;
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312 if (s->excp && excp != s->excp)
313 continue;
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314 if (msg)
315 *msg = s->msg;
4611a6fa 316 s->covered = 1;
ed7290d0 317 if (s->sev >= MCE_UC_SEVERITY && ctx == IN_KERNEL) {
f5e886ef 318 if (tolerant < 1)
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319 return MCE_PANIC_SEVERITY;
320 }
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321 return s->sev;
322 }
323}
4611a6fa 324
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325/* Default to mce_severity_intel */
326int (*mce_severity)(struct mce *m, int tolerant, char **msg, bool is_excp) =
327 mce_severity_intel;
328
329void __init mcheck_vendor_init_severity(void)
330{
331 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
332 mce_severity = mce_severity_amd;
333}
334
e34e77ce 335#ifdef CONFIG_DEBUG_FS
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336static void *s_start(struct seq_file *f, loff_t *pos)
337{
338 if (*pos >= ARRAY_SIZE(severities))
339 return NULL;
340 return &severities[*pos];
341}
342
343static void *s_next(struct seq_file *f, void *data, loff_t *pos)
344{
345 if (++(*pos) >= ARRAY_SIZE(severities))
346 return NULL;
347 return &severities[*pos];
348}
349
350static void s_stop(struct seq_file *f, void *data)
351{
352}
353
354static int s_show(struct seq_file *f, void *data)
355{
356 struct severity *ser = data;
357 seq_printf(f, "%d\t%s\n", ser->covered, ser->msg);
358 return 0;
359}
360
361static const struct seq_operations severities_seq_ops = {
362 .start = s_start,
363 .next = s_next,
364 .stop = s_stop,
365 .show = s_show,
366};
367
368static int severities_coverage_open(struct inode *inode, struct file *file)
369{
370 return seq_open(file, &severities_seq_ops);
371}
372
373static ssize_t severities_coverage_write(struct file *file,
374 const char __user *ubuf,
375 size_t count, loff_t *ppos)
376{
377 int i;
378 for (i = 0; i < ARRAY_SIZE(severities); i++)
379 severities[i].covered = 0;
380 return count;
381}
382
383static const struct file_operations severities_coverage_fops = {
384 .open = severities_coverage_open,
385 .release = seq_release,
386 .read = seq_read,
387 .write = severities_coverage_write,
6038f373 388 .llseek = seq_lseek,
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389};
390
391static int __init severities_debugfs_init(void)
392{
7639bfc7 393 struct dentry *dmce, *fsev;
4611a6fa 394
5be9ed25 395 dmce = mce_get_debugfs_dir();
7639bfc7 396 if (!dmce)
4611a6fa 397 goto err_out;
7639bfc7
HS
398
399 fsev = debugfs_create_file("severities-coverage", 0444, dmce, NULL,
400 &severities_coverage_fops);
401 if (!fsev)
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402 goto err_out;
403
404 return 0;
405
406err_out:
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407 return -ENOMEM;
408}
409late_initcall(severities_debugfs_init);
7639bfc7 410#endif /* CONFIG_DEBUG_FS */