[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / include / asm / cache.h

#ifndef _ASM_X86_CACHE_H
#define _ASM_X86_CACHE_H

#include <linux/linkage.h>

/* L1 cache line size */
#define L1_CACHE_SHIFT	(CONFIG_X86_L1_CACHE_SHIFT)
#define L1_CACHE_BYTES	(1 << L1_CACHE_SHIFT)

#define __read_mostly __attribute__((__section__(".data..read_mostly")))

#define INTERNODE_CACHE_SHIFT CONFIG_X86_INTERNODE_CACHE_SHIFT
#define INTERNODE_CACHE_BYTES (1 << INTERNODE_CACHE_SHIFT)

#ifdef CONFIG_X86_VSMP
#ifdef CONFIG_SMP
#define __cacheline_aligned_in_smp					\
	__attribute__((__aligned__(INTERNODE_CACHE_BYTES)))		\
	__page_aligned_data
#endif
#endif

#endif /* _ASM_X86_CACHE_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_CACHE_H
1965aae3 PA	2	#define _ASM_X86_CACHE_H
9bfa23df	3
abe1ee3a TA	4	#include <linux/linkage.h>
abe1ee3a TA	5
9bfa23df TG	6	/* L1 cache line size */
	7	#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
	8	#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
	9
54cb27a7	10	#define __read_mostly __attribute__((__section__(".data..read_mostly")))
9bfa23df	11
350f8f56 JB	12	#define INTERNODE_CACHE_SHIFT CONFIG_X86_INTERNODE_CACHE_SHIFT
	13	#define INTERNODE_CACHE_BYTES (1 << INTERNODE_CACHE_SHIFT)
	14
9bfa23df	15	#ifdef CONFIG_X86_VSMP
9bfa23df TG	16	#ifdef CONFIG_SMP
9bfa23df TG	17	#define __cacheline_aligned_in_smp \
350f8f56	18	__attribute__((__aligned__(INTERNODE_CACHE_BYTES))) \
abe1ee3a	19	__page_aligned_data
9bfa23df TG	20	#endif
	21	#endif
	22
1965aae3	23	#endif /* _ASM_X86_CACHE_H */