[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / Kconfig.cpu

# Put here option for CPU selection and depending optimization
if !X86_ELAN

choice
	prompt "Processor family"
	default M686 if X86_32
	default GENERIC_CPU if X86_64

config M386
	bool "386"
	depends on X86_32 && !UML
	---help---
	  This is the processor type of your CPU. This information is used for
	  optimizing purposes. In order to compile a kernel that can run on
	  all x86 CPU types (albeit not optimally fast), you can specify
	  "386" here.

	  The kernel will not necessarily run on earlier architectures than
	  the one you have chosen, e.g. a Pentium optimized kernel will run on
	  a PPro, but not necessarily on a i486.

	  Here are the settings recommended for greatest speed:
	  - "386" for the AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI
	  486DLC/DLC2, and UMC 486SX-S.  Only "386" kernels will run on a 386
	  class machine.
	  - "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or
	  SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S.
	  - "586" for generic Pentium CPUs lacking the TSC
	  (time stamp counter) register.
	  - "Pentium-Classic" for the Intel Pentium.
	  - "Pentium-MMX" for the Intel Pentium MMX.
	  - "Pentium-Pro" for the Intel Pentium Pro.
	  - "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron.
	  - "Pentium-III" for the Intel Pentium III or Coppermine Celeron.
	  - "Pentium-4" for the Intel Pentium 4 or P4-based Celeron.
	  - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D).
	  - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird).
	  - "Crusoe" for the Transmeta Crusoe series.
	  - "Efficeon" for the Transmeta Efficeon series.
	  - "Winchip-C6" for original IDT Winchip.
	  - "Winchip-2" for IDT Winchip 2.
	  - "Winchip-2A" for IDT Winchips with 3dNow! capabilities.
	  - "GeodeGX1" for Geode GX1 (Cyrix MediaGX).
	  - "Geode GX/LX" For AMD Geode GX and LX processors.
	  - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3.
	  - "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above).
	  - "VIA C7" for VIA C7.

	  If you don't know what to do, choose "386".

config M486
	bool "486"
	depends on X86_32
	help
	  Select this for a 486 series processor, either Intel or one of the
	  compatible processors from AMD, Cyrix, IBM, or Intel.  Includes DX,
	  DX2, and DX4 variants; also SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or
	  U5S.

config M586
	bool "586/K5/5x86/6x86/6x86MX"
	depends on X86_32
	help
	  Select this for an 586 or 686 series processor such as the AMD K5,
	  the Cyrix 5x86, 6x86 and 6x86MX.  This choice does not
	  assume the RDTSC (Read Time Stamp Counter) instruction.

config M586TSC
	bool "Pentium-Classic"
	depends on X86_32
	help
	  Select this for a Pentium Classic processor with the RDTSC (Read
	  Time Stamp Counter) instruction for benchmarking.

config M586MMX
	bool "Pentium-MMX"
	depends on X86_32
	help
	  Select this for a Pentium with the MMX graphics/multimedia
	  extended instructions.

config M686
	bool "Pentium-Pro"
	depends on X86_32
	help
	  Select this for Intel Pentium Pro chips.  This enables the use of
	  Pentium Pro extended instructions, and disables the init-time guard
	  against the f00f bug found in earlier Pentiums.

config MPENTIUMII
	bool "Pentium-II/Celeron(pre-Coppermine)"
	depends on X86_32
	help
	  Select this for Intel chips based on the Pentium-II and
	  pre-Coppermine Celeron core.  This option enables an unaligned
	  copy optimization, compiles the kernel with optimization flags
	  tailored for the chip, and applies any applicable Pentium Pro
	  optimizations.

config MPENTIUMIII
	bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon"
	depends on X86_32
	help
	  Select this for Intel chips based on the Pentium-III and
	  Celeron-Coppermine core.  This option enables use of some
	  extended prefetch instructions in addition to the Pentium II
	  extensions.

config MPENTIUMM
	bool "Pentium M"
	depends on X86_32
	help
	  Select this for Intel Pentium M (not Pentium-4 M)
	  notebook chips.

config MPENTIUM4
	bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon"
	depends on X86_32
	help
	  Select this for Intel Pentium 4 chips.  This includes the
	  Pentium 4, Pentium D, P4-based Celeron and Xeon, and
	  Pentium-4 M (not Pentium M) chips.  This option enables compile
	  flags optimized for the chip, uses the correct cache line size, and
	  applies any applicable optimizations.

	  CPUIDs: F[0-6][1-A] (in /proc/cpuinfo show = cpu family : 15 )

	  Select this for:
	    Pentiums (Pentium 4, Pentium D, Celeron, Celeron D) corename:
		-Willamette
		-Northwood
		-Mobile Pentium 4
		-Mobile Pentium 4 M
		-Extreme Edition (Gallatin)
		-Prescott
		-Prescott 2M
		-Cedar Mill
		-Presler
		-Smithfiled
	    Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename:
		-Foster
		-Prestonia
		-Gallatin
		-Nocona
		-Irwindale
		-Cranford
		-Potomac
		-Paxville
		-Dempsey


config MK6
	bool "K6/K6-II/K6-III"
	depends on X86_32
	help
	  Select this for an AMD K6-family processor.  Enables use of
	  some extended instructions, and passes appropriate optimization
	  flags to GCC.

config MK7
	bool "Athlon/Duron/K7"
	depends on X86_32
	help
	  Select this for an AMD Athlon K7-family processor.  Enables use of
	  some extended instructions, and passes appropriate optimization
	  flags to GCC.

config MK8
	bool "Opteron/Athlon64/Hammer/K8"
	help
	  Select this for an AMD Opteron or Athlon64 Hammer-family processor.  Enables
	  use of some extended instructions, and passes appropriate optimization
	  flags to GCC.

config MCRUSOE
	bool "Crusoe"
	depends on X86_32
	help
	  Select this for a Transmeta Crusoe processor.  Treats the processor
	  like a 586 with TSC, and sets some GCC optimization flags (like a
	  Pentium Pro with no alignment requirements).

config MEFFICEON
	bool "Efficeon"
	depends on X86_32
	help
	  Select this for a Transmeta Efficeon processor.

config MWINCHIPC6
	bool "Winchip-C6"
	depends on X86_32
	help
	  Select this for an IDT Winchip C6 chip.  Linux and GCC
	  treat this chip as a 586TSC with some extended instructions
	  and alignment requirements.

config MWINCHIP2
	bool "Winchip-2"
	depends on X86_32
	help
	  Select this for an IDT Winchip-2.  Linux and GCC
	  treat this chip as a 586TSC with some extended instructions
	  and alignment requirements.

config MWINCHIP3D
	bool "Winchip-2A/Winchip-3"
	depends on X86_32
	help
	  Select this for an IDT Winchip-2A or 3.  Linux and GCC
	  treat this chip as a 586TSC with some extended instructions
	  and alignment requirements.  Also enable out of order memory
	  stores for this CPU, which can increase performance of some
	  operations.

config MGEODEGX1
	bool "GeodeGX1"
	depends on X86_32
	help
	  Select this for a Geode GX1 (Cyrix MediaGX) chip.

config MGEODE_LX
	bool "Geode GX/LX"
	depends on X86_32
	help
	  Select this for AMD Geode GX and LX processors.

config MCYRIXIII
	bool "CyrixIII/VIA-C3"
	depends on X86_32
	help
	  Select this for a Cyrix III or C3 chip.  Presently Linux and GCC
	  treat this chip as a generic 586. Whilst the CPU is 686 class,
	  it lacks the cmov extension which gcc assumes is present when
	  generating 686 code.
	  Note that Nehemiah (Model 9) and above will not boot with this
	  kernel due to them lacking the 3DNow! instructions used in earlier
	  incarnations of the CPU.

config MVIAC3_2
	bool "VIA C3-2 (Nehemiah)"
	depends on X86_32
	help
	  Select this for a VIA C3 "Nehemiah". Selecting this enables usage
	  of SSE and tells gcc to treat the CPU as a 686.
	  Note, this kernel will not boot on older (pre model 9) C3s.

config MVIAC7
	bool "VIA C7"
	depends on X86_32
	help
	  Select this for a VIA C7.  Selecting this uses the correct cache
	  shift and tells gcc to treat the CPU as a 686.

config MPSC
	bool "Intel P4 / older Netburst based Xeon"
	depends on X86_64
	help
	  Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey
	  Xeon CPUs with Intel 64bit which is compatible with x86-64.
	  Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the
	  Netburst core and shouldn't use this option. You can distinguish them
	  using the cpu family field
	  in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one.

config MCORE2
	bool "Core 2/newer Xeon"
	help
	  Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and 53xx)
	  CPUs. You can distinguish newer from older Xeons by the CPU family
	  in /proc/cpuinfo. Newer ones have 6 and older ones 15 (not a typo)

config GENERIC_CPU
	bool "Generic-x86-64"
	depends on X86_64
	help
	  Generic x86-64 CPU.
	  Run equally well on all x86-64 CPUs.

endchoice

config X86_GENERIC
	bool "Generic x86 support"
	depends on X86_32
	help
	  Instead of just including optimizations for the selected
	  x86 variant (e.g. PII, Crusoe or Athlon), include some more
	  generic optimizations as well. This will make the kernel
	  perform better on x86 CPUs other than that selected.

	  This is really intended for distributors who need more
	  generic optimizations.

endif

config X86_CPU
	def_bool y
	select GENERIC_FIND_FIRST_BIT
	select GENERIC_FIND_NEXT_BIT

#
# Define implied options from the CPU selection here
config X86_L1_CACHE_BYTES
	int
	default "128" if GENERIC_CPU || MPSC
	default "64" if MK8 || MCORE2
	depends on X86_64

config X86_INTERNODE_CACHE_BYTES
	int
	default "4096" if X86_VSMP
	default X86_L1_CACHE_BYTES if !X86_VSMP
	depends on X86_64

config X86_CMPXCHG
	def_bool X86_64 || (X86_32 && !M386)

config X86_L1_CACHE_SHIFT
	int
	default "7" if MPENTIUM4 || X86_GENERIC || GENERIC_CPU || MPSC
	default "4" if X86_ELAN || M486 || M386 || MGEODEGX1
	default "5" if MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
	default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MVIAC7

config X86_XADD
	def_bool y
	depends on X86_32 && !M386

config X86_PPRO_FENCE
	bool "PentiumPro memory ordering errata workaround"
	depends on M686 || M586MMX || M586TSC || M586 || M486 || M386 || MGEODEGX1
	help
	  Old PentiumPro multiprocessor systems had errata that could cause memory
	  operations to violate the x86 ordering standard in rare cases. Enabling this
	  option will attempt to work around some (but not all) occurances of
	  this problem, at the cost of much heavier spinlock and memory barrier
	  operations.

	  If unsure, say n here. Even distro kernels should think twice before enabling
	  this: there are few systems, and an unlikely bug.

config X86_F00F_BUG
	def_bool y
	depends on M586MMX || M586TSC || M586 || M486 || M386

config X86_WP_WORKS_OK
	def_bool y
	depends on !M386

config X86_INVLPG
	def_bool y
	depends on X86_32 && !M386

config X86_BSWAP
	def_bool y
	depends on X86_32 && !M386

config X86_POPAD_OK
	def_bool y
	depends on X86_32 && !M386

config X86_ALIGNMENT_16
	def_bool y
	depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || X86_ELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1

config X86_INTEL_USERCOPY
	def_bool y
	depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2

config X86_USE_PPRO_CHECKSUM
	def_bool y
	depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MEFFICEON || MGEODE_LX || MCORE2

config X86_USE_3DNOW
	def_bool y
	depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML

config X86_OOSTORE
	def_bool y
	depends on (MWINCHIP3D || MWINCHIP2 || MWINCHIPC6) && MTRR

#
# P6_NOPs are a relatively minor optimization that require a family >=
# 6 processor, except that it is broken on certain VIA chips.
# Furthermore, AMD chips prefer a totally different sequence of NOPs
# (which work on all CPUs).  As a result, disallow these if we're
# compiling X86_GENERIC but not X86_64 (these NOPs do work on all
# x86-64 capable chips); the list of processors in the right-hand clause
# are the cores that benefit from this optimization.
#
config X86_P6_NOP
	def_bool y
	depends on (X86_64 || !X86_GENERIC) && (M686 || MPENTIUMII || MPENTIUMIII || MPENTIUMM || MCORE2 || MPENTIUM4 || MPSC)

config X86_TSC
	def_bool y
	depends on ((MWINCHIP3D || MWINCHIP2 || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2) && !X86_NUMAQ) || X86_64

config X86_CMPXCHG64
	def_bool y
	depends on X86_PAE || X86_64

# this should be set for all -march=.. options where the compiler
# generates cmov.
config X86_CMOV
	def_bool y
	depends on (MK7 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || X86_64)

config X86_MINIMUM_CPU_FAMILY
	int
	default "64" if X86_64
	default "6" if X86_32 && X86_P6_NOP
	default "4" if X86_32 && (X86_XADD || X86_CMPXCHG || X86_BSWAP || X86_WP_WORKS_OK)
	default "3"

config X86_DEBUGCTLMSR
	def_bool y
	depends on !(MK6 || MWINCHIPC6 || MWINCHIP2 || MWINCHIP3D || MCYRIXIII || M586MMX || M586TSC || M586 || M486 || M386)

menuconfig PROCESSOR_SELECT
	default y
	bool "Supported processor vendors" if EMBEDDED
	help
	  This lets you choose what x86 vendor support code your kernel
	  will include.

config CPU_SUP_INTEL_32
	default y
	bool "Support Intel processors" if PROCESSOR_SELECT
	depends on !64BIT
	help
	  This enables extended support for Intel processors

config CPU_SUP_INTEL_64
	default y
	bool "Support Intel processors" if PROCESSOR_SELECT
	depends on 64BIT
	help
	  This enables extended support for Intel processors

config CPU_SUP_CYRIX_32
	default y
	bool "Support Cyrix processors" if PROCESSOR_SELECT
	depends on !64BIT
	help
	  This enables extended support for Cyrix processors

config CPU_SUP_AMD
	default y
	bool "Support AMD processors" if PROCESSOR_SELECT
	help
	  This enables extended support for AMD processors

config CPU_SUP_CENTAUR_32
	default y
	bool "Support Centaur processors" if PROCESSOR_SELECT
	depends on !64BIT
	help
	  This enables extended support for Centaur processors

config CPU_SUP_CENTAUR_64
	default y
	bool "Support Centaur processors" if PROCESSOR_SELECT
	depends on 64BIT
	help
	  This enables extended support for Centaur processors

config CPU_SUP_TRANSMETA_32
	default y
	bool "Support Transmeta processors" if PROCESSOR_SELECT
	depends on !64BIT
	help
	  This enables extended support for Transmeta processors

config CPU_SUP_UMC_32
	default y
	bool "Support UMC processors" if PROCESSOR_SELECT
	depends on !64BIT
	help
	  This enables extended support for UMC processors

config X86_DS
	bool "Debug Store support"
	default y
	help
	  Add support for Debug Store.
	  This allows the kernel to provide a memory buffer to the hardware
	  to store various profiling and tracing events.

config X86_PTRACE_BTS
	bool "ptrace interface to Branch Trace Store"
	default y
	depends on (X86_DS && X86_DEBUGCTLMSR)
	help
	  Add a ptrace interface to allow collecting an execution trace
	  of the traced task.
	  This collects control flow changes in a (cyclic) buffer and allows
	  debuggers to fill in the gaps and show an execution trace of the debuggee.
Commit	Line	Data
96d55b88 PBG	1	# Put here option for CPU selection and depending optimization
	2	if !X86_ELAN
	3
	4	choice
	5	prompt "Processor family"
1032c0ba SR	6	default M686 if X86_32
1032c0ba SR	7	default GENERIC_CPU if X86_64
96d55b88 PBG	8
	9	config M386
	10	bool "386"
1032c0ba	11	depends on X86_32 && !UML
96d55b88 PBG	12	---help---
	13	This is the processor type of your CPU. This information is used for
	14	optimizing purposes. In order to compile a kernel that can run on
	15	all x86 CPU types (albeit not optimally fast), you can specify
	16	"386" here.
	17
	18	The kernel will not necessarily run on earlier architectures than
	19	the one you have chosen, e.g. a Pentium optimized kernel will run on
	20	a PPro, but not necessarily on a i486.
	21
	22	Here are the settings recommended for greatest speed:
	23	- "386" for the AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI
f7f17a67 DV	24	486DLC/DLC2, and UMC 486SX-S. Only "386" kernels will run on a 386
f7f17a67 DV	25	class machine.
96d55b88 PBG	26	- "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or
	27	SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S.
	28	- "586" for generic Pentium CPUs lacking the TSC
	29	(time stamp counter) register.
	30	- "Pentium-Classic" for the Intel Pentium.
	31	- "Pentium-MMX" for the Intel Pentium MMX.
	32	- "Pentium-Pro" for the Intel Pentium Pro.
	33	- "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron.
	34	- "Pentium-III" for the Intel Pentium III or Coppermine Celeron.
	35	- "Pentium-4" for the Intel Pentium 4 or P4-based Celeron.
	36	- "K6" for the AMD K6, K6-II and K6-III (aka K6-3D).
	37	- "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird).
	38	- "Crusoe" for the Transmeta Crusoe series.
	39	- "Efficeon" for the Transmeta Efficeon series.
	40	- "Winchip-C6" for original IDT Winchip.
	41	- "Winchip-2" for IDT Winchip 2.
	42	- "Winchip-2A" for IDT Winchips with 3dNow! capabilities.
	43	- "GeodeGX1" for Geode GX1 (Cyrix MediaGX).
f90b8116	44	- "Geode GX/LX" For AMD Geode GX and LX processors.
96d55b88	45	- "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3.
48a1204c	46	- "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above).
0949be35	47	- "VIA C7" for VIA C7.
96d55b88 PBG	48
	49	If you don't know what to do, choose "386".
	50
	51	config M486
	52	bool "486"
1032c0ba	53	depends on X86_32
96d55b88 PBG	54	help
	55	Select this for a 486 series processor, either Intel or one of the
	56	compatible processors from AMD, Cyrix, IBM, or Intel. Includes DX,
	57	DX2, and DX4 variants; also SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or
	58	U5S.
	59
	60	config M586
	61	bool "586/K5/5x86/6x86/6x86MX"
1032c0ba	62	depends on X86_32
96d55b88 PBG	63	help
	64	Select this for an 586 or 686 series processor such as the AMD K5,
	65	the Cyrix 5x86, 6x86 and 6x86MX. This choice does not
	66	assume the RDTSC (Read Time Stamp Counter) instruction.
	67
	68	config M586TSC
	69	bool "Pentium-Classic"
1032c0ba	70	depends on X86_32
96d55b88 PBG	71	help
	72	Select this for a Pentium Classic processor with the RDTSC (Read
	73	Time Stamp Counter) instruction for benchmarking.
	74
	75	config M586MMX
	76	bool "Pentium-MMX"
1032c0ba	77	depends on X86_32
96d55b88 PBG	78	help
	79	Select this for a Pentium with the MMX graphics/multimedia
	80	extended instructions.
	81
	82	config M686
	83	bool "Pentium-Pro"
1032c0ba	84	depends on X86_32
96d55b88 PBG	85	help
	86	Select this for Intel Pentium Pro chips. This enables the use of
	87	Pentium Pro extended instructions, and disables the init-time guard
	88	against the f00f bug found in earlier Pentiums.
	89
	90	config MPENTIUMII
	91	bool "Pentium-II/Celeron(pre-Coppermine)"
1032c0ba	92	depends on X86_32
96d55b88 PBG	93	help
	94	Select this for Intel chips based on the Pentium-II and
	95	pre-Coppermine Celeron core. This option enables an unaligned
	96	copy optimization, compiles the kernel with optimization flags
	97	tailored for the chip, and applies any applicable Pentium Pro
	98	optimizations.
	99
	100	config MPENTIUMIII
	101	bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon"
1032c0ba	102	depends on X86_32
96d55b88 PBG	103	help
	104	Select this for Intel chips based on the Pentium-III and
	105	Celeron-Coppermine core. This option enables use of some
	106	extended prefetch instructions in addition to the Pentium II
	107	extensions.
	108
	109	config MPENTIUMM
	110	bool "Pentium M"
1032c0ba	111	depends on X86_32
96d55b88 PBG	112	help
	113	Select this for Intel Pentium M (not Pentium-4 M)
	114	notebook chips.
	115
	116	config MPENTIUM4
c55d92d1	117	bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon"
1032c0ba	118	depends on X86_32
96d55b88 PBG	119	help
96d55b88 PBG	120	Select this for Intel Pentium 4 chips. This includes the
75e3808b OP	121	Pentium 4, Pentium D, P4-based Celeron and Xeon, and
	122	Pentium-4 M (not Pentium M) chips. This option enables compile
	123	flags optimized for the chip, uses the correct cache line size, and
	124	applies any applicable optimizations.
	125
	126	CPUIDs: F[0-6][1-A] (in /proc/cpuinfo show = cpu family : 15 )
	127
	128	Select this for:
	129	Pentiums (Pentium 4, Pentium D, Celeron, Celeron D) corename:
	130	-Willamette
	131	-Northwood
	132	-Mobile Pentium 4
	133	-Mobile Pentium 4 M
	134	-Extreme Edition (Gallatin)
	135	-Prescott
	136	-Prescott 2M
	137	-Cedar Mill
	138	-Presler
	139	-Smithfiled
	140	Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename:
	141	-Foster
	142	-Prestonia
	143	-Gallatin
	144	-Nocona
	145	-Irwindale
	146	-Cranford
	147	-Potomac
	148	-Paxville
	149	-Dempsey
	150
96d55b88 PBG	151
	152	config MK6
	153	bool "K6/K6-II/K6-III"
1032c0ba	154	depends on X86_32
96d55b88 PBG	155	help
	156	Select this for an AMD K6-family processor. Enables use of
	157	some extended instructions, and passes appropriate optimization
	158	flags to GCC.
	159
	160	config MK7
	161	bool "Athlon/Duron/K7"
1032c0ba	162	depends on X86_32
96d55b88 PBG	163	help
	164	Select this for an AMD Athlon K7-family processor. Enables use of
	165	some extended instructions, and passes appropriate optimization
	166	flags to GCC.
	167
	168	config MK8
	169	bool "Opteron/Athlon64/Hammer/K8"
	170	help
	171	Select this for an AMD Opteron or Athlon64 Hammer-family processor. Enables
	172	use of some extended instructions, and passes appropriate optimization
	173	flags to GCC.
	174
	175	config MCRUSOE
	176	bool "Crusoe"
1032c0ba	177	depends on X86_32
96d55b88 PBG	178	help
	179	Select this for a Transmeta Crusoe processor. Treats the processor
	180	like a 586 with TSC, and sets some GCC optimization flags (like a
	181	Pentium Pro with no alignment requirements).
	182
	183	config MEFFICEON
	184	bool "Efficeon"
1032c0ba	185	depends on X86_32
96d55b88 PBG	186	help
	187	Select this for a Transmeta Efficeon processor.
	188
	189	config MWINCHIPC6
	190	bool "Winchip-C6"
1032c0ba	191	depends on X86_32
96d55b88 PBG	192	help
	193	Select this for an IDT Winchip C6 chip. Linux and GCC
	194	treat this chip as a 586TSC with some extended instructions
	195	and alignment requirements.
	196
	197	config MWINCHIP2
	198	bool "Winchip-2"
1032c0ba	199	depends on X86_32
96d55b88 PBG	200	help
	201	Select this for an IDT Winchip-2. Linux and GCC
	202	treat this chip as a 586TSC with some extended instructions
	203	and alignment requirements.
	204
	205	config MWINCHIP3D
	206	bool "Winchip-2A/Winchip-3"
1032c0ba	207	depends on X86_32
96d55b88 PBG	208	help
	209	Select this for an IDT Winchip-2A or 3. Linux and GCC
	210	treat this chip as a 586TSC with some extended instructions
3dde6ad8	211	and alignment requirements. Also enable out of order memory
96d55b88 PBG	212	stores for this CPU, which can increase performance of some
	213	operations.
	214
	215	config MGEODEGX1
	216	bool "GeodeGX1"
1032c0ba	217	depends on X86_32
96d55b88 PBG	218	help
	219	Select this for a Geode GX1 (Cyrix MediaGX) chip.
	220
f90b8116	221	config MGEODE_LX
96daa8cd	222	bool "Geode GX/LX"
1032c0ba	223	depends on X86_32
96daa8cd HH	224	help
96daa8cd HH	225	Select this for AMD Geode GX and LX processors.
f90b8116	226
96d55b88 PBG	227	config MCYRIXIII
96d55b88 PBG	228	bool "CyrixIII/VIA-C3"
1032c0ba	229	depends on X86_32
96d55b88 PBG	230	help
	231	Select this for a Cyrix III or C3 chip. Presently Linux and GCC
	232	treat this chip as a generic 586. Whilst the CPU is 686 class,
	233	it lacks the cmov extension which gcc assumes is present when
	234	generating 686 code.
	235	Note that Nehemiah (Model 9) and above will not boot with this
	236	kernel due to them lacking the 3DNow! instructions used in earlier
	237	incarnations of the CPU.
	238
	239	config MVIAC3_2
	240	bool "VIA C3-2 (Nehemiah)"
1032c0ba	241	depends on X86_32
96d55b88 PBG	242	help
	243	Select this for a VIA C3 "Nehemiah". Selecting this enables usage
	244	of SSE and tells gcc to treat the CPU as a 686.
	245	Note, this kernel will not boot on older (pre model 9) C3s.
	246
0949be35 SA	247	config MVIAC7
0949be35 SA	248	bool "VIA C7"
1032c0ba	249	depends on X86_32
0949be35 SA	250	help
	251	Select this for a VIA C7. Selecting this uses the correct cache
	252	shift and tells gcc to treat the CPU as a 686.
	253
1032c0ba SR	254	config MPSC
	255	bool "Intel P4 / older Netburst based Xeon"
	256	depends on X86_64
	257	help
	258	Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey
	259	Xeon CPUs with Intel 64bit which is compatible with x86-64.
	260	Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the
96daa8cd	261	Netburst core and shouldn't use this option. You can distinguish them
1032c0ba SR	262	using the cpu family field
	263	in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one.
	264
	265	config MCORE2
	266	bool "Core 2/newer Xeon"
	267	help
	268	Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and 53xx)
	269	CPUs. You can distinguish newer from older Xeons by the CPU family
	270	in /proc/cpuinfo. Newer ones have 6 and older ones 15 (not a typo)
	271
	272	config GENERIC_CPU
	273	bool "Generic-x86-64"
	274	depends on X86_64
	275	help
	276	Generic x86-64 CPU.
	277	Run equally well on all x86-64 CPUs.
	278
96d55b88 PBG	279	endchoice
	280
	281	config X86_GENERIC
1032c0ba SR	282	bool "Generic x86 support"
	283	depends on X86_32
	284	help
96d55b88 PBG	285	Instead of just including optimizations for the selected
	286	x86 variant (e.g. PII, Crusoe or Athlon), include some more
	287	generic optimizations as well. This will make the kernel
	288	perform better on x86 CPUs other than that selected.
	289
	290	This is really intended for distributors who need more
	291	generic optimizations.
	292
	293	endif
	294
acbaa93e IM	295	config X86_CPU
	296	def_bool y
	297	select GENERIC_FIND_FIRST_BIT
	298	select GENERIC_FIND_NEXT_BIT
	299
96d55b88 PBG	300	#
96d55b88 PBG	301	# Define implied options from the CPU selection here
1032c0ba SR	302	config X86_L1_CACHE_BYTES
	303	int
	304	default "128" if GENERIC_CPU \|\| MPSC
	305	default "64" if MK8 \|\| MCORE2
	306	depends on X86_64
	307
	308	config X86_INTERNODE_CACHE_BYTES
	309	int
	310	default "4096" if X86_VSMP
	311	default X86_L1_CACHE_BYTES if !X86_VSMP
	312	depends on X86_64
	313
96d55b88	314	config X86_CMPXCHG
1032c0ba	315	def_bool X86_64 \|\| (X86_32 && !M386)
96d55b88	316
96d55b88 PBG	317	config X86_L1_CACHE_SHIFT
96d55b88 PBG	318	int
1032c0ba	319	default "7" if MPENTIUM4 \|\| X86_GENERIC \|\| GENERIC_CPU \|\| MPSC
f90b8116 JC	320	default "4" if X86_ELAN \|\| M486 \|\| M386 \|\| MGEODEGX1
f90b8116 JC	321	default "5" if MWINCHIP3D \|\| MWINCHIP2 \|\| MWINCHIPC6 \|\| MCRUSOE \|\| MEFFICEON \|\| MCYRIXIII \|\| MK6 \|\| MPENTIUMIII \|\| MPENTIUMII \|\| M686 \|\| M586MMX \|\| M586TSC \|\| M586 \|\| MVIAC3_2 \|\| MGEODE_LX
0949be35	322	default "6" if MK7 \|\| MK8 \|\| MPENTIUMM \|\| MCORE2 \|\| MVIAC7
96d55b88	323
c7f81c94	324	config X86_XADD
96daa8cd	325	def_bool y
1032c0ba	326	depends on X86_32 && !M386
96d55b88 PBG	327
96d55b88 PBG	328	config X86_PPRO_FENCE
fb0328e2	329	bool "PentiumPro memory ordering errata workaround"
96d55b88	330	depends on M686 \|\| M586MMX \|\| M586TSC \|\| M586 \|\| M486 \|\| M386 \|\| MGEODEGX1
fb0328e2 NP	331	help
	332	Old PentiumPro multiprocessor systems had errata that could cause memory
	333	operations to violate the x86 ordering standard in rare cases. Enabling this
	334	option will attempt to work around some (but not all) occurances of
	335	this problem, at the cost of much heavier spinlock and memory barrier
	336	operations.
	337
	338	If unsure, say n here. Even distro kernels should think twice before enabling
	339	this: there are few systems, and an unlikely bug.
96d55b88 PBG	340
96d55b88 PBG	341	config X86_F00F_BUG
96daa8cd	342	def_bool y
96d55b88	343	depends on M586MMX \|\| M586TSC \|\| M586 \|\| M486 \|\| M386
96d55b88 PBG	344
96d55b88 PBG	345	config X86_WP_WORKS_OK
96daa8cd	346	def_bool y
293e6a25	347	depends on !M386
96d55b88 PBG	348
96d55b88 PBG	349	config X86_INVLPG
96daa8cd	350	def_bool y
1032c0ba	351	depends on X86_32 && !M386
96d55b88 PBG	352
96d55b88 PBG	353	config X86_BSWAP
96daa8cd	354	def_bool y
1032c0ba	355	depends on X86_32 && !M386
96d55b88 PBG	356
96d55b88 PBG	357	config X86_POPAD_OK
96daa8cd	358	def_bool y
1032c0ba	359	depends on X86_32 && !M386
96d55b88	360
96d55b88	361	config X86_ALIGNMENT_16
96daa8cd	362	def_bool y
96d55b88	363	depends on MWINCHIP3D \|\| MWINCHIP2 \|\| MWINCHIPC6 \|\| MCYRIXIII \|\| X86_ELAN \|\| MK6 \|\| M586MMX \|\| M586TSC \|\| M586 \|\| M486 \|\| MVIAC3_2 \|\| MGEODEGX1
96d55b88	364
96d55b88	365	config X86_INTEL_USERCOPY
96daa8cd	366	def_bool y
c55d92d1	367	depends on MPENTIUM4 \|\| MPENTIUMM \|\| MPENTIUMIII \|\| MPENTIUMII \|\| M586MMX \|\| X86_GENERIC \|\| MK8 \|\| MK7 \|\| MEFFICEON \|\| MCORE2
96d55b88 PBG	368
96d55b88 PBG	369	config X86_USE_PPRO_CHECKSUM
96daa8cd	370	def_bool y
c55d92d1	371	depends on MWINCHIP3D \|\| MWINCHIP2 \|\| MWINCHIPC6 \|\| MCYRIXIII \|\| MK7 \|\| MK6 \|\| MPENTIUM4 \|\| MPENTIUMM \|\| MPENTIUMIII \|\| MPENTIUMII \|\| M686 \|\| MK8 \|\| MVIAC3_2 \|\| MEFFICEON \|\| MGEODE_LX \|\| MCORE2
96d55b88 PBG	372
96d55b88 PBG	373	config X86_USE_3DNOW
96daa8cd	374	def_bool y
1b4ad242	375	depends on (MCYRIXIII \|\| MK7 \|\| MGEODE_LX) && !UML
96d55b88 PBG	376
96d55b88 PBG	377	config X86_OOSTORE
96daa8cd	378	def_bool y
96d55b88	379	depends on (MWINCHIP3D \|\| MWINCHIP2 \|\| MWINCHIPC6) && MTRR
96d55b88	380
959b3be6 PA	381	#
	382	# P6_NOPs are a relatively minor optimization that require a family >=
	383	# 6 processor, except that it is broken on certain VIA chips.
	384	# Furthermore, AMD chips prefer a totally different sequence of NOPs
	385	# (which work on all CPUs). As a result, disallow these if we're
	386	# compiling X86_GENERIC but not X86_64 (these NOPs do work on all
	387	# x86-64 capable chips); the list of processors in the right-hand clause
	388	# are the cores that benefit from this optimization.
	389	#
7343b3b3 PA	390	config X86_P6_NOP
7343b3b3 PA	391	def_bool y
d2b3bab6	392	depends on (X86_64 \|\| !X86_GENERIC) && (M686 \|\| MPENTIUMII \|\| MPENTIUMIII \|\| MPENTIUMM \|\| MCORE2 \|\| MPENTIUM4 \|\| MPSC)
7343b3b3	393
96d55b88	394	config X86_TSC
96daa8cd	395	def_bool y
1032c0ba	396	depends on ((MWINCHIP3D \|\| MWINCHIP2 \|\| MCRUSOE \|\| MEFFICEON \|\| MCYRIXIII \|\| MK7 \|\| MK6 \|\| MPENTIUM4 \|\| MPENTIUMM \|\| MPENTIUMIII \|\| MPENTIUMII \|\| M686 \|\| M586MMX \|\| M586TSC \|\| MK8 \|\| MVIAC3_2 \|\| MVIAC7 \|\| MGEODEGX1 \|\| MGEODE_LX \|\| MCORE2) && !X86_NUMAQ) \|\| X86_64
c7f81c94	397
f8096f92 JB	398	config X86_CMPXCHG64
	399	def_bool y
	400	depends on X86_PAE \|\| X86_64
	401
c7f81c94 AK	402	# this should be set for all -march=.. options where the compiler
	403	# generates cmov.
	404	config X86_CMOV
96daa8cd	405	def_bool y
12d9c842	406	depends on (MK7 \|\| MPENTIUM4 \|\| MPENTIUMM \|\| MPENTIUMIII \|\| MPENTIUMII \|\| M686 \|\| MVIAC3_2 \|\| MVIAC7 \|\| X86_64)
c7f81c94	407
de32e041	408	config X86_MINIMUM_CPU_FAMILY
c7f81c94	409	int
1032c0ba	410	default "64" if X86_64
7343b3b3	411	default "6" if X86_32 && X86_P6_NOP
1032c0ba	412	default "4" if X86_32 && (X86_XADD \|\| X86_CMPXCHG \|\| X86_BSWAP \|\| X86_WP_WORKS_OK)
de32e041	413	default "3"
c7f81c94	414
0a049bb0	415	config X86_DEBUGCTLMSR
96daa8cd	416	def_bool y
d536b1f8	417	depends on !(MK6 \|\| MWINCHIPC6 \|\| MWINCHIP2 \|\| MWINCHIP3D \|\| MCYRIXIII \|\| M586MMX \|\| M586TSC \|\| M586 \|\| M486 \|\| M386)
8d02c211 TP	418
	419	menuconfig PROCESSOR_SELECT
	420	default y
	421	bool "Supported processor vendors" if EMBEDDED
	422	help
	423	This lets you choose what x86 vendor support code your kernel
	424	will include.
	425
	426	config CPU_SUP_INTEL_32
	427	default y
	428	bool "Support Intel processors" if PROCESSOR_SELECT
	429	depends on !64BIT
	430	help
	431	This enables extended support for Intel processors
	432
	433	config CPU_SUP_INTEL_64
	434	default y
	435	bool "Support Intel processors" if PROCESSOR_SELECT
	436	depends on 64BIT
	437	help
	438	This enables extended support for Intel processors
	439
	440	config CPU_SUP_CYRIX_32
	441	default y
	442	bool "Support Cyrix processors" if PROCESSOR_SELECT
	443	depends on !64BIT
	444	help
	445	This enables extended support for Cyrix processors
	446
ff73152c	447	config CPU_SUP_AMD
8d02c211 TP	448	default y
8d02c211 TP	449	bool "Support AMD processors" if PROCESSOR_SELECT
8d02c211 TP	450	help
	451	This enables extended support for AMD processors
	452
	453	config CPU_SUP_CENTAUR_32
	454	default y
	455	bool "Support Centaur processors" if PROCESSOR_SELECT
	456	depends on !64BIT
	457	help
	458	This enables extended support for Centaur processors
	459
	460	config CPU_SUP_CENTAUR_64
	461	default y
	462	bool "Support Centaur processors" if PROCESSOR_SELECT
	463	depends on 64BIT
	464	help
	465	This enables extended support for Centaur processors
	466
	467	config CPU_SUP_TRANSMETA_32
	468	default y
	469	bool "Support Transmeta processors" if PROCESSOR_SELECT
	470	depends on !64BIT
	471	help
	472	This enables extended support for Transmeta processors
	473
	474	config CPU_SUP_UMC_32
	475	default y
	476	bool "Support UMC processors" if PROCESSOR_SELECT
	477	depends on !64BIT
	478	help
	479	This enables extended support for UMC processors
81faaae4	480
93fa7636 MM	481	config X86_DS
	482	bool "Debug Store support"
	483	default y
	484	help
	485	Add support for Debug Store.
	486	This allows the kernel to provide a memory buffer to the hardware
	487	to store various profiling and tracing events.
	488
	489	config X86_PTRACE_BTS
	490	bool "ptrace interface to Branch Trace Store"
	491	default y
	492	depends on (X86_DS && X86_DEBUGCTLMSR)
	493	help
	494	Add a ptrace interface to allow collecting an execution trace
	495	of the traced task.
	496	This collects control flow changes in a (cyclic) buffer and allows
	497	debuggers to fill in the gaps and show an execution trace of the debuggee.