[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / arch / um / include / asm / cache.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __UM_CACHE_H
#define __UM_CACHE_H


#if defined(CONFIG_UML_X86) && !defined(CONFIG_64BIT)
# define L1_CACHE_SHIFT		(CONFIG_X86_L1_CACHE_SHIFT)
#elif defined(CONFIG_UML_X86) /* 64-bit */
# define L1_CACHE_SHIFT		6 /* Should be 7 on Intel */
#else
/* XXX: this was taken from x86, now it's completely random. Luckily only
 * affects SMP padding. */
# define L1_CACHE_SHIFT		5
#endif

#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)

#endif
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1da177e4 LT	2	#ifndef __UM_CACHE_H
	3	#define __UM_CACHE_H
	4
1da177e4	5
96d55b88 PBG	6	#if defined(CONFIG_UML_X86) && !defined(CONFIG_64BIT)
	7	# define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
	8	#elif defined(CONFIG_UML_X86) /* 64-bit */
	9	# define L1_CACHE_SHIFT 6 /* Should be 7 on Intel */
	10	#else
	11	/* XXX: this was taken from x86, now it's completely random. Luckily only
	12	* affects SMP padding. */
	13	# define L1_CACHE_SHIFT 5
	14	#endif
	15
96d55b88	16	#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
1da177e4 LT	17
1da177e4 LT	18	#endif