[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / arch / um / include / asm / cache.h

#ifndef __UM_CACHE_H
#define __UM_CACHE_H


#if defined(CONFIG_UML_X86) && !defined(CONFIG_64BIT)
# define L1_CACHE_SHIFT		(CONFIG_X86_L1_CACHE_SHIFT)
#elif defined(CONFIG_UML_X86) /* 64-bit */
# define L1_CACHE_SHIFT		6 /* Should be 7 on Intel */
#else
/* XXX: this was taken from x86, now it's completely random. Luckily only
 * affects SMP padding. */
# define L1_CACHE_SHIFT		5
#endif

#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)

#endif
Commit	Line	Data
1da177e4 LT	1	#ifndef __UM_CACHE_H
	2	#define __UM_CACHE_H
	3
1da177e4	4
96d55b88 PBG	5	#if defined(CONFIG_UML_X86) && !defined(CONFIG_64BIT)
	6	# define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
	7	#elif defined(CONFIG_UML_X86) /* 64-bit */
	8	# define L1_CACHE_SHIFT 6 /* Should be 7 on Intel */
	9	#else
	10	/* XXX: this was taken from x86, now it's completely random. Luckily only
	11	* affects SMP padding. */
	12	# define L1_CACHE_SHIFT 5
	13	#endif
	14
96d55b88	15	#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
1da177e4 LT	16
1da177e4 LT	17	#endif