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sparc: remove include of linux/of_device.h from asm/of_device.h
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / sparc64 / mm / init.c
CommitLineData
b00dc837 1/*
1da177e4
LT		 2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
c4bce90e 8#include <linux/module.h>
1da177e4
LT		 9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/string.h>
12#include <linux/init.h>
13#include <linux/bootmem.h>
14#include <linux/mm.h>
15#include <linux/hugetlb.h>
16#include <linux/slab.h>
17#include <linux/initrd.h>
18#include <linux/swap.h>
19#include <linux/pagemap.h>
c9cf5528 20#include <linux/poison.h>
1da177e4
LT		 21#include <linux/fs.h>
22#include <linux/seq_file.h>
05e14cb3 23#include <linux/kprobes.h>
1ac4f5eb 24#include <linux/cache.h>
13edad7a 25#include <linux/sort.h>
5cbc3073 26#include <linux/percpu.h>
3b2a7e23 27#include <linux/lmb.h>
919ee677 28#include <linux/mmzone.h>
1da177e4
LT		 29
30#include <asm/head.h>
31#include <asm/system.h>
32#include <asm/page.h>
33#include <asm/pgalloc.h>
34#include <asm/pgtable.h>
35#include <asm/oplib.h>
36#include <asm/iommu.h>
37#include <asm/io.h>
38#include <asm/uaccess.h>
39#include <asm/mmu_context.h>
40#include <asm/tlbflush.h>
41#include <asm/dma.h>
42#include <asm/starfire.h>
43#include <asm/tlb.h>
44#include <asm/spitfire.h>
45#include <asm/sections.h>
517af332 46#include <asm/tsb.h>
481295f9 47#include <asm/hypervisor.h>
372b07bb 48#include <asm/prom.h>
22d6a1cb 49#include <asm/sstate.h>
5cbc3073 50#include <asm/mdesc.h>
3d5ae6b6 51#include <asm/cpudata.h>
1da177e4 52
9cc3a1ac
DM		 53#define MAX_PHYS_ADDRESS (1UL << 42UL)
54#define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
55#define KPTE_BITMAP_BYTES \
56 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
57
58unsigned long kern_linear_pte_xor[2] __read_mostly;
59
60/* A bitmap, one bit for every 256MB of physical memory. If the bit
61 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
62 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
63 */
64unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
65
d1acb421 66#ifndef CONFIG_DEBUG_PAGEALLOC
2d9e2763
DM		 67/* A special kernel TSB for 4MB and 256MB linear mappings.
68 * Space is allocated for this right after the trap table
69 * in arch/sparc64/kernel/head.S
70 */
71extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
d1acb421 72#endif
d7744a09 73
13edad7a
DM		 74#define MAX_BANKS 32
75
76static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
13edad7a 77static int pavail_ents __initdata;
13edad7a
DM		 78
79static int cmp_p64(const void *a, const void *b)
80{
81 const struct linux_prom64_registers *x = a, *y = b;
82
83 if (x->phys_addr > y->phys_addr)
84 return 1;
85 if (x->phys_addr < y->phys_addr)
86 return -1;
87 return 0;
88}
89
90static void __init read_obp_memory(const char *property,
91 struct linux_prom64_registers *regs,
92 int *num_ents)
93{
94 int node = prom_finddevice("/memory");
95 int prop_size = prom_getproplen(node, property);
96 int ents, ret, i;
97
98 ents = prop_size / sizeof(struct linux_prom64_registers);
99 if (ents > MAX_BANKS) {
100 prom_printf("The machine has more %s property entries than "
101 "this kernel can support (%d).\n",
102 property, MAX_BANKS);
103 prom_halt();
104 }
105
106 ret = prom_getproperty(node, property, (char *) regs, prop_size);
107 if (ret == -1) {
108 prom_printf("Couldn't get %s property from /memory.\n");
109 prom_halt();
110 }
111
13edad7a
DM		 112 /* Sanitize what we got from the firmware, by page aligning
113 * everything.
114 */
115 for (i = 0; i < ents; i++) {
116 unsigned long base, size;
117
118 base = regs[i].phys_addr;
119 size = regs[i].reg_size;
10147570 120
13edad7a
DM		 121 size &= PAGE_MASK;
122 if (base & ~PAGE_MASK) {
123 unsigned long new_base = PAGE_ALIGN(base);
124
125 size -= new_base - base;
126 if ((long) size < 0L)
127 size = 0UL;
128 base = new_base;
129 }
0015d3d6
DM		 130 if (size == 0UL) {
131 /* If it is empty, simply get rid of it.
132 * This simplifies the logic of the other
133 * functions that process these arrays.
134 */
135 memmove(&regs[i], &regs[i + 1],
136 (ents - i - 1) * sizeof(regs[0]));
486ad10a 137 i--;
0015d3d6
DM		 138 ents--;
139 continue;
486ad10a 140 }
0015d3d6
DM		 141 regs[i].phys_addr = base;
142 regs[i].reg_size = size;
486ad10a
DM		 143 }
144
145 *num_ents = ents;
146
c9c10830 147 sort(regs, ents, sizeof(struct linux_prom64_registers),
13edad7a
DM		 148 cmp_p64, NULL);
149}
1da177e4 150
2bdb3cb2 151unsigned long *sparc64_valid_addr_bitmap __read_mostly;
1da177e4 152
d1112018 153/* Kernel physical address base and size in bytes. */
1ac4f5eb
DM		 154unsigned long kern_base __read_mostly;
155unsigned long kern_size __read_mostly;
1da177e4 156
1da177e4
LT		 157/* Initial ramdisk setup */
158extern unsigned long sparc_ramdisk_image64;
159extern unsigned int sparc_ramdisk_image;
160extern unsigned int sparc_ramdisk_size;
161
1ac4f5eb 162struct page *mem_map_zero __read_mostly;
35802c0b 163EXPORT_SYMBOL(mem_map_zero);
1da177e4 164
0835ae0f
DM		 165unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
166
167unsigned long sparc64_kern_pri_context __read_mostly;
168unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
169unsigned long sparc64_kern_sec_context __read_mostly;
170
64658743 171int num_kernel_image_mappings;
1da177e4 172
1da177e4
LT		 173#ifdef CONFIG_DEBUG_DCFLUSH
174atomic_t dcpage_flushes = ATOMIC_INIT(0);
175#ifdef CONFIG_SMP
176atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
177#endif
178#endif
179
7a591cfe 180inline void flush_dcache_page_impl(struct page *page)
1da177e4 181{
7a591cfe 182 BUG_ON(tlb_type == hypervisor);
1da177e4
LT		 183#ifdef CONFIG_DEBUG_DCFLUSH
184 atomic_inc(&dcpage_flushes);
185#endif
186
187#ifdef DCACHE_ALIASING_POSSIBLE
188 __flush_dcache_page(page_address(page),
189 ((tlb_type == spitfire) &&
190 page_mapping(page) != NULL));
191#else
192 if (page_mapping(page) != NULL &&
193 tlb_type == spitfire)
194 __flush_icache_page(__pa(page_address(page)));
195#endif
196}
197
198#define PG_dcache_dirty PG_arch_1
22adb358
DM		 199#define PG_dcache_cpu_shift 32UL
200#define PG_dcache_cpu_mask \
201 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
1da177e4
LT		 202
203#define dcache_dirty_cpu(page) \
48b0e548 204 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
1da177e4 205
d979f179 206static inline void set_dcache_dirty(struct page *page, int this_cpu)
1da177e4
LT		 207{
208 unsigned long mask = this_cpu;
48b0e548
DM		 209 unsigned long non_cpu_bits;
210
211 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
212 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
213
1da177e4
LT		 214 __asm__ __volatile__("1:\n\t"
215 "ldx [%2], %%g7\n\t"
216 "and %%g7, %1, %%g1\n\t"
217 "or %%g1, %0, %%g1\n\t"
218 "casx [%2], %%g7, %%g1\n\t"
219 "cmp %%g7, %%g1\n\t"
b445e26c 220 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 221 "bne,pn %%xcc, 1b\n\t"
b445e26c 222 " nop"
1da177e4
LT		 223 : /* no outputs */
224 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
225 : "g1", "g7");
226}
227
d979f179 228static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
1da177e4
LT		 229{
230 unsigned long mask = (1UL << PG_dcache_dirty);
231
232 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
233 "1:\n\t"
234 "ldx [%2], %%g7\n\t"
48b0e548 235 "srlx %%g7, %4, %%g1\n\t"
1da177e4
LT		 236 "and %%g1, %3, %%g1\n\t"
237 "cmp %%g1, %0\n\t"
238 "bne,pn %%icc, 2f\n\t"
239 " andn %%g7, %1, %%g1\n\t"
240 "casx [%2], %%g7, %%g1\n\t"
241 "cmp %%g7, %%g1\n\t"
b445e26c 242 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 243 "bne,pn %%xcc, 1b\n\t"
b445e26c 244 " nop\n"
1da177e4
LT		 245 "2:"
246 : /* no outputs */
247 : "r" (cpu), "r" (mask), "r" (&page->flags),
48b0e548
DM		 248 "i" (PG_dcache_cpu_mask),
249 "i" (PG_dcache_cpu_shift)
1da177e4
LT		 250 : "g1", "g7");
251}
252
517af332
DM		 253static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
254{
255 unsigned long tsb_addr = (unsigned long) ent;
256
3b3ab2eb 257 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
517af332
DM		 258 tsb_addr = __pa(tsb_addr);
259
260 __tsb_insert(tsb_addr, tag, pte);
261}
262
c4bce90e
DM		 263unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
264unsigned long _PAGE_SZBITS __read_mostly;
265
1da177e4
LT		 266void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
267{
bd40791e 268 struct mm_struct *mm;
74ae9987 269 struct tsb *tsb;
7a1ac526 270 unsigned long tag, flags;
dcc1e8dd 271 unsigned long tsb_index, tsb_hash_shift;
7a591cfe
DM		 272
273 if (tlb_type != hypervisor) {
274 unsigned long pfn = pte_pfn(pte);
275 unsigned long pg_flags;
276 struct page *page;
277
278 if (pfn_valid(pfn) &&
279 (page = pfn_to_page(pfn), page_mapping(page)) &&
280 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
281 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
282 PG_dcache_cpu_mask);
283 int this_cpu = get_cpu();
284
285 /* This is just to optimize away some function calls
286 * in the SMP case.
287 */
288 if (cpu == this_cpu)
289 flush_dcache_page_impl(page);
290 else
291 smp_flush_dcache_page_impl(page, cpu);
292
293 clear_dcache_dirty_cpu(page, cpu);
294
295 put_cpu();
296 }
1da177e4 297 }
bd40791e
DM		 298
299 mm = vma->vm_mm;
7a1ac526 300
dcc1e8dd
DM		 301 tsb_index = MM_TSB_BASE;
302 tsb_hash_shift = PAGE_SHIFT;
303
7a1ac526
DM		 304 spin_lock_irqsave(&mm->context.lock, flags);
305
dcc1e8dd
DM		 306#ifdef CONFIG_HUGETLB_PAGE
307 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
308 if ((tlb_type == hypervisor &&
309 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
310 (tlb_type != hypervisor &&
311 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
312 tsb_index = MM_TSB_HUGE;
313 tsb_hash_shift = HPAGE_SHIFT;
314 }
315 }
316#endif
317
318 tsb = mm->context.tsb_block[tsb_index].tsb;
319 tsb += ((address >> tsb_hash_shift) &
320 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
74ae9987
DM		 321 tag = (address >> 22UL);
322 tsb_insert(tsb, tag, pte_val(pte));
7a1ac526
DM		 323
324 spin_unlock_irqrestore(&mm->context.lock, flags);
1da177e4
LT		 325}
326
327void flush_dcache_page(struct page *page)
328{
a9546f59
DM		 329 struct address_space *mapping;
330 int this_cpu;
1da177e4 331
7a591cfe
DM		 332 if (tlb_type == hypervisor)
333 return;
334
a9546f59
DM		 335 /* Do not bother with the expensive D-cache flush if it
336 * is merely the zero page. The 'bigcore' testcase in GDB
337 * causes this case to run millions of times.
338 */
339 if (page == ZERO_PAGE(0))
340 return;
341
342 this_cpu = get_cpu();
343
344 mapping = page_mapping(page);
1da177e4 345 if (mapping && !mapping_mapped(mapping)) {
a9546f59 346 int dirty = test_bit(PG_dcache_dirty, &page->flags);
1da177e4 347 if (dirty) {
a9546f59
DM		 348 int dirty_cpu = dcache_dirty_cpu(page);
349
1da177e4
LT		 350 if (dirty_cpu == this_cpu)
351 goto out;
352 smp_flush_dcache_page_impl(page, dirty_cpu);
353 }
354 set_dcache_dirty(page, this_cpu);
355 } else {
356 /* We could delay the flush for the !page_mapping
357 * case too. But that case is for exec env/arg
358 * pages and those are %99 certainly going to get
359 * faulted into the tlb (and thus flushed) anyways.
360 */
361 flush_dcache_page_impl(page);
362 }
363
364out:
365 put_cpu();
366}
367
05e14cb3 368void __kprobes flush_icache_range(unsigned long start, unsigned long end)
1da177e4 369{
a43fe0e7 370 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
1da177e4
LT		 371 if (tlb_type == spitfire) {
372 unsigned long kaddr;
373
a94aa253
DM		 374 /* This code only runs on Spitfire cpus so this is
375 * why we can assume _PAGE_PADDR_4U.
376 */
377 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
378 unsigned long paddr, mask = _PAGE_PADDR_4U;
379
380 if (kaddr >= PAGE_OFFSET)
381 paddr = kaddr & mask;
382 else {
383 pgd_t *pgdp = pgd_offset_k(kaddr);
384 pud_t *pudp = pud_offset(pgdp, kaddr);
385 pmd_t *pmdp = pmd_offset(pudp, kaddr);
386 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
387
388 paddr = pte_val(*ptep) & mask;
389 }
390 __flush_icache_page(paddr);
391 }
1da177e4
LT		 392 }
393}
394
1da177e4
LT		 395void mmu_info(struct seq_file *m)
396{
397 if (tlb_type == cheetah)
398 seq_printf(m, "MMU Type\t: Cheetah\n");
399 else if (tlb_type == cheetah_plus)
400 seq_printf(m, "MMU Type\t: Cheetah+\n");
401 else if (tlb_type == spitfire)
402 seq_printf(m, "MMU Type\t: Spitfire\n");
a43fe0e7
DM		 403 else if (tlb_type == hypervisor)
404 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
1da177e4
LT		 405 else
406 seq_printf(m, "MMU Type\t: ???\n");
407
408#ifdef CONFIG_DEBUG_DCFLUSH
409 seq_printf(m, "DCPageFlushes\t: %d\n",
410 atomic_read(&dcpage_flushes));
411#ifdef CONFIG_SMP
412 seq_printf(m, "DCPageFlushesXC\t: %d\n",
413 atomic_read(&dcpage_flushes_xcall));
414#endif /* CONFIG_SMP */
415#endif /* CONFIG_DEBUG_DCFLUSH */
416}
417
a94aa253
DM		 418struct linux_prom_translation {
419 unsigned long virt;
420 unsigned long size;
421 unsigned long data;
422};
423
424/* Exported for kernel TLB miss handling in ktlb.S */
425struct linux_prom_translation prom_trans[512] __read_mostly;
426unsigned int prom_trans_ents __read_mostly;
427
1da177e4
LT		 428/* Exported for SMP bootup purposes. */
429unsigned long kern_locked_tte_data;
430
c9c10830
DM		 431/* The obp translations are saved based on 8k pagesize, since obp can
432 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
74bf4312 433 * HI_OBP_ADDRESS range are handled in ktlb.S.
c9c10830 434 */
5085b4a5
DM		 435static inline int in_obp_range(unsigned long vaddr)
436{
437 return (vaddr >= LOW_OBP_ADDRESS &&
438 vaddr < HI_OBP_ADDRESS);
439}
440
c9c10830 441static int cmp_ptrans(const void *a, const void *b)
405599bd 442{
c9c10830 443 const struct linux_prom_translation *x = a, *y = b;
405599bd 444
c9c10830
DM		 445 if (x->virt > y->virt)
446 return 1;
447 if (x->virt < y->virt)
448 return -1;
449 return 0;
405599bd
DM		 450}
451
c9c10830 452/* Read OBP translations property into 'prom_trans[]'. */
9ad98c5b 453static void __init read_obp_translations(void)
405599bd 454{
c9c10830 455 int n, node, ents, first, last, i;
1da177e4
LT		 456
457 node = prom_finddevice("/virtual-memory");
458 n = prom_getproplen(node, "translations");
405599bd 459 if (unlikely(n == 0 || n == -1)) {
b206fc4c 460 prom_printf("prom_mappings: Couldn't get size.\n");
1da177e4
LT		 461 prom_halt();
462 }
405599bd
DM		 463 if (unlikely(n > sizeof(prom_trans))) {
464 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
1da177e4
LT		 465 prom_halt();
466 }
405599bd 467
b206fc4c 468 if ((n = prom_getproperty(node, "translations",
405599bd
DM		 469 (char *)&prom_trans[0],
470 sizeof(prom_trans))) == -1) {
b206fc4c 471 prom_printf("prom_mappings: Couldn't get property.\n");
1da177e4
LT		 472 prom_halt();
473 }
9ad98c5b 474
b206fc4c 475 n = n / sizeof(struct linux_prom_translation);
9ad98c5b 476
c9c10830
DM		 477 ents = n;
478
479 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
480 cmp_ptrans, NULL);
481
482 /* Now kick out all the non-OBP entries. */
483 for (i = 0; i < ents; i++) {
484 if (in_obp_range(prom_trans[i].virt))
485 break;
486 }
487 first = i;
488 for (; i < ents; i++) {
489 if (!in_obp_range(prom_trans[i].virt))
490 break;
491 }
492 last = i;
493
494 for (i = 0; i < (last - first); i++) {
495 struct linux_prom_translation *src = &prom_trans[i + first];
496 struct linux_prom_translation *dest = &prom_trans[i];
497
498 *dest = *src;
499 }
500 for (; i < ents; i++) {
501 struct linux_prom_translation *dest = &prom_trans[i];
502 dest->virt = dest->size = dest->data = 0x0UL;
503 }
504
505 prom_trans_ents = last - first;
506
507 if (tlb_type == spitfire) {
508 /* Clear diag TTE bits. */
509 for (i = 0; i < prom_trans_ents; i++)
510 prom_trans[i].data &= ~0x0003fe0000000000UL;
511 }
405599bd 512}
1da177e4 513
d82ace7d
DM		 514static void __init hypervisor_tlb_lock(unsigned long vaddr,
515 unsigned long pte,
516 unsigned long mmu)
517{
7db35f31
DM		 518 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
519
520 if (ret != 0) {
12e126ad 521 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
7db35f31 522 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
12e126ad
DM		 523 prom_halt();
524 }
d82ace7d
DM		 525}
526
c4bce90e
DM		 527static unsigned long kern_large_tte(unsigned long paddr);
528
898cf0ec 529static void __init remap_kernel(void)
405599bd
DM		 530{
531 unsigned long phys_page, tte_vaddr, tte_data;
64658743 532 int i, tlb_ent = sparc64_highest_locked_tlbent();
405599bd 533
1da177e4 534 tte_vaddr = (unsigned long) KERNBASE;
bff06d55 535 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
c4bce90e 536 tte_data = kern_large_tte(phys_page);
1da177e4
LT		 537
538 kern_locked_tte_data = tte_data;
539
d82ace7d
DM		 540 /* Now lock us into the TLBs via Hypervisor or OBP. */
541 if (tlb_type == hypervisor) {
64658743 542 for (i = 0; i < num_kernel_image_mappings; i++) {
d82ace7d
DM		 543 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
544 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
64658743
DM		 545 tte_vaddr += 0x400000;
546 tte_data += 0x400000;
d82ace7d
DM		 547 }
548 } else {
64658743
DM		 549 for (i = 0; i < num_kernel_image_mappings; i++) {
550 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
551 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
552 tte_vaddr += 0x400000;
553 tte_data += 0x400000;
d82ace7d 554 }
64658743 555 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
1da177e4 556 }
0835ae0f
DM		 557 if (tlb_type == cheetah_plus) {
558 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
559 CTX_CHEETAH_PLUS_NUC);
560 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
561 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
562 }
405599bd 563}
1da177e4 564
405599bd 565
c9c10830 566static void __init inherit_prom_mappings(void)
9ad98c5b 567{
405599bd 568 /* Now fixup OBP's idea about where we really are mapped. */
3c62a2d3 569 printk("Remapping the kernel... ");
405599bd 570 remap_kernel();
3c62a2d3 571 printk("done.\n");
1da177e4
LT		 572}
573
1da177e4
LT		 574void prom_world(int enter)
575{
1da177e4
LT		 576 if (!enter)
577 set_fs((mm_segment_t) { get_thread_current_ds() });
578
3487d1d4 579 __asm__ __volatile__("flushw");
1da177e4
LT		 580}
581
1da177e4
LT		 582void __flush_dcache_range(unsigned long start, unsigned long end)
583{
584 unsigned long va;
585
586 if (tlb_type == spitfire) {
587 int n = 0;
588
589 for (va = start; va < end; va += 32) {
590 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
591 if (++n >= 512)
592 break;
593 }
a43fe0e7 594 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1da177e4
LT		 595 start = __pa(start);
596 end = __pa(end);
597 for (va = start; va < end; va += 32)
598 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
599 "membar #Sync"
600 : /* no outputs */
601 : "r" (va),
602 "i" (ASI_DCACHE_INVALIDATE));
603 }
604}
1da177e4 605
85f1e1f6
DM		 606/* get_new_mmu_context() uses "cache + 1". */
607DEFINE_SPINLOCK(ctx_alloc_lock);
608unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
609#define MAX_CTX_NR (1UL << CTX_NR_BITS)
610#define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
611DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
612
1da177e4
LT		 613/* Caller does TLB context flushing on local CPU if necessary.
614 * The caller also ensures that CTX_VALID(mm->context) is false.
615 *
616 * We must be careful about boundary cases so that we never
617 * let the user have CTX 0 (nucleus) or we ever use a CTX
618 * version of zero (and thus NO_CONTEXT would not be caught
619 * by version mis-match tests in mmu_context.h).
a0663a79
DM		 620 *
621 * Always invoked with interrupts disabled.
1da177e4
LT		 622 */
623void get_new_mmu_context(struct mm_struct *mm)
624{
625 unsigned long ctx, new_ctx;
626 unsigned long orig_pgsz_bits;
a77754b4 627 unsigned long flags;
a0663a79 628 int new_version;
1da177e4 629
a77754b4 630 spin_lock_irqsave(&ctx_alloc_lock, flags);
1da177e4
LT		 631 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
632 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
633 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
a0663a79 634 new_version = 0;
1da177e4
LT		 635 if (new_ctx >= (1 << CTX_NR_BITS)) {
636 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
637 if (new_ctx >= ctx) {
638 int i;
639 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
640 CTX_FIRST_VERSION;
641 if (new_ctx == 1)
642 new_ctx = CTX_FIRST_VERSION;
643
644 /* Don't call memset, for 16 entries that's just
645 * plain silly...
646 */
647 mmu_context_bmap[0] = 3;
648 mmu_context_bmap[1] = 0;
649 mmu_context_bmap[2] = 0;
650 mmu_context_bmap[3] = 0;
651 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
652 mmu_context_bmap[i + 0] = 0;
653 mmu_context_bmap[i + 1] = 0;
654 mmu_context_bmap[i + 2] = 0;
655 mmu_context_bmap[i + 3] = 0;
656 }
a0663a79 657 new_version = 1;
1da177e4
LT		 658 goto out;
659 }
660 }
661 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
662 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
663out:
664 tlb_context_cache = new_ctx;
665 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
a77754b4 666 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
a0663a79
DM		 667
668 if (unlikely(new_version))
669 smp_new_mmu_context_version();
1da177e4
LT		 670}
671
919ee677
DM		 672static int numa_enabled = 1;
673static int numa_debug;
674
675static int __init early_numa(char *p)
1da177e4 676{
919ee677
DM		 677 if (!p)
678 return 0;
679
680 if (strstr(p, "off"))
681 numa_enabled = 0;
d1112018 682
919ee677
DM		 683 if (strstr(p, "debug"))
684 numa_debug = 1;
d1112018 685
919ee677 686 return 0;
d1112018 687}
919ee677
DM		 688early_param("numa", early_numa);
689
690#define numadbg(f, a...) \
691do { if (numa_debug) \
692 printk(KERN_INFO f, ## a); \
693} while (0)
d1112018 694
4e82c9a6
DM		 695static void __init find_ramdisk(unsigned long phys_base)
696{
697#ifdef CONFIG_BLK_DEV_INITRD
698 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
699 unsigned long ramdisk_image;
700
701 /* Older versions of the bootloader only supported a
702 * 32-bit physical address for the ramdisk image
703 * location, stored at sparc_ramdisk_image. Newer
704 * SILO versions set sparc_ramdisk_image to zero and
705 * provide a full 64-bit physical address at
706 * sparc_ramdisk_image64.
707 */
708 ramdisk_image = sparc_ramdisk_image;
709 if (!ramdisk_image)
710 ramdisk_image = sparc_ramdisk_image64;
711
712 /* Another bootloader quirk. The bootloader normalizes
713 * the physical address to KERNBASE, so we have to
714 * factor that back out and add in the lowest valid
715 * physical page address to get the true physical address.
716 */
717 ramdisk_image -= KERNBASE;
718 ramdisk_image += phys_base;
719
919ee677
DM		 720 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
721 ramdisk_image, sparc_ramdisk_size);
722
4e82c9a6
DM		 723 initrd_start = ramdisk_image;
724 initrd_end = ramdisk_image + sparc_ramdisk_size;
3b2a7e23 725
7047901e 726 lmb_reserve(initrd_start, sparc_ramdisk_size);
d45100f7
DM		 727
728 initrd_start += PAGE_OFFSET;
729 initrd_end += PAGE_OFFSET;
4e82c9a6
DM		 730 }
731#endif
732}
733
919ee677
DM		 734struct node_mem_mask {
735 unsigned long mask;
736 unsigned long val;
737 unsigned long bootmem_paddr;
738};
739static struct node_mem_mask node_masks[MAX_NUMNODES];
740static int num_node_masks;
741
742int numa_cpu_lookup_table[NR_CPUS];
743cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
744
745#ifdef CONFIG_NEED_MULTIPLE_NODES
919ee677
DM		 746
747struct mdesc_mblock {
748 u64 base;
749 u64 size;
750 u64 offset; /* RA-to-PA */
751};
752static struct mdesc_mblock *mblocks;
753static int num_mblocks;
754
755static unsigned long ra_to_pa(unsigned long addr)
756{
757 int i;
758
759 for (i = 0; i < num_mblocks; i++) {
760 struct mdesc_mblock *m = &mblocks[i];
761
762 if (addr >= m->base &&
763 addr < (m->base + m->size)) {
764 addr += m->offset;
765 break;
766 }
767 }
768 return addr;
769}
770
771static int find_node(unsigned long addr)
772{
773 int i;
774
775 addr = ra_to_pa(addr);
776 for (i = 0; i < num_node_masks; i++) {
777 struct node_mem_mask *p = &node_masks[i];
778
779 if ((addr & p->mask) == p->val)
780 return i;
781 }
782 return -1;
783}
784
785static unsigned long nid_range(unsigned long start, unsigned long end,
786 int *nid)
787{
788 *nid = find_node(start);
789 start += PAGE_SIZE;
790 while (start < end) {
791 int n = find_node(start);
792
793 if (n != *nid)
794 break;
795 start += PAGE_SIZE;
796 }
797
798 return start;
799}
800#else
801static unsigned long nid_range(unsigned long start, unsigned long end,
802 int *nid)
803{
804 *nid = 0;
805 return end;
806}
807#endif
808
809/* This must be invoked after performing all of the necessary
810 * add_active_range() calls for 'nid'. We need to be able to get
811 * correct data from get_pfn_range_for_nid().
f1cfdb55 812 */
919ee677
DM		 813static void __init allocate_node_data(int nid)
814{
815 unsigned long paddr, num_pages, start_pfn, end_pfn;
816 struct pglist_data *p;
817
818#ifdef CONFIG_NEED_MULTIPLE_NODES
819 paddr = lmb_alloc_nid(sizeof(struct pglist_data),
820 SMP_CACHE_BYTES, nid, nid_range);
821 if (!paddr) {
822 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
823 prom_halt();
824 }
825 NODE_DATA(nid) = __va(paddr);
826 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
827
b61bfa3c 828 NODE_DATA(nid)->bdata = &bootmem_node_data[nid];
919ee677
DM		 829#endif
830
831 p = NODE_DATA(nid);
832
833 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
834 p->node_start_pfn = start_pfn;
835 p->node_spanned_pages = end_pfn - start_pfn;
836
837 if (p->node_spanned_pages) {
838 num_pages = bootmem_bootmap_pages(p->node_spanned_pages);
839
840 paddr = lmb_alloc_nid(num_pages << PAGE_SHIFT, PAGE_SIZE, nid,
841 nid_range);
842 if (!paddr) {
843 prom_printf("Cannot allocate bootmap for nid[%d]\n",
844 nid);
845 prom_halt();
846 }
847 node_masks[nid].bootmem_paddr = paddr;
848 }
849}
850
851static void init_node_masks_nonnuma(void)
d1112018 852{
1da177e4
LT		 853 int i;
854
919ee677 855 numadbg("Initializing tables for non-numa.\n");
6fc5bae7 856
919ee677
DM		 857 node_masks[0].mask = node_masks[0].val = 0;
858 num_node_masks = 1;
d1112018 859
919ee677
DM		 860 for (i = 0; i < NR_CPUS; i++)
861 numa_cpu_lookup_table[i] = 0;
1da177e4 862
919ee677
DM		 863 numa_cpumask_lookup_table[0] = CPU_MASK_ALL;
864}
865
866#ifdef CONFIG_NEED_MULTIPLE_NODES
867struct pglist_data *node_data[MAX_NUMNODES];
868
869EXPORT_SYMBOL(numa_cpu_lookup_table);
870EXPORT_SYMBOL(numa_cpumask_lookup_table);
871EXPORT_SYMBOL(node_data);
872
873struct mdesc_mlgroup {
874 u64 node;
875 u64 latency;
876 u64 match;
877 u64 mask;
878};
879static struct mdesc_mlgroup *mlgroups;
880static int num_mlgroups;
881
882static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
883 u32 cfg_handle)
884{
885 u64 arc;
886
887 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
888 u64 target = mdesc_arc_target(md, arc);
889 const u64 *val;
890
891 val = mdesc_get_property(md, target,
892 "cfg-handle", NULL);
893 if (val && *val == cfg_handle)
894 return 0;
895 }
896 return -ENODEV;
897}
898
899static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
900 u32 cfg_handle)
901{
902 u64 arc, candidate, best_latency = ~(u64)0;
903
904 candidate = MDESC_NODE_NULL;
905 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
906 u64 target = mdesc_arc_target(md, arc);
907 const char *name = mdesc_node_name(md, target);
908 const u64 *val;
909
910 if (strcmp(name, "pio-latency-group"))
911 continue;
912
913 val = mdesc_get_property(md, target, "latency", NULL);
914 if (!val)
915 continue;
916
917 if (*val < best_latency) {
918 candidate = target;
919 best_latency = *val;
920 }
921 }
922
923 if (candidate == MDESC_NODE_NULL)
924 return -ENODEV;
925
926 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
927}
928
929int of_node_to_nid(struct device_node *dp)
930{
931 const struct linux_prom64_registers *regs;
932 struct mdesc_handle *md;
933 u32 cfg_handle;
934 int count, nid;
935 u64 grp;
936
937 if (!mlgroups)
938 return -1;
939
940 regs = of_get_property(dp, "reg", NULL);
941 if (!regs)
942 return -1;
943
944 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
945
946 md = mdesc_grab();
947
948 count = 0;
949 nid = -1;
950 mdesc_for_each_node_by_name(md, grp, "group") {
951 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
952 nid = count;
953 break;
954 }
955 count++;
956 }
957
958 mdesc_release(md);
959
960 return nid;
961}
962
963static void add_node_ranges(void)
964{
965 int i;
966
967 for (i = 0; i < lmb.memory.cnt; i++) {
968 unsigned long size = lmb_size_bytes(&lmb.memory, i);
969 unsigned long start, end;
970
971 start = lmb.memory.region[i].base;
972 end = start + size;
973 while (start < end) {
974 unsigned long this_end;
975 int nid;
976
977 this_end = nid_range(start, end, &nid);
978
979 numadbg("Adding active range nid[%d] "
980 "start[%lx] end[%lx]\n",
981 nid, start, this_end);
982
983 add_active_range(nid,
984 start >> PAGE_SHIFT,
985 this_end >> PAGE_SHIFT);
986
987 start = this_end;
988 }
989 }
990}
991
992static int __init grab_mlgroups(struct mdesc_handle *md)
993{
994 unsigned long paddr;
995 int count = 0;
996 u64 node;
997
998 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
999 count++;
1000 if (!count)
1001 return -ENOENT;
1002
1003 paddr = lmb_alloc(count * sizeof(struct mdesc_mlgroup),
1004 SMP_CACHE_BYTES);
1005 if (!paddr)
1006 return -ENOMEM;
1007
1008 mlgroups = __va(paddr);
1009 num_mlgroups = count;
1010
1011 count = 0;
1012 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1013 struct mdesc_mlgroup *m = &mlgroups[count++];
1014 const u64 *val;
1015
1016 m->node = node;
1017
1018 val = mdesc_get_property(md, node, "latency", NULL);
1019 m->latency = *val;
1020 val = mdesc_get_property(md, node, "address-match", NULL);
1021 m->match = *val;
1022 val = mdesc_get_property(md, node, "address-mask", NULL);
1023 m->mask = *val;
1024
1025 numadbg("MLGROUP[%d]: node[%lx] latency[%lx] "
1026 "match[%lx] mask[%lx]\n",
1027 count - 1, m->node, m->latency, m->match, m->mask);
1028 }
1029
1030 return 0;
1031}
1032
1033static int __init grab_mblocks(struct mdesc_handle *md)
1034{
1035 unsigned long paddr;
1036 int count = 0;
1037 u64 node;
1038
1039 mdesc_for_each_node_by_name(md, node, "mblock")
1040 count++;
1041 if (!count)
1042 return -ENOENT;
1043
1044 paddr = lmb_alloc(count * sizeof(struct mdesc_mblock),
1045 SMP_CACHE_BYTES);
1046 if (!paddr)
1047 return -ENOMEM;
1048
1049 mblocks = __va(paddr);
1050 num_mblocks = count;
1051
1052 count = 0;
1053 mdesc_for_each_node_by_name(md, node, "mblock") {
1054 struct mdesc_mblock *m = &mblocks[count++];
1055 const u64 *val;
1056
1057 val = mdesc_get_property(md, node, "base", NULL);
1058 m->base = *val;
1059 val = mdesc_get_property(md, node, "size", NULL);
1060 m->size = *val;
1061 val = mdesc_get_property(md, node,
1062 "address-congruence-offset", NULL);
1063 m->offset = *val;
1064
1065 numadbg("MBLOCK[%d]: base[%lx] size[%lx] offset[%lx]\n",
1066 count - 1, m->base, m->size, m->offset);
1067 }
1068
1069 return 0;
1070}
1071
1072static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1073 u64 grp, cpumask_t *mask)
1074{
1075 u64 arc;
1076
1077 cpus_clear(*mask);
1078
1079 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1080 u64 target = mdesc_arc_target(md, arc);
1081 const char *name = mdesc_node_name(md, target);
1082 const u64 *id;
1083
1084 if (strcmp(name, "cpu"))
1085 continue;
1086 id = mdesc_get_property(md, target, "id", NULL);
1087 if (*id < NR_CPUS)
1088 cpu_set(*id, *mask);
1089 }
1090}
1091
1092static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1093{
1094 int i;
1095
1096 for (i = 0; i < num_mlgroups; i++) {
1097 struct mdesc_mlgroup *m = &mlgroups[i];
1098 if (m->node == node)
1099 return m;
1100 }
1101 return NULL;
1102}
1103
1104static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1105 int index)
1106{
1107 struct mdesc_mlgroup *candidate = NULL;
1108 u64 arc, best_latency = ~(u64)0;
1109 struct node_mem_mask *n;
1110
1111 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1112 u64 target = mdesc_arc_target(md, arc);
1113 struct mdesc_mlgroup *m = find_mlgroup(target);
1114 if (!m)
1115 continue;
1116 if (m->latency < best_latency) {
1117 candidate = m;
1118 best_latency = m->latency;
1119 }
1120 }
1121 if (!candidate)
1122 return -ENOENT;
1123
1124 if (num_node_masks != index) {
1125 printk(KERN_ERR "Inconsistent NUMA state, "
1126 "index[%d] != num_node_masks[%d]\n",
1127 index, num_node_masks);
1128 return -EINVAL;
1129 }
1130
1131 n = &node_masks[num_node_masks++];
1132
1133 n->mask = candidate->mask;
1134 n->val = candidate->match;
1da177e4 1135
919ee677
DM		 1136 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%lx])\n",
1137 index, n->mask, n->val, candidate->latency);
1da177e4 1138
919ee677
DM		 1139 return 0;
1140}
1141
1142static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1143 int index)
1144{
1145 cpumask_t mask;
1146 int cpu;
1147
1148 numa_parse_mdesc_group_cpus(md, grp, &mask);
1149
1150 for_each_cpu_mask(cpu, mask)
1151 numa_cpu_lookup_table[cpu] = index;
1152 numa_cpumask_lookup_table[index] = mask;
1153
1154 if (numa_debug) {
1155 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1156 for_each_cpu_mask(cpu, mask)
1157 printk("%d ", cpu);
1158 printk("]\n");
1159 }
1160
1161 return numa_attach_mlgroup(md, grp, index);
1162}
1163
1164static int __init numa_parse_mdesc(void)
1165{
1166 struct mdesc_handle *md = mdesc_grab();
1167 int i, err, count;
1168 u64 node;
1169
1170 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1171 if (node == MDESC_NODE_NULL) {
1172 mdesc_release(md);
1173 return -ENOENT;
1174 }
1175
1176 err = grab_mblocks(md);
1177 if (err < 0)
1178 goto out;
1179
1180 err = grab_mlgroups(md);
1181 if (err < 0)
1182 goto out;
1183
1184 count = 0;
1185 mdesc_for_each_node_by_name(md, node, "group") {
1186 err = numa_parse_mdesc_group(md, node, count);
1187 if (err < 0)
1188 break;
1189 count++;
1190 }
1191
1192 add_node_ranges();
1193
1194 for (i = 0; i < num_node_masks; i++) {
1195 allocate_node_data(i);
1196 node_set_online(i);
1197 }
1198
1199 err = 0;
1200out:
1201 mdesc_release(md);
1202 return err;
1203}
1204
1205static int __init numa_parse_sun4u(void)
1206{
1207 return -1;
1208}
1209
1210static int __init bootmem_init_numa(void)
1211{
1212 int err = -1;
1213
1214 numadbg("bootmem_init_numa()\n");
1215
1216 if (numa_enabled) {
1217 if (tlb_type == hypervisor)
1218 err = numa_parse_mdesc();
1219 else
1220 err = numa_parse_sun4u();
1221 }
1222 return err;
1223}
1224
1225#else
1da177e4 1226
919ee677
DM		 1227static int bootmem_init_numa(void)
1228{
1229 return -1;
1230}
1231
1232#endif
1233
1234static void __init bootmem_init_nonnuma(void)
1235{
1236 unsigned long top_of_ram = lmb_end_of_DRAM();
1237 unsigned long total_ram = lmb_phys_mem_size();
1238 unsigned int i;
1239
1240 numadbg("bootmem_init_nonnuma()\n");
1241
1242 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1243 top_of_ram, total_ram);
1244 printk(KERN_INFO "Memory hole size: %ldMB\n",
1245 (top_of_ram - total_ram) >> 20);
1246
1247 init_node_masks_nonnuma();
1248
1249 for (i = 0; i < lmb.memory.cnt; i++) {
1250 unsigned long size = lmb_size_bytes(&lmb.memory, i);
1251 unsigned long start_pfn, end_pfn;
1252
1253 if (!size)
1254 continue;
1da177e4 1255
9422273b 1256 start_pfn = lmb.memory.region[i].base >> PAGE_SHIFT;
919ee677
DM		 1257 end_pfn = start_pfn + lmb_size_pages(&lmb.memory, i);
1258 add_active_range(0, start_pfn, end_pfn);
1259 }
d1112018 1260
919ee677
DM		 1261 allocate_node_data(0);
1262
1263 node_set_online(0);
1264}
1265
1266static void __init reserve_range_in_node(int nid, unsigned long start,
1267 unsigned long end)
1268{
1269 numadbg(" reserve_range_in_node(nid[%d],start[%lx],end[%lx]\n",
1270 nid, start, end);
1271 while (start < end) {
1272 unsigned long this_end;
1273 int n;
1274
1275 this_end = nid_range(start, end, &n);
1276 if (n == nid) {
1277 numadbg(" MATCH reserving range [%lx:%lx]\n",
1278 start, this_end);
1279 reserve_bootmem_node(NODE_DATA(nid), start,
1280 (this_end - start), BOOTMEM_DEFAULT);
1281 } else
1282 numadbg(" NO MATCH, advancing start to %lx\n",
1283 this_end);
1284
1285 start = this_end;
d1112018 1286 }
919ee677
DM		 1287}
1288
1289static void __init trim_reserved_in_node(int nid)
1290{
1291 int i;
1292
1293 numadbg(" trim_reserved_in_node(%d)\n", nid);
1294
1295 for (i = 0; i < lmb.reserved.cnt; i++) {
1296 unsigned long start = lmb.reserved.region[i].base;
1297 unsigned long size = lmb_size_bytes(&lmb.reserved, i);
1298 unsigned long end = start + size;
1299
1300 reserve_range_in_node(nid, start, end);
1301 }
1302}
1303
1304static void __init bootmem_init_one_node(int nid)
1305{
1306 struct pglist_data *p;
1307
1308 numadbg("bootmem_init_one_node(%d)\n", nid);
1309
1310 p = NODE_DATA(nid);
1311
1312 if (p->node_spanned_pages) {
1313 unsigned long paddr = node_masks[nid].bootmem_paddr;
1314 unsigned long end_pfn;
1315
1316 end_pfn = p->node_start_pfn + p->node_spanned_pages;
1317
1318 numadbg(" init_bootmem_node(%d, %lx, %lx, %lx)\n",
1319 nid, paddr >> PAGE_SHIFT, p->node_start_pfn, end_pfn);
1320
1321 init_bootmem_node(p, paddr >> PAGE_SHIFT,
1322 p->node_start_pfn, end_pfn);
1323
1324 numadbg(" free_bootmem_with_active_regions(%d, %lx)\n",
1325 nid, end_pfn);
1326 free_bootmem_with_active_regions(nid, end_pfn);
1327
1328 trim_reserved_in_node(nid);
1329
1330 numadbg(" sparse_memory_present_with_active_regions(%d)\n",
1331 nid);
1332 sparse_memory_present_with_active_regions(nid);
1333 }
1334}
1335
1336static unsigned long __init bootmem_init(unsigned long phys_base)
1337{
1338 unsigned long end_pfn;
1339 int nid;
1340
1341 end_pfn = lmb_end_of_DRAM() >> PAGE_SHIFT;
1342 max_pfn = max_low_pfn = end_pfn;
1343 min_low_pfn = (phys_base >> PAGE_SHIFT);
1344
1345 if (bootmem_init_numa() < 0)
1346 bootmem_init_nonnuma();
1347
1348 /* XXX cpu notifier XXX */
1349
1350 for_each_online_node(nid)
1351 bootmem_init_one_node(nid);
d1112018
DM		 1352
1353 sparse_init();
1354
1da177e4
LT		 1355 return end_pfn;
1356}
1357
9cc3a1ac
DM		 1358static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1359static int pall_ents __initdata;
1360
56425306 1361#ifdef CONFIG_DEBUG_PAGEALLOC
896aef43
SR		 1362static unsigned long __ref kernel_map_range(unsigned long pstart,
1363 unsigned long pend, pgprot_t prot)
56425306
DM		 1364{
1365 unsigned long vstart = PAGE_OFFSET + pstart;
1366 unsigned long vend = PAGE_OFFSET + pend;
1367 unsigned long alloc_bytes = 0UL;
1368
1369 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
13edad7a 1370 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
56425306
DM		 1371 vstart, vend);
1372 prom_halt();
1373 }
1374
1375 while (vstart < vend) {
1376 unsigned long this_end, paddr = __pa(vstart);
1377 pgd_t *pgd = pgd_offset_k(vstart);
1378 pud_t *pud;
1379 pmd_t *pmd;
1380 pte_t *pte;
1381
1382 pud = pud_offset(pgd, vstart);
1383 if (pud_none(*pud)) {
1384 pmd_t *new;
1385
1386 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1387 alloc_bytes += PAGE_SIZE;
1388 pud_populate(&init_mm, pud, new);
1389 }
1390
1391 pmd = pmd_offset(pud, vstart);
1392 if (!pmd_present(*pmd)) {
1393 pte_t *new;
1394
1395 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1396 alloc_bytes += PAGE_SIZE;
1397 pmd_populate_kernel(&init_mm, pmd, new);
1398 }
1399
1400 pte = pte_offset_kernel(pmd, vstart);
1401 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1402 if (this_end > vend)
1403 this_end = vend;
1404
1405 while (vstart < this_end) {
1406 pte_val(*pte) = (paddr | pgprot_val(prot));
1407
1408 vstart += PAGE_SIZE;
1409 paddr += PAGE_SIZE;
1410 pte++;
1411 }
1412 }
1413
1414 return alloc_bytes;
1415}
1416
56425306 1417extern unsigned int kvmap_linear_patch[1];
9cc3a1ac
DM		 1418#endif /* CONFIG_DEBUG_PAGEALLOC */
1419
1420static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1421{
1422 const unsigned long shift_256MB = 28;
1423 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1424 const unsigned long size_256MB = (1UL << shift_256MB);
1425
1426 while (start < end) {
1427 long remains;
1428
f7c00338
DM		 1429 remains = end - start;
1430 if (remains < size_256MB)
1431 break;
1432
9cc3a1ac
DM		 1433 if (start & mask_256MB) {
1434 start = (start + size_256MB) & ~mask_256MB;
1435 continue;
1436 }
1437
9cc3a1ac
DM		 1438 while (remains >= size_256MB) {
1439 unsigned long index = start >> shift_256MB;
1440
1441 __set_bit(index, kpte_linear_bitmap);
1442
1443 start += size_256MB;
1444 remains -= size_256MB;
1445 }
1446 }
1447}
56425306 1448
8f361453 1449static void __init init_kpte_bitmap(void)
56425306 1450{
9cc3a1ac 1451 unsigned long i;
13edad7a
DM		 1452
1453 for (i = 0; i < pall_ents; i++) {
56425306
DM		 1454 unsigned long phys_start, phys_end;
1455
13edad7a
DM		 1456 phys_start = pall[i].phys_addr;
1457 phys_end = phys_start + pall[i].reg_size;
9cc3a1ac
DM		 1458
1459 mark_kpte_bitmap(phys_start, phys_end);
8f361453
DM		 1460 }
1461}
9cc3a1ac 1462
8f361453
DM		 1463static void __init kernel_physical_mapping_init(void)
1464{
9cc3a1ac 1465#ifdef CONFIG_DEBUG_PAGEALLOC
8f361453
DM		 1466 unsigned long i, mem_alloced = 0UL;
1467
1468 for (i = 0; i < pall_ents; i++) {
1469 unsigned long phys_start, phys_end;
1470
1471 phys_start = pall[i].phys_addr;
1472 phys_end = phys_start + pall[i].reg_size;
1473
56425306
DM		 1474 mem_alloced += kernel_map_range(phys_start, phys_end,
1475 PAGE_KERNEL);
56425306
DM		 1476 }
1477
1478 printk("Allocated %ld bytes for kernel page tables.\n",
1479 mem_alloced);
1480
1481 kvmap_linear_patch[0] = 0x01000000; /* nop */
1482 flushi(&kvmap_linear_patch[0]);
1483
1484 __flush_tlb_all();
9cc3a1ac 1485#endif
56425306
DM		 1486}
1487
9cc3a1ac 1488#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1489void kernel_map_pages(struct page *page, int numpages, int enable)
1490{
1491 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1492 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1493
1494 kernel_map_range(phys_start, phys_end,
1495 (enable ? PAGE_KERNEL : __pgprot(0)));
1496
74bf4312
DM		 1497 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1498 PAGE_OFFSET + phys_end);
1499
56425306
DM		 1500 /* we should perform an IPI and flush all tlbs,
1501 * but that can deadlock->flush only current cpu.
1502 */
1503 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1504 PAGE_OFFSET + phys_end);
1505}
1506#endif
1507
10147570
DM		 1508unsigned long __init find_ecache_flush_span(unsigned long size)
1509{
0836a0eb
DM		 1510 int i;
1511
13edad7a
DM		 1512 for (i = 0; i < pavail_ents; i++) {
1513 if (pavail[i].reg_size >= size)
1514 return pavail[i].phys_addr;
0836a0eb
DM		 1515 }
1516
13edad7a 1517 return ~0UL;
0836a0eb
DM		 1518}
1519
517af332
DM		 1520static void __init tsb_phys_patch(void)
1521{
d257d5da 1522 struct tsb_ldquad_phys_patch_entry *pquad;
517af332
DM		 1523 struct tsb_phys_patch_entry *p;
1524
d257d5da
DM		 1525 pquad = &__tsb_ldquad_phys_patch;
1526 while (pquad < &__tsb_ldquad_phys_patch_end) {
1527 unsigned long addr = pquad->addr;
1528
1529 if (tlb_type == hypervisor)
1530 *(unsigned int *) addr = pquad->sun4v_insn;
1531 else
1532 *(unsigned int *) addr = pquad->sun4u_insn;
1533 wmb();
1534 __asm__ __volatile__("flush %0"
1535 : /* no outputs */
1536 : "r" (addr));
1537
1538 pquad++;
1539 }
1540
517af332
DM		 1541 p = &__tsb_phys_patch;
1542 while (p < &__tsb_phys_patch_end) {
1543 unsigned long addr = p->addr;
1544
1545 *(unsigned int *) addr = p->insn;
1546 wmb();
1547 __asm__ __volatile__("flush %0"
1548 : /* no outputs */
1549 : "r" (addr));
1550
1551 p++;
1552 }
1553}
1554
490384e7 1555/* Don't mark as init, we give this to the Hypervisor. */
d1acb421
DM		 1556#ifndef CONFIG_DEBUG_PAGEALLOC
1557#define NUM_KTSB_DESCR 2
1558#else
1559#define NUM_KTSB_DESCR 1
1560#endif
1561static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
490384e7
DM		 1562extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1563
1564static void __init sun4v_ktsb_init(void)
1565{
1566 unsigned long ktsb_pa;
1567
d7744a09 1568 /* First KTSB for PAGE_SIZE mappings. */
490384e7
DM		 1569 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1570
1571 switch (PAGE_SIZE) {
1572 case 8 * 1024:
1573 default:
1574 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1575 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1576 break;
1577
1578 case 64 * 1024:
1579 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1580 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1581 break;
1582
1583 case 512 * 1024:
1584 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1585 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1586 break;
1587
1588 case 4 * 1024 * 1024:
1589 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1590 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1591 break;
1592 };
1593
3f19a84e 1594 ktsb_descr[0].assoc = 1;
490384e7
DM		 1595 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1596 ktsb_descr[0].ctx_idx = 0;
1597 ktsb_descr[0].tsb_base = ktsb_pa;
1598 ktsb_descr[0].resv = 0;
1599
d1acb421 1600#ifndef CONFIG_DEBUG_PAGEALLOC
d7744a09
DM		 1601 /* Second KTSB for 4MB/256MB mappings. */
1602 ktsb_pa = (kern_base +
1603 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1604
1605 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1606 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1607 HV_PGSZ_MASK_256MB);
1608 ktsb_descr[1].assoc = 1;
1609 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1610 ktsb_descr[1].ctx_idx = 0;
1611 ktsb_descr[1].tsb_base = ktsb_pa;
1612 ktsb_descr[1].resv = 0;
d1acb421 1613#endif
490384e7
DM		 1614}
1615
1616void __cpuinit sun4v_ktsb_register(void)
1617{
7db35f31 1618 unsigned long pa, ret;
490384e7
DM		 1619
1620 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1621
7db35f31
DM		 1622 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1623 if (ret != 0) {
1624 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1625 "errors with %lx\n", pa, ret);
1626 prom_halt();
1627 }
490384e7
DM		 1628}
1629
1da177e4
LT		 1630/* paging_init() sets up the page tables */
1631
5cbc3073
DM		 1632extern void central_probe(void);
1633
1da177e4 1634static unsigned long last_valid_pfn;
56425306 1635pgd_t swapper_pg_dir[2048];
1da177e4 1636
c4bce90e
DM		 1637static void sun4u_pgprot_init(void);
1638static void sun4v_pgprot_init(void);
1639
3afc6202 1640/* Dummy function */
1641void __init setup_per_cpu_areas(void)
1642{
1643}
1644
1da177e4
LT		 1645void __init paging_init(void)
1646{
919ee677 1647 unsigned long end_pfn, shift, phys_base;
0836a0eb
DM		 1648 unsigned long real_end, i;
1649
22adb358
DM		 1650 /* These build time checkes make sure that the dcache_dirty_cpu()
1651 * page->flags usage will work.
1652 *
1653 * When a page gets marked as dcache-dirty, we store the
1654 * cpu number starting at bit 32 in the page->flags. Also,
1655 * functions like clear_dcache_dirty_cpu use the cpu mask
1656 * in 13-bit signed-immediate instruction fields.
1657 */
9223b419
CL		 1658
1659 /*
1660 * Page flags must not reach into upper 32 bits that are used
1661 * for the cpu number
1662 */
1663 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1664
1665 /*
1666 * The bit fields placed in the high range must not reach below
1667 * the 32 bit boundary. Otherwise we cannot place the cpu field
1668 * at the 32 bit boundary.
1669 */
22adb358 1670 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
9223b419
CL		 1671 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1672
22adb358
DM		 1673 BUILD_BUG_ON(NR_CPUS > 4096);
1674
481295f9
DM		 1675 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1676 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1677
22d6a1cb
DM		 1678 sstate_booting();
1679
d7744a09 1680 /* Invalidate both kernel TSBs. */
8b234274 1681 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
d1acb421 1682#ifndef CONFIG_DEBUG_PAGEALLOC
d7744a09 1683 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
d1acb421 1684#endif
8b234274 1685
c4bce90e
DM		 1686 if (tlb_type == hypervisor)
1687 sun4v_pgprot_init();
1688 else
1689 sun4u_pgprot_init();
1690
d257d5da
DM		 1691 if (tlb_type == cheetah_plus ||
1692 tlb_type == hypervisor)
517af332
DM		 1693 tsb_phys_patch();
1694
490384e7 1695 if (tlb_type == hypervisor) {
d257d5da 1696 sun4v_patch_tlb_handlers();
490384e7
DM		 1697 sun4v_ktsb_init();
1698 }
d257d5da 1699
3b2a7e23
DM		 1700 lmb_init();
1701
a94a172d
DM		 1702 /* Find available physical memory...
1703 *
1704 * Read it twice in order to work around a bug in openfirmware.
1705 * The call to grab this table itself can cause openfirmware to
1706 * allocate memory, which in turn can take away some space from
1707 * the list of available memory. Reading it twice makes sure
1708 * we really do get the final value.
1709 */
1710 read_obp_translations();
1711 read_obp_memory("reg", &pall[0], &pall_ents);
1712 read_obp_memory("available", &pavail[0], &pavail_ents);
13edad7a 1713 read_obp_memory("available", &pavail[0], &pavail_ents);
0836a0eb
DM		 1714
1715 phys_base = 0xffffffffffffffffUL;
3b2a7e23 1716 for (i = 0; i < pavail_ents; i++) {
13edad7a 1717 phys_base = min(phys_base, pavail[i].phys_addr);
3b2a7e23
DM		 1718 lmb_add(pavail[i].phys_addr, pavail[i].reg_size);
1719 }
1720
1721 lmb_reserve(kern_base, kern_size);
0836a0eb 1722
4e82c9a6
DM		 1723 find_ramdisk(phys_base);
1724
25b0c659
DM		 1725 if (cmdline_memory_size)
1726 lmb_enforce_memory_limit(phys_base + cmdline_memory_size);
1727
3b2a7e23
DM		 1728 lmb_analyze();
1729 lmb_dump_all();
1730
1da177e4
LT		 1731 set_bit(0, mmu_context_bmap);
1732
2bdb3cb2
DM		 1733 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1734
1da177e4 1735 real_end = (unsigned long)_end;
64658743
DM		 1736 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1737 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1738 num_kernel_image_mappings);
2bdb3cb2
DM		 1739
1740 /* Set kernel pgd to upper alias so physical page computations
1da177e4
LT		 1741 * work.
1742 */
1743 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1744
56425306 1745 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1da177e4
LT		 1746
1747 /* Now can init the kernel/bad page tables. */
1748 pud_set(pud_offset(&swapper_pg_dir[0], 0),
56425306 1749 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1da177e4 1750
c9c10830 1751 inherit_prom_mappings();
5085b4a5 1752
8f361453
DM		 1753 init_kpte_bitmap();
1754
a8b900d8
DM		 1755 /* Ok, we can use our TLB miss and window trap handlers safely. */
1756 setup_tba();
1da177e4 1757
c9c10830 1758 __flush_tlb_all();
9ad98c5b 1759
490384e7
DM		 1760 if (tlb_type == hypervisor)
1761 sun4v_ktsb_register();
1762
b9709456
DM		 1763 /* We must setup the per-cpu areas before we pull in the
1764 * PROM and the MDESC. The code there fills in cpu and
1765 * other information into per-cpu data structures.
1766 */
1767 real_setup_per_cpu_areas();
1768
ad072004
DM		 1769 prom_build_devicetree();
1770
4a283339
DM		 1771 if (tlb_type == hypervisor)
1772 sun4v_mdesc_init();
1773
2bdb3cb2 1774 /* Setup bootmem... */
919ee677 1775 last_valid_pfn = end_pfn = bootmem_init(phys_base);
d1112018 1776
919ee677 1777#ifndef CONFIG_NEED_MULTIPLE_NODES
17b0e199 1778 max_mapnr = last_valid_pfn;
919ee677 1779#endif
56425306 1780 kernel_physical_mapping_init();
56425306 1781
1da177e4 1782 {
919ee677 1783 unsigned long max_zone_pfns[MAX_NR_ZONES];
1da177e4 1784
919ee677 1785 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1da177e4 1786
919ee677 1787 max_zone_pfns[ZONE_NORMAL] = end_pfn;
1da177e4 1788
919ee677 1789 free_area_init_nodes(max_zone_pfns);
1da177e4
LT		 1790 }
1791
3c62a2d3 1792 printk("Booting Linux...\n");
5cbc3073
DM		 1793
1794 central_probe();
1795 cpu_probe();
1da177e4
LT		 1796}
1797
919ee677
DM		 1798int __init page_in_phys_avail(unsigned long paddr)
1799{
1800 int i;
1801
1802 paddr &= PAGE_MASK;
1803
1804 for (i = 0; i < pavail_ents; i++) {
1805 unsigned long start, end;
1806
1807 start = pavail[i].phys_addr;
1808 end = start + pavail[i].reg_size;
1809
1810 if (paddr >= start && paddr < end)
1811 return 1;
1812 }
1813 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1814 return 1;
1815#ifdef CONFIG_BLK_DEV_INITRD
1816 if (paddr >= __pa(initrd_start) &&
1817 paddr < __pa(PAGE_ALIGN(initrd_end)))
1818 return 1;
1819#endif
1820
1821 return 0;
1822}
1823
1824static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
1825static int pavail_rescan_ents __initdata;
1826
1827/* Certain OBP calls, such as fetching "available" properties, can
1828 * claim physical memory. So, along with initializing the valid
1829 * address bitmap, what we do here is refetch the physical available
1830 * memory list again, and make sure it provides at least as much
1831 * memory as 'pavail' does.
1832 */
1833static void setup_valid_addr_bitmap_from_pavail(void)
1da177e4 1834{
1da177e4
LT		 1835 int i;
1836
13edad7a 1837 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1da177e4 1838
13edad7a 1839 for (i = 0; i < pavail_ents; i++) {
1da177e4
LT		 1840 unsigned long old_start, old_end;
1841
13edad7a 1842 old_start = pavail[i].phys_addr;
919ee677 1843 old_end = old_start + pavail[i].reg_size;
1da177e4
LT		 1844 while (old_start < old_end) {
1845 int n;
1846
c2a5a46b 1847 for (n = 0; n < pavail_rescan_ents; n++) {
1da177e4
LT		 1848 unsigned long new_start, new_end;
1849
13edad7a
DM		 1850 new_start = pavail_rescan[n].phys_addr;
1851 new_end = new_start +
1852 pavail_rescan[n].reg_size;
1da177e4
LT		 1853
1854 if (new_start <= old_start &&
1855 new_end >= (old_start + PAGE_SIZE)) {
13edad7a
DM		 1856 set_bit(old_start >> 22,
1857 sparc64_valid_addr_bitmap);
1da177e4
LT		 1858 goto do_next_page;
1859 }
1860 }
919ee677
DM		 1861
1862 prom_printf("mem_init: Lost memory in pavail\n");
1863 prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
1864 pavail[i].phys_addr,
1865 pavail[i].reg_size);
1866 prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
1867 pavail_rescan[i].phys_addr,
1868 pavail_rescan[i].reg_size);
1869 prom_printf("mem_init: Cannot continue, aborting.\n");
1870 prom_halt();
1da177e4
LT		 1871
1872 do_next_page:
1873 old_start += PAGE_SIZE;
1874 }
1875 }
1876}
1877
1878void __init mem_init(void)
1879{
1880 unsigned long codepages, datapages, initpages;
1881 unsigned long addr, last;
1882 int i;
1883
1884 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1885 i += 1;
2bdb3cb2 1886 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1da177e4
LT		 1887 if (sparc64_valid_addr_bitmap == NULL) {
1888 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1889 prom_halt();
1890 }
1891 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1892
1893 addr = PAGE_OFFSET + kern_base;
1894 last = PAGE_ALIGN(kern_size) + addr;
1895 while (addr < last) {
1896 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1897 addr += PAGE_SIZE;
1898 }
1899
919ee677 1900 setup_valid_addr_bitmap_from_pavail();
1da177e4 1901
1da177e4
LT		 1902 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1903
919ee677
DM		 1904#ifdef CONFIG_NEED_MULTIPLE_NODES
1905 for_each_online_node(i) {
1906 if (NODE_DATA(i)->node_spanned_pages != 0) {
1907 totalram_pages +=
1908 free_all_bootmem_node(NODE_DATA(i));
1909 }
1910 }
1911#else
1912 totalram_pages = free_all_bootmem();
1913#endif
1914
f1cfdb55
DM		 1915 /* We subtract one to account for the mem_map_zero page
1916 * allocated below.
1917 */
919ee677
DM		 1918 totalram_pages -= 1;
1919 num_physpages = totalram_pages;
1da177e4
LT		 1920
1921 /*
1922 * Set up the zero page, mark it reserved, so that page count
1923 * is not manipulated when freeing the page from user ptes.
1924 */
1925 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1926 if (mem_map_zero == NULL) {
1927 prom_printf("paging_init: Cannot alloc zero page.\n");
1928 prom_halt();
1929 }
1930 SetPageReserved(mem_map_zero);
1931
1932 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1933 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1934 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1935 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1936 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1937 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1938
96177299 1939 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1da177e4
LT		 1940 nr_free_pages() << (PAGE_SHIFT-10),
1941 codepages << (PAGE_SHIFT-10),
1942 datapages << (PAGE_SHIFT-10),
1943 initpages << (PAGE_SHIFT-10),
1944 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1945
1946 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1947 cheetah_ecache_flush_init();
1948}
1949
898cf0ec 1950void free_initmem(void)
1da177e4
LT		 1951{
1952 unsigned long addr, initend;
1953
1954 /*
1955 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1956 */
1957 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1958 initend = (unsigned long)(__init_end) & PAGE_MASK;
1959 for (; addr < initend; addr += PAGE_SIZE) {
1960 unsigned long page;
1961 struct page *p;
1962
1963 page = (addr +
1964 ((unsigned long) __va(kern_base)) -
1965 ((unsigned long) KERNBASE));
c9cf5528 1966 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1da177e4
LT		 1967 p = virt_to_page(page);
1968
1969 ClearPageReserved(p);
7835e98b 1970 init_page_count(p);
1da177e4
LT		 1971 __free_page(p);
1972 num_physpages++;
1973 totalram_pages++;
1974 }
1975}
1976
1977#ifdef CONFIG_BLK_DEV_INITRD
1978void free_initrd_mem(unsigned long start, unsigned long end)
1979{
1980 if (start < end)
1981 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1982 for (; start < end; start += PAGE_SIZE) {
1983 struct page *p = virt_to_page(start);
1984
1985 ClearPageReserved(p);
7835e98b 1986 init_page_count(p);
1da177e4
LT		 1987 __free_page(p);
1988 num_physpages++;
1989 totalram_pages++;
1990 }
1991}
1992#endif
c4bce90e 1993
c4bce90e
DM		 1994#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1995#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1996#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1997#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1998#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1999#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2000
2001pgprot_t PAGE_KERNEL __read_mostly;
2002EXPORT_SYMBOL(PAGE_KERNEL);
2003
2004pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2005pgprot_t PAGE_COPY __read_mostly;
0f15952a
DM		 2006
2007pgprot_t PAGE_SHARED __read_mostly;
2008EXPORT_SYMBOL(PAGE_SHARED);
2009
c4bce90e
DM		 2010pgprot_t PAGE_EXEC __read_mostly;
2011unsigned long pg_iobits __read_mostly;
2012
2013unsigned long _PAGE_IE __read_mostly;
987c74fc 2014EXPORT_SYMBOL(_PAGE_IE);
b2bef442 2015
c4bce90e 2016unsigned long _PAGE_E __read_mostly;
b2bef442
DM		 2017EXPORT_SYMBOL(_PAGE_E);
2018
c4bce90e 2019unsigned long _PAGE_CACHE __read_mostly;
b2bef442 2020EXPORT_SYMBOL(_PAGE_CACHE);
c4bce90e 2021
46644c24
DM		 2022#ifdef CONFIG_SPARSEMEM_VMEMMAP
2023
2024#define VMEMMAP_CHUNK_SHIFT 22
2025#define VMEMMAP_CHUNK (1UL << VMEMMAP_CHUNK_SHIFT)
2026#define VMEMMAP_CHUNK_MASK ~(VMEMMAP_CHUNK - 1UL)
2027#define VMEMMAP_ALIGN(x) (((x)+VMEMMAP_CHUNK-1UL)&VMEMMAP_CHUNK_MASK)
2028
2029#define VMEMMAP_SIZE ((((1UL << MAX_PHYSADDR_BITS) >> PAGE_SHIFT) * \
2030 sizeof(struct page *)) >> VMEMMAP_CHUNK_SHIFT)
2031unsigned long vmemmap_table[VMEMMAP_SIZE];
2032
2033int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
2034{
2035 unsigned long vstart = (unsigned long) start;
2036 unsigned long vend = (unsigned long) (start + nr);
2037 unsigned long phys_start = (vstart - VMEMMAP_BASE);
2038 unsigned long phys_end = (vend - VMEMMAP_BASE);
2039 unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2040 unsigned long end = VMEMMAP_ALIGN(phys_end);
2041 unsigned long pte_base;
2042
2043 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2044 _PAGE_CP_4U | _PAGE_CV_4U |
2045 _PAGE_P_4U | _PAGE_W_4U);
2046 if (tlb_type == hypervisor)
2047 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2048 _PAGE_CP_4V | _PAGE_CV_4V |
2049 _PAGE_P_4V | _PAGE_W_4V);
2050
2051 for (; addr < end; addr += VMEMMAP_CHUNK) {
2052 unsigned long *vmem_pp =
2053 vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2054 void *block;
2055
2056 if (!(*vmem_pp & _PAGE_VALID)) {
2057 block = vmemmap_alloc_block(1UL << 22, node);
2058 if (!block)
2059 return -ENOMEM;
2060
2061 *vmem_pp = pte_base | __pa(block);
2062
2063 printk(KERN_INFO "[%p-%p] page_structs=%lu "
2064 "node=%d entry=%lu/%lu\n", start, block, nr,
2065 node,
2066 addr >> VMEMMAP_CHUNK_SHIFT,
2067 VMEMMAP_SIZE >> VMEMMAP_CHUNK_SHIFT);
2068 }
2069 }
2070 return 0;
2071}
2072#endif /* CONFIG_SPARSEMEM_VMEMMAP */
2073
c4bce90e
DM		 2074static void prot_init_common(unsigned long page_none,
2075 unsigned long page_shared,
2076 unsigned long page_copy,
2077 unsigned long page_readonly,
2078 unsigned long page_exec_bit)
2079{
2080 PAGE_COPY = __pgprot(page_copy);
0f15952a 2081 PAGE_SHARED = __pgprot(page_shared);
c4bce90e
DM		 2082
2083 protection_map[0x0] = __pgprot(page_none);
2084 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2085 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2086 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2087 protection_map[0x4] = __pgprot(page_readonly);
2088 protection_map[0x5] = __pgprot(page_readonly);
2089 protection_map[0x6] = __pgprot(page_copy);
2090 protection_map[0x7] = __pgprot(page_copy);
2091 protection_map[0x8] = __pgprot(page_none);
2092 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2093 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2094 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2095 protection_map[0xc] = __pgprot(page_readonly);
2096 protection_map[0xd] = __pgprot(page_readonly);
2097 protection_map[0xe] = __pgprot(page_shared);
2098 protection_map[0xf] = __pgprot(page_shared);
2099}
2100
2101static void __init sun4u_pgprot_init(void)
2102{
2103 unsigned long page_none, page_shared, page_copy, page_readonly;
2104 unsigned long page_exec_bit;
2105
2106 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2107 _PAGE_CACHE_4U | _PAGE_P_4U |
2108 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2109 _PAGE_EXEC_4U);
2110 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2111 _PAGE_CACHE_4U | _PAGE_P_4U |
2112 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2113 _PAGE_EXEC_4U | _PAGE_L_4U);
2114 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
2115
2116 _PAGE_IE = _PAGE_IE_4U;
2117 _PAGE_E = _PAGE_E_4U;
2118 _PAGE_CACHE = _PAGE_CACHE_4U;
2119
2120 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2121 __ACCESS_BITS_4U | _PAGE_E_4U);
2122
d1acb421
DM		 2123#ifdef CONFIG_DEBUG_PAGEALLOC
2124 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
2125 0xfffff80000000000;
2126#else
9cc3a1ac 2127 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
c4bce90e 2128 0xfffff80000000000;
d1acb421 2129#endif
9cc3a1ac
DM		 2130 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2131 _PAGE_P_4U | _PAGE_W_4U);
2132
2133 /* XXX Should use 256MB on Panther. XXX */
2134 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
c4bce90e
DM		 2135
2136 _PAGE_SZBITS = _PAGE_SZBITS_4U;
2137 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2138 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2139 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2140
2141
2142 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2143 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2144 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2145 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2146 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2147 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2148 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2149
2150 page_exec_bit = _PAGE_EXEC_4U;
2151
2152 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2153 page_exec_bit);
2154}
2155
2156static void __init sun4v_pgprot_init(void)
2157{
2158 unsigned long page_none, page_shared, page_copy, page_readonly;
2159 unsigned long page_exec_bit;
2160
2161 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2162 _PAGE_CACHE_4V | _PAGE_P_4V |
2163 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2164 _PAGE_EXEC_4V);
2165 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2166 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
2167
2168 _PAGE_IE = _PAGE_IE_4V;
2169 _PAGE_E = _PAGE_E_4V;
2170 _PAGE_CACHE = _PAGE_CACHE_4V;
2171
d1acb421
DM		 2172#ifdef CONFIG_DEBUG_PAGEALLOC
2173 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2174 0xfffff80000000000;
2175#else
9cc3a1ac
DM		 2176 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2177 0xfffff80000000000;
d1acb421 2178#endif
9cc3a1ac
DM		 2179 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2180 _PAGE_P_4V | _PAGE_W_4V);
2181
d1acb421
DM		 2182#ifdef CONFIG_DEBUG_PAGEALLOC
2183 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2184 0xfffff80000000000;
2185#else
9cc3a1ac 2186 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
c4bce90e 2187 0xfffff80000000000;
d1acb421 2188#endif
9cc3a1ac
DM		 2189 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2190 _PAGE_P_4V | _PAGE_W_4V);
c4bce90e
DM		 2191
2192 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2193 __ACCESS_BITS_4V | _PAGE_E_4V);
2194
2195 _PAGE_SZBITS = _PAGE_SZBITS_4V;
2196 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2197 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2198 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2199 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2200
2201 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2202 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2203 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2204 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2205 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2206 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2207 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2208
2209 page_exec_bit = _PAGE_EXEC_4V;
2210
2211 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2212 page_exec_bit);
2213}
2214
2215unsigned long pte_sz_bits(unsigned long sz)
2216{
2217 if (tlb_type == hypervisor) {
2218 switch (sz) {
2219 case 8 * 1024:
2220 default:
2221 return _PAGE_SZ8K_4V;
2222 case 64 * 1024:
2223 return _PAGE_SZ64K_4V;
2224 case 512 * 1024:
2225 return _PAGE_SZ512K_4V;
2226 case 4 * 1024 * 1024:
2227 return _PAGE_SZ4MB_4V;
2228 };
2229 } else {
2230 switch (sz) {
2231 case 8 * 1024:
2232 default:
2233 return _PAGE_SZ8K_4U;
2234 case 64 * 1024:
2235 return _PAGE_SZ64K_4U;
2236 case 512 * 1024:
2237 return _PAGE_SZ512K_4U;
2238 case 4 * 1024 * 1024:
2239 return _PAGE_SZ4MB_4U;
2240 };
2241 }
2242}
2243
2244pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2245{
2246 pte_t pte;
cf627156
DM		 2247
2248 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
c4bce90e
DM		 2249 pte_val(pte) |= (((unsigned long)space) << 32);
2250 pte_val(pte) |= pte_sz_bits(page_size);
c4bce90e 2251
cf627156 2252 return pte;
c4bce90e
DM		 2253}
2254
2255static unsigned long kern_large_tte(unsigned long paddr)
2256{
2257 unsigned long val;
2258
2259 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2260 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2261 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2262 if (tlb_type == hypervisor)
2263 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2264 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2265 _PAGE_EXEC_4V | _PAGE_W_4V);
2266
2267 return val | paddr;
2268}
2269
c4bce90e
DM		 2270/* If not locked, zap it. */
2271void __flush_tlb_all(void)
2272{
2273 unsigned long pstate;
2274 int i;
2275
2276 __asm__ __volatile__("flushw\n\t"
2277 "rdpr %%pstate, %0\n\t"
2278 "wrpr %0, %1, %%pstate"
2279 : "=r" (pstate)
2280 : "i" (PSTATE_IE));
8f361453
DM		 2281 if (tlb_type == hypervisor) {
2282 sun4v_mmu_demap_all();
2283 } else if (tlb_type == spitfire) {
c4bce90e
DM		 2284 for (i = 0; i < 64; i++) {
2285 /* Spitfire Errata #32 workaround */
2286 /* NOTE: Always runs on spitfire, so no
2287 * cheetah+ page size encodings.
2288 */
2289 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2290 "flush %%g6"
2291 : /* No outputs */
2292 : "r" (0),
2293 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2294
2295 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2296 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2297 "membar #Sync"
2298 : /* no outputs */
2299 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2300 spitfire_put_dtlb_data(i, 0x0UL);
2301 }
2302
2303 /* Spitfire Errata #32 workaround */
2304 /* NOTE: Always runs on spitfire, so no
2305 * cheetah+ page size encodings.
2306 */
2307 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2308 "flush %%g6"
2309 : /* No outputs */
2310 : "r" (0),
2311 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2312
2313 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2314 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2315 "membar #Sync"
2316 : /* no outputs */
2317 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2318 spitfire_put_itlb_data(i, 0x0UL);
2319 }
2320 }
2321 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2322 cheetah_flush_dtlb_all();
2323 cheetah_flush_itlb_all();
2324 }
2325 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2326 : : "r" (pstate));
2327}
kernel source for telekom puls (alcatel/mediatek)