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[SPARC64]: Do not allocate prom translations using bootmem.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / sparc64 / mm / init.c
CommitLineData
1da177e4
LT		 1/* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#include <linux/config.h>
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/string.h>
12#include <linux/init.h>
13#include <linux/bootmem.h>
14#include <linux/mm.h>
15#include <linux/hugetlb.h>
16#include <linux/slab.h>
17#include <linux/initrd.h>
18#include <linux/swap.h>
19#include <linux/pagemap.h>
20#include <linux/fs.h>
21#include <linux/seq_file.h>
05e14cb3 22#include <linux/kprobes.h>
1ac4f5eb 23#include <linux/cache.h>
1da177e4
LT		 24
25#include <asm/head.h>
26#include <asm/system.h>
27#include <asm/page.h>
28#include <asm/pgalloc.h>
29#include <asm/pgtable.h>
30#include <asm/oplib.h>
31#include <asm/iommu.h>
32#include <asm/io.h>
33#include <asm/uaccess.h>
34#include <asm/mmu_context.h>
35#include <asm/tlbflush.h>
36#include <asm/dma.h>
37#include <asm/starfire.h>
38#include <asm/tlb.h>
39#include <asm/spitfire.h>
40#include <asm/sections.h>
41
42extern void device_scan(void);
43
44struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS];
45
46unsigned long *sparc64_valid_addr_bitmap;
47
48/* Ugly, but necessary... -DaveM */
1ac4f5eb
DM		 49unsigned long phys_base __read_mostly;
50unsigned long kern_base __read_mostly;
51unsigned long kern_size __read_mostly;
52unsigned long pfn_base __read_mostly;
1da177e4
LT		 53
54/* This is even uglier. We have a problem where the kernel may not be
55 * located at phys_base. However, initial __alloc_bootmem() calls need to
56 * be adjusted to be within the 4-8Megs that the kernel is mapped to, else
57 * those page mappings wont work. Things are ok after inherit_prom_mappings
58 * is called though. Dave says he'll clean this up some other time.
59 * -- BenC
60 */
61static unsigned long bootmap_base;
62
63/* get_new_mmu_context() uses "cache + 1". */
64DEFINE_SPINLOCK(ctx_alloc_lock);
65unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
66#define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
67unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
68
69/* References to special section boundaries */
70extern char _start[], _end[];
71
72/* Initial ramdisk setup */
73extern unsigned long sparc_ramdisk_image64;
74extern unsigned int sparc_ramdisk_image;
75extern unsigned int sparc_ramdisk_size;
76
1ac4f5eb 77struct page *mem_map_zero __read_mostly;
1da177e4
LT		 78
79int bigkernel = 0;
80
81/* XXX Tune this... */
82#define PGT_CACHE_LOW 25
83#define PGT_CACHE_HIGH 50
84
85void check_pgt_cache(void)
86{
87 preempt_disable();
88 if (pgtable_cache_size > PGT_CACHE_HIGH) {
89 do {
90 if (pgd_quicklist)
91 free_pgd_slow(get_pgd_fast());
92 if (pte_quicklist[0])
93 free_pte_slow(pte_alloc_one_fast(NULL, 0));
94 if (pte_quicklist[1])
95 free_pte_slow(pte_alloc_one_fast(NULL, 1 << (PAGE_SHIFT + 10)));
96 } while (pgtable_cache_size > PGT_CACHE_LOW);
97 }
98 preempt_enable();
99}
100
101#ifdef CONFIG_DEBUG_DCFLUSH
102atomic_t dcpage_flushes = ATOMIC_INIT(0);
103#ifdef CONFIG_SMP
104atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
105#endif
106#endif
107
108__inline__ void flush_dcache_page_impl(struct page *page)
109{
110#ifdef CONFIG_DEBUG_DCFLUSH
111 atomic_inc(&dcpage_flushes);
112#endif
113
114#ifdef DCACHE_ALIASING_POSSIBLE
115 __flush_dcache_page(page_address(page),
116 ((tlb_type == spitfire) &&
117 page_mapping(page) != NULL));
118#else
119 if (page_mapping(page) != NULL &&
120 tlb_type == spitfire)
121 __flush_icache_page(__pa(page_address(page)));
122#endif
123}
124
125#define PG_dcache_dirty PG_arch_1
48b0e548
DM		 126#define PG_dcache_cpu_shift 24
127#define PG_dcache_cpu_mask (256 - 1)
128
129#if NR_CPUS > 256
130#error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
131#endif
1da177e4
LT		 132
133#define dcache_dirty_cpu(page) \
48b0e548 134 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
1da177e4
LT		 135
136static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
137{
138 unsigned long mask = this_cpu;
48b0e548
DM		 139 unsigned long non_cpu_bits;
140
141 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
142 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
143
1da177e4
LT		 144 __asm__ __volatile__("1:\n\t"
145 "ldx [%2], %%g7\n\t"
146 "and %%g7, %1, %%g1\n\t"
147 "or %%g1, %0, %%g1\n\t"
148 "casx [%2], %%g7, %%g1\n\t"
149 "cmp %%g7, %%g1\n\t"
b445e26c 150 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 151 "bne,pn %%xcc, 1b\n\t"
b445e26c 152 " nop"
1da177e4
LT		 153 : /* no outputs */
154 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
155 : "g1", "g7");
156}
157
158static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
159{
160 unsigned long mask = (1UL << PG_dcache_dirty);
161
162 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
163 "1:\n\t"
164 "ldx [%2], %%g7\n\t"
48b0e548 165 "srlx %%g7, %4, %%g1\n\t"
1da177e4
LT		 166 "and %%g1, %3, %%g1\n\t"
167 "cmp %%g1, %0\n\t"
168 "bne,pn %%icc, 2f\n\t"
169 " andn %%g7, %1, %%g1\n\t"
170 "casx [%2], %%g7, %%g1\n\t"
171 "cmp %%g7, %%g1\n\t"
b445e26c 172 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 173 "bne,pn %%xcc, 1b\n\t"
b445e26c 174 " nop\n"
1da177e4
LT		 175 "2:"
176 : /* no outputs */
177 : "r" (cpu), "r" (mask), "r" (&page->flags),
48b0e548
DM		 178 "i" (PG_dcache_cpu_mask),
179 "i" (PG_dcache_cpu_shift)
1da177e4
LT		 180 : "g1", "g7");
181}
182
183extern void __update_mmu_cache(unsigned long mmu_context_hw, unsigned long address, pte_t pte, int code);
184
185void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
186{
187 struct page *page;
188 unsigned long pfn;
189 unsigned long pg_flags;
190
191 pfn = pte_pfn(pte);
192 if (pfn_valid(pfn) &&
193 (page = pfn_to_page(pfn), page_mapping(page)) &&
194 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
48b0e548
DM		 195 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
196 PG_dcache_cpu_mask);
1da177e4
LT		 197 int this_cpu = get_cpu();
198
199 /* This is just to optimize away some function calls
200 * in the SMP case.
201 */
202 if (cpu == this_cpu)
203 flush_dcache_page_impl(page);
204 else
205 smp_flush_dcache_page_impl(page, cpu);
206
207 clear_dcache_dirty_cpu(page, cpu);
208
209 put_cpu();
210 }
211
212 if (get_thread_fault_code())
213 __update_mmu_cache(CTX_NRBITS(vma->vm_mm->context),
214 address, pte, get_thread_fault_code());
215}
216
217void flush_dcache_page(struct page *page)
218{
a9546f59
DM		 219 struct address_space *mapping;
220 int this_cpu;
1da177e4 221
a9546f59
DM		 222 /* Do not bother with the expensive D-cache flush if it
223 * is merely the zero page. The 'bigcore' testcase in GDB
224 * causes this case to run millions of times.
225 */
226 if (page == ZERO_PAGE(0))
227 return;
228
229 this_cpu = get_cpu();
230
231 mapping = page_mapping(page);
1da177e4 232 if (mapping && !mapping_mapped(mapping)) {
a9546f59 233 int dirty = test_bit(PG_dcache_dirty, &page->flags);
1da177e4 234 if (dirty) {
a9546f59
DM		 235 int dirty_cpu = dcache_dirty_cpu(page);
236
1da177e4
LT		 237 if (dirty_cpu == this_cpu)
238 goto out;
239 smp_flush_dcache_page_impl(page, dirty_cpu);
240 }
241 set_dcache_dirty(page, this_cpu);
242 } else {
243 /* We could delay the flush for the !page_mapping
244 * case too. But that case is for exec env/arg
245 * pages and those are %99 certainly going to get
246 * faulted into the tlb (and thus flushed) anyways.
247 */
248 flush_dcache_page_impl(page);
249 }
250
251out:
252 put_cpu();
253}
254
05e14cb3 255void __kprobes flush_icache_range(unsigned long start, unsigned long end)
1da177e4
LT		 256{
257 /* Cheetah has coherent I-cache. */
258 if (tlb_type == spitfire) {
259 unsigned long kaddr;
260
261 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
262 __flush_icache_page(__get_phys(kaddr));
263 }
264}
265
266unsigned long page_to_pfn(struct page *page)
267{
268 return (unsigned long) ((page - mem_map) + pfn_base);
269}
270
271struct page *pfn_to_page(unsigned long pfn)
272{
273 return (mem_map + (pfn - pfn_base));
274}
275
276void show_mem(void)
277{
278 printk("Mem-info:\n");
279 show_free_areas();
280 printk("Free swap: %6ldkB\n",
281 nr_swap_pages << (PAGE_SHIFT-10));
282 printk("%ld pages of RAM\n", num_physpages);
283 printk("%d free pages\n", nr_free_pages());
284 printk("%d pages in page table cache\n",pgtable_cache_size);
285}
286
287void mmu_info(struct seq_file *m)
288{
289 if (tlb_type == cheetah)
290 seq_printf(m, "MMU Type\t: Cheetah\n");
291 else if (tlb_type == cheetah_plus)
292 seq_printf(m, "MMU Type\t: Cheetah+\n");
293 else if (tlb_type == spitfire)
294 seq_printf(m, "MMU Type\t: Spitfire\n");
295 else
296 seq_printf(m, "MMU Type\t: ???\n");
297
298#ifdef CONFIG_DEBUG_DCFLUSH
299 seq_printf(m, "DCPageFlushes\t: %d\n",
300 atomic_read(&dcpage_flushes));
301#ifdef CONFIG_SMP
302 seq_printf(m, "DCPageFlushesXC\t: %d\n",
303 atomic_read(&dcpage_flushes_xcall));
304#endif /* CONFIG_SMP */
305#endif /* CONFIG_DEBUG_DCFLUSH */
306}
307
308struct linux_prom_translation {
309 unsigned long virt;
310 unsigned long size;
311 unsigned long data;
312};
b206fc4c 313static struct linux_prom_translation prom_trans[512] __initdata;
1da177e4
LT		 314
315extern unsigned long prom_boot_page;
316extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
317extern int prom_get_mmu_ihandle(void);
318extern void register_prom_callbacks(void);
319
320/* Exported for SMP bootup purposes. */
321unsigned long kern_locked_tte_data;
322
1ac4f5eb
DM		 323/* Exported for kernel TLB miss handling in ktlb.S */
324unsigned long prom_pmd_phys __read_mostly;
325unsigned int swapper_pgd_zero __read_mostly;
326
1da177e4
LT		 327void __init early_pgtable_allocfail(char *type)
328{
329 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
330 prom_halt();
331}
332
333#define BASE_PAGE_SIZE 8192
334static pmd_t *prompmd;
335
336/*
337 * Translate PROM's mapping we capture at boot time into physical address.
338 * The second parameter is only set from prom_callback() invocations.
339 */
340unsigned long prom_virt_to_phys(unsigned long promva, int *error)
341{
342 pmd_t *pmdp = prompmd + ((promva >> 23) & 0x7ff);
343 pte_t *ptep;
344 unsigned long base;
345
346 if (pmd_none(*pmdp)) {
347 if (error)
348 *error = 1;
349 return(0);
350 }
351 ptep = (pte_t *)__pmd_page(*pmdp) + ((promva >> 13) & 0x3ff);
352 if (!pte_present(*ptep)) {
353 if (error)
354 *error = 1;
355 return(0);
356 }
357 if (error) {
358 *error = 0;
359 return(pte_val(*ptep));
360 }
361 base = pte_val(*ptep) & _PAGE_PADDR;
362 return(base + (promva & (BASE_PAGE_SIZE - 1)));
363}
364
365static void inherit_prom_mappings(void)
366{
1da177e4
LT		 367 unsigned long phys_page, tte_vaddr, tte_data;
368 void (*remap_func)(unsigned long, unsigned long, int);
369 pmd_t *pmdp;
370 pte_t *ptep;
371 int node, n, i, tsz;
1da177e4
LT		 372
373 node = prom_finddevice("/virtual-memory");
374 n = prom_getproplen(node, "translations");
375 if (n == 0 || n == -1) {
b206fc4c 376 prom_printf("prom_mappings: Couldn't get size.\n");
1da177e4
LT		 377 prom_halt();
378 }
b206fc4c
DM		 379 n += 24 * sizeof(struct linux_prom_translation);
380 if (n > sizeof(prom_trans)) {
381 prom_printf("prom_mappings: prom_trans too small, "
382 "need %Zd bytes\n", n);
1da177e4
LT		 383 prom_halt();
384 }
b206fc4c
DM		 385 tsz = n;
386 if ((n = prom_getproperty(node, "translations",
387 (char *)&prom_trans[0], tsz)) == -1) {
388 prom_printf("prom_mappings: Couldn't get property.\n");
1da177e4
LT		 389 prom_halt();
390 }
b206fc4c 391 n = n / sizeof(struct linux_prom_translation);
1da177e4 392
b206fc4c
DM		 393 /* The obp translations are saved based on 8k pagesize, since obp
394 * can use a mixture of pagesizes. Misses to the 0xf0000000 ->
395 * 0x100000000, ie obp range, are handled in entry.S and do not
396 * use the vpte scheme (see rant: inherit_locked_prom_mappings).
1da177e4
LT		 397 */
398#define OBP_PMD_SIZE 2048
399 prompmd = __alloc_bootmem(OBP_PMD_SIZE, OBP_PMD_SIZE, bootmap_base);
400 if (prompmd == NULL)
401 early_pgtable_allocfail("pmd");
402 memset(prompmd, 0, OBP_PMD_SIZE);
403 for (i = 0; i < n; i++) {
404 unsigned long vaddr;
405
b206fc4c
DM		 406 if (prom_trans[i].virt >= LOW_OBP_ADDRESS && prom_trans[i].virt < HI_OBP_ADDRESS) {
407 for (vaddr = prom_trans[i].virt;
408 ((vaddr < prom_trans[i].virt + prom_trans[i].size) &&
1da177e4
LT		 409 (vaddr < HI_OBP_ADDRESS));
410 vaddr += BASE_PAGE_SIZE) {
411 unsigned long val;
412
413 pmdp = prompmd + ((vaddr >> 23) & 0x7ff);
414 if (pmd_none(*pmdp)) {
415 ptep = __alloc_bootmem(BASE_PAGE_SIZE,
416 BASE_PAGE_SIZE,
417 bootmap_base);
418 if (ptep == NULL)
419 early_pgtable_allocfail("pte");
420 memset(ptep, 0, BASE_PAGE_SIZE);
421 pmd_set(pmdp, ptep);
422 }
423 ptep = (pte_t *)__pmd_page(*pmdp) +
424 ((vaddr >> 13) & 0x3ff);
425
b206fc4c 426 val = prom_trans[i].data;
1da177e4
LT		 427
428 /* Clear diag TTE bits. */
429 if (tlb_type == spitfire)
430 val &= ~0x0003fe0000000000UL;
431
432 set_pte_at(&init_mm, vaddr,
433 ptep, __pte(val | _PAGE_MODIFIED));
b206fc4c 434 prom_trans[i].data += BASE_PAGE_SIZE;
1da177e4
LT		 435 }
436 }
437 }
1ac4f5eb 438 prom_pmd_phys = __pa(prompmd);
1da177e4
LT		 439
440 /* Now fixup OBP's idea about where we really are mapped. */
441 prom_printf("Remapping the kernel... ");
442
443 /* Spitfire Errata #32 workaround */
444 /* NOTE: Using plain zero for the context value is
445 * correct here, we are not using the Linux trap
446 * tables yet so we should not use the special
447 * UltraSPARC-III+ page size encodings yet.
448 */
449 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
450 "flush %%g6"
451 : /* No outputs */
452 : "r" (0), "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
453
454 switch (tlb_type) {
455 default:
456 case spitfire:
457 phys_page = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
458 break;
459
460 case cheetah:
461 case cheetah_plus:
462 phys_page = cheetah_get_litlb_data(sparc64_highest_locked_tlbent());
463 break;
464 };
465
466 phys_page &= _PAGE_PADDR;
467 phys_page += ((unsigned long)&prom_boot_page -
468 (unsigned long)KERNBASE);
469
470 if (tlb_type == spitfire) {
471 /* Lock this into i/d tlb entry 59 */
472 __asm__ __volatile__(
473 "stxa %%g0, [%2] %3\n\t"
474 "stxa %0, [%1] %4\n\t"
475 "membar #Sync\n\t"
476 "flush %%g6\n\t"
477 "stxa %%g0, [%2] %5\n\t"
478 "stxa %0, [%1] %6\n\t"
479 "membar #Sync\n\t"
480 "flush %%g6"
481 : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
482 _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
483 "r" (59 << 3), "r" (TLB_TAG_ACCESS),
484 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
485 "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
486 : "memory");
487 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
488 /* Lock this into i/d tlb-0 entry 11 */
489 __asm__ __volatile__(
490 "stxa %%g0, [%2] %3\n\t"
491 "stxa %0, [%1] %4\n\t"
492 "membar #Sync\n\t"
493 "flush %%g6\n\t"
494 "stxa %%g0, [%2] %5\n\t"
495 "stxa %0, [%1] %6\n\t"
496 "membar #Sync\n\t"
497 "flush %%g6"
498 : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
499 _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
500 "r" ((0 << 16) | (11 << 3)), "r" (TLB_TAG_ACCESS),
501 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
502 "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
503 : "memory");
504 } else {
505 /* Implement me :-) */
506 BUG();
507 }
508
509 tte_vaddr = (unsigned long) KERNBASE;
510
511 /* Spitfire Errata #32 workaround */
512 /* NOTE: Using plain zero for the context value is
513 * correct here, we are not using the Linux trap
514 * tables yet so we should not use the special
515 * UltraSPARC-III+ page size encodings yet.
516 */
517 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
518 "flush %%g6"
519 : /* No outputs */
520 : "r" (0),
521 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
522
523 if (tlb_type == spitfire)
524 tte_data = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
525 else
526 tte_data = cheetah_get_ldtlb_data(sparc64_highest_locked_tlbent());
527
528 kern_locked_tte_data = tte_data;
529
530 remap_func = (void *) ((unsigned long) &prom_remap -
531 (unsigned long) &prom_boot_page);
532
533
534 /* Spitfire Errata #32 workaround */
535 /* NOTE: Using plain zero for the context value is
536 * correct here, we are not using the Linux trap
537 * tables yet so we should not use the special
538 * UltraSPARC-III+ page size encodings yet.
539 */
540 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
541 "flush %%g6"
542 : /* No outputs */
543 : "r" (0),
544 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
545
546 remap_func((tlb_type == spitfire ?
547 (spitfire_get_dtlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR) :
548 (cheetah_get_litlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR)),
549 (unsigned long) KERNBASE,
550 prom_get_mmu_ihandle());
551
552 if (bigkernel)
553 remap_func(((tte_data + 0x400000) & _PAGE_PADDR),
554 (unsigned long) KERNBASE + 0x400000, prom_get_mmu_ihandle());
555
556 /* Flush out that temporary mapping. */
557 spitfire_flush_dtlb_nucleus_page(0x0);
558 spitfire_flush_itlb_nucleus_page(0x0);
559
560 /* Now lock us back into the TLBs via OBP. */
561 prom_dtlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
562 prom_itlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
563 if (bigkernel) {
564 prom_dtlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
565 tte_vaddr + 0x400000);
566 prom_itlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
567 tte_vaddr + 0x400000);
568 }
569
570 /* Re-read translations property. */
b206fc4c
DM		 571 if ((n = prom_getproperty(node, "translations",
572 (char *)&prom_trans[0], tsz)) == -1) {
573 prom_printf("prom_mappings: Can't reread prom_trans.\n");
1da177e4
LT		 574 prom_halt();
575 }
b206fc4c 576 n = n / sizeof(struct linux_prom_translation);
1da177e4
LT		 577
578 for (i = 0; i < n; i++) {
b206fc4c
DM		 579 unsigned long vaddr = prom_trans[i].virt;
580 unsigned long size = prom_trans[i].size;
1da177e4
LT		 581
582 if (vaddr < 0xf0000000UL) {
583 unsigned long avoid_start = (unsigned long) KERNBASE;
584 unsigned long avoid_end = avoid_start + (4 * 1024 * 1024);
585
586 if (bigkernel)
587 avoid_end += (4 * 1024 * 1024);
588 if (vaddr < avoid_start) {
589 unsigned long top = vaddr + size;
590
591 if (top > avoid_start)
592 top = avoid_start;
593 prom_unmap(top - vaddr, vaddr);
594 }
595 if ((vaddr + size) > avoid_end) {
596 unsigned long bottom = vaddr;
597
598 if (bottom < avoid_end)
599 bottom = avoid_end;
600 prom_unmap((vaddr + size) - bottom, bottom);
601 }
602 }
603 }
604
605 prom_printf("done.\n");
606
607 register_prom_callbacks();
608}
609
610/* The OBP specifications for sun4u mark 0xfffffffc00000000 and
611 * upwards as reserved for use by the firmware (I wonder if this
612 * will be the same on Cheetah...). We use this virtual address
613 * range for the VPTE table mappings of the nucleus so we need
614 * to zap them when we enter the PROM. -DaveM
615 */
616static void __flush_nucleus_vptes(void)
617{
618 unsigned long prom_reserved_base = 0xfffffffc00000000UL;
619 int i;
620
621 /* Only DTLB must be checked for VPTE entries. */
622 if (tlb_type == spitfire) {
623 for (i = 0; i < 63; i++) {
624 unsigned long tag;
625
626 /* Spitfire Errata #32 workaround */
627 /* NOTE: Always runs on spitfire, so no cheetah+
628 * page size encodings.
629 */
630 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
631 "flush %%g6"
632 : /* No outputs */
633 : "r" (0),
634 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
635
636 tag = spitfire_get_dtlb_tag(i);
637 if (((tag & ~(PAGE_MASK)) == 0) &&
638 ((tag & (PAGE_MASK)) >= prom_reserved_base)) {
639 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
640 "membar #Sync"
641 : /* no outputs */
642 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
643 spitfire_put_dtlb_data(i, 0x0UL);
644 }
645 }
646 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
647 for (i = 0; i < 512; i++) {
648 unsigned long tag = cheetah_get_dtlb_tag(i, 2);
649
650 if ((tag & ~PAGE_MASK) == 0 &&
651 (tag & PAGE_MASK) >= prom_reserved_base) {
652 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
653 "membar #Sync"
654 : /* no outputs */
655 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
656 cheetah_put_dtlb_data(i, 0x0UL, 2);
657 }
658
659 if (tlb_type != cheetah_plus)
660 continue;
661
662 tag = cheetah_get_dtlb_tag(i, 3);
663
664 if ((tag & ~PAGE_MASK) == 0 &&
665 (tag & PAGE_MASK) >= prom_reserved_base) {
666 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
667 "membar #Sync"
668 : /* no outputs */
669 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
670 cheetah_put_dtlb_data(i, 0x0UL, 3);
671 }
672 }
673 } else {
674 /* Implement me :-) */
675 BUG();
676 }
677}
678
679static int prom_ditlb_set;
680struct prom_tlb_entry {
681 int tlb_ent;
682 unsigned long tlb_tag;
683 unsigned long tlb_data;
684};
685struct prom_tlb_entry prom_itlb[16], prom_dtlb[16];
686
687void prom_world(int enter)
688{
689 unsigned long pstate;
690 int i;
691
692 if (!enter)
693 set_fs((mm_segment_t) { get_thread_current_ds() });
694
695 if (!prom_ditlb_set)
696 return;
697
698 /* Make sure the following runs atomically. */
699 __asm__ __volatile__("flushw\n\t"
700 "rdpr %%pstate, %0\n\t"
701 "wrpr %0, %1, %%pstate"
702 : "=r" (pstate)
703 : "i" (PSTATE_IE));
704
705 if (enter) {
706 /* Kick out nucleus VPTEs. */
707 __flush_nucleus_vptes();
708
709 /* Install PROM world. */
710 for (i = 0; i < 16; i++) {
711 if (prom_dtlb[i].tlb_ent != -1) {
712 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
713 "membar #Sync"
714 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
715 "i" (ASI_DMMU));
716 if (tlb_type == spitfire)
717 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
718 prom_dtlb[i].tlb_data);
719 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
720 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
721 prom_dtlb[i].tlb_data);
722 }
723 if (prom_itlb[i].tlb_ent != -1) {
724 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
725 "membar #Sync"
726 : : "r" (prom_itlb[i].tlb_tag),
727 "r" (TLB_TAG_ACCESS),
728 "i" (ASI_IMMU));
729 if (tlb_type == spitfire)
730 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
731 prom_itlb[i].tlb_data);
732 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
733 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
734 prom_itlb[i].tlb_data);
735 }
736 }
737 } else {
738 for (i = 0; i < 16; i++) {
739 if (prom_dtlb[i].tlb_ent != -1) {
740 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
741 "membar #Sync"
742 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
743 if (tlb_type == spitfire)
744 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
745 else
746 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
747 }
748 if (prom_itlb[i].tlb_ent != -1) {
749 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
750 "membar #Sync"
751 : : "r" (TLB_TAG_ACCESS),
752 "i" (ASI_IMMU));
753 if (tlb_type == spitfire)
754 spitfire_put_itlb_data(prom_itlb[i].tlb_ent, 0x0UL);
755 else
756 cheetah_put_litlb_data(prom_itlb[i].tlb_ent, 0x0UL);
757 }
758 }
759 }
760 __asm__ __volatile__("wrpr %0, 0, %%pstate"
761 : : "r" (pstate));
762}
763
764void inherit_locked_prom_mappings(int save_p)
765{
766 int i;
767 int dtlb_seen = 0;
768 int itlb_seen = 0;
769
770 /* Fucking losing PROM has more mappings in the TLB, but
771 * it (conveniently) fails to mention any of these in the
772 * translations property. The only ones that matter are
773 * the locked PROM tlb entries, so we impose the following
774 * irrecovable rule on the PROM, it is allowed 8 locked
775 * entries in the ITLB and 8 in the DTLB.
776 *
777 * Supposedly the upper 16GB of the address space is
778 * reserved for OBP, BUT I WISH THIS WAS DOCUMENTED
779 * SOMEWHERE!!!!!!!!!!!!!!!!! Furthermore the entire interface
780 * used between the client program and the firmware on sun5
781 * systems to coordinate mmu mappings is also COMPLETELY
782 * UNDOCUMENTED!!!!!! Thanks S(t)un!
783 */
784 if (save_p) {
785 for (i = 0; i < 16; i++) {
786 prom_itlb[i].tlb_ent = -1;
787 prom_dtlb[i].tlb_ent = -1;
788 }
789 }
790 if (tlb_type == spitfire) {
791 int high = SPITFIRE_HIGHEST_LOCKED_TLBENT - bigkernel;
792 for (i = 0; i < high; i++) {
793 unsigned long data;
794
795 /* Spitfire Errata #32 workaround */
796 /* NOTE: Always runs on spitfire, so no cheetah+
797 * page size encodings.
798 */
799 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
800 "flush %%g6"
801 : /* No outputs */
802 : "r" (0),
803 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
804
805 data = spitfire_get_dtlb_data(i);
806 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
807 unsigned long tag;
808
809 /* Spitfire Errata #32 workaround */
810 /* NOTE: Always runs on spitfire, so no
811 * cheetah+ page size encodings.
812 */
813 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
814 "flush %%g6"
815 : /* No outputs */
816 : "r" (0),
817 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
818
819 tag = spitfire_get_dtlb_tag(i);
820 if (save_p) {
821 prom_dtlb[dtlb_seen].tlb_ent = i;
822 prom_dtlb[dtlb_seen].tlb_tag = tag;
823 prom_dtlb[dtlb_seen].tlb_data = data;
824 }
825 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
826 "membar #Sync"
827 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
828 spitfire_put_dtlb_data(i, 0x0UL);
829
830 dtlb_seen++;
831 if (dtlb_seen > 15)
832 break;
833 }
834 }
835
836 for (i = 0; i < high; i++) {
837 unsigned long data;
838
839 /* Spitfire Errata #32 workaround */
840 /* NOTE: Always runs on spitfire, so no
841 * cheetah+ page size encodings.
842 */
843 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
844 "flush %%g6"
845 : /* No outputs */
846 : "r" (0),
847 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
848
849 data = spitfire_get_itlb_data(i);
850 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
851 unsigned long tag;
852
853 /* Spitfire Errata #32 workaround */
854 /* NOTE: Always runs on spitfire, so no
855 * cheetah+ page size encodings.
856 */
857 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
858 "flush %%g6"
859 : /* No outputs */
860 : "r" (0),
861 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
862
863 tag = spitfire_get_itlb_tag(i);
864 if (save_p) {
865 prom_itlb[itlb_seen].tlb_ent = i;
866 prom_itlb[itlb_seen].tlb_tag = tag;
867 prom_itlb[itlb_seen].tlb_data = data;
868 }
869 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
870 "membar #Sync"
871 : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
872 spitfire_put_itlb_data(i, 0x0UL);
873
874 itlb_seen++;
875 if (itlb_seen > 15)
876 break;
877 }
878 }
879 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
880 int high = CHEETAH_HIGHEST_LOCKED_TLBENT - bigkernel;
881
882 for (i = 0; i < high; i++) {
883 unsigned long data;
884
885 data = cheetah_get_ldtlb_data(i);
886 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
887 unsigned long tag;
888
889 tag = cheetah_get_ldtlb_tag(i);
890 if (save_p) {
891 prom_dtlb[dtlb_seen].tlb_ent = i;
892 prom_dtlb[dtlb_seen].tlb_tag = tag;
893 prom_dtlb[dtlb_seen].tlb_data = data;
894 }
895 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
896 "membar #Sync"
897 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
898 cheetah_put_ldtlb_data(i, 0x0UL);
899
900 dtlb_seen++;
901 if (dtlb_seen > 15)
902 break;
903 }
904 }
905
906 for (i = 0; i < high; i++) {
907 unsigned long data;
908
909 data = cheetah_get_litlb_data(i);
910 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
911 unsigned long tag;
912
913 tag = cheetah_get_litlb_tag(i);
914 if (save_p) {
915 prom_itlb[itlb_seen].tlb_ent = i;
916 prom_itlb[itlb_seen].tlb_tag = tag;
917 prom_itlb[itlb_seen].tlb_data = data;
918 }
919 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
920 "membar #Sync"
921 : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
922 cheetah_put_litlb_data(i, 0x0UL);
923
924 itlb_seen++;
925 if (itlb_seen > 15)
926 break;
927 }
928 }
929 } else {
930 /* Implement me :-) */
931 BUG();
932 }
933 if (save_p)
934 prom_ditlb_set = 1;
935}
936
937/* Give PROM back his world, done during reboots... */
938void prom_reload_locked(void)
939{
940 int i;
941
942 for (i = 0; i < 16; i++) {
943 if (prom_dtlb[i].tlb_ent != -1) {
944 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
945 "membar #Sync"
946 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
947 "i" (ASI_DMMU));
948 if (tlb_type == spitfire)
949 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
950 prom_dtlb[i].tlb_data);
951 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
952 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
953 prom_dtlb[i].tlb_data);
954 }
955
956 if (prom_itlb[i].tlb_ent != -1) {
957 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
958 "membar #Sync"
959 : : "r" (prom_itlb[i].tlb_tag),
960 "r" (TLB_TAG_ACCESS),
961 "i" (ASI_IMMU));
962 if (tlb_type == spitfire)
963 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
964 prom_itlb[i].tlb_data);
965 else
966 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
967 prom_itlb[i].tlb_data);
968 }
969 }
970}
971
972#ifdef DCACHE_ALIASING_POSSIBLE
973void __flush_dcache_range(unsigned long start, unsigned long end)
974{
975 unsigned long va;
976
977 if (tlb_type == spitfire) {
978 int n = 0;
979
980 for (va = start; va < end; va += 32) {
981 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
982 if (++n >= 512)
983 break;
984 }
985 } else {
986 start = __pa(start);
987 end = __pa(end);
988 for (va = start; va < end; va += 32)
989 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
990 "membar #Sync"
991 : /* no outputs */
992 : "r" (va),
993 "i" (ASI_DCACHE_INVALIDATE));
994 }
995}
996#endif /* DCACHE_ALIASING_POSSIBLE */
997
998/* If not locked, zap it. */
999void __flush_tlb_all(void)
1000{
1001 unsigned long pstate;
1002 int i;
1003
1004 __asm__ __volatile__("flushw\n\t"
1005 "rdpr %%pstate, %0\n\t"
1006 "wrpr %0, %1, %%pstate"
1007 : "=r" (pstate)
1008 : "i" (PSTATE_IE));
1009 if (tlb_type == spitfire) {
1010 for (i = 0; i < 64; i++) {
1011 /* Spitfire Errata #32 workaround */
1012 /* NOTE: Always runs on spitfire, so no
1013 * cheetah+ page size encodings.
1014 */
1015 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1016 "flush %%g6"
1017 : /* No outputs */
1018 : "r" (0),
1019 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1020
1021 if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
1022 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1023 "membar #Sync"
1024 : /* no outputs */
1025 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1026 spitfire_put_dtlb_data(i, 0x0UL);
1027 }
1028
1029 /* Spitfire Errata #32 workaround */
1030 /* NOTE: Always runs on spitfire, so no
1031 * cheetah+ page size encodings.
1032 */
1033 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1034 "flush %%g6"
1035 : /* No outputs */
1036 : "r" (0),
1037 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1038
1039 if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
1040 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1041 "membar #Sync"
1042 : /* no outputs */
1043 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1044 spitfire_put_itlb_data(i, 0x0UL);
1045 }
1046 }
1047 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1048 cheetah_flush_dtlb_all();
1049 cheetah_flush_itlb_all();
1050 }
1051 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1052 : : "r" (pstate));
1053}
1054
1055/* Caller does TLB context flushing on local CPU if necessary.
1056 * The caller also ensures that CTX_VALID(mm->context) is false.
1057 *
1058 * We must be careful about boundary cases so that we never
1059 * let the user have CTX 0 (nucleus) or we ever use a CTX
1060 * version of zero (and thus NO_CONTEXT would not be caught
1061 * by version mis-match tests in mmu_context.h).
1062 */
1063void get_new_mmu_context(struct mm_struct *mm)
1064{
1065 unsigned long ctx, new_ctx;
1066 unsigned long orig_pgsz_bits;
1067
1068
1069 spin_lock(&ctx_alloc_lock);
1070 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
1071 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
1072 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
1073 if (new_ctx >= (1 << CTX_NR_BITS)) {
1074 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
1075 if (new_ctx >= ctx) {
1076 int i;
1077 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
1078 CTX_FIRST_VERSION;
1079 if (new_ctx == 1)
1080 new_ctx = CTX_FIRST_VERSION;
1081
1082 /* Don't call memset, for 16 entries that's just
1083 * plain silly...
1084 */
1085 mmu_context_bmap[0] = 3;
1086 mmu_context_bmap[1] = 0;
1087 mmu_context_bmap[2] = 0;
1088 mmu_context_bmap[3] = 0;
1089 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
1090 mmu_context_bmap[i + 0] = 0;
1091 mmu_context_bmap[i + 1] = 0;
1092 mmu_context_bmap[i + 2] = 0;
1093 mmu_context_bmap[i + 3] = 0;
1094 }
1095 goto out;
1096 }
1097 }
1098 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
1099 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
1100out:
1101 tlb_context_cache = new_ctx;
1102 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
1103 spin_unlock(&ctx_alloc_lock);
1104}
1105
1106#ifndef CONFIG_SMP
1107struct pgtable_cache_struct pgt_quicklists;
1108#endif
1109
1110/* OK, we have to color these pages. The page tables are accessed
1111 * by non-Dcache enabled mapping in the VPTE area by the dtlb_backend.S
1112 * code, as well as by PAGE_OFFSET range direct-mapped addresses by
1113 * other parts of the kernel. By coloring, we make sure that the tlbmiss
1114 * fast handlers do not get data from old/garbage dcache lines that
1115 * correspond to an old/stale virtual address (user/kernel) that
1116 * previously mapped the pagetable page while accessing vpte range
1117 * addresses. The idea is that if the vpte color and PAGE_OFFSET range
1118 * color is the same, then when the kernel initializes the pagetable
1119 * using the later address range, accesses with the first address
1120 * range will see the newly initialized data rather than the garbage.
1121 */
1122#ifdef DCACHE_ALIASING_POSSIBLE
1123#define DC_ALIAS_SHIFT 1
1124#else
1125#define DC_ALIAS_SHIFT 0
1126#endif
8edf72eb 1127pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
1da177e4
LT		 1128{
1129 struct page *page;
1130 unsigned long color;
1131
1132 {
1133 pte_t *ptep = pte_alloc_one_fast(mm, address);
1134
1135 if (ptep)
1136 return ptep;
1137 }
1138
1139 color = VPTE_COLOR(address);
1140 page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, DC_ALIAS_SHIFT);
1141 if (page) {
1142 unsigned long *to_free;
1143 unsigned long paddr;
1144 pte_t *pte;
1145
1146#ifdef DCACHE_ALIASING_POSSIBLE
1147 set_page_count(page, 1);
1148 ClearPageCompound(page);
1149
1150 set_page_count((page + 1), 1);
1151 ClearPageCompound(page + 1);
1152#endif
1153 paddr = (unsigned long) page_address(page);
1154 memset((char *)paddr, 0, (PAGE_SIZE << DC_ALIAS_SHIFT));
1155
1156 if (!color) {
1157 pte = (pte_t *) paddr;
1158 to_free = (unsigned long *) (paddr + PAGE_SIZE);
1159 } else {
1160 pte = (pte_t *) (paddr + PAGE_SIZE);
1161 to_free = (unsigned long *) paddr;
1162 }
1163
1164#ifdef DCACHE_ALIASING_POSSIBLE
1165 /* Now free the other one up, adjust cache size. */
1166 preempt_disable();
1167 *to_free = (unsigned long) pte_quicklist[color ^ 0x1];
1168 pte_quicklist[color ^ 0x1] = to_free;
1169 pgtable_cache_size++;
1170 preempt_enable();
1171#endif
1172
1173 return pte;
1174 }
1175 return NULL;
1176}
1177
1178void sparc_ultra_dump_itlb(void)
1179{
1180 int slot;
1181
1182 if (tlb_type == spitfire) {
1183 printk ("Contents of itlb: ");
1184 for (slot = 0; slot < 14; slot++) printk (" ");
1185 printk ("%2x:%016lx,%016lx\n",
1186 0,
1187 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
1188 for (slot = 1; slot < 64; slot+=3) {
1189 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1190 slot,
1191 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
1192 slot+1,
1193 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
1194 slot+2,
1195 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
1196 }
1197 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1198 printk ("Contents of itlb0:\n");
1199 for (slot = 0; slot < 16; slot+=2) {
1200 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1201 slot,
1202 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
1203 slot+1,
1204 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
1205 }
1206 printk ("Contents of itlb2:\n");
1207 for (slot = 0; slot < 128; slot+=2) {
1208 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1209 slot,
1210 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
1211 slot+1,
1212 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
1213 }
1214 }
1215}
1216
1217void sparc_ultra_dump_dtlb(void)
1218{
1219 int slot;
1220
1221 if (tlb_type == spitfire) {
1222 printk ("Contents of dtlb: ");
1223 for (slot = 0; slot < 14; slot++) printk (" ");
1224 printk ("%2x:%016lx,%016lx\n", 0,
1225 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
1226 for (slot = 1; slot < 64; slot+=3) {
1227 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1228 slot,
1229 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
1230 slot+1,
1231 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
1232 slot+2,
1233 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
1234 }
1235 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1236 printk ("Contents of dtlb0:\n");
1237 for (slot = 0; slot < 16; slot+=2) {
1238 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1239 slot,
1240 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
1241 slot+1,
1242 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
1243 }
1244 printk ("Contents of dtlb2:\n");
1245 for (slot = 0; slot < 512; slot+=2) {
1246 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1247 slot,
1248 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
1249 slot+1,
1250 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
1251 }
1252 if (tlb_type == cheetah_plus) {
1253 printk ("Contents of dtlb3:\n");
1254 for (slot = 0; slot < 512; slot+=2) {
1255 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1256 slot,
1257 cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
1258 slot+1,
1259 cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
1260 }
1261 }
1262 }
1263}
1264
1265extern unsigned long cmdline_memory_size;
1266
1267unsigned long __init bootmem_init(unsigned long *pages_avail)
1268{
1269 unsigned long bootmap_size, start_pfn, end_pfn;
1270 unsigned long end_of_phys_memory = 0UL;
1271 unsigned long bootmap_pfn, bytes_avail, size;
1272 int i;
1273
1274#ifdef CONFIG_DEBUG_BOOTMEM
1275 prom_printf("bootmem_init: Scan sp_banks, ");
1276#endif
1277
1278 bytes_avail = 0UL;
1279 for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1280 end_of_phys_memory = sp_banks[i].base_addr +
1281 sp_banks[i].num_bytes;
1282 bytes_avail += sp_banks[i].num_bytes;
1283 if (cmdline_memory_size) {
1284 if (bytes_avail > cmdline_memory_size) {
1285 unsigned long slack = bytes_avail - cmdline_memory_size;
1286
1287 bytes_avail -= slack;
1288 end_of_phys_memory -= slack;
1289
1290 sp_banks[i].num_bytes -= slack;
1291 if (sp_banks[i].num_bytes == 0) {
1292 sp_banks[i].base_addr = 0xdeadbeef;
1293 } else {
1294 sp_banks[i+1].num_bytes = 0;
1295 sp_banks[i+1].base_addr = 0xdeadbeef;
1296 }
1297 break;
1298 }
1299 }
1300 }
1301
1302 *pages_avail = bytes_avail >> PAGE_SHIFT;
1303
1304 /* Start with page aligned address of last symbol in kernel
1305 * image. The kernel is hard mapped below PAGE_OFFSET in a
1306 * 4MB locked TLB translation.
1307 */
1308 start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
1309
1310 bootmap_pfn = start_pfn;
1311
1312 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1313
1314#ifdef CONFIG_BLK_DEV_INITRD
1315 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
1316 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
1317 unsigned long ramdisk_image = sparc_ramdisk_image ?
1318 sparc_ramdisk_image : sparc_ramdisk_image64;
1319 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
1320 ramdisk_image -= KERNBASE;
1321 initrd_start = ramdisk_image + phys_base;
1322 initrd_end = initrd_start + sparc_ramdisk_size;
1323 if (initrd_end > end_of_phys_memory) {
1324 printk(KERN_CRIT "initrd extends beyond end of memory "
1325 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1326 initrd_end, end_of_phys_memory);
1327 initrd_start = 0;
1328 }
1329 if (initrd_start) {
1330 if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
1331 initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
1332 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
1333 }
1334 }
1335#endif
1336 /* Initialize the boot-time allocator. */
1337 max_pfn = max_low_pfn = end_pfn;
1338 min_low_pfn = pfn_base;
1339
1340#ifdef CONFIG_DEBUG_BOOTMEM
1341 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1342 min_low_pfn, bootmap_pfn, max_low_pfn);
1343#endif
1344 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
1345
1346 bootmap_base = bootmap_pfn << PAGE_SHIFT;
1347
1348 /* Now register the available physical memory with the
1349 * allocator.
1350 */
1351 for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1352#ifdef CONFIG_DEBUG_BOOTMEM
1353 prom_printf("free_bootmem(sp_banks:%d): base[%lx] size[%lx]\n",
1354 i, sp_banks[i].base_addr, sp_banks[i].num_bytes);
1355#endif
1356 free_bootmem(sp_banks[i].base_addr, sp_banks[i].num_bytes);
1357 }
1358
1359#ifdef CONFIG_BLK_DEV_INITRD
1360 if (initrd_start) {
1361 size = initrd_end - initrd_start;
1362
1363 /* Resert the initrd image area. */
1364#ifdef CONFIG_DEBUG_BOOTMEM
1365 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
1366 initrd_start, initrd_end);
1367#endif
1368 reserve_bootmem(initrd_start, size);
1369 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1370
1371 initrd_start += PAGE_OFFSET;
1372 initrd_end += PAGE_OFFSET;
1373 }
1374#endif
1375 /* Reserve the kernel text/data/bss. */
1376#ifdef CONFIG_DEBUG_BOOTMEM
1377 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1378#endif
1379 reserve_bootmem(kern_base, kern_size);
1380 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1381
1382 /* Reserve the bootmem map. We do not account for it
1383 * in pages_avail because we will release that memory
1384 * in free_all_bootmem.
1385 */
1386 size = bootmap_size;
1387#ifdef CONFIG_DEBUG_BOOTMEM
1388 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1389 (bootmap_pfn << PAGE_SHIFT), size);
1390#endif
1391 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1392 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1393
1394 return end_pfn;
1395}
1396
1397/* paging_init() sets up the page tables */
1398
1399extern void cheetah_ecache_flush_init(void);
1400
1401static unsigned long last_valid_pfn;
1402
1403void __init paging_init(void)
1404{
1405 extern pmd_t swapper_pmd_dir[1024];
1da177e4
LT		 1406 unsigned long alias_base = kern_base + PAGE_OFFSET;
1407 unsigned long second_alias_page = 0;
1408 unsigned long pt, flags, end_pfn, pages_avail;
1409 unsigned long shift = alias_base - ((unsigned long)KERNBASE);
1410 unsigned long real_end;
1411
1412 set_bit(0, mmu_context_bmap);
1413
1414 real_end = (unsigned long)_end;
1415 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1416 bigkernel = 1;
1417#ifdef CONFIG_BLK_DEV_INITRD
1418 if (sparc_ramdisk_image || sparc_ramdisk_image64)
1419 real_end = (PAGE_ALIGN(real_end) + PAGE_ALIGN(sparc_ramdisk_size));
1420#endif
1421
1422 /* We assume physical memory starts at some 4mb multiple,
1423 * if this were not true we wouldn't boot up to this point
1424 * anyways.
1425 */
1426 pt = kern_base | _PAGE_VALID | _PAGE_SZ4MB;
1427 pt |= _PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W;
1428 local_irq_save(flags);
1429 if (tlb_type == spitfire) {
1430 __asm__ __volatile__(
1431 " stxa %1, [%0] %3\n"
1432 " stxa %2, [%5] %4\n"
1433 " membar #Sync\n"
1434 " flush %%g6\n"
1435 " nop\n"
1436 " nop\n"
1437 " nop\n"
1438 : /* No outputs */
1439 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1440 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (61 << 3)
1441 : "memory");
1442 if (real_end >= KERNBASE + 0x340000) {
1443 second_alias_page = alias_base + 0x400000;
1444 __asm__ __volatile__(
1445 " stxa %1, [%0] %3\n"
1446 " stxa %2, [%5] %4\n"
1447 " membar #Sync\n"
1448 " flush %%g6\n"
1449 " nop\n"
1450 " nop\n"
1451 " nop\n"
1452 : /* No outputs */
1453 : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1454 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (60 << 3)
1455 : "memory");
1456 }
1457 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1458 __asm__ __volatile__(
1459 " stxa %1, [%0] %3\n"
1460 " stxa %2, [%5] %4\n"
1461 " membar #Sync\n"
1462 " flush %%g6\n"
1463 " nop\n"
1464 " nop\n"
1465 " nop\n"
1466 : /* No outputs */
1467 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1468 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (13<<3))
1469 : "memory");
1470 if (real_end >= KERNBASE + 0x340000) {
1471 second_alias_page = alias_base + 0x400000;
1472 __asm__ __volatile__(
1473 " stxa %1, [%0] %3\n"
1474 " stxa %2, [%5] %4\n"
1475 " membar #Sync\n"
1476 " flush %%g6\n"
1477 " nop\n"
1478 " nop\n"
1479 " nop\n"
1480 : /* No outputs */
1481 : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1482 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (12<<3))
1483 : "memory");
1484 }
1485 }
1486 local_irq_restore(flags);
1487
1488 /* Now set kernel pgd to upper alias so physical page computations
1489 * work.
1490 */
1491 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1492
1493 memset(swapper_pmd_dir, 0, sizeof(swapper_pmd_dir));
1494
1495 /* Now can init the kernel/bad page tables. */
1496 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1497 swapper_pmd_dir + (shift / sizeof(pgd_t)));
1498
1ac4f5eb 1499 swapper_pgd_zero = pgd_val(init_mm.pgd[0]);
1da177e4
LT		 1500
1501 /* Setup bootmem... */
1502 pages_avail = 0;
1503 last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1504
1505 /* Inherit non-locked OBP mappings. */
1506 inherit_prom_mappings();
1507
1508 /* Ok, we can use our TLB miss and window trap handlers safely.
1509 * We need to do a quick peek here to see if we are on StarFire
1510 * or not, so setup_tba can setup the IRQ globals correctly (it
1511 * needs to get the hard smp processor id correctly).
1512 */
1513 {
1514 extern void setup_tba(int);
1515 setup_tba(this_is_starfire);
1516 }
1517
1518 inherit_locked_prom_mappings(1);
1519
1520 /* We only created DTLB mapping of this stuff. */
1521 spitfire_flush_dtlb_nucleus_page(alias_base);
1522 if (second_alias_page)
1523 spitfire_flush_dtlb_nucleus_page(second_alias_page);
1524
1525 __flush_tlb_all();
1526
1527 {
1528 unsigned long zones_size[MAX_NR_ZONES];
1529 unsigned long zholes_size[MAX_NR_ZONES];
1530 unsigned long npages;
1531 int znum;
1532
1533 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1534 zones_size[znum] = zholes_size[znum] = 0;
1535
1536 npages = end_pfn - pfn_base;
1537 zones_size[ZONE_DMA] = npages;
1538 zholes_size[ZONE_DMA] = npages - pages_avail;
1539
1540 free_area_init_node(0, &contig_page_data, zones_size,
1541 phys_base >> PAGE_SHIFT, zholes_size);
1542 }
1543
1544 device_scan();
1545}
1546
1547/* Ok, it seems that the prom can allocate some more memory chunks
1548 * as a side effect of some prom calls we perform during the
1549 * boot sequence. My most likely theory is that it is from the
1550 * prom_set_traptable() call, and OBP is allocating a scratchpad
1551 * for saving client program register state etc.
1552 */
1553static void __init sort_memlist(struct linux_mlist_p1275 *thislist)
1554{
1555 int swapi = 0;
1556 int i, mitr;
1557 unsigned long tmpaddr, tmpsize;
1558 unsigned long lowest;
1559
1560 for (i = 0; thislist[i].theres_more != 0; i++) {
1561 lowest = thislist[i].start_adr;
1562 for (mitr = i+1; thislist[mitr-1].theres_more != 0; mitr++)
1563 if (thislist[mitr].start_adr < lowest) {
1564 lowest = thislist[mitr].start_adr;
1565 swapi = mitr;
1566 }
1567 if (lowest == thislist[i].start_adr)
1568 continue;
1569 tmpaddr = thislist[swapi].start_adr;
1570 tmpsize = thislist[swapi].num_bytes;
1571 for (mitr = swapi; mitr > i; mitr--) {
1572 thislist[mitr].start_adr = thislist[mitr-1].start_adr;
1573 thislist[mitr].num_bytes = thislist[mitr-1].num_bytes;
1574 }
1575 thislist[i].start_adr = tmpaddr;
1576 thislist[i].num_bytes = tmpsize;
1577 }
1578}
1579
1580void __init rescan_sp_banks(void)
1581{
1582 struct linux_prom64_registers memlist[64];
1583 struct linux_mlist_p1275 avail[64], *mlist;
1584 unsigned long bytes, base_paddr;
1585 int num_regs, node = prom_finddevice("/memory");
1586 int i;
1587
1588 num_regs = prom_getproperty(node, "available",
1589 (char *) memlist, sizeof(memlist));
1590 num_regs = (num_regs / sizeof(struct linux_prom64_registers));
1591 for (i = 0; i < num_regs; i++) {
1592 avail[i].start_adr = memlist[i].phys_addr;
1593 avail[i].num_bytes = memlist[i].reg_size;
1594 avail[i].theres_more = &avail[i + 1];
1595 }
1596 avail[i - 1].theres_more = NULL;
1597 sort_memlist(avail);
1598
1599 mlist = &avail[0];
1600 i = 0;
1601 bytes = mlist->num_bytes;
1602 base_paddr = mlist->start_adr;
1603
1604 sp_banks[0].base_addr = base_paddr;
1605 sp_banks[0].num_bytes = bytes;
1606
1607 while (mlist->theres_more != NULL){
1608 i++;
1609 mlist = mlist->theres_more;
1610 bytes = mlist->num_bytes;
1611 if (i >= SPARC_PHYS_BANKS-1) {
1612 printk ("The machine has more banks than "
1613 "this kernel can support\n"
1614 "Increase the SPARC_PHYS_BANKS "
1615 "setting (currently %d)\n",
1616 SPARC_PHYS_BANKS);
1617 i = SPARC_PHYS_BANKS-1;
1618 break;
1619 }
1620
1621 sp_banks[i].base_addr = mlist->start_adr;
1622 sp_banks[i].num_bytes = mlist->num_bytes;
1623 }
1624
1625 i++;
1626 sp_banks[i].base_addr = 0xdeadbeefbeefdeadUL;
1627 sp_banks[i].num_bytes = 0;
1628
1629 for (i = 0; sp_banks[i].num_bytes != 0; i++)
1630 sp_banks[i].num_bytes &= PAGE_MASK;
1631}
1632
1633static void __init taint_real_pages(void)
1634{
1635 struct sparc_phys_banks saved_sp_banks[SPARC_PHYS_BANKS];
1636 int i;
1637
1638 for (i = 0; i < SPARC_PHYS_BANKS; i++) {
1639 saved_sp_banks[i].base_addr =
1640 sp_banks[i].base_addr;
1641 saved_sp_banks[i].num_bytes =
1642 sp_banks[i].num_bytes;
1643 }
1644
1645 rescan_sp_banks();
1646
1647 /* Find changes discovered in the sp_bank rescan and
1648 * reserve the lost portions in the bootmem maps.
1649 */
1650 for (i = 0; saved_sp_banks[i].num_bytes; i++) {
1651 unsigned long old_start, old_end;
1652
1653 old_start = saved_sp_banks[i].base_addr;
1654 old_end = old_start +
1655 saved_sp_banks[i].num_bytes;
1656 while (old_start < old_end) {
1657 int n;
1658
1659 for (n = 0; sp_banks[n].num_bytes; n++) {
1660 unsigned long new_start, new_end;
1661
1662 new_start = sp_banks[n].base_addr;
1663 new_end = new_start + sp_banks[n].num_bytes;
1664
1665 if (new_start <= old_start &&
1666 new_end >= (old_start + PAGE_SIZE)) {
1667 set_bit (old_start >> 22,
1668 sparc64_valid_addr_bitmap);
1669 goto do_next_page;
1670 }
1671 }
1672 reserve_bootmem(old_start, PAGE_SIZE);
1673
1674 do_next_page:
1675 old_start += PAGE_SIZE;
1676 }
1677 }
1678}
1679
1680void __init mem_init(void)
1681{
1682 unsigned long codepages, datapages, initpages;
1683 unsigned long addr, last;
1684 int i;
1685
1686 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1687 i += 1;
1688 sparc64_valid_addr_bitmap = (unsigned long *)
1689 __alloc_bootmem(i << 3, SMP_CACHE_BYTES, bootmap_base);
1690 if (sparc64_valid_addr_bitmap == NULL) {
1691 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1692 prom_halt();
1693 }
1694 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1695
1696 addr = PAGE_OFFSET + kern_base;
1697 last = PAGE_ALIGN(kern_size) + addr;
1698 while (addr < last) {
1699 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1700 addr += PAGE_SIZE;
1701 }
1702
1703 taint_real_pages();
1704
1705 max_mapnr = last_valid_pfn - pfn_base;
1706 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1707
1708#ifdef CONFIG_DEBUG_BOOTMEM
1709 prom_printf("mem_init: Calling free_all_bootmem().\n");
1710#endif
1711 totalram_pages = num_physpages = free_all_bootmem() - 1;
1712
1713 /*
1714 * Set up the zero page, mark it reserved, so that page count
1715 * is not manipulated when freeing the page from user ptes.
1716 */
1717 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1718 if (mem_map_zero == NULL) {
1719 prom_printf("paging_init: Cannot alloc zero page.\n");
1720 prom_halt();
1721 }
1722 SetPageReserved(mem_map_zero);
1723
1724 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1725 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1726 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1727 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1728 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1729 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1730
1731 printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1732 nr_free_pages() << (PAGE_SHIFT-10),
1733 codepages << (PAGE_SHIFT-10),
1734 datapages << (PAGE_SHIFT-10),
1735 initpages << (PAGE_SHIFT-10),
1736 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1737
1738 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1739 cheetah_ecache_flush_init();
1740}
1741
1742void free_initmem (void)
1743{
1744 unsigned long addr, initend;
1745
1746 /*
1747 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1748 */
1749 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1750 initend = (unsigned long)(__init_end) & PAGE_MASK;
1751 for (; addr < initend; addr += PAGE_SIZE) {
1752 unsigned long page;
1753 struct page *p;
1754
1755 page = (addr +
1756 ((unsigned long) __va(kern_base)) -
1757 ((unsigned long) KERNBASE));
1758 memset((void *)addr, 0xcc, PAGE_SIZE);
1759 p = virt_to_page(page);
1760
1761 ClearPageReserved(p);
1762 set_page_count(p, 1);
1763 __free_page(p);
1764 num_physpages++;
1765 totalram_pages++;
1766 }
1767}
1768
1769#ifdef CONFIG_BLK_DEV_INITRD
1770void free_initrd_mem(unsigned long start, unsigned long end)
1771{
1772 if (start < end)
1773 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1774 for (; start < end; start += PAGE_SIZE) {
1775 struct page *p = virt_to_page(start);
1776
1777 ClearPageReserved(p);
1778 set_page_count(p, 1);
1779 __free_page(p);
1780 num_physpages++;
1781 totalram_pages++;
1782 }
1783}
1784#endif
kernel source for telekom puls (alcatel/mediatek)