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[SPARC64]: Use lmb_alloc() for PROM device tree.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / sparc64 / mm / init.c
CommitLineData
1da177e4
LT		 1/* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
c4bce90e 8#include <linux/module.h>
1da177e4
LT		 9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/string.h>
12#include <linux/init.h>
13#include <linux/bootmem.h>
14#include <linux/mm.h>
15#include <linux/hugetlb.h>
16#include <linux/slab.h>
17#include <linux/initrd.h>
18#include <linux/swap.h>
19#include <linux/pagemap.h>
c9cf5528 20#include <linux/poison.h>
1da177e4
LT		 21#include <linux/fs.h>
22#include <linux/seq_file.h>
05e14cb3 23#include <linux/kprobes.h>
1ac4f5eb 24#include <linux/cache.h>
13edad7a 25#include <linux/sort.h>
5cbc3073 26#include <linux/percpu.h>
3b2a7e23 27#include <linux/lmb.h>
1da177e4
LT		 28
29#include <asm/head.h>
30#include <asm/system.h>
31#include <asm/page.h>
32#include <asm/pgalloc.h>
33#include <asm/pgtable.h>
34#include <asm/oplib.h>
35#include <asm/iommu.h>
36#include <asm/io.h>
37#include <asm/uaccess.h>
38#include <asm/mmu_context.h>
39#include <asm/tlbflush.h>
40#include <asm/dma.h>
41#include <asm/starfire.h>
42#include <asm/tlb.h>
43#include <asm/spitfire.h>
44#include <asm/sections.h>
517af332 45#include <asm/tsb.h>
481295f9 46#include <asm/hypervisor.h>
372b07bb 47#include <asm/prom.h>
22d6a1cb 48#include <asm/sstate.h>
5cbc3073 49#include <asm/mdesc.h>
3d5ae6b6 50#include <asm/cpudata.h>
1da177e4 51
9cc3a1ac
DM		 52#define MAX_PHYS_ADDRESS (1UL << 42UL)
53#define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
54#define KPTE_BITMAP_BYTES \
55 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
56
57unsigned long kern_linear_pte_xor[2] __read_mostly;
58
59/* A bitmap, one bit for every 256MB of physical memory. If the bit
60 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
61 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
62 */
63unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
64
d1acb421 65#ifndef CONFIG_DEBUG_PAGEALLOC
2d9e2763
DM		 66/* A special kernel TSB for 4MB and 256MB linear mappings.
67 * Space is allocated for this right after the trap table
68 * in arch/sparc64/kernel/head.S
69 */
70extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
d1acb421 71#endif
d7744a09 72
13edad7a
DM		 73#define MAX_BANKS 32
74
75static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
76static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
77static int pavail_ents __initdata;
78static int pavail_rescan_ents __initdata;
79
80static int cmp_p64(const void *a, const void *b)
81{
82 const struct linux_prom64_registers *x = a, *y = b;
83
84 if (x->phys_addr > y->phys_addr)
85 return 1;
86 if (x->phys_addr < y->phys_addr)
87 return -1;
88 return 0;
89}
90
91static void __init read_obp_memory(const char *property,
92 struct linux_prom64_registers *regs,
93 int *num_ents)
94{
95 int node = prom_finddevice("/memory");
96 int prop_size = prom_getproplen(node, property);
97 int ents, ret, i;
98
99 ents = prop_size / sizeof(struct linux_prom64_registers);
100 if (ents > MAX_BANKS) {
101 prom_printf("The machine has more %s property entries than "
102 "this kernel can support (%d).\n",
103 property, MAX_BANKS);
104 prom_halt();
105 }
106
107 ret = prom_getproperty(node, property, (char *) regs, prop_size);
108 if (ret == -1) {
109 prom_printf("Couldn't get %s property from /memory.\n");
110 prom_halt();
111 }
112
13edad7a
DM		 113 /* Sanitize what we got from the firmware, by page aligning
114 * everything.
115 */
116 for (i = 0; i < ents; i++) {
117 unsigned long base, size;
118
119 base = regs[i].phys_addr;
120 size = regs[i].reg_size;
10147570 121
13edad7a
DM		 122 size &= PAGE_MASK;
123 if (base & ~PAGE_MASK) {
124 unsigned long new_base = PAGE_ALIGN(base);
125
126 size -= new_base - base;
127 if ((long) size < 0L)
128 size = 0UL;
129 base = new_base;
130 }
0015d3d6
DM		 131 if (size == 0UL) {
132 /* If it is empty, simply get rid of it.
133 * This simplifies the logic of the other
134 * functions that process these arrays.
135 */
136 memmove(&regs[i], &regs[i + 1],
137 (ents - i - 1) * sizeof(regs[0]));
486ad10a 138 i--;
0015d3d6
DM		 139 ents--;
140 continue;
486ad10a 141 }
0015d3d6
DM		 142 regs[i].phys_addr = base;
143 regs[i].reg_size = size;
486ad10a
DM		 144 }
145
146 *num_ents = ents;
147
c9c10830 148 sort(regs, ents, sizeof(struct linux_prom64_registers),
13edad7a
DM		 149 cmp_p64, NULL);
150}
1da177e4 151
2bdb3cb2 152unsigned long *sparc64_valid_addr_bitmap __read_mostly;
1da177e4 153
d1112018 154/* Kernel physical address base and size in bytes. */
1ac4f5eb
DM		 155unsigned long kern_base __read_mostly;
156unsigned long kern_size __read_mostly;
1da177e4 157
1da177e4
LT		 158/* Initial ramdisk setup */
159extern unsigned long sparc_ramdisk_image64;
160extern unsigned int sparc_ramdisk_image;
161extern unsigned int sparc_ramdisk_size;
162
1ac4f5eb 163struct page *mem_map_zero __read_mostly;
1da177e4 164
0835ae0f
DM		 165unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
166
167unsigned long sparc64_kern_pri_context __read_mostly;
168unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
169unsigned long sparc64_kern_sec_context __read_mostly;
170
64658743 171int num_kernel_image_mappings;
1da177e4 172
1da177e4
LT		 173#ifdef CONFIG_DEBUG_DCFLUSH
174atomic_t dcpage_flushes = ATOMIC_INIT(0);
175#ifdef CONFIG_SMP
176atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
177#endif
178#endif
179
7a591cfe 180inline void flush_dcache_page_impl(struct page *page)
1da177e4 181{
7a591cfe 182 BUG_ON(tlb_type == hypervisor);
1da177e4
LT		 183#ifdef CONFIG_DEBUG_DCFLUSH
184 atomic_inc(&dcpage_flushes);
185#endif
186
187#ifdef DCACHE_ALIASING_POSSIBLE
188 __flush_dcache_page(page_address(page),
189 ((tlb_type == spitfire) &&
190 page_mapping(page) != NULL));
191#else
192 if (page_mapping(page) != NULL &&
193 tlb_type == spitfire)
194 __flush_icache_page(__pa(page_address(page)));
195#endif
196}
197
198#define PG_dcache_dirty PG_arch_1
22adb358
DM		 199#define PG_dcache_cpu_shift 32UL
200#define PG_dcache_cpu_mask \
201 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
1da177e4
LT		 202
203#define dcache_dirty_cpu(page) \
48b0e548 204 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
1da177e4 205
d979f179 206static inline void set_dcache_dirty(struct page *page, int this_cpu)
1da177e4
LT		 207{
208 unsigned long mask = this_cpu;
48b0e548
DM		 209 unsigned long non_cpu_bits;
210
211 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
212 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
213
1da177e4
LT		 214 __asm__ __volatile__("1:\n\t"
215 "ldx [%2], %%g7\n\t"
216 "and %%g7, %1, %%g1\n\t"
217 "or %%g1, %0, %%g1\n\t"
218 "casx [%2], %%g7, %%g1\n\t"
219 "cmp %%g7, %%g1\n\t"
b445e26c 220 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 221 "bne,pn %%xcc, 1b\n\t"
b445e26c 222 " nop"
1da177e4
LT		 223 : /* no outputs */
224 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
225 : "g1", "g7");
226}
227
d979f179 228static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
1da177e4
LT		 229{
230 unsigned long mask = (1UL << PG_dcache_dirty);
231
232 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
233 "1:\n\t"
234 "ldx [%2], %%g7\n\t"
48b0e548 235 "srlx %%g7, %4, %%g1\n\t"
1da177e4
LT		 236 "and %%g1, %3, %%g1\n\t"
237 "cmp %%g1, %0\n\t"
238 "bne,pn %%icc, 2f\n\t"
239 " andn %%g7, %1, %%g1\n\t"
240 "casx [%2], %%g7, %%g1\n\t"
241 "cmp %%g7, %%g1\n\t"
b445e26c 242 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 243 "bne,pn %%xcc, 1b\n\t"
b445e26c 244 " nop\n"
1da177e4
LT		 245 "2:"
246 : /* no outputs */
247 : "r" (cpu), "r" (mask), "r" (&page->flags),
48b0e548
DM		 248 "i" (PG_dcache_cpu_mask),
249 "i" (PG_dcache_cpu_shift)
1da177e4
LT		 250 : "g1", "g7");
251}
252
517af332
DM		 253static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
254{
255 unsigned long tsb_addr = (unsigned long) ent;
256
3b3ab2eb 257 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
517af332
DM		 258 tsb_addr = __pa(tsb_addr);
259
260 __tsb_insert(tsb_addr, tag, pte);
261}
262
c4bce90e
DM		 263unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
264unsigned long _PAGE_SZBITS __read_mostly;
265
1da177e4
LT		 266void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
267{
bd40791e 268 struct mm_struct *mm;
74ae9987 269 struct tsb *tsb;
7a1ac526 270 unsigned long tag, flags;
dcc1e8dd 271 unsigned long tsb_index, tsb_hash_shift;
7a591cfe
DM		 272
273 if (tlb_type != hypervisor) {
274 unsigned long pfn = pte_pfn(pte);
275 unsigned long pg_flags;
276 struct page *page;
277
278 if (pfn_valid(pfn) &&
279 (page = pfn_to_page(pfn), page_mapping(page)) &&
280 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
281 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
282 PG_dcache_cpu_mask);
283 int this_cpu = get_cpu();
284
285 /* This is just to optimize away some function calls
286 * in the SMP case.
287 */
288 if (cpu == this_cpu)
289 flush_dcache_page_impl(page);
290 else
291 smp_flush_dcache_page_impl(page, cpu);
292
293 clear_dcache_dirty_cpu(page, cpu);
294
295 put_cpu();
296 }
1da177e4 297 }
bd40791e
DM		 298
299 mm = vma->vm_mm;
7a1ac526 300
dcc1e8dd
DM		 301 tsb_index = MM_TSB_BASE;
302 tsb_hash_shift = PAGE_SHIFT;
303
7a1ac526
DM		 304 spin_lock_irqsave(&mm->context.lock, flags);
305
dcc1e8dd
DM		 306#ifdef CONFIG_HUGETLB_PAGE
307 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
308 if ((tlb_type == hypervisor &&
309 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
310 (tlb_type != hypervisor &&
311 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
312 tsb_index = MM_TSB_HUGE;
313 tsb_hash_shift = HPAGE_SHIFT;
314 }
315 }
316#endif
317
318 tsb = mm->context.tsb_block[tsb_index].tsb;
319 tsb += ((address >> tsb_hash_shift) &
320 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
74ae9987
DM		 321 tag = (address >> 22UL);
322 tsb_insert(tsb, tag, pte_val(pte));
7a1ac526
DM		 323
324 spin_unlock_irqrestore(&mm->context.lock, flags);
1da177e4
LT		 325}
326
327void flush_dcache_page(struct page *page)
328{
a9546f59
DM		 329 struct address_space *mapping;
330 int this_cpu;
1da177e4 331
7a591cfe
DM		 332 if (tlb_type == hypervisor)
333 return;
334
a9546f59
DM		 335 /* Do not bother with the expensive D-cache flush if it
336 * is merely the zero page. The 'bigcore' testcase in GDB
337 * causes this case to run millions of times.
338 */
339 if (page == ZERO_PAGE(0))
340 return;
341
342 this_cpu = get_cpu();
343
344 mapping = page_mapping(page);
1da177e4 345 if (mapping && !mapping_mapped(mapping)) {
a9546f59 346 int dirty = test_bit(PG_dcache_dirty, &page->flags);
1da177e4 347 if (dirty) {
a9546f59
DM		 348 int dirty_cpu = dcache_dirty_cpu(page);
349
1da177e4
LT		 350 if (dirty_cpu == this_cpu)
351 goto out;
352 smp_flush_dcache_page_impl(page, dirty_cpu);
353 }
354 set_dcache_dirty(page, this_cpu);
355 } else {
356 /* We could delay the flush for the !page_mapping
357 * case too. But that case is for exec env/arg
358 * pages and those are %99 certainly going to get
359 * faulted into the tlb (and thus flushed) anyways.
360 */
361 flush_dcache_page_impl(page);
362 }
363
364out:
365 put_cpu();
366}
367
05e14cb3 368void __kprobes flush_icache_range(unsigned long start, unsigned long end)
1da177e4 369{
a43fe0e7 370 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
1da177e4
LT		 371 if (tlb_type == spitfire) {
372 unsigned long kaddr;
373
a94aa253
DM		 374 /* This code only runs on Spitfire cpus so this is
375 * why we can assume _PAGE_PADDR_4U.
376 */
377 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
378 unsigned long paddr, mask = _PAGE_PADDR_4U;
379
380 if (kaddr >= PAGE_OFFSET)
381 paddr = kaddr & mask;
382 else {
383 pgd_t *pgdp = pgd_offset_k(kaddr);
384 pud_t *pudp = pud_offset(pgdp, kaddr);
385 pmd_t *pmdp = pmd_offset(pudp, kaddr);
386 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
387
388 paddr = pte_val(*ptep) & mask;
389 }
390 __flush_icache_page(paddr);
391 }
1da177e4
LT		 392 }
393}
394
1da177e4
LT		 395void show_mem(void)
396{
5be4a963
DM		 397 unsigned long total = 0, reserved = 0;
398 unsigned long shared = 0, cached = 0;
399 pg_data_t *pgdat;
400
28256ca2 401 printk(KERN_INFO "Mem-info:\n");
1da177e4 402 show_free_areas();
28256ca2 403 printk(KERN_INFO "Free swap: %6ldkB\n",
1da177e4 404 nr_swap_pages << (PAGE_SHIFT-10));
5be4a963
DM		 405 for_each_online_pgdat(pgdat) {
406 unsigned long i, flags;
407
408 pgdat_resize_lock(pgdat, &flags);
409 for (i = 0; i < pgdat->node_spanned_pages; i++) {
410 struct page *page = pgdat_page_nr(pgdat, i);
411 total++;
412 if (PageReserved(page))
413 reserved++;
414 else if (PageSwapCache(page))
415 cached++;
416 else if (page_count(page))
417 shared += page_count(page) - 1;
418 }
419 pgdat_resize_unlock(pgdat, &flags);
420 }
421
422 printk(KERN_INFO "%lu pages of RAM\n", total);
423 printk(KERN_INFO "%lu reserved pages\n", reserved);
424 printk(KERN_INFO "%lu pages shared\n", shared);
425 printk(KERN_INFO "%lu pages swap cached\n", cached);
426
427 printk(KERN_INFO "%lu pages dirty\n",
428 global_page_state(NR_FILE_DIRTY));
429 printk(KERN_INFO "%lu pages writeback\n",
430 global_page_state(NR_WRITEBACK));
431 printk(KERN_INFO "%lu pages mapped\n",
432 global_page_state(NR_FILE_MAPPED));
433 printk(KERN_INFO "%lu pages slab\n",
434 global_page_state(NR_SLAB_RECLAIMABLE) +
435 global_page_state(NR_SLAB_UNRECLAIMABLE));
436 printk(KERN_INFO "%lu pages pagetables\n",
437 global_page_state(NR_PAGETABLE));
1da177e4
LT		 438}
439
440void mmu_info(struct seq_file *m)
441{
442 if (tlb_type == cheetah)
443 seq_printf(m, "MMU Type\t: Cheetah\n");
444 else if (tlb_type == cheetah_plus)
445 seq_printf(m, "MMU Type\t: Cheetah+\n");
446 else if (tlb_type == spitfire)
447 seq_printf(m, "MMU Type\t: Spitfire\n");
a43fe0e7
DM		 448 else if (tlb_type == hypervisor)
449 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
1da177e4
LT		 450 else
451 seq_printf(m, "MMU Type\t: ???\n");
452
453#ifdef CONFIG_DEBUG_DCFLUSH
454 seq_printf(m, "DCPageFlushes\t: %d\n",
455 atomic_read(&dcpage_flushes));
456#ifdef CONFIG_SMP
457 seq_printf(m, "DCPageFlushesXC\t: %d\n",
458 atomic_read(&dcpage_flushes_xcall));
459#endif /* CONFIG_SMP */
460#endif /* CONFIG_DEBUG_DCFLUSH */
461}
462
a94aa253
DM		 463struct linux_prom_translation {
464 unsigned long virt;
465 unsigned long size;
466 unsigned long data;
467};
468
469/* Exported for kernel TLB miss handling in ktlb.S */
470struct linux_prom_translation prom_trans[512] __read_mostly;
471unsigned int prom_trans_ents __read_mostly;
472
1da177e4
LT		 473/* Exported for SMP bootup purposes. */
474unsigned long kern_locked_tte_data;
475
c9c10830
DM		 476/* The obp translations are saved based on 8k pagesize, since obp can
477 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
74bf4312 478 * HI_OBP_ADDRESS range are handled in ktlb.S.
c9c10830 479 */
5085b4a5
DM		 480static inline int in_obp_range(unsigned long vaddr)
481{
482 return (vaddr >= LOW_OBP_ADDRESS &&
483 vaddr < HI_OBP_ADDRESS);
484}
485
c9c10830 486static int cmp_ptrans(const void *a, const void *b)
405599bd 487{
c9c10830 488 const struct linux_prom_translation *x = a, *y = b;
405599bd 489
c9c10830
DM		 490 if (x->virt > y->virt)
491 return 1;
492 if (x->virt < y->virt)
493 return -1;
494 return 0;
405599bd
DM		 495}
496
c9c10830 497/* Read OBP translations property into 'prom_trans[]'. */
9ad98c5b 498static void __init read_obp_translations(void)
405599bd 499{
c9c10830 500 int n, node, ents, first, last, i;
1da177e4
LT		 501
502 node = prom_finddevice("/virtual-memory");
503 n = prom_getproplen(node, "translations");
405599bd 504 if (unlikely(n == 0 || n == -1)) {
b206fc4c 505 prom_printf("prom_mappings: Couldn't get size.\n");
1da177e4
LT		 506 prom_halt();
507 }
405599bd
DM		 508 if (unlikely(n > sizeof(prom_trans))) {
509 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
1da177e4
LT		 510 prom_halt();
511 }
405599bd 512
b206fc4c 513 if ((n = prom_getproperty(node, "translations",
405599bd
DM		 514 (char *)&prom_trans[0],
515 sizeof(prom_trans))) == -1) {
b206fc4c 516 prom_printf("prom_mappings: Couldn't get property.\n");
1da177e4
LT		 517 prom_halt();
518 }
9ad98c5b 519
b206fc4c 520 n = n / sizeof(struct linux_prom_translation);
9ad98c5b 521
c9c10830
DM		 522 ents = n;
523
524 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
525 cmp_ptrans, NULL);
526
527 /* Now kick out all the non-OBP entries. */
528 for (i = 0; i < ents; i++) {
529 if (in_obp_range(prom_trans[i].virt))
530 break;
531 }
532 first = i;
533 for (; i < ents; i++) {
534 if (!in_obp_range(prom_trans[i].virt))
535 break;
536 }
537 last = i;
538
539 for (i = 0; i < (last - first); i++) {
540 struct linux_prom_translation *src = &prom_trans[i + first];
541 struct linux_prom_translation *dest = &prom_trans[i];
542
543 *dest = *src;
544 }
545 for (; i < ents; i++) {
546 struct linux_prom_translation *dest = &prom_trans[i];
547 dest->virt = dest->size = dest->data = 0x0UL;
548 }
549
550 prom_trans_ents = last - first;
551
552 if (tlb_type == spitfire) {
553 /* Clear diag TTE bits. */
554 for (i = 0; i < prom_trans_ents; i++)
555 prom_trans[i].data &= ~0x0003fe0000000000UL;
556 }
405599bd 557}
1da177e4 558
d82ace7d
DM		 559static void __init hypervisor_tlb_lock(unsigned long vaddr,
560 unsigned long pte,
561 unsigned long mmu)
562{
7db35f31
DM		 563 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
564
565 if (ret != 0) {
12e126ad 566 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
7db35f31 567 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
12e126ad
DM		 568 prom_halt();
569 }
d82ace7d
DM		 570}
571
c4bce90e
DM		 572static unsigned long kern_large_tte(unsigned long paddr);
573
898cf0ec 574static void __init remap_kernel(void)
405599bd
DM		 575{
576 unsigned long phys_page, tte_vaddr, tte_data;
64658743 577 int i, tlb_ent = sparc64_highest_locked_tlbent();
405599bd 578
1da177e4 579 tte_vaddr = (unsigned long) KERNBASE;
bff06d55 580 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
c4bce90e 581 tte_data = kern_large_tte(phys_page);
1da177e4
LT		 582
583 kern_locked_tte_data = tte_data;
584
d82ace7d
DM		 585 /* Now lock us into the TLBs via Hypervisor or OBP. */
586 if (tlb_type == hypervisor) {
64658743 587 for (i = 0; i < num_kernel_image_mappings; i++) {
d82ace7d
DM		 588 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
589 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
64658743
DM		 590 tte_vaddr += 0x400000;
591 tte_data += 0x400000;
d82ace7d
DM		 592 }
593 } else {
64658743
DM		 594 for (i = 0; i < num_kernel_image_mappings; i++) {
595 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
596 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
597 tte_vaddr += 0x400000;
598 tte_data += 0x400000;
d82ace7d 599 }
64658743 600 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
1da177e4 601 }
0835ae0f
DM		 602 if (tlb_type == cheetah_plus) {
603 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
604 CTX_CHEETAH_PLUS_NUC);
605 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
606 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
607 }
405599bd 608}
1da177e4 609
405599bd 610
c9c10830 611static void __init inherit_prom_mappings(void)
9ad98c5b
DM		 612{
613 read_obp_translations();
405599bd
DM		 614
615 /* Now fixup OBP's idea about where we really are mapped. */
3c62a2d3 616 printk("Remapping the kernel... ");
405599bd 617 remap_kernel();
3c62a2d3 618 printk("done.\n");
1da177e4
LT		 619}
620
1da177e4
LT		 621void prom_world(int enter)
622{
1da177e4
LT		 623 if (!enter)
624 set_fs((mm_segment_t) { get_thread_current_ds() });
625
3487d1d4 626 __asm__ __volatile__("flushw");
1da177e4
LT		 627}
628
1da177e4
LT		 629void __flush_dcache_range(unsigned long start, unsigned long end)
630{
631 unsigned long va;
632
633 if (tlb_type == spitfire) {
634 int n = 0;
635
636 for (va = start; va < end; va += 32) {
637 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
638 if (++n >= 512)
639 break;
640 }
a43fe0e7 641 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1da177e4
LT		 642 start = __pa(start);
643 end = __pa(end);
644 for (va = start; va < end; va += 32)
645 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
646 "membar #Sync"
647 : /* no outputs */
648 : "r" (va),
649 "i" (ASI_DCACHE_INVALIDATE));
650 }
651}
1da177e4 652
85f1e1f6
DM		 653/* get_new_mmu_context() uses "cache + 1". */
654DEFINE_SPINLOCK(ctx_alloc_lock);
655unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
656#define MAX_CTX_NR (1UL << CTX_NR_BITS)
657#define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
658DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
659
1da177e4
LT		 660/* Caller does TLB context flushing on local CPU if necessary.
661 * The caller also ensures that CTX_VALID(mm->context) is false.
662 *
663 * We must be careful about boundary cases so that we never
664 * let the user have CTX 0 (nucleus) or we ever use a CTX
665 * version of zero (and thus NO_CONTEXT would not be caught
666 * by version mis-match tests in mmu_context.h).
a0663a79
DM		 667 *
668 * Always invoked with interrupts disabled.
1da177e4
LT		 669 */
670void get_new_mmu_context(struct mm_struct *mm)
671{
672 unsigned long ctx, new_ctx;
673 unsigned long orig_pgsz_bits;
a77754b4 674 unsigned long flags;
a0663a79 675 int new_version;
1da177e4 676
a77754b4 677 spin_lock_irqsave(&ctx_alloc_lock, flags);
1da177e4
LT		 678 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
679 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
680 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
a0663a79 681 new_version = 0;
1da177e4
LT		 682 if (new_ctx >= (1 << CTX_NR_BITS)) {
683 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
684 if (new_ctx >= ctx) {
685 int i;
686 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
687 CTX_FIRST_VERSION;
688 if (new_ctx == 1)
689 new_ctx = CTX_FIRST_VERSION;
690
691 /* Don't call memset, for 16 entries that's just
692 * plain silly...
693 */
694 mmu_context_bmap[0] = 3;
695 mmu_context_bmap[1] = 0;
696 mmu_context_bmap[2] = 0;
697 mmu_context_bmap[3] = 0;
698 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
699 mmu_context_bmap[i + 0] = 0;
700 mmu_context_bmap[i + 1] = 0;
701 mmu_context_bmap[i + 2] = 0;
702 mmu_context_bmap[i + 3] = 0;
703 }
a0663a79 704 new_version = 1;
1da177e4
LT		 705 goto out;
706 }
707 }
708 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
709 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
710out:
711 tlb_context_cache = new_ctx;
712 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
a77754b4 713 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
a0663a79
DM		 714
715 if (unlikely(new_version))
716 smp_new_mmu_context_version();
1da177e4
LT		 717}
718
d1112018
DM		 719/* Find a free area for the bootmem map, avoiding the kernel image
720 * and the initial ramdisk.
721 */
722static unsigned long __init choose_bootmap_pfn(unsigned long start_pfn,
723 unsigned long end_pfn)
1da177e4 724{
9422273b 725 unsigned long bootmap_size;
d1112018 726
39964653
DM		 727 bootmap_size = bootmem_bootmap_pages(end_pfn - start_pfn);
728 bootmap_size <<= PAGE_SHIFT;
d1112018 729
9422273b 730 return lmb_alloc(bootmap_size, PAGE_SIZE) >> PAGE_SHIFT;
d1112018
DM		 731}
732
4e82c9a6
DM		 733static void __init find_ramdisk(unsigned long phys_base)
734{
735#ifdef CONFIG_BLK_DEV_INITRD
736 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
737 unsigned long ramdisk_image;
738
739 /* Older versions of the bootloader only supported a
740 * 32-bit physical address for the ramdisk image
741 * location, stored at sparc_ramdisk_image. Newer
742 * SILO versions set sparc_ramdisk_image to zero and
743 * provide a full 64-bit physical address at
744 * sparc_ramdisk_image64.
745 */
746 ramdisk_image = sparc_ramdisk_image;
747 if (!ramdisk_image)
748 ramdisk_image = sparc_ramdisk_image64;
749
750 /* Another bootloader quirk. The bootloader normalizes
751 * the physical address to KERNBASE, so we have to
752 * factor that back out and add in the lowest valid
753 * physical page address to get the true physical address.
754 */
755 ramdisk_image -= KERNBASE;
756 ramdisk_image += phys_base;
757
758 initrd_start = ramdisk_image;
759 initrd_end = ramdisk_image + sparc_ramdisk_size;
3b2a7e23
DM		 760
761 lmb_reserve(initrd_start, initrd_end);
4e82c9a6
DM		 762 }
763#endif
764}
765
f1cfdb55
DM		 766/* About pages_avail, this is the value we will use to calculate
767 * the zholes_size[] argument given to free_area_init_node(). The
768 * page allocator uses this to calculate nr_kernel_pages,
769 * nr_all_pages and zone->present_pages. On NUMA it is used
770 * to calculate zone->min_unmapped_pages and zone->min_slab_pages.
771 *
772 * So this number should really be set to what the page allocator
773 * actually ends up with. This means:
774 * 1) It should include bootmem map pages, we'll release those.
775 * 2) It should not include the kernel image, except for the
776 * __init sections which we will also release.
777 * 3) It should include the initrd image, since we'll release
778 * that too.
779 */
d1112018
DM		 780static unsigned long __init bootmem_init(unsigned long *pages_avail,
781 unsigned long phys_base)
782{
9422273b 783 unsigned long end_pfn;
1da177e4
LT		 784 int i;
785
25b0c659
DM		 786 *pages_avail = lmb_phys_mem_size() >> PAGE_SHIFT;
787 end_pfn = lmb_end_of_DRAM() >> PAGE_SHIFT;
6fc5bae7 788
1da177e4
LT		 789 /* Initialize the boot-time allocator. */
790 max_pfn = max_low_pfn = end_pfn;
d1112018
DM		 791 min_low_pfn = (phys_base >> PAGE_SHIFT);
792
9422273b
DM		 793 init_bootmem_node(NODE_DATA(0),
794 choose_bootmap_pfn(min_low_pfn, end_pfn),
795 min_low_pfn, end_pfn);
1da177e4 796
1da177e4
LT		 797 /* Now register the available physical memory with the
798 * allocator.
799 */
9422273b
DM		 800 for (i = 0; i < lmb.memory.cnt; i++)
801 free_bootmem(lmb.memory.region[i].base,
802 lmb_size_bytes(&lmb.memory, i));
1da177e4 803
9422273b
DM		 804 for (i = 0; i < lmb.reserved.cnt; i++)
805 reserve_bootmem(lmb.reserved.region[i].base,
806 lmb_size_bytes(&lmb.reserved, i),
807 BOOTMEM_DEFAULT);
1da177e4 808
1da177e4
LT		 809 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
810
9422273b
DM		 811 for (i = 0; i < lmb.memory.cnt; ++i) {
812 unsigned long start_pfn, end_pfn, pages;
1da177e4 813
9422273b
DM		 814 pages = lmb_size_pages(&lmb.memory, i);
815 start_pfn = lmb.memory.region[i].base >> PAGE_SHIFT;
816 end_pfn = start_pfn + pages;
d1112018 817
d1112018
DM		 818 memory_present(0, start_pfn, end_pfn);
819 }
820
821 sparse_init();
822
1da177e4
LT		 823 return end_pfn;
824}
825
9cc3a1ac
DM		 826static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
827static int pall_ents __initdata;
828
56425306 829#ifdef CONFIG_DEBUG_PAGEALLOC
896aef43
SR		 830static unsigned long __ref kernel_map_range(unsigned long pstart,
831 unsigned long pend, pgprot_t prot)
56425306
DM		 832{
833 unsigned long vstart = PAGE_OFFSET + pstart;
834 unsigned long vend = PAGE_OFFSET + pend;
835 unsigned long alloc_bytes = 0UL;
836
837 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
13edad7a 838 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
56425306
DM		 839 vstart, vend);
840 prom_halt();
841 }
842
843 while (vstart < vend) {
844 unsigned long this_end, paddr = __pa(vstart);
845 pgd_t *pgd = pgd_offset_k(vstart);
846 pud_t *pud;
847 pmd_t *pmd;
848 pte_t *pte;
849
850 pud = pud_offset(pgd, vstart);
851 if (pud_none(*pud)) {
852 pmd_t *new;
853
854 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
855 alloc_bytes += PAGE_SIZE;
856 pud_populate(&init_mm, pud, new);
857 }
858
859 pmd = pmd_offset(pud, vstart);
860 if (!pmd_present(*pmd)) {
861 pte_t *new;
862
863 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
864 alloc_bytes += PAGE_SIZE;
865 pmd_populate_kernel(&init_mm, pmd, new);
866 }
867
868 pte = pte_offset_kernel(pmd, vstart);
869 this_end = (vstart + PMD_SIZE) & PMD_MASK;
870 if (this_end > vend)
871 this_end = vend;
872
873 while (vstart < this_end) {
874 pte_val(*pte) = (paddr | pgprot_val(prot));
875
876 vstart += PAGE_SIZE;
877 paddr += PAGE_SIZE;
878 pte++;
879 }
880 }
881
882 return alloc_bytes;
883}
884
56425306 885extern unsigned int kvmap_linear_patch[1];
9cc3a1ac
DM		 886#endif /* CONFIG_DEBUG_PAGEALLOC */
887
888static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
889{
890 const unsigned long shift_256MB = 28;
891 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
892 const unsigned long size_256MB = (1UL << shift_256MB);
893
894 while (start < end) {
895 long remains;
896
f7c00338
DM		 897 remains = end - start;
898 if (remains < size_256MB)
899 break;
900
9cc3a1ac
DM		 901 if (start & mask_256MB) {
902 start = (start + size_256MB) & ~mask_256MB;
903 continue;
904 }
905
9cc3a1ac
DM		 906 while (remains >= size_256MB) {
907 unsigned long index = start >> shift_256MB;
908
909 __set_bit(index, kpte_linear_bitmap);
910
911 start += size_256MB;
912 remains -= size_256MB;
913 }
914 }
915}
56425306 916
8f361453 917static void __init init_kpte_bitmap(void)
56425306 918{
9cc3a1ac 919 unsigned long i;
13edad7a
DM		 920
921 for (i = 0; i < pall_ents; i++) {
56425306
DM		 922 unsigned long phys_start, phys_end;
923
13edad7a
DM		 924 phys_start = pall[i].phys_addr;
925 phys_end = phys_start + pall[i].reg_size;
9cc3a1ac
DM		 926
927 mark_kpte_bitmap(phys_start, phys_end);
8f361453
DM		 928 }
929}
9cc3a1ac 930
8f361453
DM		 931static void __init kernel_physical_mapping_init(void)
932{
9cc3a1ac 933#ifdef CONFIG_DEBUG_PAGEALLOC
8f361453
DM		 934 unsigned long i, mem_alloced = 0UL;
935
936 for (i = 0; i < pall_ents; i++) {
937 unsigned long phys_start, phys_end;
938
939 phys_start = pall[i].phys_addr;
940 phys_end = phys_start + pall[i].reg_size;
941
56425306
DM		 942 mem_alloced += kernel_map_range(phys_start, phys_end,
943 PAGE_KERNEL);
56425306
DM		 944 }
945
946 printk("Allocated %ld bytes for kernel page tables.\n",
947 mem_alloced);
948
949 kvmap_linear_patch[0] = 0x01000000; /* nop */
950 flushi(&kvmap_linear_patch[0]);
951
952 __flush_tlb_all();
9cc3a1ac 953#endif
56425306
DM		 954}
955
9cc3a1ac 956#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 957void kernel_map_pages(struct page *page, int numpages, int enable)
958{
959 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
960 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
961
962 kernel_map_range(phys_start, phys_end,
963 (enable ? PAGE_KERNEL : __pgprot(0)));
964
74bf4312
DM		 965 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
966 PAGE_OFFSET + phys_end);
967
56425306
DM		 968 /* we should perform an IPI and flush all tlbs,
969 * but that can deadlock->flush only current cpu.
970 */
971 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
972 PAGE_OFFSET + phys_end);
973}
974#endif
975
10147570
DM		 976unsigned long __init find_ecache_flush_span(unsigned long size)
977{
0836a0eb
DM		 978 int i;
979
13edad7a
DM		 980 for (i = 0; i < pavail_ents; i++) {
981 if (pavail[i].reg_size >= size)
982 return pavail[i].phys_addr;
0836a0eb
DM		 983 }
984
13edad7a 985 return ~0UL;
0836a0eb
DM		 986}
987
517af332
DM		 988static void __init tsb_phys_patch(void)
989{
d257d5da 990 struct tsb_ldquad_phys_patch_entry *pquad;
517af332
DM		 991 struct tsb_phys_patch_entry *p;
992
d257d5da
DM		 993 pquad = &__tsb_ldquad_phys_patch;
994 while (pquad < &__tsb_ldquad_phys_patch_end) {
995 unsigned long addr = pquad->addr;
996
997 if (tlb_type == hypervisor)
998 *(unsigned int *) addr = pquad->sun4v_insn;
999 else
1000 *(unsigned int *) addr = pquad->sun4u_insn;
1001 wmb();
1002 __asm__ __volatile__("flush %0"
1003 : /* no outputs */
1004 : "r" (addr));
1005
1006 pquad++;
1007 }
1008
517af332
DM		 1009 p = &__tsb_phys_patch;
1010 while (p < &__tsb_phys_patch_end) {
1011 unsigned long addr = p->addr;
1012
1013 *(unsigned int *) addr = p->insn;
1014 wmb();
1015 __asm__ __volatile__("flush %0"
1016 : /* no outputs */
1017 : "r" (addr));
1018
1019 p++;
1020 }
1021}
1022
490384e7 1023/* Don't mark as init, we give this to the Hypervisor. */
d1acb421
DM		 1024#ifndef CONFIG_DEBUG_PAGEALLOC
1025#define NUM_KTSB_DESCR 2
1026#else
1027#define NUM_KTSB_DESCR 1
1028#endif
1029static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
490384e7
DM		 1030extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1031
1032static void __init sun4v_ktsb_init(void)
1033{
1034 unsigned long ktsb_pa;
1035
d7744a09 1036 /* First KTSB for PAGE_SIZE mappings. */
490384e7
DM		 1037 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1038
1039 switch (PAGE_SIZE) {
1040 case 8 * 1024:
1041 default:
1042 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1043 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1044 break;
1045
1046 case 64 * 1024:
1047 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1048 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1049 break;
1050
1051 case 512 * 1024:
1052 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1053 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1054 break;
1055
1056 case 4 * 1024 * 1024:
1057 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1058 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1059 break;
1060 };
1061
3f19a84e 1062 ktsb_descr[0].assoc = 1;
490384e7
DM		 1063 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1064 ktsb_descr[0].ctx_idx = 0;
1065 ktsb_descr[0].tsb_base = ktsb_pa;
1066 ktsb_descr[0].resv = 0;
1067
d1acb421 1068#ifndef CONFIG_DEBUG_PAGEALLOC
d7744a09
DM		 1069 /* Second KTSB for 4MB/256MB mappings. */
1070 ktsb_pa = (kern_base +
1071 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1072
1073 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1074 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1075 HV_PGSZ_MASK_256MB);
1076 ktsb_descr[1].assoc = 1;
1077 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1078 ktsb_descr[1].ctx_idx = 0;
1079 ktsb_descr[1].tsb_base = ktsb_pa;
1080 ktsb_descr[1].resv = 0;
d1acb421 1081#endif
490384e7
DM		 1082}
1083
1084void __cpuinit sun4v_ktsb_register(void)
1085{
7db35f31 1086 unsigned long pa, ret;
490384e7
DM		 1087
1088 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1089
7db35f31
DM		 1090 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1091 if (ret != 0) {
1092 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1093 "errors with %lx\n", pa, ret);
1094 prom_halt();
1095 }
490384e7
DM		 1096}
1097
1da177e4
LT		 1098/* paging_init() sets up the page tables */
1099
5cbc3073
DM		 1100extern void central_probe(void);
1101
1da177e4 1102static unsigned long last_valid_pfn;
56425306 1103pgd_t swapper_pg_dir[2048];
1da177e4 1104
c4bce90e
DM		 1105static void sun4u_pgprot_init(void);
1106static void sun4v_pgprot_init(void);
1107
3afc6202 1108/* Dummy function */
1109void __init setup_per_cpu_areas(void)
1110{
1111}
1112
1da177e4
LT		 1113void __init paging_init(void)
1114{
d1112018 1115 unsigned long end_pfn, pages_avail, shift, phys_base;
0836a0eb
DM		 1116 unsigned long real_end, i;
1117
22adb358
DM		 1118 /* These build time checkes make sure that the dcache_dirty_cpu()
1119 * page->flags usage will work.
1120 *
1121 * When a page gets marked as dcache-dirty, we store the
1122 * cpu number starting at bit 32 in the page->flags. Also,
1123 * functions like clear_dcache_dirty_cpu use the cpu mask
1124 * in 13-bit signed-immediate instruction fields.
1125 */
1126 BUILD_BUG_ON(FLAGS_RESERVED != 32);
1127 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1128 ilog2(roundup_pow_of_two(NR_CPUS)) > FLAGS_RESERVED);
1129 BUILD_BUG_ON(NR_CPUS > 4096);
1130
481295f9
DM		 1131 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1132 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1133
22d6a1cb
DM		 1134 sstate_booting();
1135
d7744a09 1136 /* Invalidate both kernel TSBs. */
8b234274 1137 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
d1acb421 1138#ifndef CONFIG_DEBUG_PAGEALLOC
d7744a09 1139 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
d1acb421 1140#endif
8b234274 1141
c4bce90e
DM		 1142 if (tlb_type == hypervisor)
1143 sun4v_pgprot_init();
1144 else
1145 sun4u_pgprot_init();
1146
d257d5da
DM		 1147 if (tlb_type == cheetah_plus ||
1148 tlb_type == hypervisor)
517af332
DM		 1149 tsb_phys_patch();
1150
490384e7 1151 if (tlb_type == hypervisor) {
d257d5da 1152 sun4v_patch_tlb_handlers();
490384e7
DM		 1153 sun4v_ktsb_init();
1154 }
d257d5da 1155
3b2a7e23
DM		 1156 lmb_init();
1157
13edad7a
DM		 1158 /* Find available physical memory... */
1159 read_obp_memory("available", &pavail[0], &pavail_ents);
0836a0eb
DM		 1160
1161 phys_base = 0xffffffffffffffffUL;
3b2a7e23 1162 for (i = 0; i < pavail_ents; i++) {
13edad7a 1163 phys_base = min(phys_base, pavail[i].phys_addr);
3b2a7e23
DM		 1164 lmb_add(pavail[i].phys_addr, pavail[i].reg_size);
1165 }
1166
1167 lmb_reserve(kern_base, kern_size);
0836a0eb 1168
4e82c9a6
DM		 1169 find_ramdisk(phys_base);
1170
25b0c659
DM		 1171 if (cmdline_memory_size)
1172 lmb_enforce_memory_limit(phys_base + cmdline_memory_size);
1173
3b2a7e23
DM		 1174 lmb_analyze();
1175 lmb_dump_all();
1176
1da177e4
LT		 1177 set_bit(0, mmu_context_bmap);
1178
2bdb3cb2
DM		 1179 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1180
1da177e4 1181 real_end = (unsigned long)_end;
64658743
DM		 1182 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1183 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1184 num_kernel_image_mappings);
2bdb3cb2
DM		 1185
1186 /* Set kernel pgd to upper alias so physical page computations
1da177e4
LT		 1187 * work.
1188 */
1189 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1190
56425306 1191 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1da177e4
LT		 1192
1193 /* Now can init the kernel/bad page tables. */
1194 pud_set(pud_offset(&swapper_pg_dir[0], 0),
56425306 1195 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1da177e4 1196
c9c10830 1197 inherit_prom_mappings();
5085b4a5 1198
8f361453
DM		 1199 read_obp_memory("reg", &pall[0], &pall_ents);
1200
1201 init_kpte_bitmap();
1202
a8b900d8
DM		 1203 /* Ok, we can use our TLB miss and window trap handlers safely. */
1204 setup_tba();
1da177e4 1205
c9c10830 1206 __flush_tlb_all();
9ad98c5b 1207
490384e7
DM		 1208 if (tlb_type == hypervisor)
1209 sun4v_ktsb_register();
1210
b9709456
DM		 1211 /* We must setup the per-cpu areas before we pull in the
1212 * PROM and the MDESC. The code there fills in cpu and
1213 * other information into per-cpu data structures.
1214 */
1215 real_setup_per_cpu_areas();
1216
ad072004
DM		 1217 prom_build_devicetree();
1218
2bdb3cb2
DM		 1219 /* Setup bootmem... */
1220 pages_avail = 0;
d1112018
DM		 1221 last_valid_pfn = end_pfn = bootmem_init(&pages_avail, phys_base);
1222
17b0e199 1223 max_mapnr = last_valid_pfn;
2bdb3cb2 1224
56425306 1225 kernel_physical_mapping_init();
56425306 1226
5cbc3073
DM		 1227 if (tlb_type == hypervisor)
1228 sun4v_mdesc_init();
1229
1da177e4
LT		 1230 {
1231 unsigned long zones_size[MAX_NR_ZONES];
1232 unsigned long zholes_size[MAX_NR_ZONES];
1da177e4
LT		 1233 int znum;
1234
1235 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1236 zones_size[znum] = zholes_size[znum] = 0;
1237
1b51d3a0
DM		 1238 zones_size[ZONE_NORMAL] = end_pfn;
1239 zholes_size[ZONE_NORMAL] = end_pfn - pages_avail;
1da177e4
LT		 1240
1241 free_area_init_node(0, &contig_page_data, zones_size,
17b0e199
DM		 1242 __pa(PAGE_OFFSET) >> PAGE_SHIFT,
1243 zholes_size);
1da177e4
LT		 1244 }
1245
3c62a2d3 1246 printk("Booting Linux...\n");
5cbc3073
DM		 1247
1248 central_probe();
1249 cpu_probe();
1da177e4
LT		 1250}
1251
1da177e4
LT		 1252static void __init taint_real_pages(void)
1253{
1da177e4
LT		 1254 int i;
1255
13edad7a 1256 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1da177e4 1257
13edad7a 1258 /* Find changes discovered in the physmem available rescan and
1da177e4
LT		 1259 * reserve the lost portions in the bootmem maps.
1260 */
13edad7a 1261 for (i = 0; i < pavail_ents; i++) {
1da177e4
LT		 1262 unsigned long old_start, old_end;
1263
13edad7a 1264 old_start = pavail[i].phys_addr;
1da177e4 1265 old_end = old_start +
13edad7a 1266 pavail[i].reg_size;
1da177e4
LT		 1267 while (old_start < old_end) {
1268 int n;
1269
c2a5a46b 1270 for (n = 0; n < pavail_rescan_ents; n++) {
1da177e4
LT		 1271 unsigned long new_start, new_end;
1272
13edad7a
DM		 1273 new_start = pavail_rescan[n].phys_addr;
1274 new_end = new_start +
1275 pavail_rescan[n].reg_size;
1da177e4
LT		 1276
1277 if (new_start <= old_start &&
1278 new_end >= (old_start + PAGE_SIZE)) {
13edad7a
DM		 1279 set_bit(old_start >> 22,
1280 sparc64_valid_addr_bitmap);
1da177e4
LT		 1281 goto do_next_page;
1282 }
1283 }
72a7fe39 1284 reserve_bootmem(old_start, PAGE_SIZE, BOOTMEM_DEFAULT);
1da177e4
LT		 1285
1286 do_next_page:
1287 old_start += PAGE_SIZE;
1288 }
1289 }
1290}
1291
c2a5a46b
DM		 1292int __init page_in_phys_avail(unsigned long paddr)
1293{
1294 int i;
1295
1296 paddr &= PAGE_MASK;
1297
1298 for (i = 0; i < pavail_rescan_ents; i++) {
1299 unsigned long start, end;
1300
1301 start = pavail_rescan[i].phys_addr;
1302 end = start + pavail_rescan[i].reg_size;
1303
1304 if (paddr >= start && paddr < end)
1305 return 1;
1306 }
1307 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1308 return 1;
1309#ifdef CONFIG_BLK_DEV_INITRD
1310 if (paddr >= __pa(initrd_start) &&
1311 paddr < __pa(PAGE_ALIGN(initrd_end)))
1312 return 1;
1313#endif
1314
1315 return 0;
1316}
1317
1da177e4
LT		 1318void __init mem_init(void)
1319{
1320 unsigned long codepages, datapages, initpages;
1321 unsigned long addr, last;
1322 int i;
1323
1324 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1325 i += 1;
2bdb3cb2 1326 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1da177e4
LT		 1327 if (sparc64_valid_addr_bitmap == NULL) {
1328 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1329 prom_halt();
1330 }
1331 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1332
1333 addr = PAGE_OFFSET + kern_base;
1334 last = PAGE_ALIGN(kern_size) + addr;
1335 while (addr < last) {
1336 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1337 addr += PAGE_SIZE;
1338 }
1339
1340 taint_real_pages();
1341
1da177e4
LT		 1342 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1343
f1cfdb55
DM		 1344 /* We subtract one to account for the mem_map_zero page
1345 * allocated below.
1346 */
1da177e4
LT		 1347 totalram_pages = num_physpages = free_all_bootmem() - 1;
1348
1349 /*
1350 * Set up the zero page, mark it reserved, so that page count
1351 * is not manipulated when freeing the page from user ptes.
1352 */
1353 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1354 if (mem_map_zero == NULL) {
1355 prom_printf("paging_init: Cannot alloc zero page.\n");
1356 prom_halt();
1357 }
1358 SetPageReserved(mem_map_zero);
1359
1360 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1361 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1362 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1363 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1364 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1365 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1366
96177299 1367 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1da177e4
LT		 1368 nr_free_pages() << (PAGE_SHIFT-10),
1369 codepages << (PAGE_SHIFT-10),
1370 datapages << (PAGE_SHIFT-10),
1371 initpages << (PAGE_SHIFT-10),
1372 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1373
1374 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1375 cheetah_ecache_flush_init();
1376}
1377
898cf0ec 1378void free_initmem(void)
1da177e4
LT		 1379{
1380 unsigned long addr, initend;
1381
1382 /*
1383 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1384 */
1385 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1386 initend = (unsigned long)(__init_end) & PAGE_MASK;
1387 for (; addr < initend; addr += PAGE_SIZE) {
1388 unsigned long page;
1389 struct page *p;
1390
1391 page = (addr +
1392 ((unsigned long) __va(kern_base)) -
1393 ((unsigned long) KERNBASE));
c9cf5528 1394 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1da177e4
LT		 1395 p = virt_to_page(page);
1396
1397 ClearPageReserved(p);
7835e98b 1398 init_page_count(p);
1da177e4
LT		 1399 __free_page(p);
1400 num_physpages++;
1401 totalram_pages++;
1402 }
1403}
1404
1405#ifdef CONFIG_BLK_DEV_INITRD
1406void free_initrd_mem(unsigned long start, unsigned long end)
1407{
1408 if (start < end)
1409 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1410 for (; start < end; start += PAGE_SIZE) {
1411 struct page *p = virt_to_page(start);
1412
1413 ClearPageReserved(p);
7835e98b 1414 init_page_count(p);
1da177e4
LT		 1415 __free_page(p);
1416 num_physpages++;
1417 totalram_pages++;
1418 }
1419}
1420#endif
c4bce90e 1421
c4bce90e
DM		 1422#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1423#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1424#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1425#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1426#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1427#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1428
1429pgprot_t PAGE_KERNEL __read_mostly;
1430EXPORT_SYMBOL(PAGE_KERNEL);
1431
1432pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1433pgprot_t PAGE_COPY __read_mostly;
0f15952a
DM		 1434
1435pgprot_t PAGE_SHARED __read_mostly;
1436EXPORT_SYMBOL(PAGE_SHARED);
1437
c4bce90e
DM		 1438pgprot_t PAGE_EXEC __read_mostly;
1439unsigned long pg_iobits __read_mostly;
1440
1441unsigned long _PAGE_IE __read_mostly;
987c74fc 1442EXPORT_SYMBOL(_PAGE_IE);
b2bef442 1443
c4bce90e 1444unsigned long _PAGE_E __read_mostly;
b2bef442
DM		 1445EXPORT_SYMBOL(_PAGE_E);
1446
c4bce90e 1447unsigned long _PAGE_CACHE __read_mostly;
b2bef442 1448EXPORT_SYMBOL(_PAGE_CACHE);
c4bce90e 1449
46644c24
DM		 1450#ifdef CONFIG_SPARSEMEM_VMEMMAP
1451
1452#define VMEMMAP_CHUNK_SHIFT 22
1453#define VMEMMAP_CHUNK (1UL << VMEMMAP_CHUNK_SHIFT)
1454#define VMEMMAP_CHUNK_MASK ~(VMEMMAP_CHUNK - 1UL)
1455#define VMEMMAP_ALIGN(x) (((x)+VMEMMAP_CHUNK-1UL)&VMEMMAP_CHUNK_MASK)
1456
1457#define VMEMMAP_SIZE ((((1UL << MAX_PHYSADDR_BITS) >> PAGE_SHIFT) * \
1458 sizeof(struct page *)) >> VMEMMAP_CHUNK_SHIFT)
1459unsigned long vmemmap_table[VMEMMAP_SIZE];
1460
1461int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
1462{
1463 unsigned long vstart = (unsigned long) start;
1464 unsigned long vend = (unsigned long) (start + nr);
1465 unsigned long phys_start = (vstart - VMEMMAP_BASE);
1466 unsigned long phys_end = (vend - VMEMMAP_BASE);
1467 unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
1468 unsigned long end = VMEMMAP_ALIGN(phys_end);
1469 unsigned long pte_base;
1470
1471 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1472 _PAGE_CP_4U | _PAGE_CV_4U |
1473 _PAGE_P_4U | _PAGE_W_4U);
1474 if (tlb_type == hypervisor)
1475 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1476 _PAGE_CP_4V | _PAGE_CV_4V |
1477 _PAGE_P_4V | _PAGE_W_4V);
1478
1479 for (; addr < end; addr += VMEMMAP_CHUNK) {
1480 unsigned long *vmem_pp =
1481 vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
1482 void *block;
1483
1484 if (!(*vmem_pp & _PAGE_VALID)) {
1485 block = vmemmap_alloc_block(1UL << 22, node);
1486 if (!block)
1487 return -ENOMEM;
1488
1489 *vmem_pp = pte_base | __pa(block);
1490
1491 printk(KERN_INFO "[%p-%p] page_structs=%lu "
1492 "node=%d entry=%lu/%lu\n", start, block, nr,
1493 node,
1494 addr >> VMEMMAP_CHUNK_SHIFT,
1495 VMEMMAP_SIZE >> VMEMMAP_CHUNK_SHIFT);
1496 }
1497 }
1498 return 0;
1499}
1500#endif /* CONFIG_SPARSEMEM_VMEMMAP */
1501
c4bce90e
DM		 1502static void prot_init_common(unsigned long page_none,
1503 unsigned long page_shared,
1504 unsigned long page_copy,
1505 unsigned long page_readonly,
1506 unsigned long page_exec_bit)
1507{
1508 PAGE_COPY = __pgprot(page_copy);
0f15952a 1509 PAGE_SHARED = __pgprot(page_shared);
c4bce90e
DM		 1510
1511 protection_map[0x0] = __pgprot(page_none);
1512 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1513 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1514 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1515 protection_map[0x4] = __pgprot(page_readonly);
1516 protection_map[0x5] = __pgprot(page_readonly);
1517 protection_map[0x6] = __pgprot(page_copy);
1518 protection_map[0x7] = __pgprot(page_copy);
1519 protection_map[0x8] = __pgprot(page_none);
1520 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1521 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1522 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1523 protection_map[0xc] = __pgprot(page_readonly);
1524 protection_map[0xd] = __pgprot(page_readonly);
1525 protection_map[0xe] = __pgprot(page_shared);
1526 protection_map[0xf] = __pgprot(page_shared);
1527}
1528
1529static void __init sun4u_pgprot_init(void)
1530{
1531 unsigned long page_none, page_shared, page_copy, page_readonly;
1532 unsigned long page_exec_bit;
1533
1534 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1535 _PAGE_CACHE_4U | _PAGE_P_4U |
1536 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1537 _PAGE_EXEC_4U);
1538 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1539 _PAGE_CACHE_4U | _PAGE_P_4U |
1540 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1541 _PAGE_EXEC_4U | _PAGE_L_4U);
1542 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1543
1544 _PAGE_IE = _PAGE_IE_4U;
1545 _PAGE_E = _PAGE_E_4U;
1546 _PAGE_CACHE = _PAGE_CACHE_4U;
1547
1548 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1549 __ACCESS_BITS_4U | _PAGE_E_4U);
1550
d1acb421
DM		 1551#ifdef CONFIG_DEBUG_PAGEALLOC
1552 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
1553 0xfffff80000000000;
1554#else
9cc3a1ac 1555 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
c4bce90e 1556 0xfffff80000000000;
d1acb421 1557#endif
9cc3a1ac
DM		 1558 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1559 _PAGE_P_4U | _PAGE_W_4U);
1560
1561 /* XXX Should use 256MB on Panther. XXX */
1562 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
c4bce90e
DM		 1563
1564 _PAGE_SZBITS = _PAGE_SZBITS_4U;
1565 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1566 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1567 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1568
1569
1570 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1571 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1572 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1573 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1574 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1575 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1576 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1577
1578 page_exec_bit = _PAGE_EXEC_4U;
1579
1580 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1581 page_exec_bit);
1582}
1583
1584static void __init sun4v_pgprot_init(void)
1585{
1586 unsigned long page_none, page_shared, page_copy, page_readonly;
1587 unsigned long page_exec_bit;
1588
1589 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1590 _PAGE_CACHE_4V | _PAGE_P_4V |
1591 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1592 _PAGE_EXEC_4V);
1593 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1594 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1595
1596 _PAGE_IE = _PAGE_IE_4V;
1597 _PAGE_E = _PAGE_E_4V;
1598 _PAGE_CACHE = _PAGE_CACHE_4V;
1599
d1acb421
DM		 1600#ifdef CONFIG_DEBUG_PAGEALLOC
1601 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1602 0xfffff80000000000;
1603#else
9cc3a1ac
DM		 1604 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1605 0xfffff80000000000;
d1acb421 1606#endif
9cc3a1ac
DM		 1607 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1608 _PAGE_P_4V | _PAGE_W_4V);
1609
d1acb421
DM		 1610#ifdef CONFIG_DEBUG_PAGEALLOC
1611 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1612 0xfffff80000000000;
1613#else
9cc3a1ac 1614 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
c4bce90e 1615 0xfffff80000000000;
d1acb421 1616#endif
9cc3a1ac
DM		 1617 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1618 _PAGE_P_4V | _PAGE_W_4V);
c4bce90e
DM		 1619
1620 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1621 __ACCESS_BITS_4V | _PAGE_E_4V);
1622
1623 _PAGE_SZBITS = _PAGE_SZBITS_4V;
1624 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1625 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1626 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1627 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1628
1629 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1630 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1631 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1632 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1633 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1634 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1635 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1636
1637 page_exec_bit = _PAGE_EXEC_4V;
1638
1639 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1640 page_exec_bit);
1641}
1642
1643unsigned long pte_sz_bits(unsigned long sz)
1644{
1645 if (tlb_type == hypervisor) {
1646 switch (sz) {
1647 case 8 * 1024:
1648 default:
1649 return _PAGE_SZ8K_4V;
1650 case 64 * 1024:
1651 return _PAGE_SZ64K_4V;
1652 case 512 * 1024:
1653 return _PAGE_SZ512K_4V;
1654 case 4 * 1024 * 1024:
1655 return _PAGE_SZ4MB_4V;
1656 };
1657 } else {
1658 switch (sz) {
1659 case 8 * 1024:
1660 default:
1661 return _PAGE_SZ8K_4U;
1662 case 64 * 1024:
1663 return _PAGE_SZ64K_4U;
1664 case 512 * 1024:
1665 return _PAGE_SZ512K_4U;
1666 case 4 * 1024 * 1024:
1667 return _PAGE_SZ4MB_4U;
1668 };
1669 }
1670}
1671
1672pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1673{
1674 pte_t pte;
cf627156
DM		 1675
1676 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
c4bce90e
DM		 1677 pte_val(pte) |= (((unsigned long)space) << 32);
1678 pte_val(pte) |= pte_sz_bits(page_size);
c4bce90e 1679
cf627156 1680 return pte;
c4bce90e
DM		 1681}
1682
1683static unsigned long kern_large_tte(unsigned long paddr)
1684{
1685 unsigned long val;
1686
1687 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1688 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1689 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1690 if (tlb_type == hypervisor)
1691 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1692 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1693 _PAGE_EXEC_4V | _PAGE_W_4V);
1694
1695 return val | paddr;
1696}
1697
c4bce90e
DM		 1698/* If not locked, zap it. */
1699void __flush_tlb_all(void)
1700{
1701 unsigned long pstate;
1702 int i;
1703
1704 __asm__ __volatile__("flushw\n\t"
1705 "rdpr %%pstate, %0\n\t"
1706 "wrpr %0, %1, %%pstate"
1707 : "=r" (pstate)
1708 : "i" (PSTATE_IE));
8f361453
DM		 1709 if (tlb_type == hypervisor) {
1710 sun4v_mmu_demap_all();
1711 } else if (tlb_type == spitfire) {
c4bce90e
DM		 1712 for (i = 0; i < 64; i++) {
1713 /* Spitfire Errata #32 workaround */
1714 /* NOTE: Always runs on spitfire, so no
1715 * cheetah+ page size encodings.
1716 */
1717 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1718 "flush %%g6"
1719 : /* No outputs */
1720 : "r" (0),
1721 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1722
1723 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1724 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1725 "membar #Sync"
1726 : /* no outputs */
1727 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1728 spitfire_put_dtlb_data(i, 0x0UL);
1729 }
1730
1731 /* Spitfire Errata #32 workaround */
1732 /* NOTE: Always runs on spitfire, so no
1733 * cheetah+ page size encodings.
1734 */
1735 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1736 "flush %%g6"
1737 : /* No outputs */
1738 : "r" (0),
1739 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1740
1741 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1742 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1743 "membar #Sync"
1744 : /* no outputs */
1745 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1746 spitfire_put_itlb_data(i, 0x0UL);
1747 }
1748 }
1749 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1750 cheetah_flush_dtlb_all();
1751 cheetah_flush_itlb_all();
1752 }
1753 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1754 : : "r" (pstate));
1755}
88d70794
DM		 1756
1757#ifdef CONFIG_MEMORY_HOTPLUG
1758
1759void online_page(struct page *page)
1760{
1761 ClearPageReserved(page);
fcab1e51
NP		 1762 init_page_count(page);
1763 __free_page(page);
88d70794
DM		 1764 totalram_pages++;
1765 num_physpages++;
1766}
1767
88d70794 1768#endif /* CONFIG_MEMORY_HOTPLUG */
kernel source for telekom puls (alcatel/mediatek)