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[SPARC64]: asm/cpudata.h needs asm/asi.h
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / sparc64 / mm / init.c
CommitLineData
1da177e4
LT		 1/* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#include <linux/config.h>
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/string.h>
12#include <linux/init.h>
13#include <linux/bootmem.h>
14#include <linux/mm.h>
15#include <linux/hugetlb.h>
16#include <linux/slab.h>
17#include <linux/initrd.h>
18#include <linux/swap.h>
19#include <linux/pagemap.h>
20#include <linux/fs.h>
21#include <linux/seq_file.h>
05e14cb3 22#include <linux/kprobes.h>
1ac4f5eb 23#include <linux/cache.h>
13edad7a 24#include <linux/sort.h>
1da177e4
LT		 25
26#include <asm/head.h>
27#include <asm/system.h>
28#include <asm/page.h>
29#include <asm/pgalloc.h>
30#include <asm/pgtable.h>
31#include <asm/oplib.h>
32#include <asm/iommu.h>
33#include <asm/io.h>
34#include <asm/uaccess.h>
35#include <asm/mmu_context.h>
36#include <asm/tlbflush.h>
37#include <asm/dma.h>
38#include <asm/starfire.h>
39#include <asm/tlb.h>
40#include <asm/spitfire.h>
41#include <asm/sections.h>
517af332 42#include <asm/tsb.h>
1da177e4
LT		 43
44extern void device_scan(void);
45
13edad7a
DM		 46#define MAX_BANKS 32
47
48static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
49static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
50static int pavail_ents __initdata;
51static int pavail_rescan_ents __initdata;
52
53static int cmp_p64(const void *a, const void *b)
54{
55 const struct linux_prom64_registers *x = a, *y = b;
56
57 if (x->phys_addr > y->phys_addr)
58 return 1;
59 if (x->phys_addr < y->phys_addr)
60 return -1;
61 return 0;
62}
63
64static void __init read_obp_memory(const char *property,
65 struct linux_prom64_registers *regs,
66 int *num_ents)
67{
68 int node = prom_finddevice("/memory");
69 int prop_size = prom_getproplen(node, property);
70 int ents, ret, i;
71
72 ents = prop_size / sizeof(struct linux_prom64_registers);
73 if (ents > MAX_BANKS) {
74 prom_printf("The machine has more %s property entries than "
75 "this kernel can support (%d).\n",
76 property, MAX_BANKS);
77 prom_halt();
78 }
79
80 ret = prom_getproperty(node, property, (char *) regs, prop_size);
81 if (ret == -1) {
82 prom_printf("Couldn't get %s property from /memory.\n");
83 prom_halt();
84 }
85
86 *num_ents = ents;
10147570 87
13edad7a
DM		 88 /* Sanitize what we got from the firmware, by page aligning
89 * everything.
90 */
91 for (i = 0; i < ents; i++) {
92 unsigned long base, size;
93
94 base = regs[i].phys_addr;
95 size = regs[i].reg_size;
10147570 96
13edad7a
DM		 97 size &= PAGE_MASK;
98 if (base & ~PAGE_MASK) {
99 unsigned long new_base = PAGE_ALIGN(base);
100
101 size -= new_base - base;
102 if ((long) size < 0L)
103 size = 0UL;
104 base = new_base;
105 }
106 regs[i].phys_addr = base;
107 regs[i].reg_size = size;
108 }
c9c10830 109 sort(regs, ents, sizeof(struct linux_prom64_registers),
13edad7a
DM		 110 cmp_p64, NULL);
111}
1da177e4 112
2bdb3cb2 113unsigned long *sparc64_valid_addr_bitmap __read_mostly;
1da177e4
LT		 114
115/* Ugly, but necessary... -DaveM */
1ac4f5eb
DM		 116unsigned long phys_base __read_mostly;
117unsigned long kern_base __read_mostly;
118unsigned long kern_size __read_mostly;
119unsigned long pfn_base __read_mostly;
1da177e4 120
1da177e4
LT		 121/* get_new_mmu_context() uses "cache + 1". */
122DEFINE_SPINLOCK(ctx_alloc_lock);
123unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
124#define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
125unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
126
127/* References to special section boundaries */
128extern char _start[], _end[];
129
130/* Initial ramdisk setup */
131extern unsigned long sparc_ramdisk_image64;
132extern unsigned int sparc_ramdisk_image;
133extern unsigned int sparc_ramdisk_size;
134
1ac4f5eb 135struct page *mem_map_zero __read_mostly;
1da177e4 136
0835ae0f
DM		 137unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
138
139unsigned long sparc64_kern_pri_context __read_mostly;
140unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
141unsigned long sparc64_kern_sec_context __read_mostly;
142
1da177e4
LT		 143int bigkernel = 0;
144
3c936465 145kmem_cache_t *pgtable_cache __read_mostly;
1da177e4 146
3c936465
DM		 147static void zero_ctor(void *addr, kmem_cache_t *cache, unsigned long flags)
148{
149 clear_page(addr);
150}
05e28f9d 151
3c936465 152void pgtable_cache_init(void)
1da177e4 153{
3c936465
DM		 154 pgtable_cache = kmem_cache_create("pgtable_cache",
155 PAGE_SIZE, PAGE_SIZE,
156 SLAB_HWCACHE_ALIGN |
157 SLAB_MUST_HWCACHE_ALIGN,
158 zero_ctor,
159 NULL);
160 if (!pgtable_cache) {
161 prom_printf("pgtable_cache_init(): Could not create!\n");
162 prom_halt();
1da177e4 163 }
1da177e4
LT		 164}
165
166#ifdef CONFIG_DEBUG_DCFLUSH
167atomic_t dcpage_flushes = ATOMIC_INIT(0);
168#ifdef CONFIG_SMP
169atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
170#endif
171#endif
172
173__inline__ void flush_dcache_page_impl(struct page *page)
174{
175#ifdef CONFIG_DEBUG_DCFLUSH
176 atomic_inc(&dcpage_flushes);
177#endif
178
179#ifdef DCACHE_ALIASING_POSSIBLE
180 __flush_dcache_page(page_address(page),
181 ((tlb_type == spitfire) &&
182 page_mapping(page) != NULL));
183#else
184 if (page_mapping(page) != NULL &&
185 tlb_type == spitfire)
186 __flush_icache_page(__pa(page_address(page)));
187#endif
188}
189
190#define PG_dcache_dirty PG_arch_1
48b0e548
DM		 191#define PG_dcache_cpu_shift 24
192#define PG_dcache_cpu_mask (256 - 1)
193
194#if NR_CPUS > 256
195#error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
196#endif
1da177e4
LT		 197
198#define dcache_dirty_cpu(page) \
48b0e548 199 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
1da177e4
LT		 200
201static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
202{
203 unsigned long mask = this_cpu;
48b0e548
DM		 204 unsigned long non_cpu_bits;
205
206 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
207 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
208
1da177e4
LT		 209 __asm__ __volatile__("1:\n\t"
210 "ldx [%2], %%g7\n\t"
211 "and %%g7, %1, %%g1\n\t"
212 "or %%g1, %0, %%g1\n\t"
213 "casx [%2], %%g7, %%g1\n\t"
214 "cmp %%g7, %%g1\n\t"
b445e26c 215 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 216 "bne,pn %%xcc, 1b\n\t"
b445e26c 217 " nop"
1da177e4
LT		 218 : /* no outputs */
219 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
220 : "g1", "g7");
221}
222
223static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
224{
225 unsigned long mask = (1UL << PG_dcache_dirty);
226
227 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
228 "1:\n\t"
229 "ldx [%2], %%g7\n\t"
48b0e548 230 "srlx %%g7, %4, %%g1\n\t"
1da177e4
LT		 231 "and %%g1, %3, %%g1\n\t"
232 "cmp %%g1, %0\n\t"
233 "bne,pn %%icc, 2f\n\t"
234 " andn %%g7, %1, %%g1\n\t"
235 "casx [%2], %%g7, %%g1\n\t"
236 "cmp %%g7, %%g1\n\t"
b445e26c 237 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 238 "bne,pn %%xcc, 1b\n\t"
b445e26c 239 " nop\n"
1da177e4
LT		 240 "2:"
241 : /* no outputs */
242 : "r" (cpu), "r" (mask), "r" (&page->flags),
48b0e548
DM		 243 "i" (PG_dcache_cpu_mask),
244 "i" (PG_dcache_cpu_shift)
1da177e4
LT		 245 : "g1", "g7");
246}
247
517af332
DM		 248static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
249{
250 unsigned long tsb_addr = (unsigned long) ent;
251
252 if (tlb_type == cheetah_plus)
253 tsb_addr = __pa(tsb_addr);
254
255 __tsb_insert(tsb_addr, tag, pte);
256}
257
1da177e4
LT		 258void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
259{
bd40791e 260 struct mm_struct *mm;
1da177e4
LT		 261 struct page *page;
262 unsigned long pfn;
263 unsigned long pg_flags;
264
265 pfn = pte_pfn(pte);
266 if (pfn_valid(pfn) &&
267 (page = pfn_to_page(pfn), page_mapping(page)) &&
268 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
48b0e548
DM		 269 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
270 PG_dcache_cpu_mask);
1da177e4
LT		 271 int this_cpu = get_cpu();
272
273 /* This is just to optimize away some function calls
274 * in the SMP case.
275 */
276 if (cpu == this_cpu)
277 flush_dcache_page_impl(page);
278 else
279 smp_flush_dcache_page_impl(page, cpu);
280
281 clear_dcache_dirty_cpu(page, cpu);
282
283 put_cpu();
284 }
bd40791e
DM		 285
286 mm = vma->vm_mm;
b70c0fa1
DM		 287 if ((pte_val(pte) & _PAGE_ALL_SZ_BITS) == _PAGE_SZBITS) {
288 struct tsb *tsb;
289 unsigned long tag;
290
291 tsb = &mm->context.tsb[(address >> PAGE_SHIFT) &
292 (mm->context.tsb_nentries - 1UL)];
293 tag = (address >> 22UL) | CTX_HWBITS(mm->context) << 48UL;
294 tsb_insert(tsb, tag, pte_val(pte));
295 }
1da177e4
LT		 296}
297
298void flush_dcache_page(struct page *page)
299{
a9546f59
DM		 300 struct address_space *mapping;
301 int this_cpu;
1da177e4 302
a9546f59
DM		 303 /* Do not bother with the expensive D-cache flush if it
304 * is merely the zero page. The 'bigcore' testcase in GDB
305 * causes this case to run millions of times.
306 */
307 if (page == ZERO_PAGE(0))
308 return;
309
310 this_cpu = get_cpu();
311
312 mapping = page_mapping(page);
1da177e4 313 if (mapping && !mapping_mapped(mapping)) {
a9546f59 314 int dirty = test_bit(PG_dcache_dirty, &page->flags);
1da177e4 315 if (dirty) {
a9546f59
DM		 316 int dirty_cpu = dcache_dirty_cpu(page);
317
1da177e4
LT		 318 if (dirty_cpu == this_cpu)
319 goto out;
320 smp_flush_dcache_page_impl(page, dirty_cpu);
321 }
322 set_dcache_dirty(page, this_cpu);
323 } else {
324 /* We could delay the flush for the !page_mapping
325 * case too. But that case is for exec env/arg
326 * pages and those are %99 certainly going to get
327 * faulted into the tlb (and thus flushed) anyways.
328 */
329 flush_dcache_page_impl(page);
330 }
331
332out:
333 put_cpu();
334}
335
05e14cb3 336void __kprobes flush_icache_range(unsigned long start, unsigned long end)
1da177e4 337{
a43fe0e7 338 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
1da177e4
LT		 339 if (tlb_type == spitfire) {
340 unsigned long kaddr;
341
342 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
343 __flush_icache_page(__get_phys(kaddr));
344 }
345}
346
347unsigned long page_to_pfn(struct page *page)
348{
349 return (unsigned long) ((page - mem_map) + pfn_base);
350}
351
352struct page *pfn_to_page(unsigned long pfn)
353{
354 return (mem_map + (pfn - pfn_base));
355}
356
357void show_mem(void)
358{
359 printk("Mem-info:\n");
360 show_free_areas();
361 printk("Free swap: %6ldkB\n",
362 nr_swap_pages << (PAGE_SHIFT-10));
363 printk("%ld pages of RAM\n", num_physpages);
364 printk("%d free pages\n", nr_free_pages());
1da177e4
LT		 365}
366
367void mmu_info(struct seq_file *m)
368{
369 if (tlb_type == cheetah)
370 seq_printf(m, "MMU Type\t: Cheetah\n");
371 else if (tlb_type == cheetah_plus)
372 seq_printf(m, "MMU Type\t: Cheetah+\n");
373 else if (tlb_type == spitfire)
374 seq_printf(m, "MMU Type\t: Spitfire\n");
a43fe0e7
DM		 375 else if (tlb_type == hypervisor)
376 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
1da177e4
LT		 377 else
378 seq_printf(m, "MMU Type\t: ???\n");
379
380#ifdef CONFIG_DEBUG_DCFLUSH
381 seq_printf(m, "DCPageFlushes\t: %d\n",
382 atomic_read(&dcpage_flushes));
383#ifdef CONFIG_SMP
384 seq_printf(m, "DCPageFlushesXC\t: %d\n",
385 atomic_read(&dcpage_flushes_xcall));
386#endif /* CONFIG_SMP */
387#endif /* CONFIG_DEBUG_DCFLUSH */
388}
389
390struct linux_prom_translation {
391 unsigned long virt;
392 unsigned long size;
393 unsigned long data;
394};
c9c10830
DM		 395
396/* Exported for kernel TLB miss handling in ktlb.S */
397struct linux_prom_translation prom_trans[512] __read_mostly;
398unsigned int prom_trans_ents __read_mostly;
1da177e4
LT		 399
400extern unsigned long prom_boot_page;
401extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
402extern int prom_get_mmu_ihandle(void);
403extern void register_prom_callbacks(void);
404
405/* Exported for SMP bootup purposes. */
406unsigned long kern_locked_tte_data;
407
1da177e4
LT		 408/*
409 * Translate PROM's mapping we capture at boot time into physical address.
410 * The second parameter is only set from prom_callback() invocations.
411 */
412unsigned long prom_virt_to_phys(unsigned long promva, int *error)
413{
c9c10830 414 int i;
405599bd 415
c9c10830
DM		 416 for (i = 0; i < prom_trans_ents; i++) {
417 struct linux_prom_translation *p = &prom_trans[i];
405599bd 418
c9c10830
DM		 419 if (promva >= p->virt &&
420 promva < (p->virt + p->size)) {
421 unsigned long base = p->data & _PAGE_PADDR;
5085b4a5 422
c9c10830
DM		 423 if (error)
424 *error = 0;
425 return base + (promva & (8192 - 1));
405599bd 426 }
405599bd 427 }
c9c10830
DM		 428 if (error)
429 *error = 1;
430 return 0UL;
405599bd
DM		 431}
432
c9c10830
DM		 433/* The obp translations are saved based on 8k pagesize, since obp can
434 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
74bf4312 435 * HI_OBP_ADDRESS range are handled in ktlb.S.
c9c10830 436 */
5085b4a5
DM		 437static inline int in_obp_range(unsigned long vaddr)
438{
439 return (vaddr >= LOW_OBP_ADDRESS &&
440 vaddr < HI_OBP_ADDRESS);
441}
442
c9c10830 443static int cmp_ptrans(const void *a, const void *b)
405599bd 444{
c9c10830 445 const struct linux_prom_translation *x = a, *y = b;
405599bd 446
c9c10830
DM		 447 if (x->virt > y->virt)
448 return 1;
449 if (x->virt < y->virt)
450 return -1;
451 return 0;
405599bd
DM		 452}
453
c9c10830 454/* Read OBP translations property into 'prom_trans[]'. */
9ad98c5b 455static void __init read_obp_translations(void)
405599bd 456{
c9c10830 457 int n, node, ents, first, last, i;
1da177e4
LT		 458
459 node = prom_finddevice("/virtual-memory");
460 n = prom_getproplen(node, "translations");
405599bd 461 if (unlikely(n == 0 || n == -1)) {
b206fc4c 462 prom_printf("prom_mappings: Couldn't get size.\n");
1da177e4
LT		 463 prom_halt();
464 }
405599bd
DM		 465 if (unlikely(n > sizeof(prom_trans))) {
466 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
1da177e4
LT		 467 prom_halt();
468 }
405599bd 469
b206fc4c 470 if ((n = prom_getproperty(node, "translations",
405599bd
DM		 471 (char *)&prom_trans[0],
472 sizeof(prom_trans))) == -1) {
b206fc4c 473 prom_printf("prom_mappings: Couldn't get property.\n");
1da177e4
LT		 474 prom_halt();
475 }
9ad98c5b 476
b206fc4c 477 n = n / sizeof(struct linux_prom_translation);
9ad98c5b 478
c9c10830
DM		 479 ents = n;
480
481 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
482 cmp_ptrans, NULL);
483
484 /* Now kick out all the non-OBP entries. */
485 for (i = 0; i < ents; i++) {
486 if (in_obp_range(prom_trans[i].virt))
487 break;
488 }
489 first = i;
490 for (; i < ents; i++) {
491 if (!in_obp_range(prom_trans[i].virt))
492 break;
493 }
494 last = i;
495
496 for (i = 0; i < (last - first); i++) {
497 struct linux_prom_translation *src = &prom_trans[i + first];
498 struct linux_prom_translation *dest = &prom_trans[i];
499
500 *dest = *src;
501 }
502 for (; i < ents; i++) {
503 struct linux_prom_translation *dest = &prom_trans[i];
504 dest->virt = dest->size = dest->data = 0x0UL;
505 }
506
507 prom_trans_ents = last - first;
508
509 if (tlb_type == spitfire) {
510 /* Clear diag TTE bits. */
511 for (i = 0; i < prom_trans_ents; i++)
512 prom_trans[i].data &= ~0x0003fe0000000000UL;
513 }
405599bd 514}
1da177e4 515
898cf0ec 516static void __init remap_kernel(void)
405599bd
DM		 517{
518 unsigned long phys_page, tte_vaddr, tte_data;
405599bd
DM		 519 int tlb_ent = sparc64_highest_locked_tlbent();
520
1da177e4 521 tte_vaddr = (unsigned long) KERNBASE;
bff06d55
DM		 522 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
523 tte_data = (phys_page | (_PAGE_VALID | _PAGE_SZ4MB |
524 _PAGE_CP | _PAGE_CV | _PAGE_P |
525 _PAGE_L | _PAGE_W));
1da177e4
LT		 526
527 kern_locked_tte_data = tte_data;
528
bff06d55 529 /* Now lock us into the TLBs via OBP. */
405599bd
DM		 530 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
531 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
1da177e4 532 if (bigkernel) {
0835ae0f
DM		 533 tlb_ent -= 1;
534 prom_dtlb_load(tlb_ent,
405599bd
DM		 535 tte_data + 0x400000,
536 tte_vaddr + 0x400000);
0835ae0f 537 prom_itlb_load(tlb_ent,
405599bd
DM		 538 tte_data + 0x400000,
539 tte_vaddr + 0x400000);
1da177e4 540 }
0835ae0f
DM		 541 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
542 if (tlb_type == cheetah_plus) {
543 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
544 CTX_CHEETAH_PLUS_NUC);
545 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
546 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
547 }
405599bd 548}
1da177e4 549
405599bd 550
c9c10830 551static void __init inherit_prom_mappings(void)
9ad98c5b
DM		 552{
553 read_obp_translations();
405599bd
DM		 554
555 /* Now fixup OBP's idea about where we really are mapped. */
556 prom_printf("Remapping the kernel... ");
557 remap_kernel();
1da177e4
LT		 558 prom_printf("done.\n");
559
c9c10830 560 prom_printf("Registering callbacks... ");
1da177e4 561 register_prom_callbacks();
c9c10830 562 prom_printf("done.\n");
1da177e4
LT		 563}
564
1da177e4
LT		 565void prom_world(int enter)
566{
1da177e4
LT		 567 if (!enter)
568 set_fs((mm_segment_t) { get_thread_current_ds() });
569
3487d1d4 570 __asm__ __volatile__("flushw");
1da177e4
LT		 571}
572
573#ifdef DCACHE_ALIASING_POSSIBLE
574void __flush_dcache_range(unsigned long start, unsigned long end)
575{
576 unsigned long va;
577
578 if (tlb_type == spitfire) {
579 int n = 0;
580
581 for (va = start; va < end; va += 32) {
582 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
583 if (++n >= 512)
584 break;
585 }
a43fe0e7 586 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1da177e4
LT		 587 start = __pa(start);
588 end = __pa(end);
589 for (va = start; va < end; va += 32)
590 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
591 "membar #Sync"
592 : /* no outputs */
593 : "r" (va),
594 "i" (ASI_DCACHE_INVALIDATE));
595 }
596}
597#endif /* DCACHE_ALIASING_POSSIBLE */
598
599/* If not locked, zap it. */
600void __flush_tlb_all(void)
601{
602 unsigned long pstate;
603 int i;
604
605 __asm__ __volatile__("flushw\n\t"
606 "rdpr %%pstate, %0\n\t"
607 "wrpr %0, %1, %%pstate"
608 : "=r" (pstate)
609 : "i" (PSTATE_IE));
610 if (tlb_type == spitfire) {
611 for (i = 0; i < 64; i++) {
612 /* Spitfire Errata #32 workaround */
613 /* NOTE: Always runs on spitfire, so no
614 * cheetah+ page size encodings.
615 */
616 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
617 "flush %%g6"
618 : /* No outputs */
619 : "r" (0),
620 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
621
622 if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
623 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
624 "membar #Sync"
625 : /* no outputs */
626 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
627 spitfire_put_dtlb_data(i, 0x0UL);
628 }
629
630 /* Spitfire Errata #32 workaround */
631 /* NOTE: Always runs on spitfire, so no
632 * cheetah+ page size encodings.
633 */
634 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
635 "flush %%g6"
636 : /* No outputs */
637 : "r" (0),
638 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
639
640 if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
641 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
642 "membar #Sync"
643 : /* no outputs */
644 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
645 spitfire_put_itlb_data(i, 0x0UL);
646 }
647 }
648 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
649 cheetah_flush_dtlb_all();
650 cheetah_flush_itlb_all();
651 }
652 __asm__ __volatile__("wrpr %0, 0, %%pstate"
653 : : "r" (pstate));
654}
655
656/* Caller does TLB context flushing on local CPU if necessary.
657 * The caller also ensures that CTX_VALID(mm->context) is false.
658 *
659 * We must be careful about boundary cases so that we never
660 * let the user have CTX 0 (nucleus) or we ever use a CTX
661 * version of zero (and thus NO_CONTEXT would not be caught
662 * by version mis-match tests in mmu_context.h).
663 */
664void get_new_mmu_context(struct mm_struct *mm)
665{
666 unsigned long ctx, new_ctx;
667 unsigned long orig_pgsz_bits;
668
669
670 spin_lock(&ctx_alloc_lock);
671 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
672 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
673 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
674 if (new_ctx >= (1 << CTX_NR_BITS)) {
675 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
676 if (new_ctx >= ctx) {
677 int i;
678 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
679 CTX_FIRST_VERSION;
680 if (new_ctx == 1)
681 new_ctx = CTX_FIRST_VERSION;
682
683 /* Don't call memset, for 16 entries that's just
684 * plain silly...
685 */
686 mmu_context_bmap[0] = 3;
687 mmu_context_bmap[1] = 0;
688 mmu_context_bmap[2] = 0;
689 mmu_context_bmap[3] = 0;
690 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
691 mmu_context_bmap[i + 0] = 0;
692 mmu_context_bmap[i + 1] = 0;
693 mmu_context_bmap[i + 2] = 0;
694 mmu_context_bmap[i + 3] = 0;
695 }
696 goto out;
697 }
698 }
699 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
700 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
701out:
702 tlb_context_cache = new_ctx;
703 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
704 spin_unlock(&ctx_alloc_lock);
705}
706
1da177e4
LT		 707void sparc_ultra_dump_itlb(void)
708{
709 int slot;
710
711 if (tlb_type == spitfire) {
712 printk ("Contents of itlb: ");
713 for (slot = 0; slot < 14; slot++) printk (" ");
714 printk ("%2x:%016lx,%016lx\n",
715 0,
716 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
717 for (slot = 1; slot < 64; slot+=3) {
718 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
719 slot,
720 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
721 slot+1,
722 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
723 slot+2,
724 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
725 }
726 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
727 printk ("Contents of itlb0:\n");
728 for (slot = 0; slot < 16; slot+=2) {
729 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
730 slot,
731 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
732 slot+1,
733 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
734 }
735 printk ("Contents of itlb2:\n");
736 for (slot = 0; slot < 128; slot+=2) {
737 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
738 slot,
739 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
740 slot+1,
741 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
742 }
743 }
744}
745
746void sparc_ultra_dump_dtlb(void)
747{
748 int slot;
749
750 if (tlb_type == spitfire) {
751 printk ("Contents of dtlb: ");
752 for (slot = 0; slot < 14; slot++) printk (" ");
753 printk ("%2x:%016lx,%016lx\n", 0,
754 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
755 for (slot = 1; slot < 64; slot+=3) {
756 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
757 slot,
758 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
759 slot+1,
760 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
761 slot+2,
762 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
763 }
764 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
765 printk ("Contents of dtlb0:\n");
766 for (slot = 0; slot < 16; slot+=2) {
767 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
768 slot,
769 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
770 slot+1,
771 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
772 }
773 printk ("Contents of dtlb2:\n");
774 for (slot = 0; slot < 512; slot+=2) {
775 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
776 slot,
777 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
778 slot+1,
779 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
780 }
781 if (tlb_type == cheetah_plus) {
782 printk ("Contents of dtlb3:\n");
783 for (slot = 0; slot < 512; slot+=2) {
784 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
785 slot,
786 cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
787 slot+1,
788 cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
789 }
790 }
791 }
792}
793
3487d1d4
DM		 794static inline void spitfire_errata32(void)
795{
796 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
797 "flush %%g6"
798 : /* No outputs */
799 : "r" (0),
800 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
801}
802
1da177e4
LT		 803extern unsigned long cmdline_memory_size;
804
805unsigned long __init bootmem_init(unsigned long *pages_avail)
806{
807 unsigned long bootmap_size, start_pfn, end_pfn;
808 unsigned long end_of_phys_memory = 0UL;
809 unsigned long bootmap_pfn, bytes_avail, size;
810 int i;
811
812#ifdef CONFIG_DEBUG_BOOTMEM
13edad7a 813 prom_printf("bootmem_init: Scan pavail, ");
1da177e4
LT		 814#endif
815
816 bytes_avail = 0UL;
13edad7a
DM		 817 for (i = 0; i < pavail_ents; i++) {
818 end_of_phys_memory = pavail[i].phys_addr +
819 pavail[i].reg_size;
820 bytes_avail += pavail[i].reg_size;
1da177e4
LT		 821 if (cmdline_memory_size) {
822 if (bytes_avail > cmdline_memory_size) {
823 unsigned long slack = bytes_avail - cmdline_memory_size;
824
825 bytes_avail -= slack;
826 end_of_phys_memory -= slack;
827
13edad7a
DM		 828 pavail[i].reg_size -= slack;
829 if ((long)pavail[i].reg_size <= 0L) {
830 pavail[i].phys_addr = 0xdeadbeefUL;
831 pavail[i].reg_size = 0UL;
832 pavail_ents = i;
1da177e4 833 } else {
13edad7a
DM		 834 pavail[i+1].reg_size = 0Ul;
835 pavail[i+1].phys_addr = 0xdeadbeefUL;
836 pavail_ents = i + 1;
1da177e4
LT		 837 }
838 break;
839 }
840 }
841 }
842
843 *pages_avail = bytes_avail >> PAGE_SHIFT;
844
845 /* Start with page aligned address of last symbol in kernel
846 * image. The kernel is hard mapped below PAGE_OFFSET in a
847 * 4MB locked TLB translation.
848 */
849 start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
850
851 bootmap_pfn = start_pfn;
852
853 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
854
855#ifdef CONFIG_BLK_DEV_INITRD
856 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
857 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
858 unsigned long ramdisk_image = sparc_ramdisk_image ?
859 sparc_ramdisk_image : sparc_ramdisk_image64;
860 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
861 ramdisk_image -= KERNBASE;
862 initrd_start = ramdisk_image + phys_base;
863 initrd_end = initrd_start + sparc_ramdisk_size;
864 if (initrd_end > end_of_phys_memory) {
865 printk(KERN_CRIT "initrd extends beyond end of memory "
866 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
867 initrd_end, end_of_phys_memory);
868 initrd_start = 0;
869 }
870 if (initrd_start) {
871 if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
872 initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
873 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
874 }
875 }
876#endif
877 /* Initialize the boot-time allocator. */
878 max_pfn = max_low_pfn = end_pfn;
879 min_low_pfn = pfn_base;
880
881#ifdef CONFIG_DEBUG_BOOTMEM
882 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
883 min_low_pfn, bootmap_pfn, max_low_pfn);
884#endif
885 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
886
1da177e4
LT		 887 /* Now register the available physical memory with the
888 * allocator.
889 */
13edad7a 890 for (i = 0; i < pavail_ents; i++) {
1da177e4 891#ifdef CONFIG_DEBUG_BOOTMEM
13edad7a
DM		 892 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
893 i, pavail[i].phys_addr, pavail[i].reg_size);
1da177e4 894#endif
13edad7a 895 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
1da177e4
LT		 896 }
897
898#ifdef CONFIG_BLK_DEV_INITRD
899 if (initrd_start) {
900 size = initrd_end - initrd_start;
901
902 /* Resert the initrd image area. */
903#ifdef CONFIG_DEBUG_BOOTMEM
904 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
905 initrd_start, initrd_end);
906#endif
907 reserve_bootmem(initrd_start, size);
908 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
909
910 initrd_start += PAGE_OFFSET;
911 initrd_end += PAGE_OFFSET;
912 }
913#endif
914 /* Reserve the kernel text/data/bss. */
915#ifdef CONFIG_DEBUG_BOOTMEM
916 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
917#endif
918 reserve_bootmem(kern_base, kern_size);
919 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
920
921 /* Reserve the bootmem map. We do not account for it
922 * in pages_avail because we will release that memory
923 * in free_all_bootmem.
924 */
925 size = bootmap_size;
926#ifdef CONFIG_DEBUG_BOOTMEM
927 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
928 (bootmap_pfn << PAGE_SHIFT), size);
929#endif
930 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
931 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
932
933 return end_pfn;
934}
935
56425306
DM		 936#ifdef CONFIG_DEBUG_PAGEALLOC
937static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
938{
939 unsigned long vstart = PAGE_OFFSET + pstart;
940 unsigned long vend = PAGE_OFFSET + pend;
941 unsigned long alloc_bytes = 0UL;
942
943 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
13edad7a 944 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
56425306
DM		 945 vstart, vend);
946 prom_halt();
947 }
948
949 while (vstart < vend) {
950 unsigned long this_end, paddr = __pa(vstart);
951 pgd_t *pgd = pgd_offset_k(vstart);
952 pud_t *pud;
953 pmd_t *pmd;
954 pte_t *pte;
955
956 pud = pud_offset(pgd, vstart);
957 if (pud_none(*pud)) {
958 pmd_t *new;
959
960 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
961 alloc_bytes += PAGE_SIZE;
962 pud_populate(&init_mm, pud, new);
963 }
964
965 pmd = pmd_offset(pud, vstart);
966 if (!pmd_present(*pmd)) {
967 pte_t *new;
968
969 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
970 alloc_bytes += PAGE_SIZE;
971 pmd_populate_kernel(&init_mm, pmd, new);
972 }
973
974 pte = pte_offset_kernel(pmd, vstart);
975 this_end = (vstart + PMD_SIZE) & PMD_MASK;
976 if (this_end > vend)
977 this_end = vend;
978
979 while (vstart < this_end) {
980 pte_val(*pte) = (paddr | pgprot_val(prot));
981
982 vstart += PAGE_SIZE;
983 paddr += PAGE_SIZE;
984 pte++;
985 }
986 }
987
988 return alloc_bytes;
989}
990
13edad7a
DM		 991static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
992static int pall_ents __initdata;
993
56425306
DM		 994extern unsigned int kvmap_linear_patch[1];
995
996static void __init kernel_physical_mapping_init(void)
997{
13edad7a 998 unsigned long i, mem_alloced = 0UL;
56425306 999
13edad7a
DM		 1000 read_obp_memory("reg", &pall[0], &pall_ents);
1001
1002 for (i = 0; i < pall_ents; i++) {
56425306
DM		 1003 unsigned long phys_start, phys_end;
1004
13edad7a
DM		 1005 phys_start = pall[i].phys_addr;
1006 phys_end = phys_start + pall[i].reg_size;
56425306
DM		 1007 mem_alloced += kernel_map_range(phys_start, phys_end,
1008 PAGE_KERNEL);
56425306
DM		 1009 }
1010
1011 printk("Allocated %ld bytes for kernel page tables.\n",
1012 mem_alloced);
1013
1014 kvmap_linear_patch[0] = 0x01000000; /* nop */
1015 flushi(&kvmap_linear_patch[0]);
1016
1017 __flush_tlb_all();
1018}
1019
1020void kernel_map_pages(struct page *page, int numpages, int enable)
1021{
1022 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1023 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1024
1025 kernel_map_range(phys_start, phys_end,
1026 (enable ? PAGE_KERNEL : __pgprot(0)));
1027
74bf4312
DM		 1028 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1029 PAGE_OFFSET + phys_end);
1030
56425306
DM		 1031 /* we should perform an IPI and flush all tlbs,
1032 * but that can deadlock->flush only current cpu.
1033 */
1034 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1035 PAGE_OFFSET + phys_end);
1036}
1037#endif
1038
10147570
DM		 1039unsigned long __init find_ecache_flush_span(unsigned long size)
1040{
0836a0eb
DM		 1041 int i;
1042
13edad7a
DM		 1043 for (i = 0; i < pavail_ents; i++) {
1044 if (pavail[i].reg_size >= size)
1045 return pavail[i].phys_addr;
0836a0eb
DM		 1046 }
1047
13edad7a 1048 return ~0UL;
0836a0eb
DM		 1049}
1050
517af332
DM		 1051static void __init tsb_phys_patch(void)
1052{
d257d5da 1053 struct tsb_ldquad_phys_patch_entry *pquad;
517af332
DM		 1054 struct tsb_phys_patch_entry *p;
1055
d257d5da
DM		 1056 pquad = &__tsb_ldquad_phys_patch;
1057 while (pquad < &__tsb_ldquad_phys_patch_end) {
1058 unsigned long addr = pquad->addr;
1059
1060 if (tlb_type == hypervisor)
1061 *(unsigned int *) addr = pquad->sun4v_insn;
1062 else
1063 *(unsigned int *) addr = pquad->sun4u_insn;
1064 wmb();
1065 __asm__ __volatile__("flush %0"
1066 : /* no outputs */
1067 : "r" (addr));
1068
1069 pquad++;
1070 }
1071
517af332
DM		 1072 p = &__tsb_phys_patch;
1073 while (p < &__tsb_phys_patch_end) {
1074 unsigned long addr = p->addr;
1075
1076 *(unsigned int *) addr = p->insn;
1077 wmb();
1078 __asm__ __volatile__("flush %0"
1079 : /* no outputs */
1080 : "r" (addr));
1081
1082 p++;
1083 }
1084}
1085
1da177e4
LT		 1086/* paging_init() sets up the page tables */
1087
1088extern void cheetah_ecache_flush_init(void);
d257d5da 1089extern void sun4v_patch_tlb_handlers(void);
1da177e4
LT		 1090
1091static unsigned long last_valid_pfn;
56425306 1092pgd_t swapper_pg_dir[2048];
1da177e4
LT		 1093
1094void __init paging_init(void)
1095{
2bdb3cb2 1096 unsigned long end_pfn, pages_avail, shift;
0836a0eb
DM		 1097 unsigned long real_end, i;
1098
d257d5da
DM		 1099 if (tlb_type == cheetah_plus ||
1100 tlb_type == hypervisor)
517af332
DM		 1101 tsb_phys_patch();
1102
d257d5da
DM		 1103 if (tlb_type == hypervisor)
1104 sun4v_patch_tlb_handlers();
1105
13edad7a
DM		 1106 /* Find available physical memory... */
1107 read_obp_memory("available", &pavail[0], &pavail_ents);
0836a0eb
DM		 1108
1109 phys_base = 0xffffffffffffffffUL;
13edad7a
DM		 1110 for (i = 0; i < pavail_ents; i++)
1111 phys_base = min(phys_base, pavail[i].phys_addr);
0836a0eb 1112
0836a0eb
DM		 1113 pfn_base = phys_base >> PAGE_SHIFT;
1114
1115 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1116 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1da177e4
LT		 1117
1118 set_bit(0, mmu_context_bmap);
1119
2bdb3cb2
DM		 1120 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1121
1da177e4
LT		 1122 real_end = (unsigned long)_end;
1123 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1124 bigkernel = 1;
2bdb3cb2
DM		 1125 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1126 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1127 prom_halt();
1da177e4 1128 }
2bdb3cb2
DM		 1129
1130 /* Set kernel pgd to upper alias so physical page computations
1da177e4
LT		 1131 * work.
1132 */
1133 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1134
56425306 1135 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1da177e4
LT		 1136
1137 /* Now can init the kernel/bad page tables. */
1138 pud_set(pud_offset(&swapper_pg_dir[0], 0),
56425306 1139 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1da177e4 1140
c9c10830 1141 inherit_prom_mappings();
5085b4a5 1142
a8b900d8
DM		 1143 /* Ok, we can use our TLB miss and window trap handlers safely. */
1144 setup_tba();
1da177e4 1145
c9c10830 1146 __flush_tlb_all();
9ad98c5b 1147
2bdb3cb2
DM		 1148 /* Setup bootmem... */
1149 pages_avail = 0;
1150 last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1151
56425306
DM		 1152#ifdef CONFIG_DEBUG_PAGEALLOC
1153 kernel_physical_mapping_init();
1154#endif
1155
1da177e4
LT		 1156 {
1157 unsigned long zones_size[MAX_NR_ZONES];
1158 unsigned long zholes_size[MAX_NR_ZONES];
1159 unsigned long npages;
1160 int znum;
1161
1162 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1163 zones_size[znum] = zholes_size[znum] = 0;
1164
1165 npages = end_pfn - pfn_base;
1166 zones_size[ZONE_DMA] = npages;
1167 zholes_size[ZONE_DMA] = npages - pages_avail;
1168
1169 free_area_init_node(0, &contig_page_data, zones_size,
1170 phys_base >> PAGE_SHIFT, zholes_size);
1171 }
1172
1173 device_scan();
1174}
1175
1da177e4
LT		 1176static void __init taint_real_pages(void)
1177{
1da177e4
LT		 1178 int i;
1179
13edad7a 1180 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1da177e4 1181
13edad7a 1182 /* Find changes discovered in the physmem available rescan and
1da177e4
LT		 1183 * reserve the lost portions in the bootmem maps.
1184 */
13edad7a 1185 for (i = 0; i < pavail_ents; i++) {
1da177e4
LT		 1186 unsigned long old_start, old_end;
1187
13edad7a 1188 old_start = pavail[i].phys_addr;
1da177e4 1189 old_end = old_start +
13edad7a 1190 pavail[i].reg_size;
1da177e4
LT		 1191 while (old_start < old_end) {
1192 int n;
1193
13edad7a 1194 for (n = 0; pavail_rescan_ents; n++) {
1da177e4
LT		 1195 unsigned long new_start, new_end;
1196
13edad7a
DM		 1197 new_start = pavail_rescan[n].phys_addr;
1198 new_end = new_start +
1199 pavail_rescan[n].reg_size;
1da177e4
LT		 1200
1201 if (new_start <= old_start &&
1202 new_end >= (old_start + PAGE_SIZE)) {
13edad7a
DM		 1203 set_bit(old_start >> 22,
1204 sparc64_valid_addr_bitmap);
1da177e4
LT		 1205 goto do_next_page;
1206 }
1207 }
1208 reserve_bootmem(old_start, PAGE_SIZE);
1209
1210 do_next_page:
1211 old_start += PAGE_SIZE;
1212 }
1213 }
1214}
1215
1216void __init mem_init(void)
1217{
1218 unsigned long codepages, datapages, initpages;
1219 unsigned long addr, last;
1220 int i;
1221
1222 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1223 i += 1;
2bdb3cb2 1224 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1da177e4
LT		 1225 if (sparc64_valid_addr_bitmap == NULL) {
1226 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1227 prom_halt();
1228 }
1229 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1230
1231 addr = PAGE_OFFSET + kern_base;
1232 last = PAGE_ALIGN(kern_size) + addr;
1233 while (addr < last) {
1234 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1235 addr += PAGE_SIZE;
1236 }
1237
1238 taint_real_pages();
1239
1240 max_mapnr = last_valid_pfn - pfn_base;
1241 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1242
1243#ifdef CONFIG_DEBUG_BOOTMEM
1244 prom_printf("mem_init: Calling free_all_bootmem().\n");
1245#endif
1246 totalram_pages = num_physpages = free_all_bootmem() - 1;
1247
1248 /*
1249 * Set up the zero page, mark it reserved, so that page count
1250 * is not manipulated when freeing the page from user ptes.
1251 */
1252 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1253 if (mem_map_zero == NULL) {
1254 prom_printf("paging_init: Cannot alloc zero page.\n");
1255 prom_halt();
1256 }
1257 SetPageReserved(mem_map_zero);
1258
1259 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1260 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1261 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1262 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1263 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1264 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1265
1266 printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1267 nr_free_pages() << (PAGE_SHIFT-10),
1268 codepages << (PAGE_SHIFT-10),
1269 datapages << (PAGE_SHIFT-10),
1270 initpages << (PAGE_SHIFT-10),
1271 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1272
1273 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1274 cheetah_ecache_flush_init();
1275}
1276
898cf0ec 1277void free_initmem(void)
1da177e4
LT		 1278{
1279 unsigned long addr, initend;
1280
1281 /*
1282 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1283 */
1284 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1285 initend = (unsigned long)(__init_end) & PAGE_MASK;
1286 for (; addr < initend; addr += PAGE_SIZE) {
1287 unsigned long page;
1288 struct page *p;
1289
1290 page = (addr +
1291 ((unsigned long) __va(kern_base)) -
1292 ((unsigned long) KERNBASE));
1293 memset((void *)addr, 0xcc, PAGE_SIZE);
1294 p = virt_to_page(page);
1295
1296 ClearPageReserved(p);
1297 set_page_count(p, 1);
1298 __free_page(p);
1299 num_physpages++;
1300 totalram_pages++;
1301 }
1302}
1303
1304#ifdef CONFIG_BLK_DEV_INITRD
1305void free_initrd_mem(unsigned long start, unsigned long end)
1306{
1307 if (start < end)
1308 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1309 for (; start < end; start += PAGE_SIZE) {
1310 struct page *p = virt_to_page(start);
1311
1312 ClearPageReserved(p);
1313 set_page_count(p, 1);
1314 __free_page(p);
1315 num_physpages++;
1316 totalram_pages++;
1317 }
1318}
1319#endif
kernel source for telekom puls (alcatel/mediatek)