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[SPARC]: Mark as emulating cmpxchg, add appropriate depends for DRM.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / sparc64 / mm / init.c
CommitLineData
1da177e4
LT		 1/* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
c4bce90e 8#include <linux/module.h>
1da177e4
LT		 9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/string.h>
12#include <linux/init.h>
13#include <linux/bootmem.h>
14#include <linux/mm.h>
15#include <linux/hugetlb.h>
16#include <linux/slab.h>
17#include <linux/initrd.h>
18#include <linux/swap.h>
19#include <linux/pagemap.h>
c9cf5528 20#include <linux/poison.h>
1da177e4
LT		 21#include <linux/fs.h>
22#include <linux/seq_file.h>
05e14cb3 23#include <linux/kprobes.h>
1ac4f5eb 24#include <linux/cache.h>
13edad7a 25#include <linux/sort.h>
5cbc3073 26#include <linux/percpu.h>
1da177e4
LT		 27
28#include <asm/head.h>
29#include <asm/system.h>
30#include <asm/page.h>
31#include <asm/pgalloc.h>
32#include <asm/pgtable.h>
33#include <asm/oplib.h>
34#include <asm/iommu.h>
35#include <asm/io.h>
36#include <asm/uaccess.h>
37#include <asm/mmu_context.h>
38#include <asm/tlbflush.h>
39#include <asm/dma.h>
40#include <asm/starfire.h>
41#include <asm/tlb.h>
42#include <asm/spitfire.h>
43#include <asm/sections.h>
517af332 44#include <asm/tsb.h>
481295f9 45#include <asm/hypervisor.h>
372b07bb 46#include <asm/prom.h>
22d6a1cb 47#include <asm/sstate.h>
5cbc3073 48#include <asm/mdesc.h>
1da177e4 49
9cc3a1ac
DM		 50#define MAX_PHYS_ADDRESS (1UL << 42UL)
51#define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
52#define KPTE_BITMAP_BYTES \
53 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
54
55unsigned long kern_linear_pte_xor[2] __read_mostly;
56
57/* A bitmap, one bit for every 256MB of physical memory. If the bit
58 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
59 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
60 */
61unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
62
d1acb421 63#ifndef CONFIG_DEBUG_PAGEALLOC
d7744a09
DM		 64/* A special kernel TSB for 4MB and 256MB linear mappings. */
65struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
d1acb421 66#endif
d7744a09 67
13edad7a
DM		 68#define MAX_BANKS 32
69
70static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
71static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
72static int pavail_ents __initdata;
73static int pavail_rescan_ents __initdata;
74
75static int cmp_p64(const void *a, const void *b)
76{
77 const struct linux_prom64_registers *x = a, *y = b;
78
79 if (x->phys_addr > y->phys_addr)
80 return 1;
81 if (x->phys_addr < y->phys_addr)
82 return -1;
83 return 0;
84}
85
86static void __init read_obp_memory(const char *property,
87 struct linux_prom64_registers *regs,
88 int *num_ents)
89{
90 int node = prom_finddevice("/memory");
91 int prop_size = prom_getproplen(node, property);
92 int ents, ret, i;
93
94 ents = prop_size / sizeof(struct linux_prom64_registers);
95 if (ents > MAX_BANKS) {
96 prom_printf("The machine has more %s property entries than "
97 "this kernel can support (%d).\n",
98 property, MAX_BANKS);
99 prom_halt();
100 }
101
102 ret = prom_getproperty(node, property, (char *) regs, prop_size);
103 if (ret == -1) {
104 prom_printf("Couldn't get %s property from /memory.\n");
105 prom_halt();
106 }
107
13edad7a
DM		 108 /* Sanitize what we got from the firmware, by page aligning
109 * everything.
110 */
111 for (i = 0; i < ents; i++) {
112 unsigned long base, size;
113
114 base = regs[i].phys_addr;
115 size = regs[i].reg_size;
10147570 116
13edad7a
DM		 117 size &= PAGE_MASK;
118 if (base & ~PAGE_MASK) {
119 unsigned long new_base = PAGE_ALIGN(base);
120
121 size -= new_base - base;
122 if ((long) size < 0L)
123 size = 0UL;
124 base = new_base;
125 }
0015d3d6
DM		 126 if (size == 0UL) {
127 /* If it is empty, simply get rid of it.
128 * This simplifies the logic of the other
129 * functions that process these arrays.
130 */
131 memmove(&regs[i], &regs[i + 1],
132 (ents - i - 1) * sizeof(regs[0]));
486ad10a 133 i--;
0015d3d6
DM		 134 ents--;
135 continue;
486ad10a 136 }
0015d3d6
DM		 137 regs[i].phys_addr = base;
138 regs[i].reg_size = size;
486ad10a
DM		 139 }
140
141 *num_ents = ents;
142
c9c10830 143 sort(regs, ents, sizeof(struct linux_prom64_registers),
13edad7a
DM		 144 cmp_p64, NULL);
145}
1da177e4 146
2bdb3cb2 147unsigned long *sparc64_valid_addr_bitmap __read_mostly;
1da177e4 148
d1112018 149/* Kernel physical address base and size in bytes. */
1ac4f5eb
DM		 150unsigned long kern_base __read_mostly;
151unsigned long kern_size __read_mostly;
1da177e4 152
1da177e4
LT		 153/* Initial ramdisk setup */
154extern unsigned long sparc_ramdisk_image64;
155extern unsigned int sparc_ramdisk_image;
156extern unsigned int sparc_ramdisk_size;
157
1ac4f5eb 158struct page *mem_map_zero __read_mostly;
1da177e4 159
0835ae0f
DM		 160unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
161
162unsigned long sparc64_kern_pri_context __read_mostly;
163unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
164unsigned long sparc64_kern_sec_context __read_mostly;
165
1da177e4
LT		 166int bigkernel = 0;
167
1da177e4
LT		 168#ifdef CONFIG_DEBUG_DCFLUSH
169atomic_t dcpage_flushes = ATOMIC_INIT(0);
170#ifdef CONFIG_SMP
171atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
172#endif
173#endif
174
7a591cfe 175inline void flush_dcache_page_impl(struct page *page)
1da177e4 176{
7a591cfe 177 BUG_ON(tlb_type == hypervisor);
1da177e4
LT		 178#ifdef CONFIG_DEBUG_DCFLUSH
179 atomic_inc(&dcpage_flushes);
180#endif
181
182#ifdef DCACHE_ALIASING_POSSIBLE
183 __flush_dcache_page(page_address(page),
184 ((tlb_type == spitfire) &&
185 page_mapping(page) != NULL));
186#else
187 if (page_mapping(page) != NULL &&
188 tlb_type == spitfire)
189 __flush_icache_page(__pa(page_address(page)));
190#endif
191}
192
193#define PG_dcache_dirty PG_arch_1
22adb358
DM		 194#define PG_dcache_cpu_shift 32UL
195#define PG_dcache_cpu_mask \
196 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
1da177e4
LT		 197
198#define dcache_dirty_cpu(page) \
48b0e548 199 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
1da177e4
LT		 200
201static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
202{
203 unsigned long mask = this_cpu;
48b0e548
DM		 204 unsigned long non_cpu_bits;
205
206 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
207 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
208
1da177e4
LT		 209 __asm__ __volatile__("1:\n\t"
210 "ldx [%2], %%g7\n\t"
211 "and %%g7, %1, %%g1\n\t"
212 "or %%g1, %0, %%g1\n\t"
213 "casx [%2], %%g7, %%g1\n\t"
214 "cmp %%g7, %%g1\n\t"
b445e26c 215 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 216 "bne,pn %%xcc, 1b\n\t"
b445e26c 217 " nop"
1da177e4
LT		 218 : /* no outputs */
219 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
220 : "g1", "g7");
221}
222
223static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
224{
225 unsigned long mask = (1UL << PG_dcache_dirty);
226
227 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
228 "1:\n\t"
229 "ldx [%2], %%g7\n\t"
48b0e548 230 "srlx %%g7, %4, %%g1\n\t"
1da177e4
LT		 231 "and %%g1, %3, %%g1\n\t"
232 "cmp %%g1, %0\n\t"
233 "bne,pn %%icc, 2f\n\t"
234 " andn %%g7, %1, %%g1\n\t"
235 "casx [%2], %%g7, %%g1\n\t"
236 "cmp %%g7, %%g1\n\t"
b445e26c 237 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 238 "bne,pn %%xcc, 1b\n\t"
b445e26c 239 " nop\n"
1da177e4
LT		 240 "2:"
241 : /* no outputs */
242 : "r" (cpu), "r" (mask), "r" (&page->flags),
48b0e548
DM		 243 "i" (PG_dcache_cpu_mask),
244 "i" (PG_dcache_cpu_shift)
1da177e4
LT		 245 : "g1", "g7");
246}
247
517af332
DM		 248static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
249{
250 unsigned long tsb_addr = (unsigned long) ent;
251
3b3ab2eb 252 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
517af332
DM		 253 tsb_addr = __pa(tsb_addr);
254
255 __tsb_insert(tsb_addr, tag, pte);
256}
257
c4bce90e
DM		 258unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
259unsigned long _PAGE_SZBITS __read_mostly;
260
1da177e4
LT		 261void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
262{
bd40791e 263 struct mm_struct *mm;
74ae9987 264 struct tsb *tsb;
7a1ac526 265 unsigned long tag, flags;
dcc1e8dd 266 unsigned long tsb_index, tsb_hash_shift;
7a591cfe
DM		 267
268 if (tlb_type != hypervisor) {
269 unsigned long pfn = pte_pfn(pte);
270 unsigned long pg_flags;
271 struct page *page;
272
273 if (pfn_valid(pfn) &&
274 (page = pfn_to_page(pfn), page_mapping(page)) &&
275 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
276 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
277 PG_dcache_cpu_mask);
278 int this_cpu = get_cpu();
279
280 /* This is just to optimize away some function calls
281 * in the SMP case.
282 */
283 if (cpu == this_cpu)
284 flush_dcache_page_impl(page);
285 else
286 smp_flush_dcache_page_impl(page, cpu);
287
288 clear_dcache_dirty_cpu(page, cpu);
289
290 put_cpu();
291 }
1da177e4 292 }
bd40791e
DM		 293
294 mm = vma->vm_mm;
7a1ac526 295
dcc1e8dd
DM		 296 tsb_index = MM_TSB_BASE;
297 tsb_hash_shift = PAGE_SHIFT;
298
7a1ac526
DM		 299 spin_lock_irqsave(&mm->context.lock, flags);
300
dcc1e8dd
DM		 301#ifdef CONFIG_HUGETLB_PAGE
302 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
303 if ((tlb_type == hypervisor &&
304 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
305 (tlb_type != hypervisor &&
306 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
307 tsb_index = MM_TSB_HUGE;
308 tsb_hash_shift = HPAGE_SHIFT;
309 }
310 }
311#endif
312
313 tsb = mm->context.tsb_block[tsb_index].tsb;
314 tsb += ((address >> tsb_hash_shift) &
315 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
74ae9987
DM		 316 tag = (address >> 22UL);
317 tsb_insert(tsb, tag, pte_val(pte));
7a1ac526
DM		 318
319 spin_unlock_irqrestore(&mm->context.lock, flags);
1da177e4
LT		 320}
321
322void flush_dcache_page(struct page *page)
323{
a9546f59
DM		 324 struct address_space *mapping;
325 int this_cpu;
1da177e4 326
7a591cfe
DM		 327 if (tlb_type == hypervisor)
328 return;
329
a9546f59
DM		 330 /* Do not bother with the expensive D-cache flush if it
331 * is merely the zero page. The 'bigcore' testcase in GDB
332 * causes this case to run millions of times.
333 */
334 if (page == ZERO_PAGE(0))
335 return;
336
337 this_cpu = get_cpu();
338
339 mapping = page_mapping(page);
1da177e4 340 if (mapping && !mapping_mapped(mapping)) {
a9546f59 341 int dirty = test_bit(PG_dcache_dirty, &page->flags);
1da177e4 342 if (dirty) {
a9546f59
DM		 343 int dirty_cpu = dcache_dirty_cpu(page);
344
1da177e4
LT		 345 if (dirty_cpu == this_cpu)
346 goto out;
347 smp_flush_dcache_page_impl(page, dirty_cpu);
348 }
349 set_dcache_dirty(page, this_cpu);
350 } else {
351 /* We could delay the flush for the !page_mapping
352 * case too. But that case is for exec env/arg
353 * pages and those are %99 certainly going to get
354 * faulted into the tlb (and thus flushed) anyways.
355 */
356 flush_dcache_page_impl(page);
357 }
358
359out:
360 put_cpu();
361}
362
05e14cb3 363void __kprobes flush_icache_range(unsigned long start, unsigned long end)
1da177e4 364{
a43fe0e7 365 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
1da177e4
LT		 366 if (tlb_type == spitfire) {
367 unsigned long kaddr;
368
a94aa253
DM		 369 /* This code only runs on Spitfire cpus so this is
370 * why we can assume _PAGE_PADDR_4U.
371 */
372 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
373 unsigned long paddr, mask = _PAGE_PADDR_4U;
374
375 if (kaddr >= PAGE_OFFSET)
376 paddr = kaddr & mask;
377 else {
378 pgd_t *pgdp = pgd_offset_k(kaddr);
379 pud_t *pudp = pud_offset(pgdp, kaddr);
380 pmd_t *pmdp = pmd_offset(pudp, kaddr);
381 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
382
383 paddr = pte_val(*ptep) & mask;
384 }
385 __flush_icache_page(paddr);
386 }
1da177e4
LT		 387 }
388}
389
1da177e4
LT		 390void show_mem(void)
391{
5be4a963
DM		 392 unsigned long total = 0, reserved = 0;
393 unsigned long shared = 0, cached = 0;
394 pg_data_t *pgdat;
395
28256ca2 396 printk(KERN_INFO "Mem-info:\n");
1da177e4 397 show_free_areas();
28256ca2 398 printk(KERN_INFO "Free swap: %6ldkB\n",
1da177e4 399 nr_swap_pages << (PAGE_SHIFT-10));
5be4a963
DM		 400 for_each_online_pgdat(pgdat) {
401 unsigned long i, flags;
402
403 pgdat_resize_lock(pgdat, &flags);
404 for (i = 0; i < pgdat->node_spanned_pages; i++) {
405 struct page *page = pgdat_page_nr(pgdat, i);
406 total++;
407 if (PageReserved(page))
408 reserved++;
409 else if (PageSwapCache(page))
410 cached++;
411 else if (page_count(page))
412 shared += page_count(page) - 1;
413 }
414 pgdat_resize_unlock(pgdat, &flags);
415 }
416
417 printk(KERN_INFO "%lu pages of RAM\n", total);
418 printk(KERN_INFO "%lu reserved pages\n", reserved);
419 printk(KERN_INFO "%lu pages shared\n", shared);
420 printk(KERN_INFO "%lu pages swap cached\n", cached);
421
422 printk(KERN_INFO "%lu pages dirty\n",
423 global_page_state(NR_FILE_DIRTY));
424 printk(KERN_INFO "%lu pages writeback\n",
425 global_page_state(NR_WRITEBACK));
426 printk(KERN_INFO "%lu pages mapped\n",
427 global_page_state(NR_FILE_MAPPED));
428 printk(KERN_INFO "%lu pages slab\n",
429 global_page_state(NR_SLAB_RECLAIMABLE) +
430 global_page_state(NR_SLAB_UNRECLAIMABLE));
431 printk(KERN_INFO "%lu pages pagetables\n",
432 global_page_state(NR_PAGETABLE));
1da177e4
LT		 433}
434
435void mmu_info(struct seq_file *m)
436{
437 if (tlb_type == cheetah)
438 seq_printf(m, "MMU Type\t: Cheetah\n");
439 else if (tlb_type == cheetah_plus)
440 seq_printf(m, "MMU Type\t: Cheetah+\n");
441 else if (tlb_type == spitfire)
442 seq_printf(m, "MMU Type\t: Spitfire\n");
a43fe0e7
DM		 443 else if (tlb_type == hypervisor)
444 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
1da177e4
LT		 445 else
446 seq_printf(m, "MMU Type\t: ???\n");
447
448#ifdef CONFIG_DEBUG_DCFLUSH
449 seq_printf(m, "DCPageFlushes\t: %d\n",
450 atomic_read(&dcpage_flushes));
451#ifdef CONFIG_SMP
452 seq_printf(m, "DCPageFlushesXC\t: %d\n",
453 atomic_read(&dcpage_flushes_xcall));
454#endif /* CONFIG_SMP */
455#endif /* CONFIG_DEBUG_DCFLUSH */
456}
457
a94aa253
DM		 458struct linux_prom_translation {
459 unsigned long virt;
460 unsigned long size;
461 unsigned long data;
462};
463
464/* Exported for kernel TLB miss handling in ktlb.S */
465struct linux_prom_translation prom_trans[512] __read_mostly;
466unsigned int prom_trans_ents __read_mostly;
467
1da177e4
LT		 468/* Exported for SMP bootup purposes. */
469unsigned long kern_locked_tte_data;
470
c9c10830
DM		 471/* The obp translations are saved based on 8k pagesize, since obp can
472 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
74bf4312 473 * HI_OBP_ADDRESS range are handled in ktlb.S.
c9c10830 474 */
5085b4a5
DM		 475static inline int in_obp_range(unsigned long vaddr)
476{
477 return (vaddr >= LOW_OBP_ADDRESS &&
478 vaddr < HI_OBP_ADDRESS);
479}
480
c9c10830 481static int cmp_ptrans(const void *a, const void *b)
405599bd 482{
c9c10830 483 const struct linux_prom_translation *x = a, *y = b;
405599bd 484
c9c10830
DM		 485 if (x->virt > y->virt)
486 return 1;
487 if (x->virt < y->virt)
488 return -1;
489 return 0;
405599bd
DM		 490}
491
c9c10830 492/* Read OBP translations property into 'prom_trans[]'. */
9ad98c5b 493static void __init read_obp_translations(void)
405599bd 494{
c9c10830 495 int n, node, ents, first, last, i;
1da177e4
LT		 496
497 node = prom_finddevice("/virtual-memory");
498 n = prom_getproplen(node, "translations");
405599bd 499 if (unlikely(n == 0 || n == -1)) {
b206fc4c 500 prom_printf("prom_mappings: Couldn't get size.\n");
1da177e4
LT		 501 prom_halt();
502 }
405599bd
DM		 503 if (unlikely(n > sizeof(prom_trans))) {
504 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
1da177e4
LT		 505 prom_halt();
506 }
405599bd 507
b206fc4c 508 if ((n = prom_getproperty(node, "translations",
405599bd
DM		 509 (char *)&prom_trans[0],
510 sizeof(prom_trans))) == -1) {
b206fc4c 511 prom_printf("prom_mappings: Couldn't get property.\n");
1da177e4
LT		 512 prom_halt();
513 }
9ad98c5b 514
b206fc4c 515 n = n / sizeof(struct linux_prom_translation);
9ad98c5b 516
c9c10830
DM		 517 ents = n;
518
519 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
520 cmp_ptrans, NULL);
521
522 /* Now kick out all the non-OBP entries. */
523 for (i = 0; i < ents; i++) {
524 if (in_obp_range(prom_trans[i].virt))
525 break;
526 }
527 first = i;
528 for (; i < ents; i++) {
529 if (!in_obp_range(prom_trans[i].virt))
530 break;
531 }
532 last = i;
533
534 for (i = 0; i < (last - first); i++) {
535 struct linux_prom_translation *src = &prom_trans[i + first];
536 struct linux_prom_translation *dest = &prom_trans[i];
537
538 *dest = *src;
539 }
540 for (; i < ents; i++) {
541 struct linux_prom_translation *dest = &prom_trans[i];
542 dest->virt = dest->size = dest->data = 0x0UL;
543 }
544
545 prom_trans_ents = last - first;
546
547 if (tlb_type == spitfire) {
548 /* Clear diag TTE bits. */
549 for (i = 0; i < prom_trans_ents; i++)
550 prom_trans[i].data &= ~0x0003fe0000000000UL;
551 }
405599bd 552}
1da177e4 553
d82ace7d
DM		 554static void __init hypervisor_tlb_lock(unsigned long vaddr,
555 unsigned long pte,
556 unsigned long mmu)
557{
164c220f
DM		 558 register unsigned long func asm("%o5");
559 register unsigned long arg0 asm("%o0");
560 register unsigned long arg1 asm("%o1");
561 register unsigned long arg2 asm("%o2");
562 register unsigned long arg3 asm("%o3");
d82ace7d
DM		 563
564 func = HV_FAST_MMU_MAP_PERM_ADDR;
565 arg0 = vaddr;
566 arg1 = 0;
567 arg2 = pte;
568 arg3 = mmu;
569 __asm__ __volatile__("ta 0x80"
570 : "=&r" (func), "=&r" (arg0),
571 "=&r" (arg1), "=&r" (arg2),
572 "=&r" (arg3)
573 : "0" (func), "1" (arg0), "2" (arg1),
574 "3" (arg2), "4" (arg3));
12e126ad
DM		 575 if (arg0 != 0) {
576 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
577 "errors with %lx\n", vaddr, 0, pte, mmu, arg0);
578 prom_halt();
579 }
d82ace7d
DM		 580}
581
c4bce90e
DM		 582static unsigned long kern_large_tte(unsigned long paddr);
583
898cf0ec 584static void __init remap_kernel(void)
405599bd
DM		 585{
586 unsigned long phys_page, tte_vaddr, tte_data;
405599bd
DM		 587 int tlb_ent = sparc64_highest_locked_tlbent();
588
1da177e4 589 tte_vaddr = (unsigned long) KERNBASE;
bff06d55 590 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
c4bce90e 591 tte_data = kern_large_tte(phys_page);
1da177e4
LT		 592
593 kern_locked_tte_data = tte_data;
594
d82ace7d
DM		 595 /* Now lock us into the TLBs via Hypervisor or OBP. */
596 if (tlb_type == hypervisor) {
597 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
598 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
599 if (bigkernel) {
600 tte_vaddr += 0x400000;
601 tte_data += 0x400000;
602 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
603 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
604 }
605 } else {
606 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
607 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
608 if (bigkernel) {
609 tlb_ent -= 1;
610 prom_dtlb_load(tlb_ent,
611 tte_data + 0x400000,
612 tte_vaddr + 0x400000);
613 prom_itlb_load(tlb_ent,
614 tte_data + 0x400000,
615 tte_vaddr + 0x400000);
616 }
617 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
1da177e4 618 }
0835ae0f
DM		 619 if (tlb_type == cheetah_plus) {
620 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
621 CTX_CHEETAH_PLUS_NUC);
622 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
623 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
624 }
405599bd 625}
1da177e4 626
405599bd 627
c9c10830 628static void __init inherit_prom_mappings(void)
9ad98c5b
DM		 629{
630 read_obp_translations();
405599bd
DM		 631
632 /* Now fixup OBP's idea about where we really are mapped. */
633 prom_printf("Remapping the kernel... ");
634 remap_kernel();
1da177e4 635 prom_printf("done.\n");
1da177e4
LT		 636}
637
1da177e4
LT		 638void prom_world(int enter)
639{
1da177e4
LT		 640 if (!enter)
641 set_fs((mm_segment_t) { get_thread_current_ds() });
642
3487d1d4 643 __asm__ __volatile__("flushw");
1da177e4
LT		 644}
645
646#ifdef DCACHE_ALIASING_POSSIBLE
647void __flush_dcache_range(unsigned long start, unsigned long end)
648{
649 unsigned long va;
650
651 if (tlb_type == spitfire) {
652 int n = 0;
653
654 for (va = start; va < end; va += 32) {
655 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
656 if (++n >= 512)
657 break;
658 }
a43fe0e7 659 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1da177e4
LT		 660 start = __pa(start);
661 end = __pa(end);
662 for (va = start; va < end; va += 32)
663 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
664 "membar #Sync"
665 : /* no outputs */
666 : "r" (va),
667 "i" (ASI_DCACHE_INVALIDATE));
668 }
669}
670#endif /* DCACHE_ALIASING_POSSIBLE */
671
85f1e1f6
DM		 672/* get_new_mmu_context() uses "cache + 1". */
673DEFINE_SPINLOCK(ctx_alloc_lock);
674unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
675#define MAX_CTX_NR (1UL << CTX_NR_BITS)
676#define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
677DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
678
1da177e4
LT		 679/* Caller does TLB context flushing on local CPU if necessary.
680 * The caller also ensures that CTX_VALID(mm->context) is false.
681 *
682 * We must be careful about boundary cases so that we never
683 * let the user have CTX 0 (nucleus) or we ever use a CTX
684 * version of zero (and thus NO_CONTEXT would not be caught
685 * by version mis-match tests in mmu_context.h).
a0663a79
DM		 686 *
687 * Always invoked with interrupts disabled.
1da177e4
LT		 688 */
689void get_new_mmu_context(struct mm_struct *mm)
690{
691 unsigned long ctx, new_ctx;
692 unsigned long orig_pgsz_bits;
a77754b4 693 unsigned long flags;
a0663a79 694 int new_version;
1da177e4 695
a77754b4 696 spin_lock_irqsave(&ctx_alloc_lock, flags);
1da177e4
LT		 697 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
698 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
699 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
a0663a79 700 new_version = 0;
1da177e4
LT		 701 if (new_ctx >= (1 << CTX_NR_BITS)) {
702 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
703 if (new_ctx >= ctx) {
704 int i;
705 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
706 CTX_FIRST_VERSION;
707 if (new_ctx == 1)
708 new_ctx = CTX_FIRST_VERSION;
709
710 /* Don't call memset, for 16 entries that's just
711 * plain silly...
712 */
713 mmu_context_bmap[0] = 3;
714 mmu_context_bmap[1] = 0;
715 mmu_context_bmap[2] = 0;
716 mmu_context_bmap[3] = 0;
717 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
718 mmu_context_bmap[i + 0] = 0;
719 mmu_context_bmap[i + 1] = 0;
720 mmu_context_bmap[i + 2] = 0;
721 mmu_context_bmap[i + 3] = 0;
722 }
a0663a79 723 new_version = 1;
1da177e4
LT		 724 goto out;
725 }
726 }
727 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
728 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
729out:
730 tlb_context_cache = new_ctx;
731 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
a77754b4 732 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
a0663a79
DM		 733
734 if (unlikely(new_version))
735 smp_new_mmu_context_version();
1da177e4
LT		 736}
737
d1112018
DM		 738/* Find a free area for the bootmem map, avoiding the kernel image
739 * and the initial ramdisk.
740 */
741static unsigned long __init choose_bootmap_pfn(unsigned long start_pfn,
742 unsigned long end_pfn)
1da177e4 743{
d1112018
DM		 744 unsigned long avoid_start, avoid_end, bootmap_size;
745 int i;
746
39964653
DM		 747 bootmap_size = bootmem_bootmap_pages(end_pfn - start_pfn);
748 bootmap_size <<= PAGE_SHIFT;
d1112018
DM		 749
750 avoid_start = avoid_end = 0;
751#ifdef CONFIG_BLK_DEV_INITRD
752 avoid_start = initrd_start;
753 avoid_end = PAGE_ALIGN(initrd_end);
754#endif
755
756#ifdef CONFIG_DEBUG_BOOTMEM
757 prom_printf("choose_bootmap_pfn: kern[%lx:%lx] avoid[%lx:%lx]\n",
758 kern_base, PAGE_ALIGN(kern_base + kern_size),
759 avoid_start, avoid_end);
760#endif
761 for (i = 0; i < pavail_ents; i++) {
762 unsigned long start, end;
763
764 start = pavail[i].phys_addr;
765 end = start + pavail[i].reg_size;
766
767 while (start < end) {
768 if (start >= kern_base &&
769 start < PAGE_ALIGN(kern_base + kern_size)) {
770 start = PAGE_ALIGN(kern_base + kern_size);
771 continue;
772 }
773 if (start >= avoid_start && start < avoid_end) {
774 start = avoid_end;
775 continue;
776 }
777
778 if ((end - start) < bootmap_size)
779 break;
780
781 if (start < kern_base &&
782 (start + bootmap_size) > kern_base) {
783 start = PAGE_ALIGN(kern_base + kern_size);
784 continue;
785 }
786
787 if (start < avoid_start &&
788 (start + bootmap_size) > avoid_start) {
789 start = avoid_end;
790 continue;
791 }
792
793 /* OK, it doesn't overlap anything, use it. */
794#ifdef CONFIG_DEBUG_BOOTMEM
795 prom_printf("choose_bootmap_pfn: Using %lx [%lx]\n",
796 start >> PAGE_SHIFT, start);
797#endif
798 return start >> PAGE_SHIFT;
799 }
800 }
801
802 prom_printf("Cannot find free area for bootmap, aborting.\n");
803 prom_halt();
804}
805
6fc5bae7
DM		 806static void __init trim_pavail(unsigned long *cur_size_p,
807 unsigned long *end_of_phys_p)
808{
809 unsigned long to_trim = *cur_size_p - cmdline_memory_size;
810 unsigned long avoid_start, avoid_end;
811 int i;
812
813 to_trim = PAGE_ALIGN(to_trim);
814
815 avoid_start = avoid_end = 0;
816#ifdef CONFIG_BLK_DEV_INITRD
817 avoid_start = initrd_start;
818 avoid_end = PAGE_ALIGN(initrd_end);
819#endif
820
821 /* Trim some pavail[] entries in order to satisfy the
822 * requested "mem=xxx" kernel command line specification.
823 *
824 * We must not trim off the kernel image area nor the
825 * initial ramdisk range (if any). Also, we must not trim
826 * any pavail[] entry down to zero in order to preserve
827 * the invariant that all pavail[] entries have a non-zero
828 * size which is assumed by all of the code in here.
829 */
830 for (i = 0; i < pavail_ents; i++) {
831 unsigned long start, end, kern_end;
832 unsigned long trim_low, trim_high, n;
833
834 kern_end = PAGE_ALIGN(kern_base + kern_size);
835
836 trim_low = start = pavail[i].phys_addr;
837 trim_high = end = start + pavail[i].reg_size;
838
839 if (kern_base >= start &&
840 kern_base < end) {
841 trim_low = kern_base;
842 if (kern_end >= end)
843 continue;
844 }
845 if (kern_end >= start &&
846 kern_end < end) {
847 trim_high = kern_end;
848 }
849 if (avoid_start &&
850 avoid_start >= start &&
851 avoid_start < end) {
852 if (trim_low > avoid_start)
853 trim_low = avoid_start;
854 if (avoid_end >= end)
855 continue;
856 }
857 if (avoid_end &&
858 avoid_end >= start &&
859 avoid_end < end) {
860 if (trim_high < avoid_end)
861 trim_high = avoid_end;
862 }
863
864 if (trim_high <= trim_low)
865 continue;
866
867 if (trim_low == start && trim_high == end) {
868 /* Whole chunk is available for trimming.
869 * Trim all except one page, in order to keep
870 * entry non-empty.
871 */
872 n = (end - start) - PAGE_SIZE;
873 if (n > to_trim)
874 n = to_trim;
875
876 if (n) {
877 pavail[i].phys_addr += n;
878 pavail[i].reg_size -= n;
879 to_trim -= n;
880 }
881 } else {
882 n = (trim_low - start);
883 if (n > to_trim)
884 n = to_trim;
885
886 if (n) {
887 pavail[i].phys_addr += n;
888 pavail[i].reg_size -= n;
889 to_trim -= n;
890 }
891 if (to_trim) {
892 n = end - trim_high;
893 if (n > to_trim)
894 n = to_trim;
895 if (n) {
896 pavail[i].reg_size -= n;
897 to_trim -= n;
898 }
899 }
900 }
901
902 if (!to_trim)
903 break;
904 }
905
906 /* Recalculate. */
907 *cur_size_p = 0UL;
908 for (i = 0; i < pavail_ents; i++) {
909 *end_of_phys_p = pavail[i].phys_addr +
910 pavail[i].reg_size;
911 *cur_size_p += pavail[i].reg_size;
912 }
913}
914
f1cfdb55
DM		 915/* About pages_avail, this is the value we will use to calculate
916 * the zholes_size[] argument given to free_area_init_node(). The
917 * page allocator uses this to calculate nr_kernel_pages,
918 * nr_all_pages and zone->present_pages. On NUMA it is used
919 * to calculate zone->min_unmapped_pages and zone->min_slab_pages.
920 *
921 * So this number should really be set to what the page allocator
922 * actually ends up with. This means:
923 * 1) It should include bootmem map pages, we'll release those.
924 * 2) It should not include the kernel image, except for the
925 * __init sections which we will also release.
926 * 3) It should include the initrd image, since we'll release
927 * that too.
928 */
d1112018
DM		 929static unsigned long __init bootmem_init(unsigned long *pages_avail,
930 unsigned long phys_base)
931{
932 unsigned long bootmap_size, end_pfn;
1da177e4
LT		 933 unsigned long end_of_phys_memory = 0UL;
934 unsigned long bootmap_pfn, bytes_avail, size;
935 int i;
936
937#ifdef CONFIG_DEBUG_BOOTMEM
13edad7a 938 prom_printf("bootmem_init: Scan pavail, ");
1da177e4
LT		 939#endif
940
941 bytes_avail = 0UL;
13edad7a
DM		 942 for (i = 0; i < pavail_ents; i++) {
943 end_of_phys_memory = pavail[i].phys_addr +
944 pavail[i].reg_size;
945 bytes_avail += pavail[i].reg_size;
1da177e4
LT		 946 }
947
6fc5bae7
DM		 948 /* Determine the location of the initial ramdisk before trying
949 * to honor the "mem=xxx" command line argument. We must know
950 * where the kernel image and the ramdisk image are so that we
951 * do not trim those two areas from the physical memory map.
952 */
1da177e4
LT		 953
954#ifdef CONFIG_BLK_DEV_INITRD
955 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
956 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
957 unsigned long ramdisk_image = sparc_ramdisk_image ?
958 sparc_ramdisk_image : sparc_ramdisk_image64;
715a0ecc 959 ramdisk_image -= KERNBASE;
1da177e4
LT		 960 initrd_start = ramdisk_image + phys_base;
961 initrd_end = initrd_start + sparc_ramdisk_size;
962 if (initrd_end > end_of_phys_memory) {
963 printk(KERN_CRIT "initrd extends beyond end of memory "
964 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
965 initrd_end, end_of_phys_memory);
966 initrd_start = 0;
d1112018 967 initrd_end = 0;
1da177e4
LT		 968 }
969 }
970#endif
6fc5bae7
DM		 971
972 if (cmdline_memory_size &&
973 bytes_avail > cmdline_memory_size)
974 trim_pavail(&bytes_avail,
975 &end_of_phys_memory);
976
977 *pages_avail = bytes_avail >> PAGE_SHIFT;
978
979 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
980
1da177e4
LT		 981 /* Initialize the boot-time allocator. */
982 max_pfn = max_low_pfn = end_pfn;
d1112018
DM		 983 min_low_pfn = (phys_base >> PAGE_SHIFT);
984
985 bootmap_pfn = choose_bootmap_pfn(min_low_pfn, end_pfn);
1da177e4
LT		 986
987#ifdef CONFIG_DEBUG_BOOTMEM
988 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
989 min_low_pfn, bootmap_pfn, max_low_pfn);
990#endif
d1112018 991 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn,
17b0e199 992 min_low_pfn, end_pfn);
1da177e4 993
1da177e4
LT		 994 /* Now register the available physical memory with the
995 * allocator.
996 */
13edad7a 997 for (i = 0; i < pavail_ents; i++) {
1da177e4 998#ifdef CONFIG_DEBUG_BOOTMEM
13edad7a
DM		 999 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
1000 i, pavail[i].phys_addr, pavail[i].reg_size);
1da177e4 1001#endif
13edad7a 1002 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
1da177e4
LT		 1003 }
1004
1005#ifdef CONFIG_BLK_DEV_INITRD
1006 if (initrd_start) {
1007 size = initrd_end - initrd_start;
1008
e5dd42e4 1009 /* Reserve the initrd image area. */
1da177e4
LT		 1010#ifdef CONFIG_DEBUG_BOOTMEM
1011 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
1012 initrd_start, initrd_end);
1013#endif
1014 reserve_bootmem(initrd_start, size);
1da177e4
LT		 1015
1016 initrd_start += PAGE_OFFSET;
1017 initrd_end += PAGE_OFFSET;
1018 }
1019#endif
1020 /* Reserve the kernel text/data/bss. */
1021#ifdef CONFIG_DEBUG_BOOTMEM
1022 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1023#endif
1024 reserve_bootmem(kern_base, kern_size);
1025 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1026
f1cfdb55
DM		 1027 /* Add back in the initmem pages. */
1028 size = ((unsigned long)(__init_end) & PAGE_MASK) -
1029 PAGE_ALIGN((unsigned long)__init_begin);
1030 *pages_avail += size >> PAGE_SHIFT;
1031
1da177e4
LT		 1032 /* Reserve the bootmem map. We do not account for it
1033 * in pages_avail because we will release that memory
1034 * in free_all_bootmem.
1035 */
1036 size = bootmap_size;
1037#ifdef CONFIG_DEBUG_BOOTMEM
1038 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1039 (bootmap_pfn << PAGE_SHIFT), size);
1040#endif
1041 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1da177e4 1042
d1112018
DM		 1043 for (i = 0; i < pavail_ents; i++) {
1044 unsigned long start_pfn, end_pfn;
1045
1046 start_pfn = pavail[i].phys_addr >> PAGE_SHIFT;
1047 end_pfn = (start_pfn + (pavail[i].reg_size >> PAGE_SHIFT));
1048#ifdef CONFIG_DEBUG_BOOTMEM
1049 prom_printf("memory_present(0, %lx, %lx)\n",
1050 start_pfn, end_pfn);
1051#endif
1052 memory_present(0, start_pfn, end_pfn);
1053 }
1054
1055 sparse_init();
1056
1da177e4
LT		 1057 return end_pfn;
1058}
1059
9cc3a1ac
DM		 1060static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1061static int pall_ents __initdata;
1062
56425306
DM		 1063#ifdef CONFIG_DEBUG_PAGEALLOC
1064static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
1065{
1066 unsigned long vstart = PAGE_OFFSET + pstart;
1067 unsigned long vend = PAGE_OFFSET + pend;
1068 unsigned long alloc_bytes = 0UL;
1069
1070 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
13edad7a 1071 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
56425306
DM		 1072 vstart, vend);
1073 prom_halt();
1074 }
1075
1076 while (vstart < vend) {
1077 unsigned long this_end, paddr = __pa(vstart);
1078 pgd_t *pgd = pgd_offset_k(vstart);
1079 pud_t *pud;
1080 pmd_t *pmd;
1081 pte_t *pte;
1082
1083 pud = pud_offset(pgd, vstart);
1084 if (pud_none(*pud)) {
1085 pmd_t *new;
1086
1087 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1088 alloc_bytes += PAGE_SIZE;
1089 pud_populate(&init_mm, pud, new);
1090 }
1091
1092 pmd = pmd_offset(pud, vstart);
1093 if (!pmd_present(*pmd)) {
1094 pte_t *new;
1095
1096 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1097 alloc_bytes += PAGE_SIZE;
1098 pmd_populate_kernel(&init_mm, pmd, new);
1099 }
1100
1101 pte = pte_offset_kernel(pmd, vstart);
1102 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1103 if (this_end > vend)
1104 this_end = vend;
1105
1106 while (vstart < this_end) {
1107 pte_val(*pte) = (paddr | pgprot_val(prot));
1108
1109 vstart += PAGE_SIZE;
1110 paddr += PAGE_SIZE;
1111 pte++;
1112 }
1113 }
1114
1115 return alloc_bytes;
1116}
1117
56425306 1118extern unsigned int kvmap_linear_patch[1];
9cc3a1ac
DM		 1119#endif /* CONFIG_DEBUG_PAGEALLOC */
1120
1121static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1122{
1123 const unsigned long shift_256MB = 28;
1124 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1125 const unsigned long size_256MB = (1UL << shift_256MB);
1126
1127 while (start < end) {
1128 long remains;
1129
f7c00338
DM		 1130 remains = end - start;
1131 if (remains < size_256MB)
1132 break;
1133
9cc3a1ac
DM		 1134 if (start & mask_256MB) {
1135 start = (start + size_256MB) & ~mask_256MB;
1136 continue;
1137 }
1138
9cc3a1ac
DM		 1139 while (remains >= size_256MB) {
1140 unsigned long index = start >> shift_256MB;
1141
1142 __set_bit(index, kpte_linear_bitmap);
1143
1144 start += size_256MB;
1145 remains -= size_256MB;
1146 }
1147 }
1148}
56425306
DM		 1149
1150static void __init kernel_physical_mapping_init(void)
1151{
9cc3a1ac
DM		 1152 unsigned long i;
1153#ifdef CONFIG_DEBUG_PAGEALLOC
1154 unsigned long mem_alloced = 0UL;
1155#endif
56425306 1156
13edad7a
DM		 1157 read_obp_memory("reg", &pall[0], &pall_ents);
1158
1159 for (i = 0; i < pall_ents; i++) {
56425306
DM		 1160 unsigned long phys_start, phys_end;
1161
13edad7a
DM		 1162 phys_start = pall[i].phys_addr;
1163 phys_end = phys_start + pall[i].reg_size;
9cc3a1ac
DM		 1164
1165 mark_kpte_bitmap(phys_start, phys_end);
1166
1167#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1168 mem_alloced += kernel_map_range(phys_start, phys_end,
1169 PAGE_KERNEL);
9cc3a1ac 1170#endif
56425306
DM		 1171 }
1172
9cc3a1ac 1173#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1174 printk("Allocated %ld bytes for kernel page tables.\n",
1175 mem_alloced);
1176
1177 kvmap_linear_patch[0] = 0x01000000; /* nop */
1178 flushi(&kvmap_linear_patch[0]);
1179
1180 __flush_tlb_all();
9cc3a1ac 1181#endif
56425306
DM		 1182}
1183
9cc3a1ac 1184#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1185void kernel_map_pages(struct page *page, int numpages, int enable)
1186{
1187 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1188 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1189
1190 kernel_map_range(phys_start, phys_end,
1191 (enable ? PAGE_KERNEL : __pgprot(0)));
1192
74bf4312
DM		 1193 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1194 PAGE_OFFSET + phys_end);
1195
56425306
DM		 1196 /* we should perform an IPI and flush all tlbs,
1197 * but that can deadlock->flush only current cpu.
1198 */
1199 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1200 PAGE_OFFSET + phys_end);
1201}
1202#endif
1203
10147570
DM		 1204unsigned long __init find_ecache_flush_span(unsigned long size)
1205{
0836a0eb
DM		 1206 int i;
1207
13edad7a
DM		 1208 for (i = 0; i < pavail_ents; i++) {
1209 if (pavail[i].reg_size >= size)
1210 return pavail[i].phys_addr;
0836a0eb
DM		 1211 }
1212
13edad7a 1213 return ~0UL;
0836a0eb
DM		 1214}
1215
517af332
DM		 1216static void __init tsb_phys_patch(void)
1217{
d257d5da 1218 struct tsb_ldquad_phys_patch_entry *pquad;
517af332
DM		 1219 struct tsb_phys_patch_entry *p;
1220
d257d5da
DM		 1221 pquad = &__tsb_ldquad_phys_patch;
1222 while (pquad < &__tsb_ldquad_phys_patch_end) {
1223 unsigned long addr = pquad->addr;
1224
1225 if (tlb_type == hypervisor)
1226 *(unsigned int *) addr = pquad->sun4v_insn;
1227 else
1228 *(unsigned int *) addr = pquad->sun4u_insn;
1229 wmb();
1230 __asm__ __volatile__("flush %0"
1231 : /* no outputs */
1232 : "r" (addr));
1233
1234 pquad++;
1235 }
1236
517af332
DM		 1237 p = &__tsb_phys_patch;
1238 while (p < &__tsb_phys_patch_end) {
1239 unsigned long addr = p->addr;
1240
1241 *(unsigned int *) addr = p->insn;
1242 wmb();
1243 __asm__ __volatile__("flush %0"
1244 : /* no outputs */
1245 : "r" (addr));
1246
1247 p++;
1248 }
1249}
1250
490384e7 1251/* Don't mark as init, we give this to the Hypervisor. */
d1acb421
DM		 1252#ifndef CONFIG_DEBUG_PAGEALLOC
1253#define NUM_KTSB_DESCR 2
1254#else
1255#define NUM_KTSB_DESCR 1
1256#endif
1257static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
490384e7
DM		 1258extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1259
1260static void __init sun4v_ktsb_init(void)
1261{
1262 unsigned long ktsb_pa;
1263
d7744a09 1264 /* First KTSB for PAGE_SIZE mappings. */
490384e7
DM		 1265 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1266
1267 switch (PAGE_SIZE) {
1268 case 8 * 1024:
1269 default:
1270 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1271 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1272 break;
1273
1274 case 64 * 1024:
1275 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1276 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1277 break;
1278
1279 case 512 * 1024:
1280 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1281 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1282 break;
1283
1284 case 4 * 1024 * 1024:
1285 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1286 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1287 break;
1288 };
1289
3f19a84e 1290 ktsb_descr[0].assoc = 1;
490384e7
DM		 1291 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1292 ktsb_descr[0].ctx_idx = 0;
1293 ktsb_descr[0].tsb_base = ktsb_pa;
1294 ktsb_descr[0].resv = 0;
1295
d1acb421 1296#ifndef CONFIG_DEBUG_PAGEALLOC
d7744a09
DM		 1297 /* Second KTSB for 4MB/256MB mappings. */
1298 ktsb_pa = (kern_base +
1299 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1300
1301 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1302 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1303 HV_PGSZ_MASK_256MB);
1304 ktsb_descr[1].assoc = 1;
1305 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1306 ktsb_descr[1].ctx_idx = 0;
1307 ktsb_descr[1].tsb_base = ktsb_pa;
1308 ktsb_descr[1].resv = 0;
d1acb421 1309#endif
490384e7
DM		 1310}
1311
1312void __cpuinit sun4v_ktsb_register(void)
1313{
1314 register unsigned long func asm("%o5");
1315 register unsigned long arg0 asm("%o0");
1316 register unsigned long arg1 asm("%o1");
1317 unsigned long pa;
1318
1319 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1320
1321 func = HV_FAST_MMU_TSB_CTX0;
d1acb421 1322 arg0 = NUM_KTSB_DESCR;
490384e7
DM		 1323 arg1 = pa;
1324 __asm__ __volatile__("ta %6"
1325 : "=&r" (func), "=&r" (arg0), "=&r" (arg1)
1326 : "0" (func), "1" (arg0), "2" (arg1),
1327 "i" (HV_FAST_TRAP));
1328}
1329
1da177e4
LT		 1330/* paging_init() sets up the page tables */
1331
1332extern void cheetah_ecache_flush_init(void);
d257d5da 1333extern void sun4v_patch_tlb_handlers(void);
1da177e4 1334
5cbc3073
DM		 1335extern void cpu_probe(void);
1336extern void central_probe(void);
1337
1da177e4 1338static unsigned long last_valid_pfn;
56425306 1339pgd_t swapper_pg_dir[2048];
1da177e4 1340
c4bce90e
DM		 1341static void sun4u_pgprot_init(void);
1342static void sun4v_pgprot_init(void);
1343
1da177e4
LT		 1344void __init paging_init(void)
1345{
d1112018 1346 unsigned long end_pfn, pages_avail, shift, phys_base;
0836a0eb
DM		 1347 unsigned long real_end, i;
1348
22adb358
DM		 1349 /* These build time checkes make sure that the dcache_dirty_cpu()
1350 * page->flags usage will work.
1351 *
1352 * When a page gets marked as dcache-dirty, we store the
1353 * cpu number starting at bit 32 in the page->flags. Also,
1354 * functions like clear_dcache_dirty_cpu use the cpu mask
1355 * in 13-bit signed-immediate instruction fields.
1356 */
1357 BUILD_BUG_ON(FLAGS_RESERVED != 32);
1358 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1359 ilog2(roundup_pow_of_two(NR_CPUS)) > FLAGS_RESERVED);
1360 BUILD_BUG_ON(NR_CPUS > 4096);
1361
481295f9
DM		 1362 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1363 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1364
22d6a1cb
DM		 1365 sstate_booting();
1366
d7744a09 1367 /* Invalidate both kernel TSBs. */
8b234274 1368 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
d1acb421 1369#ifndef CONFIG_DEBUG_PAGEALLOC
d7744a09 1370 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
d1acb421 1371#endif
8b234274 1372
c4bce90e
DM		 1373 if (tlb_type == hypervisor)
1374 sun4v_pgprot_init();
1375 else
1376 sun4u_pgprot_init();
1377
d257d5da
DM		 1378 if (tlb_type == cheetah_plus ||
1379 tlb_type == hypervisor)
517af332
DM		 1380 tsb_phys_patch();
1381
490384e7 1382 if (tlb_type == hypervisor) {
d257d5da 1383 sun4v_patch_tlb_handlers();
490384e7
DM		 1384 sun4v_ktsb_init();
1385 }
d257d5da 1386
13edad7a
DM		 1387 /* Find available physical memory... */
1388 read_obp_memory("available", &pavail[0], &pavail_ents);
0836a0eb
DM		 1389
1390 phys_base = 0xffffffffffffffffUL;
13edad7a
DM		 1391 for (i = 0; i < pavail_ents; i++)
1392 phys_base = min(phys_base, pavail[i].phys_addr);
0836a0eb 1393
1da177e4
LT		 1394 set_bit(0, mmu_context_bmap);
1395
2bdb3cb2
DM		 1396 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1397
1da177e4
LT		 1398 real_end = (unsigned long)_end;
1399 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1400 bigkernel = 1;
2bdb3cb2
DM		 1401 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1402 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1403 prom_halt();
1da177e4 1404 }
2bdb3cb2
DM		 1405
1406 /* Set kernel pgd to upper alias so physical page computations
1da177e4
LT		 1407 * work.
1408 */
1409 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1410
56425306 1411 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1da177e4
LT		 1412
1413 /* Now can init the kernel/bad page tables. */
1414 pud_set(pud_offset(&swapper_pg_dir[0], 0),
56425306 1415 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1da177e4 1416
c9c10830 1417 inherit_prom_mappings();
5085b4a5 1418
a8b900d8
DM		 1419 /* Ok, we can use our TLB miss and window trap handlers safely. */
1420 setup_tba();
1da177e4 1421
c9c10830 1422 __flush_tlb_all();
9ad98c5b 1423
490384e7
DM		 1424 if (tlb_type == hypervisor)
1425 sun4v_ktsb_register();
1426
2bdb3cb2
DM		 1427 /* Setup bootmem... */
1428 pages_avail = 0;
d1112018
DM		 1429 last_valid_pfn = end_pfn = bootmem_init(&pages_avail, phys_base);
1430
17b0e199 1431 max_mapnr = last_valid_pfn;
2bdb3cb2 1432
56425306 1433 kernel_physical_mapping_init();
56425306 1434
5cbc3073
DM		 1435 real_setup_per_cpu_areas();
1436
372b07bb
DM		 1437 prom_build_devicetree();
1438
5cbc3073
DM		 1439 if (tlb_type == hypervisor)
1440 sun4v_mdesc_init();
1441
1da177e4
LT		 1442 {
1443 unsigned long zones_size[MAX_NR_ZONES];
1444 unsigned long zholes_size[MAX_NR_ZONES];
1da177e4
LT		 1445 int znum;
1446
1447 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1448 zones_size[znum] = zholes_size[znum] = 0;
1449
1b51d3a0
DM		 1450 zones_size[ZONE_NORMAL] = end_pfn;
1451 zholes_size[ZONE_NORMAL] = end_pfn - pages_avail;
1da177e4
LT		 1452
1453 free_area_init_node(0, &contig_page_data, zones_size,
17b0e199
DM		 1454 __pa(PAGE_OFFSET) >> PAGE_SHIFT,
1455 zholes_size);
1da177e4
LT		 1456 }
1457
5cbc3073
DM		 1458 prom_printf("Booting Linux...\n");
1459
1460 central_probe();
1461 cpu_probe();
1da177e4
LT		 1462}
1463
1da177e4
LT		 1464static void __init taint_real_pages(void)
1465{
1da177e4
LT		 1466 int i;
1467
13edad7a 1468 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1da177e4 1469
13edad7a 1470 /* Find changes discovered in the physmem available rescan and
1da177e4
LT		 1471 * reserve the lost portions in the bootmem maps.
1472 */
13edad7a 1473 for (i = 0; i < pavail_ents; i++) {
1da177e4
LT		 1474 unsigned long old_start, old_end;
1475
13edad7a 1476 old_start = pavail[i].phys_addr;
1da177e4 1477 old_end = old_start +
13edad7a 1478 pavail[i].reg_size;
1da177e4
LT		 1479 while (old_start < old_end) {
1480 int n;
1481
c2a5a46b 1482 for (n = 0; n < pavail_rescan_ents; n++) {
1da177e4
LT		 1483 unsigned long new_start, new_end;
1484
13edad7a
DM		 1485 new_start = pavail_rescan[n].phys_addr;
1486 new_end = new_start +
1487 pavail_rescan[n].reg_size;
1da177e4
LT		 1488
1489 if (new_start <= old_start &&
1490 new_end >= (old_start + PAGE_SIZE)) {
13edad7a
DM		 1491 set_bit(old_start >> 22,
1492 sparc64_valid_addr_bitmap);
1da177e4
LT		 1493 goto do_next_page;
1494 }
1495 }
1496 reserve_bootmem(old_start, PAGE_SIZE);
1497
1498 do_next_page:
1499 old_start += PAGE_SIZE;
1500 }
1501 }
1502}
1503
c2a5a46b
DM		 1504int __init page_in_phys_avail(unsigned long paddr)
1505{
1506 int i;
1507
1508 paddr &= PAGE_MASK;
1509
1510 for (i = 0; i < pavail_rescan_ents; i++) {
1511 unsigned long start, end;
1512
1513 start = pavail_rescan[i].phys_addr;
1514 end = start + pavail_rescan[i].reg_size;
1515
1516 if (paddr >= start && paddr < end)
1517 return 1;
1518 }
1519 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1520 return 1;
1521#ifdef CONFIG_BLK_DEV_INITRD
1522 if (paddr >= __pa(initrd_start) &&
1523 paddr < __pa(PAGE_ALIGN(initrd_end)))
1524 return 1;
1525#endif
1526
1527 return 0;
1528}
1529
1da177e4
LT		 1530void __init mem_init(void)
1531{
1532 unsigned long codepages, datapages, initpages;
1533 unsigned long addr, last;
1534 int i;
1535
1536 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1537 i += 1;
2bdb3cb2 1538 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1da177e4
LT		 1539 if (sparc64_valid_addr_bitmap == NULL) {
1540 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1541 prom_halt();
1542 }
1543 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1544
1545 addr = PAGE_OFFSET + kern_base;
1546 last = PAGE_ALIGN(kern_size) + addr;
1547 while (addr < last) {
1548 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1549 addr += PAGE_SIZE;
1550 }
1551
1552 taint_real_pages();
1553
1da177e4
LT		 1554 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1555
1556#ifdef CONFIG_DEBUG_BOOTMEM
1557 prom_printf("mem_init: Calling free_all_bootmem().\n");
1558#endif
f1cfdb55
DM		 1559
1560 /* We subtract one to account for the mem_map_zero page
1561 * allocated below.
1562 */
1da177e4
LT		 1563 totalram_pages = num_physpages = free_all_bootmem() - 1;
1564
1565 /*
1566 * Set up the zero page, mark it reserved, so that page count
1567 * is not manipulated when freeing the page from user ptes.
1568 */
1569 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1570 if (mem_map_zero == NULL) {
1571 prom_printf("paging_init: Cannot alloc zero page.\n");
1572 prom_halt();
1573 }
1574 SetPageReserved(mem_map_zero);
1575
1576 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1577 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1578 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1579 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1580 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1581 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1582
96177299 1583 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1da177e4
LT		 1584 nr_free_pages() << (PAGE_SHIFT-10),
1585 codepages << (PAGE_SHIFT-10),
1586 datapages << (PAGE_SHIFT-10),
1587 initpages << (PAGE_SHIFT-10),
1588 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1589
1590 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1591 cheetah_ecache_flush_init();
1592}
1593
898cf0ec 1594void free_initmem(void)
1da177e4
LT		 1595{
1596 unsigned long addr, initend;
1597
1598 /*
1599 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1600 */
1601 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1602 initend = (unsigned long)(__init_end) & PAGE_MASK;
1603 for (; addr < initend; addr += PAGE_SIZE) {
1604 unsigned long page;
1605 struct page *p;
1606
1607 page = (addr +
1608 ((unsigned long) __va(kern_base)) -
1609 ((unsigned long) KERNBASE));
c9cf5528 1610 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1da177e4
LT		 1611 p = virt_to_page(page);
1612
1613 ClearPageReserved(p);
7835e98b 1614 init_page_count(p);
1da177e4
LT		 1615 __free_page(p);
1616 num_physpages++;
1617 totalram_pages++;
1618 }
1619}
1620
1621#ifdef CONFIG_BLK_DEV_INITRD
1622void free_initrd_mem(unsigned long start, unsigned long end)
1623{
1624 if (start < end)
1625 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1626 for (; start < end; start += PAGE_SIZE) {
1627 struct page *p = virt_to_page(start);
1628
1629 ClearPageReserved(p);
7835e98b 1630 init_page_count(p);
1da177e4
LT		 1631 __free_page(p);
1632 num_physpages++;
1633 totalram_pages++;
1634 }
1635}
1636#endif
c4bce90e 1637
c4bce90e
DM		 1638#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1639#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1640#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1641#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1642#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1643#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1644
1645pgprot_t PAGE_KERNEL __read_mostly;
1646EXPORT_SYMBOL(PAGE_KERNEL);
1647
1648pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1649pgprot_t PAGE_COPY __read_mostly;
0f15952a
DM		 1650
1651pgprot_t PAGE_SHARED __read_mostly;
1652EXPORT_SYMBOL(PAGE_SHARED);
1653
c4bce90e
DM		 1654pgprot_t PAGE_EXEC __read_mostly;
1655unsigned long pg_iobits __read_mostly;
1656
1657unsigned long _PAGE_IE __read_mostly;
987c74fc 1658EXPORT_SYMBOL(_PAGE_IE);
b2bef442 1659
c4bce90e 1660unsigned long _PAGE_E __read_mostly;
b2bef442
DM		 1661EXPORT_SYMBOL(_PAGE_E);
1662
c4bce90e 1663unsigned long _PAGE_CACHE __read_mostly;
b2bef442 1664EXPORT_SYMBOL(_PAGE_CACHE);
c4bce90e
DM		 1665
1666static void prot_init_common(unsigned long page_none,
1667 unsigned long page_shared,
1668 unsigned long page_copy,
1669 unsigned long page_readonly,
1670 unsigned long page_exec_bit)
1671{
1672 PAGE_COPY = __pgprot(page_copy);
0f15952a 1673 PAGE_SHARED = __pgprot(page_shared);
c4bce90e
DM		 1674
1675 protection_map[0x0] = __pgprot(page_none);
1676 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1677 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1678 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1679 protection_map[0x4] = __pgprot(page_readonly);
1680 protection_map[0x5] = __pgprot(page_readonly);
1681 protection_map[0x6] = __pgprot(page_copy);
1682 protection_map[0x7] = __pgprot(page_copy);
1683 protection_map[0x8] = __pgprot(page_none);
1684 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1685 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1686 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1687 protection_map[0xc] = __pgprot(page_readonly);
1688 protection_map[0xd] = __pgprot(page_readonly);
1689 protection_map[0xe] = __pgprot(page_shared);
1690 protection_map[0xf] = __pgprot(page_shared);
1691}
1692
1693static void __init sun4u_pgprot_init(void)
1694{
1695 unsigned long page_none, page_shared, page_copy, page_readonly;
1696 unsigned long page_exec_bit;
1697
1698 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1699 _PAGE_CACHE_4U | _PAGE_P_4U |
1700 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1701 _PAGE_EXEC_4U);
1702 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1703 _PAGE_CACHE_4U | _PAGE_P_4U |
1704 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1705 _PAGE_EXEC_4U | _PAGE_L_4U);
1706 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1707
1708 _PAGE_IE = _PAGE_IE_4U;
1709 _PAGE_E = _PAGE_E_4U;
1710 _PAGE_CACHE = _PAGE_CACHE_4U;
1711
1712 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1713 __ACCESS_BITS_4U | _PAGE_E_4U);
1714
d1acb421
DM		 1715#ifdef CONFIG_DEBUG_PAGEALLOC
1716 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
1717 0xfffff80000000000;
1718#else
9cc3a1ac 1719 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
c4bce90e 1720 0xfffff80000000000;
d1acb421 1721#endif
9cc3a1ac
DM		 1722 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1723 _PAGE_P_4U | _PAGE_W_4U);
1724
1725 /* XXX Should use 256MB on Panther. XXX */
1726 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
c4bce90e
DM		 1727
1728 _PAGE_SZBITS = _PAGE_SZBITS_4U;
1729 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1730 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1731 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1732
1733
1734 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1735 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1736 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1737 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1738 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1739 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1740 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1741
1742 page_exec_bit = _PAGE_EXEC_4U;
1743
1744 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1745 page_exec_bit);
1746}
1747
1748static void __init sun4v_pgprot_init(void)
1749{
1750 unsigned long page_none, page_shared, page_copy, page_readonly;
1751 unsigned long page_exec_bit;
1752
1753 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1754 _PAGE_CACHE_4V | _PAGE_P_4V |
1755 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1756 _PAGE_EXEC_4V);
1757 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1758 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1759
1760 _PAGE_IE = _PAGE_IE_4V;
1761 _PAGE_E = _PAGE_E_4V;
1762 _PAGE_CACHE = _PAGE_CACHE_4V;
1763
d1acb421
DM		 1764#ifdef CONFIG_DEBUG_PAGEALLOC
1765 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1766 0xfffff80000000000;
1767#else
9cc3a1ac
DM		 1768 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1769 0xfffff80000000000;
d1acb421 1770#endif
9cc3a1ac
DM		 1771 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1772 _PAGE_P_4V | _PAGE_W_4V);
1773
d1acb421
DM		 1774#ifdef CONFIG_DEBUG_PAGEALLOC
1775 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1776 0xfffff80000000000;
1777#else
9cc3a1ac 1778 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
c4bce90e 1779 0xfffff80000000000;
d1acb421 1780#endif
9cc3a1ac
DM		 1781 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1782 _PAGE_P_4V | _PAGE_W_4V);
c4bce90e
DM		 1783
1784 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1785 __ACCESS_BITS_4V | _PAGE_E_4V);
1786
1787 _PAGE_SZBITS = _PAGE_SZBITS_4V;
1788 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1789 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1790 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1791 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1792
1793 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1794 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1795 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1796 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1797 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1798 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1799 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1800
1801 page_exec_bit = _PAGE_EXEC_4V;
1802
1803 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1804 page_exec_bit);
1805}
1806
1807unsigned long pte_sz_bits(unsigned long sz)
1808{
1809 if (tlb_type == hypervisor) {
1810 switch (sz) {
1811 case 8 * 1024:
1812 default:
1813 return _PAGE_SZ8K_4V;
1814 case 64 * 1024:
1815 return _PAGE_SZ64K_4V;
1816 case 512 * 1024:
1817 return _PAGE_SZ512K_4V;
1818 case 4 * 1024 * 1024:
1819 return _PAGE_SZ4MB_4V;
1820 };
1821 } else {
1822 switch (sz) {
1823 case 8 * 1024:
1824 default:
1825 return _PAGE_SZ8K_4U;
1826 case 64 * 1024:
1827 return _PAGE_SZ64K_4U;
1828 case 512 * 1024:
1829 return _PAGE_SZ512K_4U;
1830 case 4 * 1024 * 1024:
1831 return _PAGE_SZ4MB_4U;
1832 };
1833 }
1834}
1835
1836pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1837{
1838 pte_t pte;
cf627156
DM		 1839
1840 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
c4bce90e
DM		 1841 pte_val(pte) |= (((unsigned long)space) << 32);
1842 pte_val(pte) |= pte_sz_bits(page_size);
c4bce90e 1843
cf627156 1844 return pte;
c4bce90e
DM		 1845}
1846
1847static unsigned long kern_large_tte(unsigned long paddr)
1848{
1849 unsigned long val;
1850
1851 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1852 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1853 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1854 if (tlb_type == hypervisor)
1855 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1856 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1857 _PAGE_EXEC_4V | _PAGE_W_4V);
1858
1859 return val | paddr;
1860}
1861
c4bce90e
DM		 1862/* If not locked, zap it. */
1863void __flush_tlb_all(void)
1864{
1865 unsigned long pstate;
1866 int i;
1867
1868 __asm__ __volatile__("flushw\n\t"
1869 "rdpr %%pstate, %0\n\t"
1870 "wrpr %0, %1, %%pstate"
1871 : "=r" (pstate)
1872 : "i" (PSTATE_IE));
1873 if (tlb_type == spitfire) {
1874 for (i = 0; i < 64; i++) {
1875 /* Spitfire Errata #32 workaround */
1876 /* NOTE: Always runs on spitfire, so no
1877 * cheetah+ page size encodings.
1878 */
1879 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1880 "flush %%g6"
1881 : /* No outputs */
1882 : "r" (0),
1883 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1884
1885 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1886 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1887 "membar #Sync"
1888 : /* no outputs */
1889 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1890 spitfire_put_dtlb_data(i, 0x0UL);
1891 }
1892
1893 /* Spitfire Errata #32 workaround */
1894 /* NOTE: Always runs on spitfire, so no
1895 * cheetah+ page size encodings.
1896 */
1897 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1898 "flush %%g6"
1899 : /* No outputs */
1900 : "r" (0),
1901 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1902
1903 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1904 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1905 "membar #Sync"
1906 : /* no outputs */
1907 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1908 spitfire_put_itlb_data(i, 0x0UL);
1909 }
1910 }
1911 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1912 cheetah_flush_dtlb_all();
1913 cheetah_flush_itlb_all();
1914 }
1915 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1916 : : "r" (pstate));
1917}
88d70794
DM		 1918
1919#ifdef CONFIG_MEMORY_HOTPLUG
1920
1921void online_page(struct page *page)
1922{
1923 ClearPageReserved(page);
fcab1e51
NP		 1924 init_page_count(page);
1925 __free_page(page);
88d70794
DM		 1926 totalram_pages++;
1927 num_physpages++;
1928}
1929
1930int remove_memory(u64 start, u64 size)
1931{
1932 return -EINVAL;
1933}
1934
1935#endif /* CONFIG_MEMORY_HOTPLUG */
kernel source for telekom puls (alcatel/mediatek)