projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[SPARC64]: Initialize LMB tables.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / sparc64 / mm / init.c
CommitLineData
1da177e4
LT		 1/* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
c4bce90e 8#include <linux/module.h>
1da177e4
LT		 9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/string.h>
12#include <linux/init.h>
13#include <linux/bootmem.h>
14#include <linux/mm.h>
15#include <linux/hugetlb.h>
16#include <linux/slab.h>
17#include <linux/initrd.h>
18#include <linux/swap.h>
19#include <linux/pagemap.h>
c9cf5528 20#include <linux/poison.h>
1da177e4
LT		 21#include <linux/fs.h>
22#include <linux/seq_file.h>
05e14cb3 23#include <linux/kprobes.h>
1ac4f5eb 24#include <linux/cache.h>
13edad7a 25#include <linux/sort.h>
5cbc3073 26#include <linux/percpu.h>
3b2a7e23 27#include <linux/lmb.h>
1da177e4
LT		 28
29#include <asm/head.h>
30#include <asm/system.h>
31#include <asm/page.h>
32#include <asm/pgalloc.h>
33#include <asm/pgtable.h>
34#include <asm/oplib.h>
35#include <asm/iommu.h>
36#include <asm/io.h>
37#include <asm/uaccess.h>
38#include <asm/mmu_context.h>
39#include <asm/tlbflush.h>
40#include <asm/dma.h>
41#include <asm/starfire.h>
42#include <asm/tlb.h>
43#include <asm/spitfire.h>
44#include <asm/sections.h>
517af332 45#include <asm/tsb.h>
481295f9 46#include <asm/hypervisor.h>
372b07bb 47#include <asm/prom.h>
22d6a1cb 48#include <asm/sstate.h>
5cbc3073 49#include <asm/mdesc.h>
3d5ae6b6 50#include <asm/cpudata.h>
1da177e4 51
9cc3a1ac
DM		 52#define MAX_PHYS_ADDRESS (1UL << 42UL)
53#define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
54#define KPTE_BITMAP_BYTES \
55 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
56
57unsigned long kern_linear_pte_xor[2] __read_mostly;
58
59/* A bitmap, one bit for every 256MB of physical memory. If the bit
60 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
61 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
62 */
63unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
64
d1acb421 65#ifndef CONFIG_DEBUG_PAGEALLOC
2d9e2763
DM		 66/* A special kernel TSB for 4MB and 256MB linear mappings.
67 * Space is allocated for this right after the trap table
68 * in arch/sparc64/kernel/head.S
69 */
70extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
d1acb421 71#endif
d7744a09 72
13edad7a
DM		 73#define MAX_BANKS 32
74
75static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
76static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
77static int pavail_ents __initdata;
78static int pavail_rescan_ents __initdata;
79
80static int cmp_p64(const void *a, const void *b)
81{
82 const struct linux_prom64_registers *x = a, *y = b;
83
84 if (x->phys_addr > y->phys_addr)
85 return 1;
86 if (x->phys_addr < y->phys_addr)
87 return -1;
88 return 0;
89}
90
91static void __init read_obp_memory(const char *property,
92 struct linux_prom64_registers *regs,
93 int *num_ents)
94{
95 int node = prom_finddevice("/memory");
96 int prop_size = prom_getproplen(node, property);
97 int ents, ret, i;
98
99 ents = prop_size / sizeof(struct linux_prom64_registers);
100 if (ents > MAX_BANKS) {
101 prom_printf("The machine has more %s property entries than "
102 "this kernel can support (%d).\n",
103 property, MAX_BANKS);
104 prom_halt();
105 }
106
107 ret = prom_getproperty(node, property, (char *) regs, prop_size);
108 if (ret == -1) {
109 prom_printf("Couldn't get %s property from /memory.\n");
110 prom_halt();
111 }
112
13edad7a
DM		 113 /* Sanitize what we got from the firmware, by page aligning
114 * everything.
115 */
116 for (i = 0; i < ents; i++) {
117 unsigned long base, size;
118
119 base = regs[i].phys_addr;
120 size = regs[i].reg_size;
10147570 121
13edad7a
DM		 122 size &= PAGE_MASK;
123 if (base & ~PAGE_MASK) {
124 unsigned long new_base = PAGE_ALIGN(base);
125
126 size -= new_base - base;
127 if ((long) size < 0L)
128 size = 0UL;
129 base = new_base;
130 }
0015d3d6
DM		 131 if (size == 0UL) {
132 /* If it is empty, simply get rid of it.
133 * This simplifies the logic of the other
134 * functions that process these arrays.
135 */
136 memmove(&regs[i], &regs[i + 1],
137 (ents - i - 1) * sizeof(regs[0]));
486ad10a 138 i--;
0015d3d6
DM		 139 ents--;
140 continue;
486ad10a 141 }
0015d3d6
DM		 142 regs[i].phys_addr = base;
143 regs[i].reg_size = size;
486ad10a
DM		 144 }
145
146 *num_ents = ents;
147
c9c10830 148 sort(regs, ents, sizeof(struct linux_prom64_registers),
13edad7a
DM		 149 cmp_p64, NULL);
150}
1da177e4 151
2bdb3cb2 152unsigned long *sparc64_valid_addr_bitmap __read_mostly;
1da177e4 153
d1112018 154/* Kernel physical address base and size in bytes. */
1ac4f5eb
DM		 155unsigned long kern_base __read_mostly;
156unsigned long kern_size __read_mostly;
1da177e4 157
1da177e4
LT		 158/* Initial ramdisk setup */
159extern unsigned long sparc_ramdisk_image64;
160extern unsigned int sparc_ramdisk_image;
161extern unsigned int sparc_ramdisk_size;
162
1ac4f5eb 163struct page *mem_map_zero __read_mostly;
1da177e4 164
0835ae0f
DM		 165unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
166
167unsigned long sparc64_kern_pri_context __read_mostly;
168unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
169unsigned long sparc64_kern_sec_context __read_mostly;
170
64658743 171int num_kernel_image_mappings;
1da177e4 172
1da177e4
LT		 173#ifdef CONFIG_DEBUG_DCFLUSH
174atomic_t dcpage_flushes = ATOMIC_INIT(0);
175#ifdef CONFIG_SMP
176atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
177#endif
178#endif
179
7a591cfe 180inline void flush_dcache_page_impl(struct page *page)
1da177e4 181{
7a591cfe 182 BUG_ON(tlb_type == hypervisor);
1da177e4
LT		 183#ifdef CONFIG_DEBUG_DCFLUSH
184 atomic_inc(&dcpage_flushes);
185#endif
186
187#ifdef DCACHE_ALIASING_POSSIBLE
188 __flush_dcache_page(page_address(page),
189 ((tlb_type == spitfire) &&
190 page_mapping(page) != NULL));
191#else
192 if (page_mapping(page) != NULL &&
193 tlb_type == spitfire)
194 __flush_icache_page(__pa(page_address(page)));
195#endif
196}
197
198#define PG_dcache_dirty PG_arch_1
22adb358
DM		 199#define PG_dcache_cpu_shift 32UL
200#define PG_dcache_cpu_mask \
201 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
1da177e4
LT		 202
203#define dcache_dirty_cpu(page) \
48b0e548 204 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
1da177e4 205
d979f179 206static inline void set_dcache_dirty(struct page *page, int this_cpu)
1da177e4
LT		 207{
208 unsigned long mask = this_cpu;
48b0e548
DM		 209 unsigned long non_cpu_bits;
210
211 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
212 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
213
1da177e4
LT		 214 __asm__ __volatile__("1:\n\t"
215 "ldx [%2], %%g7\n\t"
216 "and %%g7, %1, %%g1\n\t"
217 "or %%g1, %0, %%g1\n\t"
218 "casx [%2], %%g7, %%g1\n\t"
219 "cmp %%g7, %%g1\n\t"
b445e26c 220 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 221 "bne,pn %%xcc, 1b\n\t"
b445e26c 222 " nop"
1da177e4
LT		 223 : /* no outputs */
224 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
225 : "g1", "g7");
226}
227
d979f179 228static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
1da177e4
LT		 229{
230 unsigned long mask = (1UL << PG_dcache_dirty);
231
232 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
233 "1:\n\t"
234 "ldx [%2], %%g7\n\t"
48b0e548 235 "srlx %%g7, %4, %%g1\n\t"
1da177e4
LT		 236 "and %%g1, %3, %%g1\n\t"
237 "cmp %%g1, %0\n\t"
238 "bne,pn %%icc, 2f\n\t"
239 " andn %%g7, %1, %%g1\n\t"
240 "casx [%2], %%g7, %%g1\n\t"
241 "cmp %%g7, %%g1\n\t"
b445e26c 242 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 243 "bne,pn %%xcc, 1b\n\t"
b445e26c 244 " nop\n"
1da177e4
LT		 245 "2:"
246 : /* no outputs */
247 : "r" (cpu), "r" (mask), "r" (&page->flags),
48b0e548
DM		 248 "i" (PG_dcache_cpu_mask),
249 "i" (PG_dcache_cpu_shift)
1da177e4
LT		 250 : "g1", "g7");
251}
252
517af332
DM		 253static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
254{
255 unsigned long tsb_addr = (unsigned long) ent;
256
3b3ab2eb 257 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
517af332
DM		 258 tsb_addr = __pa(tsb_addr);
259
260 __tsb_insert(tsb_addr, tag, pte);
261}
262
c4bce90e
DM		 263unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
264unsigned long _PAGE_SZBITS __read_mostly;
265
1da177e4
LT		 266void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
267{
bd40791e 268 struct mm_struct *mm;
74ae9987 269 struct tsb *tsb;
7a1ac526 270 unsigned long tag, flags;
dcc1e8dd 271 unsigned long tsb_index, tsb_hash_shift;
7a591cfe
DM		 272
273 if (tlb_type != hypervisor) {
274 unsigned long pfn = pte_pfn(pte);
275 unsigned long pg_flags;
276 struct page *page;
277
278 if (pfn_valid(pfn) &&
279 (page = pfn_to_page(pfn), page_mapping(page)) &&
280 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
281 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
282 PG_dcache_cpu_mask);
283 int this_cpu = get_cpu();
284
285 /* This is just to optimize away some function calls
286 * in the SMP case.
287 */
288 if (cpu == this_cpu)
289 flush_dcache_page_impl(page);
290 else
291 smp_flush_dcache_page_impl(page, cpu);
292
293 clear_dcache_dirty_cpu(page, cpu);
294
295 put_cpu();
296 }
1da177e4 297 }
bd40791e
DM		 298
299 mm = vma->vm_mm;
7a1ac526 300
dcc1e8dd
DM		 301 tsb_index = MM_TSB_BASE;
302 tsb_hash_shift = PAGE_SHIFT;
303
7a1ac526
DM		 304 spin_lock_irqsave(&mm->context.lock, flags);
305
dcc1e8dd
DM		 306#ifdef CONFIG_HUGETLB_PAGE
307 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
308 if ((tlb_type == hypervisor &&
309 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
310 (tlb_type != hypervisor &&
311 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
312 tsb_index = MM_TSB_HUGE;
313 tsb_hash_shift = HPAGE_SHIFT;
314 }
315 }
316#endif
317
318 tsb = mm->context.tsb_block[tsb_index].tsb;
319 tsb += ((address >> tsb_hash_shift) &
320 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
74ae9987
DM		 321 tag = (address >> 22UL);
322 tsb_insert(tsb, tag, pte_val(pte));
7a1ac526
DM		 323
324 spin_unlock_irqrestore(&mm->context.lock, flags);
1da177e4
LT		 325}
326
327void flush_dcache_page(struct page *page)
328{
a9546f59
DM		 329 struct address_space *mapping;
330 int this_cpu;
1da177e4 331
7a591cfe
DM		 332 if (tlb_type == hypervisor)
333 return;
334
a9546f59
DM		 335 /* Do not bother with the expensive D-cache flush if it
336 * is merely the zero page. The 'bigcore' testcase in GDB
337 * causes this case to run millions of times.
338 */
339 if (page == ZERO_PAGE(0))
340 return;
341
342 this_cpu = get_cpu();
343
344 mapping = page_mapping(page);
1da177e4 345 if (mapping && !mapping_mapped(mapping)) {
a9546f59 346 int dirty = test_bit(PG_dcache_dirty, &page->flags);
1da177e4 347 if (dirty) {
a9546f59
DM		 348 int dirty_cpu = dcache_dirty_cpu(page);
349
1da177e4
LT		 350 if (dirty_cpu == this_cpu)
351 goto out;
352 smp_flush_dcache_page_impl(page, dirty_cpu);
353 }
354 set_dcache_dirty(page, this_cpu);
355 } else {
356 /* We could delay the flush for the !page_mapping
357 * case too. But that case is for exec env/arg
358 * pages and those are %99 certainly going to get
359 * faulted into the tlb (and thus flushed) anyways.
360 */
361 flush_dcache_page_impl(page);
362 }
363
364out:
365 put_cpu();
366}
367
05e14cb3 368void __kprobes flush_icache_range(unsigned long start, unsigned long end)
1da177e4 369{
a43fe0e7 370 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
1da177e4
LT		 371 if (tlb_type == spitfire) {
372 unsigned long kaddr;
373
a94aa253
DM		 374 /* This code only runs on Spitfire cpus so this is
375 * why we can assume _PAGE_PADDR_4U.
376 */
377 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
378 unsigned long paddr, mask = _PAGE_PADDR_4U;
379
380 if (kaddr >= PAGE_OFFSET)
381 paddr = kaddr & mask;
382 else {
383 pgd_t *pgdp = pgd_offset_k(kaddr);
384 pud_t *pudp = pud_offset(pgdp, kaddr);
385 pmd_t *pmdp = pmd_offset(pudp, kaddr);
386 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
387
388 paddr = pte_val(*ptep) & mask;
389 }
390 __flush_icache_page(paddr);
391 }
1da177e4
LT		 392 }
393}
394
1da177e4
LT		 395void show_mem(void)
396{
5be4a963
DM		 397 unsigned long total = 0, reserved = 0;
398 unsigned long shared = 0, cached = 0;
399 pg_data_t *pgdat;
400
28256ca2 401 printk(KERN_INFO "Mem-info:\n");
1da177e4 402 show_free_areas();
28256ca2 403 printk(KERN_INFO "Free swap: %6ldkB\n",
1da177e4 404 nr_swap_pages << (PAGE_SHIFT-10));
5be4a963
DM		 405 for_each_online_pgdat(pgdat) {
406 unsigned long i, flags;
407
408 pgdat_resize_lock(pgdat, &flags);
409 for (i = 0; i < pgdat->node_spanned_pages; i++) {
410 struct page *page = pgdat_page_nr(pgdat, i);
411 total++;
412 if (PageReserved(page))
413 reserved++;
414 else if (PageSwapCache(page))
415 cached++;
416 else if (page_count(page))
417 shared += page_count(page) - 1;
418 }
419 pgdat_resize_unlock(pgdat, &flags);
420 }
421
422 printk(KERN_INFO "%lu pages of RAM\n", total);
423 printk(KERN_INFO "%lu reserved pages\n", reserved);
424 printk(KERN_INFO "%lu pages shared\n", shared);
425 printk(KERN_INFO "%lu pages swap cached\n", cached);
426
427 printk(KERN_INFO "%lu pages dirty\n",
428 global_page_state(NR_FILE_DIRTY));
429 printk(KERN_INFO "%lu pages writeback\n",
430 global_page_state(NR_WRITEBACK));
431 printk(KERN_INFO "%lu pages mapped\n",
432 global_page_state(NR_FILE_MAPPED));
433 printk(KERN_INFO "%lu pages slab\n",
434 global_page_state(NR_SLAB_RECLAIMABLE) +
435 global_page_state(NR_SLAB_UNRECLAIMABLE));
436 printk(KERN_INFO "%lu pages pagetables\n",
437 global_page_state(NR_PAGETABLE));
1da177e4
LT		 438}
439
440void mmu_info(struct seq_file *m)
441{
442 if (tlb_type == cheetah)
443 seq_printf(m, "MMU Type\t: Cheetah\n");
444 else if (tlb_type == cheetah_plus)
445 seq_printf(m, "MMU Type\t: Cheetah+\n");
446 else if (tlb_type == spitfire)
447 seq_printf(m, "MMU Type\t: Spitfire\n");
a43fe0e7
DM		 448 else if (tlb_type == hypervisor)
449 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
1da177e4
LT		 450 else
451 seq_printf(m, "MMU Type\t: ???\n");
452
453#ifdef CONFIG_DEBUG_DCFLUSH
454 seq_printf(m, "DCPageFlushes\t: %d\n",
455 atomic_read(&dcpage_flushes));
456#ifdef CONFIG_SMP
457 seq_printf(m, "DCPageFlushesXC\t: %d\n",
458 atomic_read(&dcpage_flushes_xcall));
459#endif /* CONFIG_SMP */
460#endif /* CONFIG_DEBUG_DCFLUSH */
461}
462
a94aa253
DM		 463struct linux_prom_translation {
464 unsigned long virt;
465 unsigned long size;
466 unsigned long data;
467};
468
469/* Exported for kernel TLB miss handling in ktlb.S */
470struct linux_prom_translation prom_trans[512] __read_mostly;
471unsigned int prom_trans_ents __read_mostly;
472
1da177e4
LT		 473/* Exported for SMP bootup purposes. */
474unsigned long kern_locked_tte_data;
475
c9c10830
DM		 476/* The obp translations are saved based on 8k pagesize, since obp can
477 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
74bf4312 478 * HI_OBP_ADDRESS range are handled in ktlb.S.
c9c10830 479 */
5085b4a5
DM		 480static inline int in_obp_range(unsigned long vaddr)
481{
482 return (vaddr >= LOW_OBP_ADDRESS &&
483 vaddr < HI_OBP_ADDRESS);
484}
485
c9c10830 486static int cmp_ptrans(const void *a, const void *b)
405599bd 487{
c9c10830 488 const struct linux_prom_translation *x = a, *y = b;
405599bd 489
c9c10830
DM		 490 if (x->virt > y->virt)
491 return 1;
492 if (x->virt < y->virt)
493 return -1;
494 return 0;
405599bd
DM		 495}
496
c9c10830 497/* Read OBP translations property into 'prom_trans[]'. */
9ad98c5b 498static void __init read_obp_translations(void)
405599bd 499{
c9c10830 500 int n, node, ents, first, last, i;
1da177e4
LT		 501
502 node = prom_finddevice("/virtual-memory");
503 n = prom_getproplen(node, "translations");
405599bd 504 if (unlikely(n == 0 || n == -1)) {
b206fc4c 505 prom_printf("prom_mappings: Couldn't get size.\n");
1da177e4
LT		 506 prom_halt();
507 }
405599bd
DM		 508 if (unlikely(n > sizeof(prom_trans))) {
509 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
1da177e4
LT		 510 prom_halt();
511 }
405599bd 512
b206fc4c 513 if ((n = prom_getproperty(node, "translations",
405599bd
DM		 514 (char *)&prom_trans[0],
515 sizeof(prom_trans))) == -1) {
b206fc4c 516 prom_printf("prom_mappings: Couldn't get property.\n");
1da177e4
LT		 517 prom_halt();
518 }
9ad98c5b 519
b206fc4c 520 n = n / sizeof(struct linux_prom_translation);
9ad98c5b 521
c9c10830
DM		 522 ents = n;
523
524 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
525 cmp_ptrans, NULL);
526
527 /* Now kick out all the non-OBP entries. */
528 for (i = 0; i < ents; i++) {
529 if (in_obp_range(prom_trans[i].virt))
530 break;
531 }
532 first = i;
533 for (; i < ents; i++) {
534 if (!in_obp_range(prom_trans[i].virt))
535 break;
536 }
537 last = i;
538
539 for (i = 0; i < (last - first); i++) {
540 struct linux_prom_translation *src = &prom_trans[i + first];
541 struct linux_prom_translation *dest = &prom_trans[i];
542
543 *dest = *src;
544 }
545 for (; i < ents; i++) {
546 struct linux_prom_translation *dest = &prom_trans[i];
547 dest->virt = dest->size = dest->data = 0x0UL;
548 }
549
550 prom_trans_ents = last - first;
551
552 if (tlb_type == spitfire) {
553 /* Clear diag TTE bits. */
554 for (i = 0; i < prom_trans_ents; i++)
555 prom_trans[i].data &= ~0x0003fe0000000000UL;
556 }
405599bd 557}
1da177e4 558
d82ace7d
DM		 559static void __init hypervisor_tlb_lock(unsigned long vaddr,
560 unsigned long pte,
561 unsigned long mmu)
562{
7db35f31
DM		 563 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
564
565 if (ret != 0) {
12e126ad 566 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
7db35f31 567 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
12e126ad
DM		 568 prom_halt();
569 }
d82ace7d
DM		 570}
571
c4bce90e
DM		 572static unsigned long kern_large_tte(unsigned long paddr);
573
898cf0ec 574static void __init remap_kernel(void)
405599bd
DM		 575{
576 unsigned long phys_page, tte_vaddr, tte_data;
64658743 577 int i, tlb_ent = sparc64_highest_locked_tlbent();
405599bd 578
1da177e4 579 tte_vaddr = (unsigned long) KERNBASE;
bff06d55 580 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
c4bce90e 581 tte_data = kern_large_tte(phys_page);
1da177e4
LT		 582
583 kern_locked_tte_data = tte_data;
584
d82ace7d
DM		 585 /* Now lock us into the TLBs via Hypervisor or OBP. */
586 if (tlb_type == hypervisor) {
64658743 587 for (i = 0; i < num_kernel_image_mappings; i++) {
d82ace7d
DM		 588 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
589 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
64658743
DM		 590 tte_vaddr += 0x400000;
591 tte_data += 0x400000;
d82ace7d
DM		 592 }
593 } else {
64658743
DM		 594 for (i = 0; i < num_kernel_image_mappings; i++) {
595 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
596 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
597 tte_vaddr += 0x400000;
598 tte_data += 0x400000;
d82ace7d 599 }
64658743 600 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
1da177e4 601 }
0835ae0f
DM		 602 if (tlb_type == cheetah_plus) {
603 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
604 CTX_CHEETAH_PLUS_NUC);
605 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
606 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
607 }
405599bd 608}
1da177e4 609
405599bd 610
c9c10830 611static void __init inherit_prom_mappings(void)
9ad98c5b
DM		 612{
613 read_obp_translations();
405599bd
DM		 614
615 /* Now fixup OBP's idea about where we really are mapped. */
3c62a2d3 616 printk("Remapping the kernel... ");
405599bd 617 remap_kernel();
3c62a2d3 618 printk("done.\n");
1da177e4
LT		 619}
620
1da177e4
LT		 621void prom_world(int enter)
622{
1da177e4
LT		 623 if (!enter)
624 set_fs((mm_segment_t) { get_thread_current_ds() });
625
3487d1d4 626 __asm__ __volatile__("flushw");
1da177e4
LT		 627}
628
1da177e4
LT		 629void __flush_dcache_range(unsigned long start, unsigned long end)
630{
631 unsigned long va;
632
633 if (tlb_type == spitfire) {
634 int n = 0;
635
636 for (va = start; va < end; va += 32) {
637 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
638 if (++n >= 512)
639 break;
640 }
a43fe0e7 641 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1da177e4
LT		 642 start = __pa(start);
643 end = __pa(end);
644 for (va = start; va < end; va += 32)
645 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
646 "membar #Sync"
647 : /* no outputs */
648 : "r" (va),
649 "i" (ASI_DCACHE_INVALIDATE));
650 }
651}
1da177e4 652
85f1e1f6
DM		 653/* get_new_mmu_context() uses "cache + 1". */
654DEFINE_SPINLOCK(ctx_alloc_lock);
655unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
656#define MAX_CTX_NR (1UL << CTX_NR_BITS)
657#define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
658DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
659
1da177e4
LT		 660/* Caller does TLB context flushing on local CPU if necessary.
661 * The caller also ensures that CTX_VALID(mm->context) is false.
662 *
663 * We must be careful about boundary cases so that we never
664 * let the user have CTX 0 (nucleus) or we ever use a CTX
665 * version of zero (and thus NO_CONTEXT would not be caught
666 * by version mis-match tests in mmu_context.h).
a0663a79
DM		 667 *
668 * Always invoked with interrupts disabled.
1da177e4
LT		 669 */
670void get_new_mmu_context(struct mm_struct *mm)
671{
672 unsigned long ctx, new_ctx;
673 unsigned long orig_pgsz_bits;
a77754b4 674 unsigned long flags;
a0663a79 675 int new_version;
1da177e4 676
a77754b4 677 spin_lock_irqsave(&ctx_alloc_lock, flags);
1da177e4
LT		 678 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
679 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
680 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
a0663a79 681 new_version = 0;
1da177e4
LT		 682 if (new_ctx >= (1 << CTX_NR_BITS)) {
683 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
684 if (new_ctx >= ctx) {
685 int i;
686 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
687 CTX_FIRST_VERSION;
688 if (new_ctx == 1)
689 new_ctx = CTX_FIRST_VERSION;
690
691 /* Don't call memset, for 16 entries that's just
692 * plain silly...
693 */
694 mmu_context_bmap[0] = 3;
695 mmu_context_bmap[1] = 0;
696 mmu_context_bmap[2] = 0;
697 mmu_context_bmap[3] = 0;
698 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
699 mmu_context_bmap[i + 0] = 0;
700 mmu_context_bmap[i + 1] = 0;
701 mmu_context_bmap[i + 2] = 0;
702 mmu_context_bmap[i + 3] = 0;
703 }
a0663a79 704 new_version = 1;
1da177e4
LT		 705 goto out;
706 }
707 }
708 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
709 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
710out:
711 tlb_context_cache = new_ctx;
712 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
a77754b4 713 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
a0663a79
DM		 714
715 if (unlikely(new_version))
716 smp_new_mmu_context_version();
1da177e4
LT		 717}
718
d1112018
DM		 719/* Find a free area for the bootmem map, avoiding the kernel image
720 * and the initial ramdisk.
721 */
722static unsigned long __init choose_bootmap_pfn(unsigned long start_pfn,
723 unsigned long end_pfn)
1da177e4 724{
d1112018
DM		 725 unsigned long avoid_start, avoid_end, bootmap_size;
726 int i;
727
39964653
DM		 728 bootmap_size = bootmem_bootmap_pages(end_pfn - start_pfn);
729 bootmap_size <<= PAGE_SHIFT;
d1112018
DM		 730
731 avoid_start = avoid_end = 0;
732#ifdef CONFIG_BLK_DEV_INITRD
733 avoid_start = initrd_start;
734 avoid_end = PAGE_ALIGN(initrd_end);
735#endif
736
d1112018
DM		 737 for (i = 0; i < pavail_ents; i++) {
738 unsigned long start, end;
739
740 start = pavail[i].phys_addr;
741 end = start + pavail[i].reg_size;
742
743 while (start < end) {
744 if (start >= kern_base &&
745 start < PAGE_ALIGN(kern_base + kern_size)) {
746 start = PAGE_ALIGN(kern_base + kern_size);
747 continue;
748 }
749 if (start >= avoid_start && start < avoid_end) {
750 start = avoid_end;
751 continue;
752 }
753
754 if ((end - start) < bootmap_size)
755 break;
756
757 if (start < kern_base &&
758 (start + bootmap_size) > kern_base) {
759 start = PAGE_ALIGN(kern_base + kern_size);
760 continue;
761 }
762
763 if (start < avoid_start &&
764 (start + bootmap_size) > avoid_start) {
765 start = avoid_end;
766 continue;
767 }
768
769 /* OK, it doesn't overlap anything, use it. */
d1112018
DM		 770 return start >> PAGE_SHIFT;
771 }
772 }
773
774 prom_printf("Cannot find free area for bootmap, aborting.\n");
775 prom_halt();
776}
777
6fc5bae7
DM		 778static void __init trim_pavail(unsigned long *cur_size_p,
779 unsigned long *end_of_phys_p)
780{
781 unsigned long to_trim = *cur_size_p - cmdline_memory_size;
782 unsigned long avoid_start, avoid_end;
783 int i;
784
785 to_trim = PAGE_ALIGN(to_trim);
786
787 avoid_start = avoid_end = 0;
788#ifdef CONFIG_BLK_DEV_INITRD
789 avoid_start = initrd_start;
790 avoid_end = PAGE_ALIGN(initrd_end);
791#endif
792
793 /* Trim some pavail[] entries in order to satisfy the
794 * requested "mem=xxx" kernel command line specification.
795 *
796 * We must not trim off the kernel image area nor the
797 * initial ramdisk range (if any). Also, we must not trim
798 * any pavail[] entry down to zero in order to preserve
799 * the invariant that all pavail[] entries have a non-zero
800 * size which is assumed by all of the code in here.
801 */
802 for (i = 0; i < pavail_ents; i++) {
803 unsigned long start, end, kern_end;
804 unsigned long trim_low, trim_high, n;
805
806 kern_end = PAGE_ALIGN(kern_base + kern_size);
807
808 trim_low = start = pavail[i].phys_addr;
809 trim_high = end = start + pavail[i].reg_size;
810
811 if (kern_base >= start &&
812 kern_base < end) {
813 trim_low = kern_base;
814 if (kern_end >= end)
815 continue;
816 }
817 if (kern_end >= start &&
818 kern_end < end) {
819 trim_high = kern_end;
820 }
821 if (avoid_start &&
822 avoid_start >= start &&
823 avoid_start < end) {
824 if (trim_low > avoid_start)
825 trim_low = avoid_start;
826 if (avoid_end >= end)
827 continue;
828 }
829 if (avoid_end &&
830 avoid_end >= start &&
831 avoid_end < end) {
832 if (trim_high < avoid_end)
833 trim_high = avoid_end;
834 }
835
836 if (trim_high <= trim_low)
837 continue;
838
839 if (trim_low == start && trim_high == end) {
840 /* Whole chunk is available for trimming.
841 * Trim all except one page, in order to keep
842 * entry non-empty.
843 */
844 n = (end - start) - PAGE_SIZE;
845 if (n > to_trim)
846 n = to_trim;
847
848 if (n) {
849 pavail[i].phys_addr += n;
850 pavail[i].reg_size -= n;
851 to_trim -= n;
852 }
853 } else {
854 n = (trim_low - start);
855 if (n > to_trim)
856 n = to_trim;
857
858 if (n) {
859 pavail[i].phys_addr += n;
860 pavail[i].reg_size -= n;
861 to_trim -= n;
862 }
863 if (to_trim) {
864 n = end - trim_high;
865 if (n > to_trim)
866 n = to_trim;
867 if (n) {
868 pavail[i].reg_size -= n;
869 to_trim -= n;
870 }
871 }
872 }
873
874 if (!to_trim)
875 break;
876 }
877
878 /* Recalculate. */
879 *cur_size_p = 0UL;
880 for (i = 0; i < pavail_ents; i++) {
881 *end_of_phys_p = pavail[i].phys_addr +
882 pavail[i].reg_size;
883 *cur_size_p += pavail[i].reg_size;
884 }
885}
886
4e82c9a6
DM		 887static void __init find_ramdisk(unsigned long phys_base)
888{
889#ifdef CONFIG_BLK_DEV_INITRD
890 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
891 unsigned long ramdisk_image;
892
893 /* Older versions of the bootloader only supported a
894 * 32-bit physical address for the ramdisk image
895 * location, stored at sparc_ramdisk_image. Newer
896 * SILO versions set sparc_ramdisk_image to zero and
897 * provide a full 64-bit physical address at
898 * sparc_ramdisk_image64.
899 */
900 ramdisk_image = sparc_ramdisk_image;
901 if (!ramdisk_image)
902 ramdisk_image = sparc_ramdisk_image64;
903
904 /* Another bootloader quirk. The bootloader normalizes
905 * the physical address to KERNBASE, so we have to
906 * factor that back out and add in the lowest valid
907 * physical page address to get the true physical address.
908 */
909 ramdisk_image -= KERNBASE;
910 ramdisk_image += phys_base;
911
912 initrd_start = ramdisk_image;
913 initrd_end = ramdisk_image + sparc_ramdisk_size;
3b2a7e23
DM		 914
915 lmb_reserve(initrd_start, initrd_end);
4e82c9a6
DM		 916 }
917#endif
918}
919
f1cfdb55
DM		 920/* About pages_avail, this is the value we will use to calculate
921 * the zholes_size[] argument given to free_area_init_node(). The
922 * page allocator uses this to calculate nr_kernel_pages,
923 * nr_all_pages and zone->present_pages. On NUMA it is used
924 * to calculate zone->min_unmapped_pages and zone->min_slab_pages.
925 *
926 * So this number should really be set to what the page allocator
927 * actually ends up with. This means:
928 * 1) It should include bootmem map pages, we'll release those.
929 * 2) It should not include the kernel image, except for the
930 * __init sections which we will also release.
931 * 3) It should include the initrd image, since we'll release
932 * that too.
933 */
d1112018
DM		 934static unsigned long __init bootmem_init(unsigned long *pages_avail,
935 unsigned long phys_base)
936{
937 unsigned long bootmap_size, end_pfn;
1da177e4
LT		 938 unsigned long end_of_phys_memory = 0UL;
939 unsigned long bootmap_pfn, bytes_avail, size;
940 int i;
941
1da177e4 942 bytes_avail = 0UL;
13edad7a
DM		 943 for (i = 0; i < pavail_ents; i++) {
944 end_of_phys_memory = pavail[i].phys_addr +
945 pavail[i].reg_size;
946 bytes_avail += pavail[i].reg_size;
1da177e4
LT		 947 }
948
6fc5bae7
DM		 949 if (cmdline_memory_size &&
950 bytes_avail > cmdline_memory_size)
951 trim_pavail(&bytes_avail,
952 &end_of_phys_memory);
953
954 *pages_avail = bytes_avail >> PAGE_SHIFT;
955
956 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
957
1da177e4
LT		 958 /* Initialize the boot-time allocator. */
959 max_pfn = max_low_pfn = end_pfn;
d1112018
DM		 960 min_low_pfn = (phys_base >> PAGE_SHIFT);
961
962 bootmap_pfn = choose_bootmap_pfn(min_low_pfn, end_pfn);
1da177e4 963
d1112018 964 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn,
17b0e199 965 min_low_pfn, end_pfn);
1da177e4 966
1da177e4
LT		 967 /* Now register the available physical memory with the
968 * allocator.
969 */
0f78e754 970 for (i = 0; i < pavail_ents; i++)
13edad7a 971 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
1da177e4
LT		 972
973#ifdef CONFIG_BLK_DEV_INITRD
974 if (initrd_start) {
975 size = initrd_end - initrd_start;
976
e5dd42e4 977 /* Reserve the initrd image area. */
72a7fe39 978 reserve_bootmem(initrd_start, size, BOOTMEM_DEFAULT);
1da177e4
LT		 979
980 initrd_start += PAGE_OFFSET;
981 initrd_end += PAGE_OFFSET;
982 }
983#endif
984 /* Reserve the kernel text/data/bss. */
72a7fe39 985 reserve_bootmem(kern_base, kern_size, BOOTMEM_DEFAULT);
1da177e4
LT		 986 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
987
f1cfdb55
DM		 988 /* Add back in the initmem pages. */
989 size = ((unsigned long)(__init_end) & PAGE_MASK) -
990 PAGE_ALIGN((unsigned long)__init_begin);
991 *pages_avail += size >> PAGE_SHIFT;
992
1da177e4
LT		 993 /* Reserve the bootmem map. We do not account for it
994 * in pages_avail because we will release that memory
995 * in free_all_bootmem.
996 */
997 size = bootmap_size;
72a7fe39 998 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size, BOOTMEM_DEFAULT);
1da177e4 999
d1112018
DM		 1000 for (i = 0; i < pavail_ents; i++) {
1001 unsigned long start_pfn, end_pfn;
1002
1003 start_pfn = pavail[i].phys_addr >> PAGE_SHIFT;
1004 end_pfn = (start_pfn + (pavail[i].reg_size >> PAGE_SHIFT));
d1112018
DM		 1005 memory_present(0, start_pfn, end_pfn);
1006 }
1007
1008 sparse_init();
1009
1da177e4
LT		 1010 return end_pfn;
1011}
1012
9cc3a1ac
DM		 1013static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1014static int pall_ents __initdata;
1015
56425306 1016#ifdef CONFIG_DEBUG_PAGEALLOC
896aef43
SR		 1017static unsigned long __ref kernel_map_range(unsigned long pstart,
1018 unsigned long pend, pgprot_t prot)
56425306
DM		 1019{
1020 unsigned long vstart = PAGE_OFFSET + pstart;
1021 unsigned long vend = PAGE_OFFSET + pend;
1022 unsigned long alloc_bytes = 0UL;
1023
1024 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
13edad7a 1025 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
56425306
DM		 1026 vstart, vend);
1027 prom_halt();
1028 }
1029
1030 while (vstart < vend) {
1031 unsigned long this_end, paddr = __pa(vstart);
1032 pgd_t *pgd = pgd_offset_k(vstart);
1033 pud_t *pud;
1034 pmd_t *pmd;
1035 pte_t *pte;
1036
1037 pud = pud_offset(pgd, vstart);
1038 if (pud_none(*pud)) {
1039 pmd_t *new;
1040
1041 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1042 alloc_bytes += PAGE_SIZE;
1043 pud_populate(&init_mm, pud, new);
1044 }
1045
1046 pmd = pmd_offset(pud, vstart);
1047 if (!pmd_present(*pmd)) {
1048 pte_t *new;
1049
1050 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1051 alloc_bytes += PAGE_SIZE;
1052 pmd_populate_kernel(&init_mm, pmd, new);
1053 }
1054
1055 pte = pte_offset_kernel(pmd, vstart);
1056 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1057 if (this_end > vend)
1058 this_end = vend;
1059
1060 while (vstart < this_end) {
1061 pte_val(*pte) = (paddr | pgprot_val(prot));
1062
1063 vstart += PAGE_SIZE;
1064 paddr += PAGE_SIZE;
1065 pte++;
1066 }
1067 }
1068
1069 return alloc_bytes;
1070}
1071
56425306 1072extern unsigned int kvmap_linear_patch[1];
9cc3a1ac
DM		 1073#endif /* CONFIG_DEBUG_PAGEALLOC */
1074
1075static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1076{
1077 const unsigned long shift_256MB = 28;
1078 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1079 const unsigned long size_256MB = (1UL << shift_256MB);
1080
1081 while (start < end) {
1082 long remains;
1083
f7c00338
DM		 1084 remains = end - start;
1085 if (remains < size_256MB)
1086 break;
1087
9cc3a1ac
DM		 1088 if (start & mask_256MB) {
1089 start = (start + size_256MB) & ~mask_256MB;
1090 continue;
1091 }
1092
9cc3a1ac
DM		 1093 while (remains >= size_256MB) {
1094 unsigned long index = start >> shift_256MB;
1095
1096 __set_bit(index, kpte_linear_bitmap);
1097
1098 start += size_256MB;
1099 remains -= size_256MB;
1100 }
1101 }
1102}
56425306 1103
8f361453 1104static void __init init_kpte_bitmap(void)
56425306 1105{
9cc3a1ac 1106 unsigned long i;
13edad7a
DM		 1107
1108 for (i = 0; i < pall_ents; i++) {
56425306
DM		 1109 unsigned long phys_start, phys_end;
1110
13edad7a
DM		 1111 phys_start = pall[i].phys_addr;
1112 phys_end = phys_start + pall[i].reg_size;
9cc3a1ac
DM		 1113
1114 mark_kpte_bitmap(phys_start, phys_end);
8f361453
DM		 1115 }
1116}
9cc3a1ac 1117
8f361453
DM		 1118static void __init kernel_physical_mapping_init(void)
1119{
9cc3a1ac 1120#ifdef CONFIG_DEBUG_PAGEALLOC
8f361453
DM		 1121 unsigned long i, mem_alloced = 0UL;
1122
1123 for (i = 0; i < pall_ents; i++) {
1124 unsigned long phys_start, phys_end;
1125
1126 phys_start = pall[i].phys_addr;
1127 phys_end = phys_start + pall[i].reg_size;
1128
56425306
DM		 1129 mem_alloced += kernel_map_range(phys_start, phys_end,
1130 PAGE_KERNEL);
56425306
DM		 1131 }
1132
1133 printk("Allocated %ld bytes for kernel page tables.\n",
1134 mem_alloced);
1135
1136 kvmap_linear_patch[0] = 0x01000000; /* nop */
1137 flushi(&kvmap_linear_patch[0]);
1138
1139 __flush_tlb_all();
9cc3a1ac 1140#endif
56425306
DM		 1141}
1142
9cc3a1ac 1143#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1144void kernel_map_pages(struct page *page, int numpages, int enable)
1145{
1146 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1147 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1148
1149 kernel_map_range(phys_start, phys_end,
1150 (enable ? PAGE_KERNEL : __pgprot(0)));
1151
74bf4312
DM		 1152 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1153 PAGE_OFFSET + phys_end);
1154
56425306
DM		 1155 /* we should perform an IPI and flush all tlbs,
1156 * but that can deadlock->flush only current cpu.
1157 */
1158 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1159 PAGE_OFFSET + phys_end);
1160}
1161#endif
1162
10147570
DM		 1163unsigned long __init find_ecache_flush_span(unsigned long size)
1164{
0836a0eb
DM		 1165 int i;
1166
13edad7a
DM		 1167 for (i = 0; i < pavail_ents; i++) {
1168 if (pavail[i].reg_size >= size)
1169 return pavail[i].phys_addr;
0836a0eb
DM		 1170 }
1171
13edad7a 1172 return ~0UL;
0836a0eb
DM		 1173}
1174
517af332
DM		 1175static void __init tsb_phys_patch(void)
1176{
d257d5da 1177 struct tsb_ldquad_phys_patch_entry *pquad;
517af332
DM		 1178 struct tsb_phys_patch_entry *p;
1179
d257d5da
DM		 1180 pquad = &__tsb_ldquad_phys_patch;
1181 while (pquad < &__tsb_ldquad_phys_patch_end) {
1182 unsigned long addr = pquad->addr;
1183
1184 if (tlb_type == hypervisor)
1185 *(unsigned int *) addr = pquad->sun4v_insn;
1186 else
1187 *(unsigned int *) addr = pquad->sun4u_insn;
1188 wmb();
1189 __asm__ __volatile__("flush %0"
1190 : /* no outputs */
1191 : "r" (addr));
1192
1193 pquad++;
1194 }
1195
517af332
DM		 1196 p = &__tsb_phys_patch;
1197 while (p < &__tsb_phys_patch_end) {
1198 unsigned long addr = p->addr;
1199
1200 *(unsigned int *) addr = p->insn;
1201 wmb();
1202 __asm__ __volatile__("flush %0"
1203 : /* no outputs */
1204 : "r" (addr));
1205
1206 p++;
1207 }
1208}
1209
490384e7 1210/* Don't mark as init, we give this to the Hypervisor. */
d1acb421
DM		 1211#ifndef CONFIG_DEBUG_PAGEALLOC
1212#define NUM_KTSB_DESCR 2
1213#else
1214#define NUM_KTSB_DESCR 1
1215#endif
1216static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
490384e7
DM		 1217extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1218
1219static void __init sun4v_ktsb_init(void)
1220{
1221 unsigned long ktsb_pa;
1222
d7744a09 1223 /* First KTSB for PAGE_SIZE mappings. */
490384e7
DM		 1224 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1225
1226 switch (PAGE_SIZE) {
1227 case 8 * 1024:
1228 default:
1229 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1230 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1231 break;
1232
1233 case 64 * 1024:
1234 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1235 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1236 break;
1237
1238 case 512 * 1024:
1239 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1240 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1241 break;
1242
1243 case 4 * 1024 * 1024:
1244 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1245 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1246 break;
1247 };
1248
3f19a84e 1249 ktsb_descr[0].assoc = 1;
490384e7
DM		 1250 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1251 ktsb_descr[0].ctx_idx = 0;
1252 ktsb_descr[0].tsb_base = ktsb_pa;
1253 ktsb_descr[0].resv = 0;
1254
d1acb421 1255#ifndef CONFIG_DEBUG_PAGEALLOC
d7744a09
DM		 1256 /* Second KTSB for 4MB/256MB mappings. */
1257 ktsb_pa = (kern_base +
1258 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1259
1260 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1261 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1262 HV_PGSZ_MASK_256MB);
1263 ktsb_descr[1].assoc = 1;
1264 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1265 ktsb_descr[1].ctx_idx = 0;
1266 ktsb_descr[1].tsb_base = ktsb_pa;
1267 ktsb_descr[1].resv = 0;
d1acb421 1268#endif
490384e7
DM		 1269}
1270
1271void __cpuinit sun4v_ktsb_register(void)
1272{
7db35f31 1273 unsigned long pa, ret;
490384e7
DM		 1274
1275 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1276
7db35f31
DM		 1277 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1278 if (ret != 0) {
1279 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1280 "errors with %lx\n", pa, ret);
1281 prom_halt();
1282 }
490384e7
DM		 1283}
1284
1da177e4
LT		 1285/* paging_init() sets up the page tables */
1286
5cbc3073
DM		 1287extern void central_probe(void);
1288
1da177e4 1289static unsigned long last_valid_pfn;
56425306 1290pgd_t swapper_pg_dir[2048];
1da177e4 1291
c4bce90e
DM		 1292static void sun4u_pgprot_init(void);
1293static void sun4v_pgprot_init(void);
1294
3afc6202 1295/* Dummy function */
1296void __init setup_per_cpu_areas(void)
1297{
1298}
1299
1da177e4
LT		 1300void __init paging_init(void)
1301{
d1112018 1302 unsigned long end_pfn, pages_avail, shift, phys_base;
0836a0eb
DM		 1303 unsigned long real_end, i;
1304
22adb358
DM		 1305 /* These build time checkes make sure that the dcache_dirty_cpu()
1306 * page->flags usage will work.
1307 *
1308 * When a page gets marked as dcache-dirty, we store the
1309 * cpu number starting at bit 32 in the page->flags. Also,
1310 * functions like clear_dcache_dirty_cpu use the cpu mask
1311 * in 13-bit signed-immediate instruction fields.
1312 */
1313 BUILD_BUG_ON(FLAGS_RESERVED != 32);
1314 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1315 ilog2(roundup_pow_of_two(NR_CPUS)) > FLAGS_RESERVED);
1316 BUILD_BUG_ON(NR_CPUS > 4096);
1317
481295f9
DM		 1318 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1319 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1320
22d6a1cb
DM		 1321 sstate_booting();
1322
d7744a09 1323 /* Invalidate both kernel TSBs. */
8b234274 1324 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
d1acb421 1325#ifndef CONFIG_DEBUG_PAGEALLOC
d7744a09 1326 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
d1acb421 1327#endif
8b234274 1328
c4bce90e
DM		 1329 if (tlb_type == hypervisor)
1330 sun4v_pgprot_init();
1331 else
1332 sun4u_pgprot_init();
1333
d257d5da
DM		 1334 if (tlb_type == cheetah_plus ||
1335 tlb_type == hypervisor)
517af332
DM		 1336 tsb_phys_patch();
1337
490384e7 1338 if (tlb_type == hypervisor) {
d257d5da 1339 sun4v_patch_tlb_handlers();
490384e7
DM		 1340 sun4v_ktsb_init();
1341 }
d257d5da 1342
3b2a7e23
DM		 1343 lmb_init();
1344
13edad7a
DM		 1345 /* Find available physical memory... */
1346 read_obp_memory("available", &pavail[0], &pavail_ents);
0836a0eb
DM		 1347
1348 phys_base = 0xffffffffffffffffUL;
3b2a7e23 1349 for (i = 0; i < pavail_ents; i++) {
13edad7a 1350 phys_base = min(phys_base, pavail[i].phys_addr);
3b2a7e23
DM		 1351 lmb_add(pavail[i].phys_addr, pavail[i].reg_size);
1352 }
1353
1354 lmb_reserve(kern_base, kern_size);
0836a0eb 1355
4e82c9a6
DM		 1356 find_ramdisk(phys_base);
1357
3b2a7e23
DM		 1358 lmb_analyze();
1359 lmb_dump_all();
1360
1da177e4
LT		 1361 set_bit(0, mmu_context_bmap);
1362
2bdb3cb2
DM		 1363 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1364
1da177e4 1365 real_end = (unsigned long)_end;
64658743
DM		 1366 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1367 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1368 num_kernel_image_mappings);
2bdb3cb2
DM		 1369
1370 /* Set kernel pgd to upper alias so physical page computations
1da177e4
LT		 1371 * work.
1372 */
1373 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1374
56425306 1375 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1da177e4
LT		 1376
1377 /* Now can init the kernel/bad page tables. */
1378 pud_set(pud_offset(&swapper_pg_dir[0], 0),
56425306 1379 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1da177e4 1380
c9c10830 1381 inherit_prom_mappings();
5085b4a5 1382
8f361453
DM		 1383 read_obp_memory("reg", &pall[0], &pall_ents);
1384
1385 init_kpte_bitmap();
1386
a8b900d8
DM		 1387 /* Ok, we can use our TLB miss and window trap handlers safely. */
1388 setup_tba();
1da177e4 1389
c9c10830 1390 __flush_tlb_all();
9ad98c5b 1391
490384e7
DM		 1392 if (tlb_type == hypervisor)
1393 sun4v_ktsb_register();
1394
2bdb3cb2
DM		 1395 /* Setup bootmem... */
1396 pages_avail = 0;
d1112018
DM		 1397 last_valid_pfn = end_pfn = bootmem_init(&pages_avail, phys_base);
1398
17b0e199 1399 max_mapnr = last_valid_pfn;
2bdb3cb2 1400
56425306 1401 kernel_physical_mapping_init();
56425306 1402
5cbc3073
DM		 1403 real_setup_per_cpu_areas();
1404
372b07bb
DM		 1405 prom_build_devicetree();
1406
5cbc3073
DM		 1407 if (tlb_type == hypervisor)
1408 sun4v_mdesc_init();
1409
1da177e4
LT		 1410 {
1411 unsigned long zones_size[MAX_NR_ZONES];
1412 unsigned long zholes_size[MAX_NR_ZONES];
1da177e4
LT		 1413 int znum;
1414
1415 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1416 zones_size[znum] = zholes_size[znum] = 0;
1417
1b51d3a0
DM		 1418 zones_size[ZONE_NORMAL] = end_pfn;
1419 zholes_size[ZONE_NORMAL] = end_pfn - pages_avail;
1da177e4
LT		 1420
1421 free_area_init_node(0, &contig_page_data, zones_size,
17b0e199
DM		 1422 __pa(PAGE_OFFSET) >> PAGE_SHIFT,
1423 zholes_size);
1da177e4
LT		 1424 }
1425
3c62a2d3 1426 printk("Booting Linux...\n");
5cbc3073
DM		 1427
1428 central_probe();
1429 cpu_probe();
1da177e4
LT		 1430}
1431
1da177e4
LT		 1432static void __init taint_real_pages(void)
1433{
1da177e4
LT		 1434 int i;
1435
13edad7a 1436 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1da177e4 1437
13edad7a 1438 /* Find changes discovered in the physmem available rescan and
1da177e4
LT		 1439 * reserve the lost portions in the bootmem maps.
1440 */
13edad7a 1441 for (i = 0; i < pavail_ents; i++) {
1da177e4
LT		 1442 unsigned long old_start, old_end;
1443
13edad7a 1444 old_start = pavail[i].phys_addr;
1da177e4 1445 old_end = old_start +
13edad7a 1446 pavail[i].reg_size;
1da177e4
LT		 1447 while (old_start < old_end) {
1448 int n;
1449
c2a5a46b 1450 for (n = 0; n < pavail_rescan_ents; n++) {
1da177e4
LT		 1451 unsigned long new_start, new_end;
1452
13edad7a
DM		 1453 new_start = pavail_rescan[n].phys_addr;
1454 new_end = new_start +
1455 pavail_rescan[n].reg_size;
1da177e4
LT		 1456
1457 if (new_start <= old_start &&
1458 new_end >= (old_start + PAGE_SIZE)) {
13edad7a
DM		 1459 set_bit(old_start >> 22,
1460 sparc64_valid_addr_bitmap);
1da177e4
LT		 1461 goto do_next_page;
1462 }
1463 }
72a7fe39 1464 reserve_bootmem(old_start, PAGE_SIZE, BOOTMEM_DEFAULT);
1da177e4
LT		 1465
1466 do_next_page:
1467 old_start += PAGE_SIZE;
1468 }
1469 }
1470}
1471
c2a5a46b
DM		 1472int __init page_in_phys_avail(unsigned long paddr)
1473{
1474 int i;
1475
1476 paddr &= PAGE_MASK;
1477
1478 for (i = 0; i < pavail_rescan_ents; i++) {
1479 unsigned long start, end;
1480
1481 start = pavail_rescan[i].phys_addr;
1482 end = start + pavail_rescan[i].reg_size;
1483
1484 if (paddr >= start && paddr < end)
1485 return 1;
1486 }
1487 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1488 return 1;
1489#ifdef CONFIG_BLK_DEV_INITRD
1490 if (paddr >= __pa(initrd_start) &&
1491 paddr < __pa(PAGE_ALIGN(initrd_end)))
1492 return 1;
1493#endif
1494
1495 return 0;
1496}
1497
1da177e4
LT		 1498void __init mem_init(void)
1499{
1500 unsigned long codepages, datapages, initpages;
1501 unsigned long addr, last;
1502 int i;
1503
1504 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1505 i += 1;
2bdb3cb2 1506 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1da177e4
LT		 1507 if (sparc64_valid_addr_bitmap == NULL) {
1508 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1509 prom_halt();
1510 }
1511 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1512
1513 addr = PAGE_OFFSET + kern_base;
1514 last = PAGE_ALIGN(kern_size) + addr;
1515 while (addr < last) {
1516 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1517 addr += PAGE_SIZE;
1518 }
1519
1520 taint_real_pages();
1521
1da177e4
LT		 1522 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1523
f1cfdb55
DM		 1524 /* We subtract one to account for the mem_map_zero page
1525 * allocated below.
1526 */
1da177e4
LT		 1527 totalram_pages = num_physpages = free_all_bootmem() - 1;
1528
1529 /*
1530 * Set up the zero page, mark it reserved, so that page count
1531 * is not manipulated when freeing the page from user ptes.
1532 */
1533 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1534 if (mem_map_zero == NULL) {
1535 prom_printf("paging_init: Cannot alloc zero page.\n");
1536 prom_halt();
1537 }
1538 SetPageReserved(mem_map_zero);
1539
1540 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1541 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1542 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1543 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1544 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1545 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1546
96177299 1547 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1da177e4
LT		 1548 nr_free_pages() << (PAGE_SHIFT-10),
1549 codepages << (PAGE_SHIFT-10),
1550 datapages << (PAGE_SHIFT-10),
1551 initpages << (PAGE_SHIFT-10),
1552 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1553
1554 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1555 cheetah_ecache_flush_init();
1556}
1557
898cf0ec 1558void free_initmem(void)
1da177e4
LT		 1559{
1560 unsigned long addr, initend;
1561
1562 /*
1563 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1564 */
1565 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1566 initend = (unsigned long)(__init_end) & PAGE_MASK;
1567 for (; addr < initend; addr += PAGE_SIZE) {
1568 unsigned long page;
1569 struct page *p;
1570
1571 page = (addr +
1572 ((unsigned long) __va(kern_base)) -
1573 ((unsigned long) KERNBASE));
c9cf5528 1574 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1da177e4
LT		 1575 p = virt_to_page(page);
1576
1577 ClearPageReserved(p);
7835e98b 1578 init_page_count(p);
1da177e4
LT		 1579 __free_page(p);
1580 num_physpages++;
1581 totalram_pages++;
1582 }
1583}
1584
1585#ifdef CONFIG_BLK_DEV_INITRD
1586void free_initrd_mem(unsigned long start, unsigned long end)
1587{
1588 if (start < end)
1589 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1590 for (; start < end; start += PAGE_SIZE) {
1591 struct page *p = virt_to_page(start);
1592
1593 ClearPageReserved(p);
7835e98b 1594 init_page_count(p);
1da177e4
LT		 1595 __free_page(p);
1596 num_physpages++;
1597 totalram_pages++;
1598 }
1599}
1600#endif
c4bce90e 1601
c4bce90e
DM		 1602#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1603#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1604#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1605#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1606#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1607#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1608
1609pgprot_t PAGE_KERNEL __read_mostly;
1610EXPORT_SYMBOL(PAGE_KERNEL);
1611
1612pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1613pgprot_t PAGE_COPY __read_mostly;
0f15952a
DM		 1614
1615pgprot_t PAGE_SHARED __read_mostly;
1616EXPORT_SYMBOL(PAGE_SHARED);
1617
c4bce90e
DM		 1618pgprot_t PAGE_EXEC __read_mostly;
1619unsigned long pg_iobits __read_mostly;
1620
1621unsigned long _PAGE_IE __read_mostly;
987c74fc 1622EXPORT_SYMBOL(_PAGE_IE);
b2bef442 1623
c4bce90e 1624unsigned long _PAGE_E __read_mostly;
b2bef442
DM		 1625EXPORT_SYMBOL(_PAGE_E);
1626
c4bce90e 1627unsigned long _PAGE_CACHE __read_mostly;
b2bef442 1628EXPORT_SYMBOL(_PAGE_CACHE);
c4bce90e 1629
46644c24
DM		 1630#ifdef CONFIG_SPARSEMEM_VMEMMAP
1631
1632#define VMEMMAP_CHUNK_SHIFT 22
1633#define VMEMMAP_CHUNK (1UL << VMEMMAP_CHUNK_SHIFT)
1634#define VMEMMAP_CHUNK_MASK ~(VMEMMAP_CHUNK - 1UL)
1635#define VMEMMAP_ALIGN(x) (((x)+VMEMMAP_CHUNK-1UL)&VMEMMAP_CHUNK_MASK)
1636
1637#define VMEMMAP_SIZE ((((1UL << MAX_PHYSADDR_BITS) >> PAGE_SHIFT) * \
1638 sizeof(struct page *)) >> VMEMMAP_CHUNK_SHIFT)
1639unsigned long vmemmap_table[VMEMMAP_SIZE];
1640
1641int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
1642{
1643 unsigned long vstart = (unsigned long) start;
1644 unsigned long vend = (unsigned long) (start + nr);
1645 unsigned long phys_start = (vstart - VMEMMAP_BASE);
1646 unsigned long phys_end = (vend - VMEMMAP_BASE);
1647 unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
1648 unsigned long end = VMEMMAP_ALIGN(phys_end);
1649 unsigned long pte_base;
1650
1651 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1652 _PAGE_CP_4U | _PAGE_CV_4U |
1653 _PAGE_P_4U | _PAGE_W_4U);
1654 if (tlb_type == hypervisor)
1655 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1656 _PAGE_CP_4V | _PAGE_CV_4V |
1657 _PAGE_P_4V | _PAGE_W_4V);
1658
1659 for (; addr < end; addr += VMEMMAP_CHUNK) {
1660 unsigned long *vmem_pp =
1661 vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
1662 void *block;
1663
1664 if (!(*vmem_pp & _PAGE_VALID)) {
1665 block = vmemmap_alloc_block(1UL << 22, node);
1666 if (!block)
1667 return -ENOMEM;
1668
1669 *vmem_pp = pte_base | __pa(block);
1670
1671 printk(KERN_INFO "[%p-%p] page_structs=%lu "
1672 "node=%d entry=%lu/%lu\n", start, block, nr,
1673 node,
1674 addr >> VMEMMAP_CHUNK_SHIFT,
1675 VMEMMAP_SIZE >> VMEMMAP_CHUNK_SHIFT);
1676 }
1677 }
1678 return 0;
1679}
1680#endif /* CONFIG_SPARSEMEM_VMEMMAP */
1681
c4bce90e
DM		 1682static void prot_init_common(unsigned long page_none,
1683 unsigned long page_shared,
1684 unsigned long page_copy,
1685 unsigned long page_readonly,
1686 unsigned long page_exec_bit)
1687{
1688 PAGE_COPY = __pgprot(page_copy);
0f15952a 1689 PAGE_SHARED = __pgprot(page_shared);
c4bce90e
DM		 1690
1691 protection_map[0x0] = __pgprot(page_none);
1692 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1693 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1694 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1695 protection_map[0x4] = __pgprot(page_readonly);
1696 protection_map[0x5] = __pgprot(page_readonly);
1697 protection_map[0x6] = __pgprot(page_copy);
1698 protection_map[0x7] = __pgprot(page_copy);
1699 protection_map[0x8] = __pgprot(page_none);
1700 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1701 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1702 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1703 protection_map[0xc] = __pgprot(page_readonly);
1704 protection_map[0xd] = __pgprot(page_readonly);
1705 protection_map[0xe] = __pgprot(page_shared);
1706 protection_map[0xf] = __pgprot(page_shared);
1707}
1708
1709static void __init sun4u_pgprot_init(void)
1710{
1711 unsigned long page_none, page_shared, page_copy, page_readonly;
1712 unsigned long page_exec_bit;
1713
1714 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1715 _PAGE_CACHE_4U | _PAGE_P_4U |
1716 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1717 _PAGE_EXEC_4U);
1718 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1719 _PAGE_CACHE_4U | _PAGE_P_4U |
1720 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1721 _PAGE_EXEC_4U | _PAGE_L_4U);
1722 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1723
1724 _PAGE_IE = _PAGE_IE_4U;
1725 _PAGE_E = _PAGE_E_4U;
1726 _PAGE_CACHE = _PAGE_CACHE_4U;
1727
1728 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1729 __ACCESS_BITS_4U | _PAGE_E_4U);
1730
d1acb421
DM		 1731#ifdef CONFIG_DEBUG_PAGEALLOC
1732 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
1733 0xfffff80000000000;
1734#else
9cc3a1ac 1735 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
c4bce90e 1736 0xfffff80000000000;
d1acb421 1737#endif
9cc3a1ac
DM		 1738 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1739 _PAGE_P_4U | _PAGE_W_4U);
1740
1741 /* XXX Should use 256MB on Panther. XXX */
1742 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
c4bce90e
DM		 1743
1744 _PAGE_SZBITS = _PAGE_SZBITS_4U;
1745 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1746 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1747 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1748
1749
1750 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1751 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1752 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1753 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1754 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1755 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1756 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1757
1758 page_exec_bit = _PAGE_EXEC_4U;
1759
1760 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1761 page_exec_bit);
1762}
1763
1764static void __init sun4v_pgprot_init(void)
1765{
1766 unsigned long page_none, page_shared, page_copy, page_readonly;
1767 unsigned long page_exec_bit;
1768
1769 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1770 _PAGE_CACHE_4V | _PAGE_P_4V |
1771 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1772 _PAGE_EXEC_4V);
1773 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1774 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1775
1776 _PAGE_IE = _PAGE_IE_4V;
1777 _PAGE_E = _PAGE_E_4V;
1778 _PAGE_CACHE = _PAGE_CACHE_4V;
1779
d1acb421
DM		 1780#ifdef CONFIG_DEBUG_PAGEALLOC
1781 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1782 0xfffff80000000000;
1783#else
9cc3a1ac
DM		 1784 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1785 0xfffff80000000000;
d1acb421 1786#endif
9cc3a1ac
DM		 1787 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1788 _PAGE_P_4V | _PAGE_W_4V);
1789
d1acb421
DM		 1790#ifdef CONFIG_DEBUG_PAGEALLOC
1791 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1792 0xfffff80000000000;
1793#else
9cc3a1ac 1794 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
c4bce90e 1795 0xfffff80000000000;
d1acb421 1796#endif
9cc3a1ac
DM		 1797 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1798 _PAGE_P_4V | _PAGE_W_4V);
c4bce90e
DM		 1799
1800 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1801 __ACCESS_BITS_4V | _PAGE_E_4V);
1802
1803 _PAGE_SZBITS = _PAGE_SZBITS_4V;
1804 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1805 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1806 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1807 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1808
1809 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1810 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1811 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1812 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1813 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1814 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1815 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1816
1817 page_exec_bit = _PAGE_EXEC_4V;
1818
1819 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1820 page_exec_bit);
1821}
1822
1823unsigned long pte_sz_bits(unsigned long sz)
1824{
1825 if (tlb_type == hypervisor) {
1826 switch (sz) {
1827 case 8 * 1024:
1828 default:
1829 return _PAGE_SZ8K_4V;
1830 case 64 * 1024:
1831 return _PAGE_SZ64K_4V;
1832 case 512 * 1024:
1833 return _PAGE_SZ512K_4V;
1834 case 4 * 1024 * 1024:
1835 return _PAGE_SZ4MB_4V;
1836 };
1837 } else {
1838 switch (sz) {
1839 case 8 * 1024:
1840 default:
1841 return _PAGE_SZ8K_4U;
1842 case 64 * 1024:
1843 return _PAGE_SZ64K_4U;
1844 case 512 * 1024:
1845 return _PAGE_SZ512K_4U;
1846 case 4 * 1024 * 1024:
1847 return _PAGE_SZ4MB_4U;
1848 };
1849 }
1850}
1851
1852pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1853{
1854 pte_t pte;
cf627156
DM		 1855
1856 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
c4bce90e
DM		 1857 pte_val(pte) |= (((unsigned long)space) << 32);
1858 pte_val(pte) |= pte_sz_bits(page_size);
c4bce90e 1859
cf627156 1860 return pte;
c4bce90e
DM		 1861}
1862
1863static unsigned long kern_large_tte(unsigned long paddr)
1864{
1865 unsigned long val;
1866
1867 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1868 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1869 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1870 if (tlb_type == hypervisor)
1871 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1872 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1873 _PAGE_EXEC_4V | _PAGE_W_4V);
1874
1875 return val | paddr;
1876}
1877
c4bce90e
DM		 1878/* If not locked, zap it. */
1879void __flush_tlb_all(void)
1880{
1881 unsigned long pstate;
1882 int i;
1883
1884 __asm__ __volatile__("flushw\n\t"
1885 "rdpr %%pstate, %0\n\t"
1886 "wrpr %0, %1, %%pstate"
1887 : "=r" (pstate)
1888 : "i" (PSTATE_IE));
8f361453
DM		 1889 if (tlb_type == hypervisor) {
1890 sun4v_mmu_demap_all();
1891 } else if (tlb_type == spitfire) {
c4bce90e
DM		 1892 for (i = 0; i < 64; i++) {
1893 /* Spitfire Errata #32 workaround */
1894 /* NOTE: Always runs on spitfire, so no
1895 * cheetah+ page size encodings.
1896 */
1897 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1898 "flush %%g6"
1899 : /* No outputs */
1900 : "r" (0),
1901 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1902
1903 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1904 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1905 "membar #Sync"
1906 : /* no outputs */
1907 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1908 spitfire_put_dtlb_data(i, 0x0UL);
1909 }
1910
1911 /* Spitfire Errata #32 workaround */
1912 /* NOTE: Always runs on spitfire, so no
1913 * cheetah+ page size encodings.
1914 */
1915 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1916 "flush %%g6"
1917 : /* No outputs */
1918 : "r" (0),
1919 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1920
1921 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1922 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1923 "membar #Sync"
1924 : /* no outputs */
1925 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1926 spitfire_put_itlb_data(i, 0x0UL);
1927 }
1928 }
1929 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1930 cheetah_flush_dtlb_all();
1931 cheetah_flush_itlb_all();
1932 }
1933 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1934 : : "r" (pstate));
1935}
88d70794
DM		 1936
1937#ifdef CONFIG_MEMORY_HOTPLUG
1938
1939void online_page(struct page *page)
1940{
1941 ClearPageReserved(page);
fcab1e51
NP		 1942 init_page_count(page);
1943 __free_page(page);
88d70794
DM		 1944 totalram_pages++;
1945 num_physpages++;
1946}
1947
88d70794 1948#endif /* CONFIG_MEMORY_HOTPLUG */
kernel source for telekom puls (alcatel/mediatek)