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[PATCH] Kprobes: prevent possible race conditions ia64 changes
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / sparc64 / mm / init.c
CommitLineData
1da177e4
LT		 1/* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#include <linux/config.h>
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/string.h>
12#include <linux/init.h>
13#include <linux/bootmem.h>
14#include <linux/mm.h>
15#include <linux/hugetlb.h>
16#include <linux/slab.h>
17#include <linux/initrd.h>
18#include <linux/swap.h>
19#include <linux/pagemap.h>
20#include <linux/fs.h>
21#include <linux/seq_file.h>
22
23#include <asm/head.h>
24#include <asm/system.h>
25#include <asm/page.h>
26#include <asm/pgalloc.h>
27#include <asm/pgtable.h>
28#include <asm/oplib.h>
29#include <asm/iommu.h>
30#include <asm/io.h>
31#include <asm/uaccess.h>
32#include <asm/mmu_context.h>
33#include <asm/tlbflush.h>
34#include <asm/dma.h>
35#include <asm/starfire.h>
36#include <asm/tlb.h>
37#include <asm/spitfire.h>
38#include <asm/sections.h>
39
40extern void device_scan(void);
41
42struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS];
43
44unsigned long *sparc64_valid_addr_bitmap;
45
46/* Ugly, but necessary... -DaveM */
47unsigned long phys_base;
48unsigned long kern_base;
49unsigned long kern_size;
50unsigned long pfn_base;
51
52/* This is even uglier. We have a problem where the kernel may not be
53 * located at phys_base. However, initial __alloc_bootmem() calls need to
54 * be adjusted to be within the 4-8Megs that the kernel is mapped to, else
55 * those page mappings wont work. Things are ok after inherit_prom_mappings
56 * is called though. Dave says he'll clean this up some other time.
57 * -- BenC
58 */
59static unsigned long bootmap_base;
60
61/* get_new_mmu_context() uses "cache + 1". */
62DEFINE_SPINLOCK(ctx_alloc_lock);
63unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
64#define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
65unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
66
67/* References to special section boundaries */
68extern char _start[], _end[];
69
70/* Initial ramdisk setup */
71extern unsigned long sparc_ramdisk_image64;
72extern unsigned int sparc_ramdisk_image;
73extern unsigned int sparc_ramdisk_size;
74
75struct page *mem_map_zero;
76
77int bigkernel = 0;
78
79/* XXX Tune this... */
80#define PGT_CACHE_LOW 25
81#define PGT_CACHE_HIGH 50
82
83void check_pgt_cache(void)
84{
85 preempt_disable();
86 if (pgtable_cache_size > PGT_CACHE_HIGH) {
87 do {
88 if (pgd_quicklist)
89 free_pgd_slow(get_pgd_fast());
90 if (pte_quicklist[0])
91 free_pte_slow(pte_alloc_one_fast(NULL, 0));
92 if (pte_quicklist[1])
93 free_pte_slow(pte_alloc_one_fast(NULL, 1 << (PAGE_SHIFT + 10)));
94 } while (pgtable_cache_size > PGT_CACHE_LOW);
95 }
96 preempt_enable();
97}
98
99#ifdef CONFIG_DEBUG_DCFLUSH
100atomic_t dcpage_flushes = ATOMIC_INIT(0);
101#ifdef CONFIG_SMP
102atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
103#endif
104#endif
105
106__inline__ void flush_dcache_page_impl(struct page *page)
107{
108#ifdef CONFIG_DEBUG_DCFLUSH
109 atomic_inc(&dcpage_flushes);
110#endif
111
112#ifdef DCACHE_ALIASING_POSSIBLE
113 __flush_dcache_page(page_address(page),
114 ((tlb_type == spitfire) &&
115 page_mapping(page) != NULL));
116#else
117 if (page_mapping(page) != NULL &&
118 tlb_type == spitfire)
119 __flush_icache_page(__pa(page_address(page)));
120#endif
121}
122
123#define PG_dcache_dirty PG_arch_1
48b0e548
DM		 124#define PG_dcache_cpu_shift 24
125#define PG_dcache_cpu_mask (256 - 1)
126
127#if NR_CPUS > 256
128#error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
129#endif
1da177e4
LT		 130
131#define dcache_dirty_cpu(page) \
48b0e548 132 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
1da177e4
LT		 133
134static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
135{
136 unsigned long mask = this_cpu;
48b0e548
DM		 137 unsigned long non_cpu_bits;
138
139 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
140 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
141
1da177e4
LT		 142 __asm__ __volatile__("1:\n\t"
143 "ldx [%2], %%g7\n\t"
144 "and %%g7, %1, %%g1\n\t"
145 "or %%g1, %0, %%g1\n\t"
146 "casx [%2], %%g7, %%g1\n\t"
147 "cmp %%g7, %%g1\n\t"
b445e26c 148 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 149 "bne,pn %%xcc, 1b\n\t"
b445e26c 150 " nop"
1da177e4
LT		 151 : /* no outputs */
152 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
153 : "g1", "g7");
154}
155
156static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
157{
158 unsigned long mask = (1UL << PG_dcache_dirty);
159
160 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
161 "1:\n\t"
162 "ldx [%2], %%g7\n\t"
48b0e548 163 "srlx %%g7, %4, %%g1\n\t"
1da177e4
LT		 164 "and %%g1, %3, %%g1\n\t"
165 "cmp %%g1, %0\n\t"
166 "bne,pn %%icc, 2f\n\t"
167 " andn %%g7, %1, %%g1\n\t"
168 "casx [%2], %%g7, %%g1\n\t"
169 "cmp %%g7, %%g1\n\t"
b445e26c 170 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 171 "bne,pn %%xcc, 1b\n\t"
b445e26c 172 " nop\n"
1da177e4
LT		 173 "2:"
174 : /* no outputs */
175 : "r" (cpu), "r" (mask), "r" (&page->flags),
48b0e548
DM		 176 "i" (PG_dcache_cpu_mask),
177 "i" (PG_dcache_cpu_shift)
1da177e4
LT		 178 : "g1", "g7");
179}
180
181extern void __update_mmu_cache(unsigned long mmu_context_hw, unsigned long address, pte_t pte, int code);
182
183void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
184{
185 struct page *page;
186 unsigned long pfn;
187 unsigned long pg_flags;
188
189 pfn = pte_pfn(pte);
190 if (pfn_valid(pfn) &&
191 (page = pfn_to_page(pfn), page_mapping(page)) &&
192 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
48b0e548
DM		 193 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
194 PG_dcache_cpu_mask);
1da177e4
LT		 195 int this_cpu = get_cpu();
196
197 /* This is just to optimize away some function calls
198 * in the SMP case.
199 */
200 if (cpu == this_cpu)
201 flush_dcache_page_impl(page);
202 else
203 smp_flush_dcache_page_impl(page, cpu);
204
205 clear_dcache_dirty_cpu(page, cpu);
206
207 put_cpu();
208 }
209
210 if (get_thread_fault_code())
211 __update_mmu_cache(CTX_NRBITS(vma->vm_mm->context),
212 address, pte, get_thread_fault_code());
213}
214
215void flush_dcache_page(struct page *page)
216{
a9546f59
DM		 217 struct address_space *mapping;
218 int this_cpu;
1da177e4 219
a9546f59
DM		 220 /* Do not bother with the expensive D-cache flush if it
221 * is merely the zero page. The 'bigcore' testcase in GDB
222 * causes this case to run millions of times.
223 */
224 if (page == ZERO_PAGE(0))
225 return;
226
227 this_cpu = get_cpu();
228
229 mapping = page_mapping(page);
1da177e4 230 if (mapping && !mapping_mapped(mapping)) {
a9546f59 231 int dirty = test_bit(PG_dcache_dirty, &page->flags);
1da177e4 232 if (dirty) {
a9546f59
DM		 233 int dirty_cpu = dcache_dirty_cpu(page);
234
1da177e4
LT		 235 if (dirty_cpu == this_cpu)
236 goto out;
237 smp_flush_dcache_page_impl(page, dirty_cpu);
238 }
239 set_dcache_dirty(page, this_cpu);
240 } else {
241 /* We could delay the flush for the !page_mapping
242 * case too. But that case is for exec env/arg
243 * pages and those are %99 certainly going to get
244 * faulted into the tlb (and thus flushed) anyways.
245 */
246 flush_dcache_page_impl(page);
247 }
248
249out:
250 put_cpu();
251}
252
253void flush_icache_range(unsigned long start, unsigned long end)
254{
255 /* Cheetah has coherent I-cache. */
256 if (tlb_type == spitfire) {
257 unsigned long kaddr;
258
259 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
260 __flush_icache_page(__get_phys(kaddr));
261 }
262}
263
264unsigned long page_to_pfn(struct page *page)
265{
266 return (unsigned long) ((page - mem_map) + pfn_base);
267}
268
269struct page *pfn_to_page(unsigned long pfn)
270{
271 return (mem_map + (pfn - pfn_base));
272}
273
274void show_mem(void)
275{
276 printk("Mem-info:\n");
277 show_free_areas();
278 printk("Free swap: %6ldkB\n",
279 nr_swap_pages << (PAGE_SHIFT-10));
280 printk("%ld pages of RAM\n", num_physpages);
281 printk("%d free pages\n", nr_free_pages());
282 printk("%d pages in page table cache\n",pgtable_cache_size);
283}
284
285void mmu_info(struct seq_file *m)
286{
287 if (tlb_type == cheetah)
288 seq_printf(m, "MMU Type\t: Cheetah\n");
289 else if (tlb_type == cheetah_plus)
290 seq_printf(m, "MMU Type\t: Cheetah+\n");
291 else if (tlb_type == spitfire)
292 seq_printf(m, "MMU Type\t: Spitfire\n");
293 else
294 seq_printf(m, "MMU Type\t: ???\n");
295
296#ifdef CONFIG_DEBUG_DCFLUSH
297 seq_printf(m, "DCPageFlushes\t: %d\n",
298 atomic_read(&dcpage_flushes));
299#ifdef CONFIG_SMP
300 seq_printf(m, "DCPageFlushesXC\t: %d\n",
301 atomic_read(&dcpage_flushes_xcall));
302#endif /* CONFIG_SMP */
303#endif /* CONFIG_DEBUG_DCFLUSH */
304}
305
306struct linux_prom_translation {
307 unsigned long virt;
308 unsigned long size;
309 unsigned long data;
310};
311
312extern unsigned long prom_boot_page;
313extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
314extern int prom_get_mmu_ihandle(void);
315extern void register_prom_callbacks(void);
316
317/* Exported for SMP bootup purposes. */
318unsigned long kern_locked_tte_data;
319
320void __init early_pgtable_allocfail(char *type)
321{
322 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
323 prom_halt();
324}
325
326#define BASE_PAGE_SIZE 8192
327static pmd_t *prompmd;
328
329/*
330 * Translate PROM's mapping we capture at boot time into physical address.
331 * The second parameter is only set from prom_callback() invocations.
332 */
333unsigned long prom_virt_to_phys(unsigned long promva, int *error)
334{
335 pmd_t *pmdp = prompmd + ((promva >> 23) & 0x7ff);
336 pte_t *ptep;
337 unsigned long base;
338
339 if (pmd_none(*pmdp)) {
340 if (error)
341 *error = 1;
342 return(0);
343 }
344 ptep = (pte_t *)__pmd_page(*pmdp) + ((promva >> 13) & 0x3ff);
345 if (!pte_present(*ptep)) {
346 if (error)
347 *error = 1;
348 return(0);
349 }
350 if (error) {
351 *error = 0;
352 return(pte_val(*ptep));
353 }
354 base = pte_val(*ptep) & _PAGE_PADDR;
355 return(base + (promva & (BASE_PAGE_SIZE - 1)));
356}
357
358static void inherit_prom_mappings(void)
359{
360 struct linux_prom_translation *trans;
361 unsigned long phys_page, tte_vaddr, tte_data;
362 void (*remap_func)(unsigned long, unsigned long, int);
363 pmd_t *pmdp;
364 pte_t *ptep;
365 int node, n, i, tsz;
366 extern unsigned int obp_iaddr_patch[2], obp_daddr_patch[2];
367
368 node = prom_finddevice("/virtual-memory");
369 n = prom_getproplen(node, "translations");
370 if (n == 0 || n == -1) {
371 prom_printf("Couldn't get translation property\n");
372 prom_halt();
373 }
374 n += 5 * sizeof(struct linux_prom_translation);
375 for (tsz = 1; tsz < n; tsz <<= 1)
376 /* empty */;
377 trans = __alloc_bootmem(tsz, SMP_CACHE_BYTES, bootmap_base);
378 if (trans == NULL) {
379 prom_printf("inherit_prom_mappings: Cannot alloc translations.\n");
380 prom_halt();
381 }
382 memset(trans, 0, tsz);
383
384 if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) {
385 prom_printf("Couldn't get translation property\n");
386 prom_halt();
387 }
388 n = n / sizeof(*trans);
389
390 /*
391 * The obp translations are saved based on 8k pagesize, since obp can
392 * use a mixture of pagesizes. Misses to the 0xf0000000 - 0x100000000,
393 * ie obp range, are handled in entry.S and do not use the vpte scheme
394 * (see rant in inherit_locked_prom_mappings()).
395 */
396#define OBP_PMD_SIZE 2048
397 prompmd = __alloc_bootmem(OBP_PMD_SIZE, OBP_PMD_SIZE, bootmap_base);
398 if (prompmd == NULL)
399 early_pgtable_allocfail("pmd");
400 memset(prompmd, 0, OBP_PMD_SIZE);
401 for (i = 0; i < n; i++) {
402 unsigned long vaddr;
403
404 if (trans[i].virt >= LOW_OBP_ADDRESS && trans[i].virt < HI_OBP_ADDRESS) {
405 for (vaddr = trans[i].virt;
406 ((vaddr < trans[i].virt + trans[i].size) &&
407 (vaddr < HI_OBP_ADDRESS));
408 vaddr += BASE_PAGE_SIZE) {
409 unsigned long val;
410
411 pmdp = prompmd + ((vaddr >> 23) & 0x7ff);
412 if (pmd_none(*pmdp)) {
413 ptep = __alloc_bootmem(BASE_PAGE_SIZE,
414 BASE_PAGE_SIZE,
415 bootmap_base);
416 if (ptep == NULL)
417 early_pgtable_allocfail("pte");
418 memset(ptep, 0, BASE_PAGE_SIZE);
419 pmd_set(pmdp, ptep);
420 }
421 ptep = (pte_t *)__pmd_page(*pmdp) +
422 ((vaddr >> 13) & 0x3ff);
423
424 val = trans[i].data;
425
426 /* Clear diag TTE bits. */
427 if (tlb_type == spitfire)
428 val &= ~0x0003fe0000000000UL;
429
430 set_pte_at(&init_mm, vaddr,
431 ptep, __pte(val | _PAGE_MODIFIED));
432 trans[i].data += BASE_PAGE_SIZE;
433 }
434 }
435 }
436 phys_page = __pa(prompmd);
437 obp_iaddr_patch[0] |= (phys_page >> 10);
438 obp_iaddr_patch[1] |= (phys_page & 0x3ff);
439 flushi((long)&obp_iaddr_patch[0]);
440 obp_daddr_patch[0] |= (phys_page >> 10);
441 obp_daddr_patch[1] |= (phys_page & 0x3ff);
442 flushi((long)&obp_daddr_patch[0]);
443
444 /* Now fixup OBP's idea about where we really are mapped. */
445 prom_printf("Remapping the kernel... ");
446
447 /* Spitfire Errata #32 workaround */
448 /* NOTE: Using plain zero for the context value is
449 * correct here, we are not using the Linux trap
450 * tables yet so we should not use the special
451 * UltraSPARC-III+ page size encodings yet.
452 */
453 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
454 "flush %%g6"
455 : /* No outputs */
456 : "r" (0), "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
457
458 switch (tlb_type) {
459 default:
460 case spitfire:
461 phys_page = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
462 break;
463
464 case cheetah:
465 case cheetah_plus:
466 phys_page = cheetah_get_litlb_data(sparc64_highest_locked_tlbent());
467 break;
468 };
469
470 phys_page &= _PAGE_PADDR;
471 phys_page += ((unsigned long)&prom_boot_page -
472 (unsigned long)KERNBASE);
473
474 if (tlb_type == spitfire) {
475 /* Lock this into i/d tlb entry 59 */
476 __asm__ __volatile__(
477 "stxa %%g0, [%2] %3\n\t"
478 "stxa %0, [%1] %4\n\t"
479 "membar #Sync\n\t"
480 "flush %%g6\n\t"
481 "stxa %%g0, [%2] %5\n\t"
482 "stxa %0, [%1] %6\n\t"
483 "membar #Sync\n\t"
484 "flush %%g6"
485 : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
486 _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
487 "r" (59 << 3), "r" (TLB_TAG_ACCESS),
488 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
489 "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
490 : "memory");
491 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
492 /* Lock this into i/d tlb-0 entry 11 */
493 __asm__ __volatile__(
494 "stxa %%g0, [%2] %3\n\t"
495 "stxa %0, [%1] %4\n\t"
496 "membar #Sync\n\t"
497 "flush %%g6\n\t"
498 "stxa %%g0, [%2] %5\n\t"
499 "stxa %0, [%1] %6\n\t"
500 "membar #Sync\n\t"
501 "flush %%g6"
502 : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
503 _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
504 "r" ((0 << 16) | (11 << 3)), "r" (TLB_TAG_ACCESS),
505 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
506 "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
507 : "memory");
508 } else {
509 /* Implement me :-) */
510 BUG();
511 }
512
513 tte_vaddr = (unsigned long) KERNBASE;
514
515 /* Spitfire Errata #32 workaround */
516 /* NOTE: Using plain zero for the context value is
517 * correct here, we are not using the Linux trap
518 * tables yet so we should not use the special
519 * UltraSPARC-III+ page size encodings yet.
520 */
521 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
522 "flush %%g6"
523 : /* No outputs */
524 : "r" (0),
525 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
526
527 if (tlb_type == spitfire)
528 tte_data = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
529 else
530 tte_data = cheetah_get_ldtlb_data(sparc64_highest_locked_tlbent());
531
532 kern_locked_tte_data = tte_data;
533
534 remap_func = (void *) ((unsigned long) &prom_remap -
535 (unsigned long) &prom_boot_page);
536
537
538 /* Spitfire Errata #32 workaround */
539 /* NOTE: Using plain zero for the context value is
540 * correct here, we are not using the Linux trap
541 * tables yet so we should not use the special
542 * UltraSPARC-III+ page size encodings yet.
543 */
544 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
545 "flush %%g6"
546 : /* No outputs */
547 : "r" (0),
548 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
549
550 remap_func((tlb_type == spitfire ?
551 (spitfire_get_dtlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR) :
552 (cheetah_get_litlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR)),
553 (unsigned long) KERNBASE,
554 prom_get_mmu_ihandle());
555
556 if (bigkernel)
557 remap_func(((tte_data + 0x400000) & _PAGE_PADDR),
558 (unsigned long) KERNBASE + 0x400000, prom_get_mmu_ihandle());
559
560 /* Flush out that temporary mapping. */
561 spitfire_flush_dtlb_nucleus_page(0x0);
562 spitfire_flush_itlb_nucleus_page(0x0);
563
564 /* Now lock us back into the TLBs via OBP. */
565 prom_dtlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
566 prom_itlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
567 if (bigkernel) {
568 prom_dtlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
569 tte_vaddr + 0x400000);
570 prom_itlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
571 tte_vaddr + 0x400000);
572 }
573
574 /* Re-read translations property. */
575 if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) {
576 prom_printf("Couldn't get translation property\n");
577 prom_halt();
578 }
579 n = n / sizeof(*trans);
580
581 for (i = 0; i < n; i++) {
582 unsigned long vaddr = trans[i].virt;
583 unsigned long size = trans[i].size;
584
585 if (vaddr < 0xf0000000UL) {
586 unsigned long avoid_start = (unsigned long) KERNBASE;
587 unsigned long avoid_end = avoid_start + (4 * 1024 * 1024);
588
589 if (bigkernel)
590 avoid_end += (4 * 1024 * 1024);
591 if (vaddr < avoid_start) {
592 unsigned long top = vaddr + size;
593
594 if (top > avoid_start)
595 top = avoid_start;
596 prom_unmap(top - vaddr, vaddr);
597 }
598 if ((vaddr + size) > avoid_end) {
599 unsigned long bottom = vaddr;
600
601 if (bottom < avoid_end)
602 bottom = avoid_end;
603 prom_unmap((vaddr + size) - bottom, bottom);
604 }
605 }
606 }
607
608 prom_printf("done.\n");
609
610 register_prom_callbacks();
611}
612
613/* The OBP specifications for sun4u mark 0xfffffffc00000000 and
614 * upwards as reserved for use by the firmware (I wonder if this
615 * will be the same on Cheetah...). We use this virtual address
616 * range for the VPTE table mappings of the nucleus so we need
617 * to zap them when we enter the PROM. -DaveM
618 */
619static void __flush_nucleus_vptes(void)
620{
621 unsigned long prom_reserved_base = 0xfffffffc00000000UL;
622 int i;
623
624 /* Only DTLB must be checked for VPTE entries. */
625 if (tlb_type == spitfire) {
626 for (i = 0; i < 63; i++) {
627 unsigned long tag;
628
629 /* Spitfire Errata #32 workaround */
630 /* NOTE: Always runs on spitfire, so no cheetah+
631 * page size encodings.
632 */
633 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
634 "flush %%g6"
635 : /* No outputs */
636 : "r" (0),
637 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
638
639 tag = spitfire_get_dtlb_tag(i);
640 if (((tag & ~(PAGE_MASK)) == 0) &&
641 ((tag & (PAGE_MASK)) >= prom_reserved_base)) {
642 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
643 "membar #Sync"
644 : /* no outputs */
645 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
646 spitfire_put_dtlb_data(i, 0x0UL);
647 }
648 }
649 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
650 for (i = 0; i < 512; i++) {
651 unsigned long tag = cheetah_get_dtlb_tag(i, 2);
652
653 if ((tag & ~PAGE_MASK) == 0 &&
654 (tag & PAGE_MASK) >= prom_reserved_base) {
655 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
656 "membar #Sync"
657 : /* no outputs */
658 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
659 cheetah_put_dtlb_data(i, 0x0UL, 2);
660 }
661
662 if (tlb_type != cheetah_plus)
663 continue;
664
665 tag = cheetah_get_dtlb_tag(i, 3);
666
667 if ((tag & ~PAGE_MASK) == 0 &&
668 (tag & PAGE_MASK) >= prom_reserved_base) {
669 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
670 "membar #Sync"
671 : /* no outputs */
672 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
673 cheetah_put_dtlb_data(i, 0x0UL, 3);
674 }
675 }
676 } else {
677 /* Implement me :-) */
678 BUG();
679 }
680}
681
682static int prom_ditlb_set;
683struct prom_tlb_entry {
684 int tlb_ent;
685 unsigned long tlb_tag;
686 unsigned long tlb_data;
687};
688struct prom_tlb_entry prom_itlb[16], prom_dtlb[16];
689
690void prom_world(int enter)
691{
692 unsigned long pstate;
693 int i;
694
695 if (!enter)
696 set_fs((mm_segment_t) { get_thread_current_ds() });
697
698 if (!prom_ditlb_set)
699 return;
700
701 /* Make sure the following runs atomically. */
702 __asm__ __volatile__("flushw\n\t"
703 "rdpr %%pstate, %0\n\t"
704 "wrpr %0, %1, %%pstate"
705 : "=r" (pstate)
706 : "i" (PSTATE_IE));
707
708 if (enter) {
709 /* Kick out nucleus VPTEs. */
710 __flush_nucleus_vptes();
711
712 /* Install PROM world. */
713 for (i = 0; i < 16; i++) {
714 if (prom_dtlb[i].tlb_ent != -1) {
715 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
716 "membar #Sync"
717 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
718 "i" (ASI_DMMU));
719 if (tlb_type == spitfire)
720 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
721 prom_dtlb[i].tlb_data);
722 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
723 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
724 prom_dtlb[i].tlb_data);
725 }
726 if (prom_itlb[i].tlb_ent != -1) {
727 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
728 "membar #Sync"
729 : : "r" (prom_itlb[i].tlb_tag),
730 "r" (TLB_TAG_ACCESS),
731 "i" (ASI_IMMU));
732 if (tlb_type == spitfire)
733 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
734 prom_itlb[i].tlb_data);
735 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
736 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
737 prom_itlb[i].tlb_data);
738 }
739 }
740 } else {
741 for (i = 0; i < 16; i++) {
742 if (prom_dtlb[i].tlb_ent != -1) {
743 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
744 "membar #Sync"
745 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
746 if (tlb_type == spitfire)
747 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
748 else
749 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
750 }
751 if (prom_itlb[i].tlb_ent != -1) {
752 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
753 "membar #Sync"
754 : : "r" (TLB_TAG_ACCESS),
755 "i" (ASI_IMMU));
756 if (tlb_type == spitfire)
757 spitfire_put_itlb_data(prom_itlb[i].tlb_ent, 0x0UL);
758 else
759 cheetah_put_litlb_data(prom_itlb[i].tlb_ent, 0x0UL);
760 }
761 }
762 }
763 __asm__ __volatile__("wrpr %0, 0, %%pstate"
764 : : "r" (pstate));
765}
766
767void inherit_locked_prom_mappings(int save_p)
768{
769 int i;
770 int dtlb_seen = 0;
771 int itlb_seen = 0;
772
773 /* Fucking losing PROM has more mappings in the TLB, but
774 * it (conveniently) fails to mention any of these in the
775 * translations property. The only ones that matter are
776 * the locked PROM tlb entries, so we impose the following
777 * irrecovable rule on the PROM, it is allowed 8 locked
778 * entries in the ITLB and 8 in the DTLB.
779 *
780 * Supposedly the upper 16GB of the address space is
781 * reserved for OBP, BUT I WISH THIS WAS DOCUMENTED
782 * SOMEWHERE!!!!!!!!!!!!!!!!! Furthermore the entire interface
783 * used between the client program and the firmware on sun5
784 * systems to coordinate mmu mappings is also COMPLETELY
785 * UNDOCUMENTED!!!!!! Thanks S(t)un!
786 */
787 if (save_p) {
788 for (i = 0; i < 16; i++) {
789 prom_itlb[i].tlb_ent = -1;
790 prom_dtlb[i].tlb_ent = -1;
791 }
792 }
793 if (tlb_type == spitfire) {
794 int high = SPITFIRE_HIGHEST_LOCKED_TLBENT - bigkernel;
795 for (i = 0; i < high; i++) {
796 unsigned long data;
797
798 /* Spitfire Errata #32 workaround */
799 /* NOTE: Always runs on spitfire, so no cheetah+
800 * page size encodings.
801 */
802 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
803 "flush %%g6"
804 : /* No outputs */
805 : "r" (0),
806 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
807
808 data = spitfire_get_dtlb_data(i);
809 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
810 unsigned long tag;
811
812 /* Spitfire Errata #32 workaround */
813 /* NOTE: Always runs on spitfire, so no
814 * cheetah+ page size encodings.
815 */
816 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
817 "flush %%g6"
818 : /* No outputs */
819 : "r" (0),
820 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
821
822 tag = spitfire_get_dtlb_tag(i);
823 if (save_p) {
824 prom_dtlb[dtlb_seen].tlb_ent = i;
825 prom_dtlb[dtlb_seen].tlb_tag = tag;
826 prom_dtlb[dtlb_seen].tlb_data = data;
827 }
828 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
829 "membar #Sync"
830 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
831 spitfire_put_dtlb_data(i, 0x0UL);
832
833 dtlb_seen++;
834 if (dtlb_seen > 15)
835 break;
836 }
837 }
838
839 for (i = 0; i < high; i++) {
840 unsigned long data;
841
842 /* Spitfire Errata #32 workaround */
843 /* NOTE: Always runs on spitfire, so no
844 * cheetah+ page size encodings.
845 */
846 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
847 "flush %%g6"
848 : /* No outputs */
849 : "r" (0),
850 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
851
852 data = spitfire_get_itlb_data(i);
853 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
854 unsigned long tag;
855
856 /* Spitfire Errata #32 workaround */
857 /* NOTE: Always runs on spitfire, so no
858 * cheetah+ page size encodings.
859 */
860 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
861 "flush %%g6"
862 : /* No outputs */
863 : "r" (0),
864 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
865
866 tag = spitfire_get_itlb_tag(i);
867 if (save_p) {
868 prom_itlb[itlb_seen].tlb_ent = i;
869 prom_itlb[itlb_seen].tlb_tag = tag;
870 prom_itlb[itlb_seen].tlb_data = data;
871 }
872 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
873 "membar #Sync"
874 : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
875 spitfire_put_itlb_data(i, 0x0UL);
876
877 itlb_seen++;
878 if (itlb_seen > 15)
879 break;
880 }
881 }
882 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
883 int high = CHEETAH_HIGHEST_LOCKED_TLBENT - bigkernel;
884
885 for (i = 0; i < high; i++) {
886 unsigned long data;
887
888 data = cheetah_get_ldtlb_data(i);
889 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
890 unsigned long tag;
891
892 tag = cheetah_get_ldtlb_tag(i);
893 if (save_p) {
894 prom_dtlb[dtlb_seen].tlb_ent = i;
895 prom_dtlb[dtlb_seen].tlb_tag = tag;
896 prom_dtlb[dtlb_seen].tlb_data = data;
897 }
898 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
899 "membar #Sync"
900 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
901 cheetah_put_ldtlb_data(i, 0x0UL);
902
903 dtlb_seen++;
904 if (dtlb_seen > 15)
905 break;
906 }
907 }
908
909 for (i = 0; i < high; i++) {
910 unsigned long data;
911
912 data = cheetah_get_litlb_data(i);
913 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
914 unsigned long tag;
915
916 tag = cheetah_get_litlb_tag(i);
917 if (save_p) {
918 prom_itlb[itlb_seen].tlb_ent = i;
919 prom_itlb[itlb_seen].tlb_tag = tag;
920 prom_itlb[itlb_seen].tlb_data = data;
921 }
922 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
923 "membar #Sync"
924 : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
925 cheetah_put_litlb_data(i, 0x0UL);
926
927 itlb_seen++;
928 if (itlb_seen > 15)
929 break;
930 }
931 }
932 } else {
933 /* Implement me :-) */
934 BUG();
935 }
936 if (save_p)
937 prom_ditlb_set = 1;
938}
939
940/* Give PROM back his world, done during reboots... */
941void prom_reload_locked(void)
942{
943 int i;
944
945 for (i = 0; i < 16; i++) {
946 if (prom_dtlb[i].tlb_ent != -1) {
947 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
948 "membar #Sync"
949 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
950 "i" (ASI_DMMU));
951 if (tlb_type == spitfire)
952 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
953 prom_dtlb[i].tlb_data);
954 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
955 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
956 prom_dtlb[i].tlb_data);
957 }
958
959 if (prom_itlb[i].tlb_ent != -1) {
960 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
961 "membar #Sync"
962 : : "r" (prom_itlb[i].tlb_tag),
963 "r" (TLB_TAG_ACCESS),
964 "i" (ASI_IMMU));
965 if (tlb_type == spitfire)
966 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
967 prom_itlb[i].tlb_data);
968 else
969 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
970 prom_itlb[i].tlb_data);
971 }
972 }
973}
974
975#ifdef DCACHE_ALIASING_POSSIBLE
976void __flush_dcache_range(unsigned long start, unsigned long end)
977{
978 unsigned long va;
979
980 if (tlb_type == spitfire) {
981 int n = 0;
982
983 for (va = start; va < end; va += 32) {
984 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
985 if (++n >= 512)
986 break;
987 }
988 } else {
989 start = __pa(start);
990 end = __pa(end);
991 for (va = start; va < end; va += 32)
992 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
993 "membar #Sync"
994 : /* no outputs */
995 : "r" (va),
996 "i" (ASI_DCACHE_INVALIDATE));
997 }
998}
999#endif /* DCACHE_ALIASING_POSSIBLE */
1000
1001/* If not locked, zap it. */
1002void __flush_tlb_all(void)
1003{
1004 unsigned long pstate;
1005 int i;
1006
1007 __asm__ __volatile__("flushw\n\t"
1008 "rdpr %%pstate, %0\n\t"
1009 "wrpr %0, %1, %%pstate"
1010 : "=r" (pstate)
1011 : "i" (PSTATE_IE));
1012 if (tlb_type == spitfire) {
1013 for (i = 0; i < 64; i++) {
1014 /* Spitfire Errata #32 workaround */
1015 /* NOTE: Always runs on spitfire, so no
1016 * cheetah+ page size encodings.
1017 */
1018 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1019 "flush %%g6"
1020 : /* No outputs */
1021 : "r" (0),
1022 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1023
1024 if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
1025 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1026 "membar #Sync"
1027 : /* no outputs */
1028 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1029 spitfire_put_dtlb_data(i, 0x0UL);
1030 }
1031
1032 /* Spitfire Errata #32 workaround */
1033 /* NOTE: Always runs on spitfire, so no
1034 * cheetah+ page size encodings.
1035 */
1036 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1037 "flush %%g6"
1038 : /* No outputs */
1039 : "r" (0),
1040 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1041
1042 if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
1043 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1044 "membar #Sync"
1045 : /* no outputs */
1046 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1047 spitfire_put_itlb_data(i, 0x0UL);
1048 }
1049 }
1050 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1051 cheetah_flush_dtlb_all();
1052 cheetah_flush_itlb_all();
1053 }
1054 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1055 : : "r" (pstate));
1056}
1057
1058/* Caller does TLB context flushing on local CPU if necessary.
1059 * The caller also ensures that CTX_VALID(mm->context) is false.
1060 *
1061 * We must be careful about boundary cases so that we never
1062 * let the user have CTX 0 (nucleus) or we ever use a CTX
1063 * version of zero (and thus NO_CONTEXT would not be caught
1064 * by version mis-match tests in mmu_context.h).
1065 */
1066void get_new_mmu_context(struct mm_struct *mm)
1067{
1068 unsigned long ctx, new_ctx;
1069 unsigned long orig_pgsz_bits;
1070
1071
1072 spin_lock(&ctx_alloc_lock);
1073 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
1074 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
1075 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
1076 if (new_ctx >= (1 << CTX_NR_BITS)) {
1077 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
1078 if (new_ctx >= ctx) {
1079 int i;
1080 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
1081 CTX_FIRST_VERSION;
1082 if (new_ctx == 1)
1083 new_ctx = CTX_FIRST_VERSION;
1084
1085 /* Don't call memset, for 16 entries that's just
1086 * plain silly...
1087 */
1088 mmu_context_bmap[0] = 3;
1089 mmu_context_bmap[1] = 0;
1090 mmu_context_bmap[2] = 0;
1091 mmu_context_bmap[3] = 0;
1092 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
1093 mmu_context_bmap[i + 0] = 0;
1094 mmu_context_bmap[i + 1] = 0;
1095 mmu_context_bmap[i + 2] = 0;
1096 mmu_context_bmap[i + 3] = 0;
1097 }
1098 goto out;
1099 }
1100 }
1101 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
1102 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
1103out:
1104 tlb_context_cache = new_ctx;
1105 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
1106 spin_unlock(&ctx_alloc_lock);
1107}
1108
1109#ifndef CONFIG_SMP
1110struct pgtable_cache_struct pgt_quicklists;
1111#endif
1112
1113/* OK, we have to color these pages. The page tables are accessed
1114 * by non-Dcache enabled mapping in the VPTE area by the dtlb_backend.S
1115 * code, as well as by PAGE_OFFSET range direct-mapped addresses by
1116 * other parts of the kernel. By coloring, we make sure that the tlbmiss
1117 * fast handlers do not get data from old/garbage dcache lines that
1118 * correspond to an old/stale virtual address (user/kernel) that
1119 * previously mapped the pagetable page while accessing vpte range
1120 * addresses. The idea is that if the vpte color and PAGE_OFFSET range
1121 * color is the same, then when the kernel initializes the pagetable
1122 * using the later address range, accesses with the first address
1123 * range will see the newly initialized data rather than the garbage.
1124 */
1125#ifdef DCACHE_ALIASING_POSSIBLE
1126#define DC_ALIAS_SHIFT 1
1127#else
1128#define DC_ALIAS_SHIFT 0
1129#endif
8edf72eb 1130pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
1da177e4
LT		 1131{
1132 struct page *page;
1133 unsigned long color;
1134
1135 {
1136 pte_t *ptep = pte_alloc_one_fast(mm, address);
1137
1138 if (ptep)
1139 return ptep;
1140 }
1141
1142 color = VPTE_COLOR(address);
1143 page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, DC_ALIAS_SHIFT);
1144 if (page) {
1145 unsigned long *to_free;
1146 unsigned long paddr;
1147 pte_t *pte;
1148
1149#ifdef DCACHE_ALIASING_POSSIBLE
1150 set_page_count(page, 1);
1151 ClearPageCompound(page);
1152
1153 set_page_count((page + 1), 1);
1154 ClearPageCompound(page + 1);
1155#endif
1156 paddr = (unsigned long) page_address(page);
1157 memset((char *)paddr, 0, (PAGE_SIZE << DC_ALIAS_SHIFT));
1158
1159 if (!color) {
1160 pte = (pte_t *) paddr;
1161 to_free = (unsigned long *) (paddr + PAGE_SIZE);
1162 } else {
1163 pte = (pte_t *) (paddr + PAGE_SIZE);
1164 to_free = (unsigned long *) paddr;
1165 }
1166
1167#ifdef DCACHE_ALIASING_POSSIBLE
1168 /* Now free the other one up, adjust cache size. */
1169 preempt_disable();
1170 *to_free = (unsigned long) pte_quicklist[color ^ 0x1];
1171 pte_quicklist[color ^ 0x1] = to_free;
1172 pgtable_cache_size++;
1173 preempt_enable();
1174#endif
1175
1176 return pte;
1177 }
1178 return NULL;
1179}
1180
1181void sparc_ultra_dump_itlb(void)
1182{
1183 int slot;
1184
1185 if (tlb_type == spitfire) {
1186 printk ("Contents of itlb: ");
1187 for (slot = 0; slot < 14; slot++) printk (" ");
1188 printk ("%2x:%016lx,%016lx\n",
1189 0,
1190 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
1191 for (slot = 1; slot < 64; slot+=3) {
1192 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1193 slot,
1194 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
1195 slot+1,
1196 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
1197 slot+2,
1198 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
1199 }
1200 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1201 printk ("Contents of itlb0:\n");
1202 for (slot = 0; slot < 16; slot+=2) {
1203 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1204 slot,
1205 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
1206 slot+1,
1207 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
1208 }
1209 printk ("Contents of itlb2:\n");
1210 for (slot = 0; slot < 128; slot+=2) {
1211 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1212 slot,
1213 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
1214 slot+1,
1215 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
1216 }
1217 }
1218}
1219
1220void sparc_ultra_dump_dtlb(void)
1221{
1222 int slot;
1223
1224 if (tlb_type == spitfire) {
1225 printk ("Contents of dtlb: ");
1226 for (slot = 0; slot < 14; slot++) printk (" ");
1227 printk ("%2x:%016lx,%016lx\n", 0,
1228 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
1229 for (slot = 1; slot < 64; slot+=3) {
1230 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1231 slot,
1232 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
1233 slot+1,
1234 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
1235 slot+2,
1236 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
1237 }
1238 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1239 printk ("Contents of dtlb0:\n");
1240 for (slot = 0; slot < 16; slot+=2) {
1241 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1242 slot,
1243 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
1244 slot+1,
1245 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
1246 }
1247 printk ("Contents of dtlb2:\n");
1248 for (slot = 0; slot < 512; slot+=2) {
1249 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1250 slot,
1251 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
1252 slot+1,
1253 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
1254 }
1255 if (tlb_type == cheetah_plus) {
1256 printk ("Contents of dtlb3:\n");
1257 for (slot = 0; slot < 512; slot+=2) {
1258 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1259 slot,
1260 cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
1261 slot+1,
1262 cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
1263 }
1264 }
1265 }
1266}
1267
1268extern unsigned long cmdline_memory_size;
1269
1270unsigned long __init bootmem_init(unsigned long *pages_avail)
1271{
1272 unsigned long bootmap_size, start_pfn, end_pfn;
1273 unsigned long end_of_phys_memory = 0UL;
1274 unsigned long bootmap_pfn, bytes_avail, size;
1275 int i;
1276
1277#ifdef CONFIG_DEBUG_BOOTMEM
1278 prom_printf("bootmem_init: Scan sp_banks, ");
1279#endif
1280
1281 bytes_avail = 0UL;
1282 for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1283 end_of_phys_memory = sp_banks[i].base_addr +
1284 sp_banks[i].num_bytes;
1285 bytes_avail += sp_banks[i].num_bytes;
1286 if (cmdline_memory_size) {
1287 if (bytes_avail > cmdline_memory_size) {
1288 unsigned long slack = bytes_avail - cmdline_memory_size;
1289
1290 bytes_avail -= slack;
1291 end_of_phys_memory -= slack;
1292
1293 sp_banks[i].num_bytes -= slack;
1294 if (sp_banks[i].num_bytes == 0) {
1295 sp_banks[i].base_addr = 0xdeadbeef;
1296 } else {
1297 sp_banks[i+1].num_bytes = 0;
1298 sp_banks[i+1].base_addr = 0xdeadbeef;
1299 }
1300 break;
1301 }
1302 }
1303 }
1304
1305 *pages_avail = bytes_avail >> PAGE_SHIFT;
1306
1307 /* Start with page aligned address of last symbol in kernel
1308 * image. The kernel is hard mapped below PAGE_OFFSET in a
1309 * 4MB locked TLB translation.
1310 */
1311 start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
1312
1313 bootmap_pfn = start_pfn;
1314
1315 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1316
1317#ifdef CONFIG_BLK_DEV_INITRD
1318 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
1319 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
1320 unsigned long ramdisk_image = sparc_ramdisk_image ?
1321 sparc_ramdisk_image : sparc_ramdisk_image64;
1322 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
1323 ramdisk_image -= KERNBASE;
1324 initrd_start = ramdisk_image + phys_base;
1325 initrd_end = initrd_start + sparc_ramdisk_size;
1326 if (initrd_end > end_of_phys_memory) {
1327 printk(KERN_CRIT "initrd extends beyond end of memory "
1328 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1329 initrd_end, end_of_phys_memory);
1330 initrd_start = 0;
1331 }
1332 if (initrd_start) {
1333 if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
1334 initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
1335 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
1336 }
1337 }
1338#endif
1339 /* Initialize the boot-time allocator. */
1340 max_pfn = max_low_pfn = end_pfn;
1341 min_low_pfn = pfn_base;
1342
1343#ifdef CONFIG_DEBUG_BOOTMEM
1344 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1345 min_low_pfn, bootmap_pfn, max_low_pfn);
1346#endif
1347 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
1348
1349 bootmap_base = bootmap_pfn << PAGE_SHIFT;
1350
1351 /* Now register the available physical memory with the
1352 * allocator.
1353 */
1354 for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1355#ifdef CONFIG_DEBUG_BOOTMEM
1356 prom_printf("free_bootmem(sp_banks:%d): base[%lx] size[%lx]\n",
1357 i, sp_banks[i].base_addr, sp_banks[i].num_bytes);
1358#endif
1359 free_bootmem(sp_banks[i].base_addr, sp_banks[i].num_bytes);
1360 }
1361
1362#ifdef CONFIG_BLK_DEV_INITRD
1363 if (initrd_start) {
1364 size = initrd_end - initrd_start;
1365
1366 /* Resert the initrd image area. */
1367#ifdef CONFIG_DEBUG_BOOTMEM
1368 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
1369 initrd_start, initrd_end);
1370#endif
1371 reserve_bootmem(initrd_start, size);
1372 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1373
1374 initrd_start += PAGE_OFFSET;
1375 initrd_end += PAGE_OFFSET;
1376 }
1377#endif
1378 /* Reserve the kernel text/data/bss. */
1379#ifdef CONFIG_DEBUG_BOOTMEM
1380 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1381#endif
1382 reserve_bootmem(kern_base, kern_size);
1383 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1384
1385 /* Reserve the bootmem map. We do not account for it
1386 * in pages_avail because we will release that memory
1387 * in free_all_bootmem.
1388 */
1389 size = bootmap_size;
1390#ifdef CONFIG_DEBUG_BOOTMEM
1391 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1392 (bootmap_pfn << PAGE_SHIFT), size);
1393#endif
1394 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1395 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1396
1397 return end_pfn;
1398}
1399
1400/* paging_init() sets up the page tables */
1401
1402extern void cheetah_ecache_flush_init(void);
1403
1404static unsigned long last_valid_pfn;
1405
1406void __init paging_init(void)
1407{
1408 extern pmd_t swapper_pmd_dir[1024];
1409 extern unsigned int sparc64_vpte_patchme1[1];
1410 extern unsigned int sparc64_vpte_patchme2[1];
1411 unsigned long alias_base = kern_base + PAGE_OFFSET;
1412 unsigned long second_alias_page = 0;
1413 unsigned long pt, flags, end_pfn, pages_avail;
1414 unsigned long shift = alias_base - ((unsigned long)KERNBASE);
1415 unsigned long real_end;
1416
1417 set_bit(0, mmu_context_bmap);
1418
1419 real_end = (unsigned long)_end;
1420 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1421 bigkernel = 1;
1422#ifdef CONFIG_BLK_DEV_INITRD
1423 if (sparc_ramdisk_image || sparc_ramdisk_image64)
1424 real_end = (PAGE_ALIGN(real_end) + PAGE_ALIGN(sparc_ramdisk_size));
1425#endif
1426
1427 /* We assume physical memory starts at some 4mb multiple,
1428 * if this were not true we wouldn't boot up to this point
1429 * anyways.
1430 */
1431 pt = kern_base | _PAGE_VALID | _PAGE_SZ4MB;
1432 pt |= _PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W;
1433 local_irq_save(flags);
1434 if (tlb_type == spitfire) {
1435 __asm__ __volatile__(
1436 " stxa %1, [%0] %3\n"
1437 " stxa %2, [%5] %4\n"
1438 " membar #Sync\n"
1439 " flush %%g6\n"
1440 " nop\n"
1441 " nop\n"
1442 " nop\n"
1443 : /* No outputs */
1444 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1445 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (61 << 3)
1446 : "memory");
1447 if (real_end >= KERNBASE + 0x340000) {
1448 second_alias_page = alias_base + 0x400000;
1449 __asm__ __volatile__(
1450 " stxa %1, [%0] %3\n"
1451 " stxa %2, [%5] %4\n"
1452 " membar #Sync\n"
1453 " flush %%g6\n"
1454 " nop\n"
1455 " nop\n"
1456 " nop\n"
1457 : /* No outputs */
1458 : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1459 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (60 << 3)
1460 : "memory");
1461 }
1462 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1463 __asm__ __volatile__(
1464 " stxa %1, [%0] %3\n"
1465 " stxa %2, [%5] %4\n"
1466 " membar #Sync\n"
1467 " flush %%g6\n"
1468 " nop\n"
1469 " nop\n"
1470 " nop\n"
1471 : /* No outputs */
1472 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1473 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (13<<3))
1474 : "memory");
1475 if (real_end >= KERNBASE + 0x340000) {
1476 second_alias_page = alias_base + 0x400000;
1477 __asm__ __volatile__(
1478 " stxa %1, [%0] %3\n"
1479 " stxa %2, [%5] %4\n"
1480 " membar #Sync\n"
1481 " flush %%g6\n"
1482 " nop\n"
1483 " nop\n"
1484 " nop\n"
1485 : /* No outputs */
1486 : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1487 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (12<<3))
1488 : "memory");
1489 }
1490 }
1491 local_irq_restore(flags);
1492
1493 /* Now set kernel pgd to upper alias so physical page computations
1494 * work.
1495 */
1496 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1497
1498 memset(swapper_pmd_dir, 0, sizeof(swapper_pmd_dir));
1499
1500 /* Now can init the kernel/bad page tables. */
1501 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1502 swapper_pmd_dir + (shift / sizeof(pgd_t)));
1503
1504 sparc64_vpte_patchme1[0] |=
1505 (((unsigned long)pgd_val(init_mm.pgd[0])) >> 10);
1506 sparc64_vpte_patchme2[0] |=
1507 (((unsigned long)pgd_val(init_mm.pgd[0])) & 0x3ff);
1508 flushi((long)&sparc64_vpte_patchme1[0]);
1509
1510 /* Setup bootmem... */
1511 pages_avail = 0;
1512 last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1513
1514 /* Inherit non-locked OBP mappings. */
1515 inherit_prom_mappings();
1516
1517 /* Ok, we can use our TLB miss and window trap handlers safely.
1518 * We need to do a quick peek here to see if we are on StarFire
1519 * or not, so setup_tba can setup the IRQ globals correctly (it
1520 * needs to get the hard smp processor id correctly).
1521 */
1522 {
1523 extern void setup_tba(int);
1524 setup_tba(this_is_starfire);
1525 }
1526
1527 inherit_locked_prom_mappings(1);
1528
1529 /* We only created DTLB mapping of this stuff. */
1530 spitfire_flush_dtlb_nucleus_page(alias_base);
1531 if (second_alias_page)
1532 spitfire_flush_dtlb_nucleus_page(second_alias_page);
1533
1534 __flush_tlb_all();
1535
1536 {
1537 unsigned long zones_size[MAX_NR_ZONES];
1538 unsigned long zholes_size[MAX_NR_ZONES];
1539 unsigned long npages;
1540 int znum;
1541
1542 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1543 zones_size[znum] = zholes_size[znum] = 0;
1544
1545 npages = end_pfn - pfn_base;
1546 zones_size[ZONE_DMA] = npages;
1547 zholes_size[ZONE_DMA] = npages - pages_avail;
1548
1549 free_area_init_node(0, &contig_page_data, zones_size,
1550 phys_base >> PAGE_SHIFT, zholes_size);
1551 }
1552
1553 device_scan();
1554}
1555
1556/* Ok, it seems that the prom can allocate some more memory chunks
1557 * as a side effect of some prom calls we perform during the
1558 * boot sequence. My most likely theory is that it is from the
1559 * prom_set_traptable() call, and OBP is allocating a scratchpad
1560 * for saving client program register state etc.
1561 */
1562static void __init sort_memlist(struct linux_mlist_p1275 *thislist)
1563{
1564 int swapi = 0;
1565 int i, mitr;
1566 unsigned long tmpaddr, tmpsize;
1567 unsigned long lowest;
1568
1569 for (i = 0; thislist[i].theres_more != 0; i++) {
1570 lowest = thislist[i].start_adr;
1571 for (mitr = i+1; thislist[mitr-1].theres_more != 0; mitr++)
1572 if (thislist[mitr].start_adr < lowest) {
1573 lowest = thislist[mitr].start_adr;
1574 swapi = mitr;
1575 }
1576 if (lowest == thislist[i].start_adr)
1577 continue;
1578 tmpaddr = thislist[swapi].start_adr;
1579 tmpsize = thislist[swapi].num_bytes;
1580 for (mitr = swapi; mitr > i; mitr--) {
1581 thislist[mitr].start_adr = thislist[mitr-1].start_adr;
1582 thislist[mitr].num_bytes = thislist[mitr-1].num_bytes;
1583 }
1584 thislist[i].start_adr = tmpaddr;
1585 thislist[i].num_bytes = tmpsize;
1586 }
1587}
1588
1589void __init rescan_sp_banks(void)
1590{
1591 struct linux_prom64_registers memlist[64];
1592 struct linux_mlist_p1275 avail[64], *mlist;
1593 unsigned long bytes, base_paddr;
1594 int num_regs, node = prom_finddevice("/memory");
1595 int i;
1596
1597 num_regs = prom_getproperty(node, "available",
1598 (char *) memlist, sizeof(memlist));
1599 num_regs = (num_regs / sizeof(struct linux_prom64_registers));
1600 for (i = 0; i < num_regs; i++) {
1601 avail[i].start_adr = memlist[i].phys_addr;
1602 avail[i].num_bytes = memlist[i].reg_size;
1603 avail[i].theres_more = &avail[i + 1];
1604 }
1605 avail[i - 1].theres_more = NULL;
1606 sort_memlist(avail);
1607
1608 mlist = &avail[0];
1609 i = 0;
1610 bytes = mlist->num_bytes;
1611 base_paddr = mlist->start_adr;
1612
1613 sp_banks[0].base_addr = base_paddr;
1614 sp_banks[0].num_bytes = bytes;
1615
1616 while (mlist->theres_more != NULL){
1617 i++;
1618 mlist = mlist->theres_more;
1619 bytes = mlist->num_bytes;
1620 if (i >= SPARC_PHYS_BANKS-1) {
1621 printk ("The machine has more banks than "
1622 "this kernel can support\n"
1623 "Increase the SPARC_PHYS_BANKS "
1624 "setting (currently %d)\n",
1625 SPARC_PHYS_BANKS);
1626 i = SPARC_PHYS_BANKS-1;
1627 break;
1628 }
1629
1630 sp_banks[i].base_addr = mlist->start_adr;
1631 sp_banks[i].num_bytes = mlist->num_bytes;
1632 }
1633
1634 i++;
1635 sp_banks[i].base_addr = 0xdeadbeefbeefdeadUL;
1636 sp_banks[i].num_bytes = 0;
1637
1638 for (i = 0; sp_banks[i].num_bytes != 0; i++)
1639 sp_banks[i].num_bytes &= PAGE_MASK;
1640}
1641
1642static void __init taint_real_pages(void)
1643{
1644 struct sparc_phys_banks saved_sp_banks[SPARC_PHYS_BANKS];
1645 int i;
1646
1647 for (i = 0; i < SPARC_PHYS_BANKS; i++) {
1648 saved_sp_banks[i].base_addr =
1649 sp_banks[i].base_addr;
1650 saved_sp_banks[i].num_bytes =
1651 sp_banks[i].num_bytes;
1652 }
1653
1654 rescan_sp_banks();
1655
1656 /* Find changes discovered in the sp_bank rescan and
1657 * reserve the lost portions in the bootmem maps.
1658 */
1659 for (i = 0; saved_sp_banks[i].num_bytes; i++) {
1660 unsigned long old_start, old_end;
1661
1662 old_start = saved_sp_banks[i].base_addr;
1663 old_end = old_start +
1664 saved_sp_banks[i].num_bytes;
1665 while (old_start < old_end) {
1666 int n;
1667
1668 for (n = 0; sp_banks[n].num_bytes; n++) {
1669 unsigned long new_start, new_end;
1670
1671 new_start = sp_banks[n].base_addr;
1672 new_end = new_start + sp_banks[n].num_bytes;
1673
1674 if (new_start <= old_start &&
1675 new_end >= (old_start + PAGE_SIZE)) {
1676 set_bit (old_start >> 22,
1677 sparc64_valid_addr_bitmap);
1678 goto do_next_page;
1679 }
1680 }
1681 reserve_bootmem(old_start, PAGE_SIZE);
1682
1683 do_next_page:
1684 old_start += PAGE_SIZE;
1685 }
1686 }
1687}
1688
1689void __init mem_init(void)
1690{
1691 unsigned long codepages, datapages, initpages;
1692 unsigned long addr, last;
1693 int i;
1694
1695 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1696 i += 1;
1697 sparc64_valid_addr_bitmap = (unsigned long *)
1698 __alloc_bootmem(i << 3, SMP_CACHE_BYTES, bootmap_base);
1699 if (sparc64_valid_addr_bitmap == NULL) {
1700 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1701 prom_halt();
1702 }
1703 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1704
1705 addr = PAGE_OFFSET + kern_base;
1706 last = PAGE_ALIGN(kern_size) + addr;
1707 while (addr < last) {
1708 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1709 addr += PAGE_SIZE;
1710 }
1711
1712 taint_real_pages();
1713
1714 max_mapnr = last_valid_pfn - pfn_base;
1715 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1716
1717#ifdef CONFIG_DEBUG_BOOTMEM
1718 prom_printf("mem_init: Calling free_all_bootmem().\n");
1719#endif
1720 totalram_pages = num_physpages = free_all_bootmem() - 1;
1721
1722 /*
1723 * Set up the zero page, mark it reserved, so that page count
1724 * is not manipulated when freeing the page from user ptes.
1725 */
1726 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1727 if (mem_map_zero == NULL) {
1728 prom_printf("paging_init: Cannot alloc zero page.\n");
1729 prom_halt();
1730 }
1731 SetPageReserved(mem_map_zero);
1732
1733 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1734 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1735 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1736 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1737 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1738 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1739
1740 printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1741 nr_free_pages() << (PAGE_SHIFT-10),
1742 codepages << (PAGE_SHIFT-10),
1743 datapages << (PAGE_SHIFT-10),
1744 initpages << (PAGE_SHIFT-10),
1745 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1746
1747 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1748 cheetah_ecache_flush_init();
1749}
1750
1751void free_initmem (void)
1752{
1753 unsigned long addr, initend;
1754
1755 /*
1756 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1757 */
1758 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1759 initend = (unsigned long)(__init_end) & PAGE_MASK;
1760 for (; addr < initend; addr += PAGE_SIZE) {
1761 unsigned long page;
1762 struct page *p;
1763
1764 page = (addr +
1765 ((unsigned long) __va(kern_base)) -
1766 ((unsigned long) KERNBASE));
1767 memset((void *)addr, 0xcc, PAGE_SIZE);
1768 p = virt_to_page(page);
1769
1770 ClearPageReserved(p);
1771 set_page_count(p, 1);
1772 __free_page(p);
1773 num_physpages++;
1774 totalram_pages++;
1775 }
1776}
1777
1778#ifdef CONFIG_BLK_DEV_INITRD
1779void free_initrd_mem(unsigned long start, unsigned long end)
1780{
1781 if (start < end)
1782 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1783 for (; start < end; start += PAGE_SIZE) {
1784 struct page *p = virt_to_page(start);
1785
1786 ClearPageReserved(p);
1787 set_page_count(p, 1);
1788 __free_page(p);
1789 num_physpages++;
1790 totalram_pages++;
1791 }
1792}
1793#endif
kernel source for telekom puls (alcatel/mediatek)