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[SPARC64]: Put syscall tables after trap table.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / sparc64 / mm / init.c
CommitLineData
1da177e4
LT		 1/* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#include <linux/config.h>
c4bce90e 9#include <linux/module.h>
1da177e4
LT		 10#include <linux/kernel.h>
11#include <linux/sched.h>
12#include <linux/string.h>
13#include <linux/init.h>
14#include <linux/bootmem.h>
15#include <linux/mm.h>
16#include <linux/hugetlb.h>
17#include <linux/slab.h>
18#include <linux/initrd.h>
19#include <linux/swap.h>
20#include <linux/pagemap.h>
21#include <linux/fs.h>
22#include <linux/seq_file.h>
05e14cb3 23#include <linux/kprobes.h>
1ac4f5eb 24#include <linux/cache.h>
13edad7a 25#include <linux/sort.h>
1da177e4
LT		 26
27#include <asm/head.h>
28#include <asm/system.h>
29#include <asm/page.h>
30#include <asm/pgalloc.h>
31#include <asm/pgtable.h>
32#include <asm/oplib.h>
33#include <asm/iommu.h>
34#include <asm/io.h>
35#include <asm/uaccess.h>
36#include <asm/mmu_context.h>
37#include <asm/tlbflush.h>
38#include <asm/dma.h>
39#include <asm/starfire.h>
40#include <asm/tlb.h>
41#include <asm/spitfire.h>
42#include <asm/sections.h>
517af332 43#include <asm/tsb.h>
481295f9 44#include <asm/hypervisor.h>
1da177e4
LT		 45
46extern void device_scan(void);
47
9cc3a1ac
DM		 48#define MAX_PHYS_ADDRESS (1UL << 42UL)
49#define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
50#define KPTE_BITMAP_BYTES \
51 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
52
53unsigned long kern_linear_pte_xor[2] __read_mostly;
54
55/* A bitmap, one bit for every 256MB of physical memory. If the bit
56 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
57 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
58 */
59unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
60
d7744a09
DM		 61/* A special kernel TSB for 4MB and 256MB linear mappings. */
62struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
63
13edad7a
DM		 64#define MAX_BANKS 32
65
66static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
67static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
68static int pavail_ents __initdata;
69static int pavail_rescan_ents __initdata;
70
71static int cmp_p64(const void *a, const void *b)
72{
73 const struct linux_prom64_registers *x = a, *y = b;
74
75 if (x->phys_addr > y->phys_addr)
76 return 1;
77 if (x->phys_addr < y->phys_addr)
78 return -1;
79 return 0;
80}
81
82static void __init read_obp_memory(const char *property,
83 struct linux_prom64_registers *regs,
84 int *num_ents)
85{
86 int node = prom_finddevice("/memory");
87 int prop_size = prom_getproplen(node, property);
88 int ents, ret, i;
89
90 ents = prop_size / sizeof(struct linux_prom64_registers);
91 if (ents > MAX_BANKS) {
92 prom_printf("The machine has more %s property entries than "
93 "this kernel can support (%d).\n",
94 property, MAX_BANKS);
95 prom_halt();
96 }
97
98 ret = prom_getproperty(node, property, (char *) regs, prop_size);
99 if (ret == -1) {
100 prom_printf("Couldn't get %s property from /memory.\n");
101 prom_halt();
102 }
103
104 *num_ents = ents;
10147570 105
13edad7a
DM		 106 /* Sanitize what we got from the firmware, by page aligning
107 * everything.
108 */
109 for (i = 0; i < ents; i++) {
110 unsigned long base, size;
111
112 base = regs[i].phys_addr;
113 size = regs[i].reg_size;
10147570 114
13edad7a
DM		 115 size &= PAGE_MASK;
116 if (base & ~PAGE_MASK) {
117 unsigned long new_base = PAGE_ALIGN(base);
118
119 size -= new_base - base;
120 if ((long) size < 0L)
121 size = 0UL;
122 base = new_base;
123 }
124 regs[i].phys_addr = base;
125 regs[i].reg_size = size;
126 }
c9c10830 127 sort(regs, ents, sizeof(struct linux_prom64_registers),
13edad7a
DM		 128 cmp_p64, NULL);
129}
1da177e4 130
2bdb3cb2 131unsigned long *sparc64_valid_addr_bitmap __read_mostly;
1da177e4
LT		 132
133/* Ugly, but necessary... -DaveM */
1ac4f5eb
DM		 134unsigned long phys_base __read_mostly;
135unsigned long kern_base __read_mostly;
136unsigned long kern_size __read_mostly;
137unsigned long pfn_base __read_mostly;
1da177e4 138
1da177e4
LT		 139/* get_new_mmu_context() uses "cache + 1". */
140DEFINE_SPINLOCK(ctx_alloc_lock);
141unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
142#define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
143unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
144
145/* References to special section boundaries */
146extern char _start[], _end[];
147
148/* Initial ramdisk setup */
149extern unsigned long sparc_ramdisk_image64;
150extern unsigned int sparc_ramdisk_image;
151extern unsigned int sparc_ramdisk_size;
152
1ac4f5eb 153struct page *mem_map_zero __read_mostly;
1da177e4 154
0835ae0f
DM		 155unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
156
157unsigned long sparc64_kern_pri_context __read_mostly;
158unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
159unsigned long sparc64_kern_sec_context __read_mostly;
160
1da177e4
LT		 161int bigkernel = 0;
162
3c936465 163kmem_cache_t *pgtable_cache __read_mostly;
1da177e4 164
3c936465
DM		 165static void zero_ctor(void *addr, kmem_cache_t *cache, unsigned long flags)
166{
167 clear_page(addr);
168}
05e28f9d 169
3c936465 170void pgtable_cache_init(void)
1da177e4 171{
3c936465
DM		 172 pgtable_cache = kmem_cache_create("pgtable_cache",
173 PAGE_SIZE, PAGE_SIZE,
174 SLAB_HWCACHE_ALIGN |
175 SLAB_MUST_HWCACHE_ALIGN,
176 zero_ctor,
177 NULL);
178 if (!pgtable_cache) {
179 prom_printf("pgtable_cache_init(): Could not create!\n");
180 prom_halt();
1da177e4 181 }
1da177e4
LT		 182}
183
184#ifdef CONFIG_DEBUG_DCFLUSH
185atomic_t dcpage_flushes = ATOMIC_INIT(0);
186#ifdef CONFIG_SMP
187atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
188#endif
189#endif
190
191__inline__ void flush_dcache_page_impl(struct page *page)
192{
193#ifdef CONFIG_DEBUG_DCFLUSH
194 atomic_inc(&dcpage_flushes);
195#endif
196
197#ifdef DCACHE_ALIASING_POSSIBLE
198 __flush_dcache_page(page_address(page),
199 ((tlb_type == spitfire) &&
200 page_mapping(page) != NULL));
201#else
202 if (page_mapping(page) != NULL &&
203 tlb_type == spitfire)
204 __flush_icache_page(__pa(page_address(page)));
205#endif
206}
207
208#define PG_dcache_dirty PG_arch_1
48b0e548
DM		 209#define PG_dcache_cpu_shift 24
210#define PG_dcache_cpu_mask (256 - 1)
211
212#if NR_CPUS > 256
213#error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
214#endif
1da177e4
LT		 215
216#define dcache_dirty_cpu(page) \
48b0e548 217 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
1da177e4
LT		 218
219static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
220{
221 unsigned long mask = this_cpu;
48b0e548
DM		 222 unsigned long non_cpu_bits;
223
224 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
225 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
226
1da177e4
LT		 227 __asm__ __volatile__("1:\n\t"
228 "ldx [%2], %%g7\n\t"
229 "and %%g7, %1, %%g1\n\t"
230 "or %%g1, %0, %%g1\n\t"
231 "casx [%2], %%g7, %%g1\n\t"
232 "cmp %%g7, %%g1\n\t"
b445e26c 233 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 234 "bne,pn %%xcc, 1b\n\t"
b445e26c 235 " nop"
1da177e4
LT		 236 : /* no outputs */
237 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
238 : "g1", "g7");
239}
240
241static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
242{
243 unsigned long mask = (1UL << PG_dcache_dirty);
244
245 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
246 "1:\n\t"
247 "ldx [%2], %%g7\n\t"
48b0e548 248 "srlx %%g7, %4, %%g1\n\t"
1da177e4
LT		 249 "and %%g1, %3, %%g1\n\t"
250 "cmp %%g1, %0\n\t"
251 "bne,pn %%icc, 2f\n\t"
252 " andn %%g7, %1, %%g1\n\t"
253 "casx [%2], %%g7, %%g1\n\t"
254 "cmp %%g7, %%g1\n\t"
b445e26c 255 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 256 "bne,pn %%xcc, 1b\n\t"
b445e26c 257 " nop\n"
1da177e4
LT		 258 "2:"
259 : /* no outputs */
260 : "r" (cpu), "r" (mask), "r" (&page->flags),
48b0e548
DM		 261 "i" (PG_dcache_cpu_mask),
262 "i" (PG_dcache_cpu_shift)
1da177e4
LT		 263 : "g1", "g7");
264}
265
517af332
DM		 266static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
267{
268 unsigned long tsb_addr = (unsigned long) ent;
269
3b3ab2eb 270 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
517af332
DM		 271 tsb_addr = __pa(tsb_addr);
272
273 __tsb_insert(tsb_addr, tag, pte);
274}
275
c4bce90e
DM		 276unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
277unsigned long _PAGE_SZBITS __read_mostly;
278
1da177e4
LT		 279void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
280{
bd40791e 281 struct mm_struct *mm;
1da177e4
LT		 282 struct page *page;
283 unsigned long pfn;
284 unsigned long pg_flags;
285
286 pfn = pte_pfn(pte);
287 if (pfn_valid(pfn) &&
288 (page = pfn_to_page(pfn), page_mapping(page)) &&
289 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
48b0e548
DM		 290 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
291 PG_dcache_cpu_mask);
1da177e4
LT		 292 int this_cpu = get_cpu();
293
294 /* This is just to optimize away some function calls
295 * in the SMP case.
296 */
297 if (cpu == this_cpu)
298 flush_dcache_page_impl(page);
299 else
300 smp_flush_dcache_page_impl(page, cpu);
301
302 clear_dcache_dirty_cpu(page, cpu);
303
304 put_cpu();
305 }
bd40791e
DM		 306
307 mm = vma->vm_mm;
b70c0fa1
DM		 308 if ((pte_val(pte) & _PAGE_ALL_SZ_BITS) == _PAGE_SZBITS) {
309 struct tsb *tsb;
310 unsigned long tag;
311
312 tsb = &mm->context.tsb[(address >> PAGE_SHIFT) &
313 (mm->context.tsb_nentries - 1UL)];
8b234274 314 tag = (address >> 22UL);
b70c0fa1
DM		 315 tsb_insert(tsb, tag, pte_val(pte));
316 }
1da177e4
LT		 317}
318
319void flush_dcache_page(struct page *page)
320{
a9546f59
DM		 321 struct address_space *mapping;
322 int this_cpu;
1da177e4 323
a9546f59
DM		 324 /* Do not bother with the expensive D-cache flush if it
325 * is merely the zero page. The 'bigcore' testcase in GDB
326 * causes this case to run millions of times.
327 */
328 if (page == ZERO_PAGE(0))
329 return;
330
331 this_cpu = get_cpu();
332
333 mapping = page_mapping(page);
1da177e4 334 if (mapping && !mapping_mapped(mapping)) {
a9546f59 335 int dirty = test_bit(PG_dcache_dirty, &page->flags);
1da177e4 336 if (dirty) {
a9546f59
DM		 337 int dirty_cpu = dcache_dirty_cpu(page);
338
1da177e4
LT		 339 if (dirty_cpu == this_cpu)
340 goto out;
341 smp_flush_dcache_page_impl(page, dirty_cpu);
342 }
343 set_dcache_dirty(page, this_cpu);
344 } else {
345 /* We could delay the flush for the !page_mapping
346 * case too. But that case is for exec env/arg
347 * pages and those are %99 certainly going to get
348 * faulted into the tlb (and thus flushed) anyways.
349 */
350 flush_dcache_page_impl(page);
351 }
352
353out:
354 put_cpu();
355}
356
05e14cb3 357void __kprobes flush_icache_range(unsigned long start, unsigned long end)
1da177e4 358{
a43fe0e7 359 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
1da177e4
LT		 360 if (tlb_type == spitfire) {
361 unsigned long kaddr;
362
363 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
364 __flush_icache_page(__get_phys(kaddr));
365 }
366}
367
368unsigned long page_to_pfn(struct page *page)
369{
370 return (unsigned long) ((page - mem_map) + pfn_base);
371}
372
373struct page *pfn_to_page(unsigned long pfn)
374{
375 return (mem_map + (pfn - pfn_base));
376}
377
378void show_mem(void)
379{
380 printk("Mem-info:\n");
381 show_free_areas();
382 printk("Free swap: %6ldkB\n",
383 nr_swap_pages << (PAGE_SHIFT-10));
384 printk("%ld pages of RAM\n", num_physpages);
385 printk("%d free pages\n", nr_free_pages());
1da177e4
LT		 386}
387
388void mmu_info(struct seq_file *m)
389{
390 if (tlb_type == cheetah)
391 seq_printf(m, "MMU Type\t: Cheetah\n");
392 else if (tlb_type == cheetah_plus)
393 seq_printf(m, "MMU Type\t: Cheetah+\n");
394 else if (tlb_type == spitfire)
395 seq_printf(m, "MMU Type\t: Spitfire\n");
a43fe0e7
DM		 396 else if (tlb_type == hypervisor)
397 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
1da177e4
LT		 398 else
399 seq_printf(m, "MMU Type\t: ???\n");
400
401#ifdef CONFIG_DEBUG_DCFLUSH
402 seq_printf(m, "DCPageFlushes\t: %d\n",
403 atomic_read(&dcpage_flushes));
404#ifdef CONFIG_SMP
405 seq_printf(m, "DCPageFlushesXC\t: %d\n",
406 atomic_read(&dcpage_flushes_xcall));
407#endif /* CONFIG_SMP */
408#endif /* CONFIG_DEBUG_DCFLUSH */
409}
410
411struct linux_prom_translation {
412 unsigned long virt;
413 unsigned long size;
414 unsigned long data;
415};
c9c10830
DM		 416
417/* Exported for kernel TLB miss handling in ktlb.S */
418struct linux_prom_translation prom_trans[512] __read_mostly;
419unsigned int prom_trans_ents __read_mostly;
1da177e4 420
1da177e4
LT		 421/* Exported for SMP bootup purposes. */
422unsigned long kern_locked_tte_data;
423
c9c10830
DM		 424/* The obp translations are saved based on 8k pagesize, since obp can
425 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
74bf4312 426 * HI_OBP_ADDRESS range are handled in ktlb.S.
c9c10830 427 */
5085b4a5
DM		 428static inline int in_obp_range(unsigned long vaddr)
429{
430 return (vaddr >= LOW_OBP_ADDRESS &&
431 vaddr < HI_OBP_ADDRESS);
432}
433
c9c10830 434static int cmp_ptrans(const void *a, const void *b)
405599bd 435{
c9c10830 436 const struct linux_prom_translation *x = a, *y = b;
405599bd 437
c9c10830
DM		 438 if (x->virt > y->virt)
439 return 1;
440 if (x->virt < y->virt)
441 return -1;
442 return 0;
405599bd
DM		 443}
444
c9c10830 445/* Read OBP translations property into 'prom_trans[]'. */
9ad98c5b 446static void __init read_obp_translations(void)
405599bd 447{
c9c10830 448 int n, node, ents, first, last, i;
1da177e4
LT		 449
450 node = prom_finddevice("/virtual-memory");
451 n = prom_getproplen(node, "translations");
405599bd 452 if (unlikely(n == 0 || n == -1)) {
b206fc4c 453 prom_printf("prom_mappings: Couldn't get size.\n");
1da177e4
LT		 454 prom_halt();
455 }
405599bd
DM		 456 if (unlikely(n > sizeof(prom_trans))) {
457 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
1da177e4
LT		 458 prom_halt();
459 }
405599bd 460
b206fc4c 461 if ((n = prom_getproperty(node, "translations",
405599bd
DM		 462 (char *)&prom_trans[0],
463 sizeof(prom_trans))) == -1) {
b206fc4c 464 prom_printf("prom_mappings: Couldn't get property.\n");
1da177e4
LT		 465 prom_halt();
466 }
9ad98c5b 467
b206fc4c 468 n = n / sizeof(struct linux_prom_translation);
9ad98c5b 469
c9c10830
DM		 470 ents = n;
471
472 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
473 cmp_ptrans, NULL);
474
475 /* Now kick out all the non-OBP entries. */
476 for (i = 0; i < ents; i++) {
477 if (in_obp_range(prom_trans[i].virt))
478 break;
479 }
480 first = i;
481 for (; i < ents; i++) {
482 if (!in_obp_range(prom_trans[i].virt))
483 break;
484 }
485 last = i;
486
487 for (i = 0; i < (last - first); i++) {
488 struct linux_prom_translation *src = &prom_trans[i + first];
489 struct linux_prom_translation *dest = &prom_trans[i];
490
491 *dest = *src;
492 }
493 for (; i < ents; i++) {
494 struct linux_prom_translation *dest = &prom_trans[i];
495 dest->virt = dest->size = dest->data = 0x0UL;
496 }
497
498 prom_trans_ents = last - first;
499
500 if (tlb_type == spitfire) {
501 /* Clear diag TTE bits. */
502 for (i = 0; i < prom_trans_ents; i++)
503 prom_trans[i].data &= ~0x0003fe0000000000UL;
504 }
405599bd 505}
1da177e4 506
d82ace7d
DM		 507static void __init hypervisor_tlb_lock(unsigned long vaddr,
508 unsigned long pte,
509 unsigned long mmu)
510{
164c220f
DM		 511 register unsigned long func asm("%o5");
512 register unsigned long arg0 asm("%o0");
513 register unsigned long arg1 asm("%o1");
514 register unsigned long arg2 asm("%o2");
515 register unsigned long arg3 asm("%o3");
d82ace7d
DM		 516
517 func = HV_FAST_MMU_MAP_PERM_ADDR;
518 arg0 = vaddr;
519 arg1 = 0;
520 arg2 = pte;
521 arg3 = mmu;
522 __asm__ __volatile__("ta 0x80"
523 : "=&r" (func), "=&r" (arg0),
524 "=&r" (arg1), "=&r" (arg2),
525 "=&r" (arg3)
526 : "0" (func), "1" (arg0), "2" (arg1),
527 "3" (arg2), "4" (arg3));
12e126ad
DM		 528 if (arg0 != 0) {
529 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
530 "errors with %lx\n", vaddr, 0, pte, mmu, arg0);
531 prom_halt();
532 }
d82ace7d
DM		 533}
534
c4bce90e
DM		 535static unsigned long kern_large_tte(unsigned long paddr);
536
898cf0ec 537static void __init remap_kernel(void)
405599bd
DM		 538{
539 unsigned long phys_page, tte_vaddr, tte_data;
405599bd
DM		 540 int tlb_ent = sparc64_highest_locked_tlbent();
541
1da177e4 542 tte_vaddr = (unsigned long) KERNBASE;
bff06d55 543 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
c4bce90e 544 tte_data = kern_large_tte(phys_page);
1da177e4
LT		 545
546 kern_locked_tte_data = tte_data;
547
d82ace7d
DM		 548 /* Now lock us into the TLBs via Hypervisor or OBP. */
549 if (tlb_type == hypervisor) {
550 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
551 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
552 if (bigkernel) {
553 tte_vaddr += 0x400000;
554 tte_data += 0x400000;
555 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
556 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
557 }
558 } else {
559 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
560 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
561 if (bigkernel) {
562 tlb_ent -= 1;
563 prom_dtlb_load(tlb_ent,
564 tte_data + 0x400000,
565 tte_vaddr + 0x400000);
566 prom_itlb_load(tlb_ent,
567 tte_data + 0x400000,
568 tte_vaddr + 0x400000);
569 }
570 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
1da177e4 571 }
0835ae0f
DM		 572 if (tlb_type == cheetah_plus) {
573 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
574 CTX_CHEETAH_PLUS_NUC);
575 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
576 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
577 }
405599bd 578}
1da177e4 579
405599bd 580
c9c10830 581static void __init inherit_prom_mappings(void)
9ad98c5b
DM		 582{
583 read_obp_translations();
405599bd
DM		 584
585 /* Now fixup OBP's idea about where we really are mapped. */
586 prom_printf("Remapping the kernel... ");
587 remap_kernel();
1da177e4 588 prom_printf("done.\n");
1da177e4
LT		 589}
590
1da177e4
LT		 591void prom_world(int enter)
592{
1da177e4
LT		 593 if (!enter)
594 set_fs((mm_segment_t) { get_thread_current_ds() });
595
3487d1d4 596 __asm__ __volatile__("flushw");
1da177e4
LT		 597}
598
599#ifdef DCACHE_ALIASING_POSSIBLE
600void __flush_dcache_range(unsigned long start, unsigned long end)
601{
602 unsigned long va;
603
604 if (tlb_type == spitfire) {
605 int n = 0;
606
607 for (va = start; va < end; va += 32) {
608 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
609 if (++n >= 512)
610 break;
611 }
a43fe0e7 612 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1da177e4
LT		 613 start = __pa(start);
614 end = __pa(end);
615 for (va = start; va < end; va += 32)
616 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
617 "membar #Sync"
618 : /* no outputs */
619 : "r" (va),
620 "i" (ASI_DCACHE_INVALIDATE));
621 }
622}
623#endif /* DCACHE_ALIASING_POSSIBLE */
624
1da177e4
LT		 625/* Caller does TLB context flushing on local CPU if necessary.
626 * The caller also ensures that CTX_VALID(mm->context) is false.
627 *
628 * We must be careful about boundary cases so that we never
629 * let the user have CTX 0 (nucleus) or we ever use a CTX
630 * version of zero (and thus NO_CONTEXT would not be caught
631 * by version mis-match tests in mmu_context.h).
632 */
633void get_new_mmu_context(struct mm_struct *mm)
634{
635 unsigned long ctx, new_ctx;
636 unsigned long orig_pgsz_bits;
637
638
639 spin_lock(&ctx_alloc_lock);
640 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
641 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
642 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
643 if (new_ctx >= (1 << CTX_NR_BITS)) {
644 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
645 if (new_ctx >= ctx) {
646 int i;
647 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
648 CTX_FIRST_VERSION;
649 if (new_ctx == 1)
650 new_ctx = CTX_FIRST_VERSION;
651
652 /* Don't call memset, for 16 entries that's just
653 * plain silly...
654 */
655 mmu_context_bmap[0] = 3;
656 mmu_context_bmap[1] = 0;
657 mmu_context_bmap[2] = 0;
658 mmu_context_bmap[3] = 0;
659 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
660 mmu_context_bmap[i + 0] = 0;
661 mmu_context_bmap[i + 1] = 0;
662 mmu_context_bmap[i + 2] = 0;
663 mmu_context_bmap[i + 3] = 0;
664 }
665 goto out;
666 }
667 }
668 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
669 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
670out:
671 tlb_context_cache = new_ctx;
672 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
673 spin_unlock(&ctx_alloc_lock);
674}
675
1da177e4
LT		 676void sparc_ultra_dump_itlb(void)
677{
678 int slot;
679
680 if (tlb_type == spitfire) {
681 printk ("Contents of itlb: ");
682 for (slot = 0; slot < 14; slot++) printk (" ");
683 printk ("%2x:%016lx,%016lx\n",
684 0,
685 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
686 for (slot = 1; slot < 64; slot+=3) {
687 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
688 slot,
689 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
690 slot+1,
691 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
692 slot+2,
693 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
694 }
695 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
696 printk ("Contents of itlb0:\n");
697 for (slot = 0; slot < 16; slot+=2) {
698 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
699 slot,
700 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
701 slot+1,
702 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
703 }
704 printk ("Contents of itlb2:\n");
705 for (slot = 0; slot < 128; slot+=2) {
706 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
707 slot,
708 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
709 slot+1,
710 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
711 }
712 }
713}
714
715void sparc_ultra_dump_dtlb(void)
716{
717 int slot;
718
719 if (tlb_type == spitfire) {
720 printk ("Contents of dtlb: ");
721 for (slot = 0; slot < 14; slot++) printk (" ");
722 printk ("%2x:%016lx,%016lx\n", 0,
723 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
724 for (slot = 1; slot < 64; slot+=3) {
725 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
726 slot,
727 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
728 slot+1,
729 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
730 slot+2,
731 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
732 }
733 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
734 printk ("Contents of dtlb0:\n");
735 for (slot = 0; slot < 16; slot+=2) {
736 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
737 slot,
738 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
739 slot+1,
740 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
741 }
742 printk ("Contents of dtlb2:\n");
743 for (slot = 0; slot < 512; slot+=2) {
744 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
745 slot,
746 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
747 slot+1,
748 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
749 }
750 if (tlb_type == cheetah_plus) {
751 printk ("Contents of dtlb3:\n");
752 for (slot = 0; slot < 512; slot+=2) {
753 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
754 slot,
755 cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
756 slot+1,
757 cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
758 }
759 }
760 }
761}
762
763extern unsigned long cmdline_memory_size;
764
765unsigned long __init bootmem_init(unsigned long *pages_avail)
766{
767 unsigned long bootmap_size, start_pfn, end_pfn;
768 unsigned long end_of_phys_memory = 0UL;
769 unsigned long bootmap_pfn, bytes_avail, size;
770 int i;
771
772#ifdef CONFIG_DEBUG_BOOTMEM
13edad7a 773 prom_printf("bootmem_init: Scan pavail, ");
1da177e4
LT		 774#endif
775
776 bytes_avail = 0UL;
13edad7a
DM		 777 for (i = 0; i < pavail_ents; i++) {
778 end_of_phys_memory = pavail[i].phys_addr +
779 pavail[i].reg_size;
780 bytes_avail += pavail[i].reg_size;
1da177e4
LT		 781 if (cmdline_memory_size) {
782 if (bytes_avail > cmdline_memory_size) {
783 unsigned long slack = bytes_avail - cmdline_memory_size;
784
785 bytes_avail -= slack;
786 end_of_phys_memory -= slack;
787
13edad7a
DM		 788 pavail[i].reg_size -= slack;
789 if ((long)pavail[i].reg_size <= 0L) {
790 pavail[i].phys_addr = 0xdeadbeefUL;
791 pavail[i].reg_size = 0UL;
792 pavail_ents = i;
1da177e4 793 } else {
13edad7a
DM		 794 pavail[i+1].reg_size = 0Ul;
795 pavail[i+1].phys_addr = 0xdeadbeefUL;
796 pavail_ents = i + 1;
1da177e4
LT		 797 }
798 break;
799 }
800 }
801 }
802
803 *pages_avail = bytes_avail >> PAGE_SHIFT;
804
805 /* Start with page aligned address of last symbol in kernel
806 * image. The kernel is hard mapped below PAGE_OFFSET in a
807 * 4MB locked TLB translation.
808 */
809 start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
810
811 bootmap_pfn = start_pfn;
812
813 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
814
815#ifdef CONFIG_BLK_DEV_INITRD
816 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
817 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
818 unsigned long ramdisk_image = sparc_ramdisk_image ?
819 sparc_ramdisk_image : sparc_ramdisk_image64;
820 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
821 ramdisk_image -= KERNBASE;
822 initrd_start = ramdisk_image + phys_base;
823 initrd_end = initrd_start + sparc_ramdisk_size;
824 if (initrd_end > end_of_phys_memory) {
825 printk(KERN_CRIT "initrd extends beyond end of memory "
826 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
827 initrd_end, end_of_phys_memory);
828 initrd_start = 0;
829 }
830 if (initrd_start) {
831 if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
832 initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
833 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
834 }
835 }
836#endif
837 /* Initialize the boot-time allocator. */
838 max_pfn = max_low_pfn = end_pfn;
839 min_low_pfn = pfn_base;
840
841#ifdef CONFIG_DEBUG_BOOTMEM
842 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
843 min_low_pfn, bootmap_pfn, max_low_pfn);
844#endif
845 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
846
1da177e4
LT		 847 /* Now register the available physical memory with the
848 * allocator.
849 */
13edad7a 850 for (i = 0; i < pavail_ents; i++) {
1da177e4 851#ifdef CONFIG_DEBUG_BOOTMEM
13edad7a
DM		 852 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
853 i, pavail[i].phys_addr, pavail[i].reg_size);
1da177e4 854#endif
13edad7a 855 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
1da177e4
LT		 856 }
857
858#ifdef CONFIG_BLK_DEV_INITRD
859 if (initrd_start) {
860 size = initrd_end - initrd_start;
861
862 /* Resert the initrd image area. */
863#ifdef CONFIG_DEBUG_BOOTMEM
864 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
865 initrd_start, initrd_end);
866#endif
867 reserve_bootmem(initrd_start, size);
868 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
869
870 initrd_start += PAGE_OFFSET;
871 initrd_end += PAGE_OFFSET;
872 }
873#endif
874 /* Reserve the kernel text/data/bss. */
875#ifdef CONFIG_DEBUG_BOOTMEM
876 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
877#endif
878 reserve_bootmem(kern_base, kern_size);
879 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
880
881 /* Reserve the bootmem map. We do not account for it
882 * in pages_avail because we will release that memory
883 * in free_all_bootmem.
884 */
885 size = bootmap_size;
886#ifdef CONFIG_DEBUG_BOOTMEM
887 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
888 (bootmap_pfn << PAGE_SHIFT), size);
889#endif
890 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
891 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
892
893 return end_pfn;
894}
895
9cc3a1ac
DM		 896static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
897static int pall_ents __initdata;
898
56425306
DM		 899#ifdef CONFIG_DEBUG_PAGEALLOC
900static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
901{
902 unsigned long vstart = PAGE_OFFSET + pstart;
903 unsigned long vend = PAGE_OFFSET + pend;
904 unsigned long alloc_bytes = 0UL;
905
906 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
13edad7a 907 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
56425306
DM		 908 vstart, vend);
909 prom_halt();
910 }
911
912 while (vstart < vend) {
913 unsigned long this_end, paddr = __pa(vstart);
914 pgd_t *pgd = pgd_offset_k(vstart);
915 pud_t *pud;
916 pmd_t *pmd;
917 pte_t *pte;
918
919 pud = pud_offset(pgd, vstart);
920 if (pud_none(*pud)) {
921 pmd_t *new;
922
923 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
924 alloc_bytes += PAGE_SIZE;
925 pud_populate(&init_mm, pud, new);
926 }
927
928 pmd = pmd_offset(pud, vstart);
929 if (!pmd_present(*pmd)) {
930 pte_t *new;
931
932 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
933 alloc_bytes += PAGE_SIZE;
934 pmd_populate_kernel(&init_mm, pmd, new);
935 }
936
937 pte = pte_offset_kernel(pmd, vstart);
938 this_end = (vstart + PMD_SIZE) & PMD_MASK;
939 if (this_end > vend)
940 this_end = vend;
941
942 while (vstart < this_end) {
943 pte_val(*pte) = (paddr | pgprot_val(prot));
944
945 vstart += PAGE_SIZE;
946 paddr += PAGE_SIZE;
947 pte++;
948 }
949 }
950
951 return alloc_bytes;
952}
953
56425306 954extern unsigned int kvmap_linear_patch[1];
9cc3a1ac
DM		 955#endif /* CONFIG_DEBUG_PAGEALLOC */
956
957static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
958{
959 const unsigned long shift_256MB = 28;
960 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
961 const unsigned long size_256MB = (1UL << shift_256MB);
962
963 while (start < end) {
964 long remains;
965
966 if (start & mask_256MB) {
967 start = (start + size_256MB) & ~mask_256MB;
968 continue;
969 }
970
971 remains = end - start;
972 while (remains >= size_256MB) {
973 unsigned long index = start >> shift_256MB;
974
975 __set_bit(index, kpte_linear_bitmap);
976
977 start += size_256MB;
978 remains -= size_256MB;
979 }
980 }
981}
56425306
DM		 982
983static void __init kernel_physical_mapping_init(void)
984{
9cc3a1ac
DM		 985 unsigned long i;
986#ifdef CONFIG_DEBUG_PAGEALLOC
987 unsigned long mem_alloced = 0UL;
988#endif
56425306 989
13edad7a
DM		 990 read_obp_memory("reg", &pall[0], &pall_ents);
991
992 for (i = 0; i < pall_ents; i++) {
56425306
DM		 993 unsigned long phys_start, phys_end;
994
13edad7a
DM		 995 phys_start = pall[i].phys_addr;
996 phys_end = phys_start + pall[i].reg_size;
9cc3a1ac
DM		 997
998 mark_kpte_bitmap(phys_start, phys_end);
999
1000#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1001 mem_alloced += kernel_map_range(phys_start, phys_end,
1002 PAGE_KERNEL);
9cc3a1ac 1003#endif
56425306
DM		 1004 }
1005
9cc3a1ac 1006#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1007 printk("Allocated %ld bytes for kernel page tables.\n",
1008 mem_alloced);
1009
1010 kvmap_linear_patch[0] = 0x01000000; /* nop */
1011 flushi(&kvmap_linear_patch[0]);
1012
1013 __flush_tlb_all();
9cc3a1ac 1014#endif
56425306
DM		 1015}
1016
9cc3a1ac 1017#ifdef CONFIG_DEBUG_PAGEALLOC
56425306
DM		 1018void kernel_map_pages(struct page *page, int numpages, int enable)
1019{
1020 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1021 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1022
1023 kernel_map_range(phys_start, phys_end,
1024 (enable ? PAGE_KERNEL : __pgprot(0)));
1025
74bf4312
DM		 1026 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1027 PAGE_OFFSET + phys_end);
1028
56425306
DM		 1029 /* we should perform an IPI and flush all tlbs,
1030 * but that can deadlock->flush only current cpu.
1031 */
1032 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1033 PAGE_OFFSET + phys_end);
1034}
1035#endif
1036
10147570
DM		 1037unsigned long __init find_ecache_flush_span(unsigned long size)
1038{
0836a0eb
DM		 1039 int i;
1040
13edad7a
DM		 1041 for (i = 0; i < pavail_ents; i++) {
1042 if (pavail[i].reg_size >= size)
1043 return pavail[i].phys_addr;
0836a0eb
DM		 1044 }
1045
13edad7a 1046 return ~0UL;
0836a0eb
DM		 1047}
1048
517af332
DM		 1049static void __init tsb_phys_patch(void)
1050{
d257d5da 1051 struct tsb_ldquad_phys_patch_entry *pquad;
517af332
DM		 1052 struct tsb_phys_patch_entry *p;
1053
d257d5da
DM		 1054 pquad = &__tsb_ldquad_phys_patch;
1055 while (pquad < &__tsb_ldquad_phys_patch_end) {
1056 unsigned long addr = pquad->addr;
1057
1058 if (tlb_type == hypervisor)
1059 *(unsigned int *) addr = pquad->sun4v_insn;
1060 else
1061 *(unsigned int *) addr = pquad->sun4u_insn;
1062 wmb();
1063 __asm__ __volatile__("flush %0"
1064 : /* no outputs */
1065 : "r" (addr));
1066
1067 pquad++;
1068 }
1069
517af332
DM		 1070 p = &__tsb_phys_patch;
1071 while (p < &__tsb_phys_patch_end) {
1072 unsigned long addr = p->addr;
1073
1074 *(unsigned int *) addr = p->insn;
1075 wmb();
1076 __asm__ __volatile__("flush %0"
1077 : /* no outputs */
1078 : "r" (addr));
1079
1080 p++;
1081 }
1082}
1083
490384e7
DM		 1084/* Don't mark as init, we give this to the Hypervisor. */
1085static struct hv_tsb_descr ktsb_descr[2];
1086extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1087
1088static void __init sun4v_ktsb_init(void)
1089{
1090 unsigned long ktsb_pa;
1091
d7744a09 1092 /* First KTSB for PAGE_SIZE mappings. */
490384e7
DM		 1093 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1094
1095 switch (PAGE_SIZE) {
1096 case 8 * 1024:
1097 default:
1098 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1099 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1100 break;
1101
1102 case 64 * 1024:
1103 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1104 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1105 break;
1106
1107 case 512 * 1024:
1108 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1109 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1110 break;
1111
1112 case 4 * 1024 * 1024:
1113 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1114 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1115 break;
1116 };
1117
3f19a84e 1118 ktsb_descr[0].assoc = 1;
490384e7
DM		 1119 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1120 ktsb_descr[0].ctx_idx = 0;
1121 ktsb_descr[0].tsb_base = ktsb_pa;
1122 ktsb_descr[0].resv = 0;
1123
d7744a09
DM		 1124 /* Second KTSB for 4MB/256MB mappings. */
1125 ktsb_pa = (kern_base +
1126 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1127
1128 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1129 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1130 HV_PGSZ_MASK_256MB);
1131 ktsb_descr[1].assoc = 1;
1132 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1133 ktsb_descr[1].ctx_idx = 0;
1134 ktsb_descr[1].tsb_base = ktsb_pa;
1135 ktsb_descr[1].resv = 0;
490384e7
DM		 1136}
1137
1138void __cpuinit sun4v_ktsb_register(void)
1139{
1140 register unsigned long func asm("%o5");
1141 register unsigned long arg0 asm("%o0");
1142 register unsigned long arg1 asm("%o1");
1143 unsigned long pa;
1144
1145 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1146
1147 func = HV_FAST_MMU_TSB_CTX0;
d7744a09 1148 arg0 = 2;
490384e7
DM		 1149 arg1 = pa;
1150 __asm__ __volatile__("ta %6"
1151 : "=&r" (func), "=&r" (arg0), "=&r" (arg1)
1152 : "0" (func), "1" (arg0), "2" (arg1),
1153 "i" (HV_FAST_TRAP));
1154}
1155
1da177e4
LT		 1156/* paging_init() sets up the page tables */
1157
1158extern void cheetah_ecache_flush_init(void);
d257d5da 1159extern void sun4v_patch_tlb_handlers(void);
1da177e4
LT		 1160
1161static unsigned long last_valid_pfn;
56425306 1162pgd_t swapper_pg_dir[2048];
1da177e4 1163
c4bce90e
DM		 1164static void sun4u_pgprot_init(void);
1165static void sun4v_pgprot_init(void);
1166
1da177e4
LT		 1167void __init paging_init(void)
1168{
2bdb3cb2 1169 unsigned long end_pfn, pages_avail, shift;
0836a0eb
DM		 1170 unsigned long real_end, i;
1171
481295f9
DM		 1172 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1173 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1174
d7744a09 1175 /* Invalidate both kernel TSBs. */
8b234274 1176 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
d7744a09 1177 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
8b234274 1178
c4bce90e
DM		 1179 if (tlb_type == hypervisor)
1180 sun4v_pgprot_init();
1181 else
1182 sun4u_pgprot_init();
1183
d257d5da
DM		 1184 if (tlb_type == cheetah_plus ||
1185 tlb_type == hypervisor)
517af332
DM		 1186 tsb_phys_patch();
1187
490384e7 1188 if (tlb_type == hypervisor) {
d257d5da 1189 sun4v_patch_tlb_handlers();
490384e7
DM		 1190 sun4v_ktsb_init();
1191 }
d257d5da 1192
13edad7a
DM		 1193 /* Find available physical memory... */
1194 read_obp_memory("available", &pavail[0], &pavail_ents);
0836a0eb
DM		 1195
1196 phys_base = 0xffffffffffffffffUL;
13edad7a
DM		 1197 for (i = 0; i < pavail_ents; i++)
1198 phys_base = min(phys_base, pavail[i].phys_addr);
0836a0eb 1199
0836a0eb
DM		 1200 pfn_base = phys_base >> PAGE_SHIFT;
1201
1da177e4
LT		 1202 set_bit(0, mmu_context_bmap);
1203
2bdb3cb2
DM		 1204 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1205
1da177e4
LT		 1206 real_end = (unsigned long)_end;
1207 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1208 bigkernel = 1;
2bdb3cb2
DM		 1209 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1210 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1211 prom_halt();
1da177e4 1212 }
2bdb3cb2
DM		 1213
1214 /* Set kernel pgd to upper alias so physical page computations
1da177e4
LT		 1215 * work.
1216 */
1217 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1218
56425306 1219 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1da177e4
LT		 1220
1221 /* Now can init the kernel/bad page tables. */
1222 pud_set(pud_offset(&swapper_pg_dir[0], 0),
56425306 1223 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1da177e4 1224
c9c10830 1225 inherit_prom_mappings();
5085b4a5 1226
a8b900d8
DM		 1227 /* Ok, we can use our TLB miss and window trap handlers safely. */
1228 setup_tba();
1da177e4 1229
c9c10830 1230 __flush_tlb_all();
9ad98c5b 1231
490384e7
DM		 1232 if (tlb_type == hypervisor)
1233 sun4v_ktsb_register();
1234
2bdb3cb2
DM		 1235 /* Setup bootmem... */
1236 pages_avail = 0;
1237 last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1238
56425306 1239 kernel_physical_mapping_init();
56425306 1240
1da177e4
LT		 1241 {
1242 unsigned long zones_size[MAX_NR_ZONES];
1243 unsigned long zholes_size[MAX_NR_ZONES];
1244 unsigned long npages;
1245 int znum;
1246
1247 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1248 zones_size[znum] = zholes_size[znum] = 0;
1249
1250 npages = end_pfn - pfn_base;
1251 zones_size[ZONE_DMA] = npages;
1252 zholes_size[ZONE_DMA] = npages - pages_avail;
1253
1254 free_area_init_node(0, &contig_page_data, zones_size,
1255 phys_base >> PAGE_SHIFT, zholes_size);
1256 }
1257
1258 device_scan();
1259}
1260
1da177e4
LT		 1261static void __init taint_real_pages(void)
1262{
1da177e4
LT		 1263 int i;
1264
13edad7a 1265 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1da177e4 1266
13edad7a 1267 /* Find changes discovered in the physmem available rescan and
1da177e4
LT		 1268 * reserve the lost portions in the bootmem maps.
1269 */
13edad7a 1270 for (i = 0; i < pavail_ents; i++) {
1da177e4
LT		 1271 unsigned long old_start, old_end;
1272
13edad7a 1273 old_start = pavail[i].phys_addr;
1da177e4 1274 old_end = old_start +
13edad7a 1275 pavail[i].reg_size;
1da177e4
LT		 1276 while (old_start < old_end) {
1277 int n;
1278
13edad7a 1279 for (n = 0; pavail_rescan_ents; n++) {
1da177e4
LT		 1280 unsigned long new_start, new_end;
1281
13edad7a
DM		 1282 new_start = pavail_rescan[n].phys_addr;
1283 new_end = new_start +
1284 pavail_rescan[n].reg_size;
1da177e4
LT		 1285
1286 if (new_start <= old_start &&
1287 new_end >= (old_start + PAGE_SIZE)) {
13edad7a
DM		 1288 set_bit(old_start >> 22,
1289 sparc64_valid_addr_bitmap);
1da177e4
LT		 1290 goto do_next_page;
1291 }
1292 }
1293 reserve_bootmem(old_start, PAGE_SIZE);
1294
1295 do_next_page:
1296 old_start += PAGE_SIZE;
1297 }
1298 }
1299}
1300
1301void __init mem_init(void)
1302{
1303 unsigned long codepages, datapages, initpages;
1304 unsigned long addr, last;
1305 int i;
1306
1307 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1308 i += 1;
2bdb3cb2 1309 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1da177e4
LT		 1310 if (sparc64_valid_addr_bitmap == NULL) {
1311 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1312 prom_halt();
1313 }
1314 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1315
1316 addr = PAGE_OFFSET + kern_base;
1317 last = PAGE_ALIGN(kern_size) + addr;
1318 while (addr < last) {
1319 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1320 addr += PAGE_SIZE;
1321 }
1322
1323 taint_real_pages();
1324
1325 max_mapnr = last_valid_pfn - pfn_base;
1326 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1327
1328#ifdef CONFIG_DEBUG_BOOTMEM
1329 prom_printf("mem_init: Calling free_all_bootmem().\n");
1330#endif
1331 totalram_pages = num_physpages = free_all_bootmem() - 1;
1332
1333 /*
1334 * Set up the zero page, mark it reserved, so that page count
1335 * is not manipulated when freeing the page from user ptes.
1336 */
1337 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1338 if (mem_map_zero == NULL) {
1339 prom_printf("paging_init: Cannot alloc zero page.\n");
1340 prom_halt();
1341 }
1342 SetPageReserved(mem_map_zero);
1343
1344 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1345 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1346 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1347 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1348 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1349 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1350
1351 printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1352 nr_free_pages() << (PAGE_SHIFT-10),
1353 codepages << (PAGE_SHIFT-10),
1354 datapages << (PAGE_SHIFT-10),
1355 initpages << (PAGE_SHIFT-10),
1356 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1357
1358 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1359 cheetah_ecache_flush_init();
1360}
1361
898cf0ec 1362void free_initmem(void)
1da177e4
LT		 1363{
1364 unsigned long addr, initend;
1365
1366 /*
1367 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1368 */
1369 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1370 initend = (unsigned long)(__init_end) & PAGE_MASK;
1371 for (; addr < initend; addr += PAGE_SIZE) {
1372 unsigned long page;
1373 struct page *p;
1374
1375 page = (addr +
1376 ((unsigned long) __va(kern_base)) -
1377 ((unsigned long) KERNBASE));
1378 memset((void *)addr, 0xcc, PAGE_SIZE);
1379 p = virt_to_page(page);
1380
1381 ClearPageReserved(p);
1382 set_page_count(p, 1);
1383 __free_page(p);
1384 num_physpages++;
1385 totalram_pages++;
1386 }
1387}
1388
1389#ifdef CONFIG_BLK_DEV_INITRD
1390void free_initrd_mem(unsigned long start, unsigned long end)
1391{
1392 if (start < end)
1393 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1394 for (; start < end; start += PAGE_SIZE) {
1395 struct page *p = virt_to_page(start);
1396
1397 ClearPageReserved(p);
1398 set_page_count(p, 1);
1399 __free_page(p);
1400 num_physpages++;
1401 totalram_pages++;
1402 }
1403}
1404#endif
c4bce90e 1405
c4bce90e
DM		 1406#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1407#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1408#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1409#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1410#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1411#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1412
1413pgprot_t PAGE_KERNEL __read_mostly;
1414EXPORT_SYMBOL(PAGE_KERNEL);
1415
1416pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1417pgprot_t PAGE_COPY __read_mostly;
0f15952a
DM		 1418
1419pgprot_t PAGE_SHARED __read_mostly;
1420EXPORT_SYMBOL(PAGE_SHARED);
1421
c4bce90e
DM		 1422pgprot_t PAGE_EXEC __read_mostly;
1423unsigned long pg_iobits __read_mostly;
1424
1425unsigned long _PAGE_IE __read_mostly;
b2bef442 1426
c4bce90e 1427unsigned long _PAGE_E __read_mostly;
b2bef442
DM		 1428EXPORT_SYMBOL(_PAGE_E);
1429
c4bce90e 1430unsigned long _PAGE_CACHE __read_mostly;
b2bef442 1431EXPORT_SYMBOL(_PAGE_CACHE);
c4bce90e
DM		 1432
1433static void prot_init_common(unsigned long page_none,
1434 unsigned long page_shared,
1435 unsigned long page_copy,
1436 unsigned long page_readonly,
1437 unsigned long page_exec_bit)
1438{
1439 PAGE_COPY = __pgprot(page_copy);
0f15952a 1440 PAGE_SHARED = __pgprot(page_shared);
c4bce90e
DM		 1441
1442 protection_map[0x0] = __pgprot(page_none);
1443 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1444 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1445 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1446 protection_map[0x4] = __pgprot(page_readonly);
1447 protection_map[0x5] = __pgprot(page_readonly);
1448 protection_map[0x6] = __pgprot(page_copy);
1449 protection_map[0x7] = __pgprot(page_copy);
1450 protection_map[0x8] = __pgprot(page_none);
1451 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1452 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1453 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1454 protection_map[0xc] = __pgprot(page_readonly);
1455 protection_map[0xd] = __pgprot(page_readonly);
1456 protection_map[0xe] = __pgprot(page_shared);
1457 protection_map[0xf] = __pgprot(page_shared);
1458}
1459
1460static void __init sun4u_pgprot_init(void)
1461{
1462 unsigned long page_none, page_shared, page_copy, page_readonly;
1463 unsigned long page_exec_bit;
1464
1465 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1466 _PAGE_CACHE_4U | _PAGE_P_4U |
1467 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1468 _PAGE_EXEC_4U);
1469 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1470 _PAGE_CACHE_4U | _PAGE_P_4U |
1471 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1472 _PAGE_EXEC_4U | _PAGE_L_4U);
1473 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1474
1475 _PAGE_IE = _PAGE_IE_4U;
1476 _PAGE_E = _PAGE_E_4U;
1477 _PAGE_CACHE = _PAGE_CACHE_4U;
1478
1479 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1480 __ACCESS_BITS_4U | _PAGE_E_4U);
1481
9cc3a1ac 1482 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
c4bce90e 1483 0xfffff80000000000;
9cc3a1ac
DM		 1484 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1485 _PAGE_P_4U | _PAGE_W_4U);
1486
1487 /* XXX Should use 256MB on Panther. XXX */
1488 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
c4bce90e
DM		 1489
1490 _PAGE_SZBITS = _PAGE_SZBITS_4U;
1491 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1492 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1493 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1494
1495
1496 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1497 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1498 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1499 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1500 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1501 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1502 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1503
1504 page_exec_bit = _PAGE_EXEC_4U;
1505
1506 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1507 page_exec_bit);
1508}
1509
1510static void __init sun4v_pgprot_init(void)
1511{
1512 unsigned long page_none, page_shared, page_copy, page_readonly;
1513 unsigned long page_exec_bit;
1514
1515 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1516 _PAGE_CACHE_4V | _PAGE_P_4V |
1517 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1518 _PAGE_EXEC_4V);
1519 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1520 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1521
1522 _PAGE_IE = _PAGE_IE_4V;
1523 _PAGE_E = _PAGE_E_4V;
1524 _PAGE_CACHE = _PAGE_CACHE_4V;
1525
9cc3a1ac
DM		 1526 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1527 0xfffff80000000000;
1528 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1529 _PAGE_P_4V | _PAGE_W_4V);
1530
1531 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
c4bce90e 1532 0xfffff80000000000;
9cc3a1ac
DM		 1533 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1534 _PAGE_P_4V | _PAGE_W_4V);
c4bce90e
DM		 1535
1536 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1537 __ACCESS_BITS_4V | _PAGE_E_4V);
1538
1539 _PAGE_SZBITS = _PAGE_SZBITS_4V;
1540 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1541 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1542 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1543 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1544
1545 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1546 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1547 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1548 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1549 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1550 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1551 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1552
1553 page_exec_bit = _PAGE_EXEC_4V;
1554
1555 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1556 page_exec_bit);
1557}
1558
1559unsigned long pte_sz_bits(unsigned long sz)
1560{
1561 if (tlb_type == hypervisor) {
1562 switch (sz) {
1563 case 8 * 1024:
1564 default:
1565 return _PAGE_SZ8K_4V;
1566 case 64 * 1024:
1567 return _PAGE_SZ64K_4V;
1568 case 512 * 1024:
1569 return _PAGE_SZ512K_4V;
1570 case 4 * 1024 * 1024:
1571 return _PAGE_SZ4MB_4V;
1572 };
1573 } else {
1574 switch (sz) {
1575 case 8 * 1024:
1576 default:
1577 return _PAGE_SZ8K_4U;
1578 case 64 * 1024:
1579 return _PAGE_SZ64K_4U;
1580 case 512 * 1024:
1581 return _PAGE_SZ512K_4U;
1582 case 4 * 1024 * 1024:
1583 return _PAGE_SZ4MB_4U;
1584 };
1585 }
1586}
1587
1588pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1589{
1590 pte_t pte;
cf627156
DM		 1591
1592 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
c4bce90e
DM		 1593 pte_val(pte) |= (((unsigned long)space) << 32);
1594 pte_val(pte) |= pte_sz_bits(page_size);
c4bce90e 1595
cf627156 1596 return pte;
c4bce90e
DM		 1597}
1598
1599static unsigned long kern_large_tte(unsigned long paddr)
1600{
1601 unsigned long val;
1602
1603 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1604 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1605 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1606 if (tlb_type == hypervisor)
1607 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1608 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1609 _PAGE_EXEC_4V | _PAGE_W_4V);
1610
1611 return val | paddr;
1612}
1613
1614/*
1615 * Translate PROM's mapping we capture at boot time into physical address.
1616 * The second parameter is only set from prom_callback() invocations.
1617 */
1618unsigned long prom_virt_to_phys(unsigned long promva, int *error)
1619{
1620 unsigned long mask;
1621 int i;
1622
1623 mask = _PAGE_PADDR_4U;
1624 if (tlb_type == hypervisor)
1625 mask = _PAGE_PADDR_4V;
1626
1627 for (i = 0; i < prom_trans_ents; i++) {
1628 struct linux_prom_translation *p = &prom_trans[i];
1629
1630 if (promva >= p->virt &&
1631 promva < (p->virt + p->size)) {
1632 unsigned long base = p->data & mask;
1633
1634 if (error)
1635 *error = 0;
1636 return base + (promva & (8192 - 1));
1637 }
1638 }
1639 if (error)
1640 *error = 1;
1641 return 0UL;
1642}
1643
1644/* XXX We should kill off this ugly thing at so me point. XXX */
1645unsigned long sun4u_get_pte(unsigned long addr)
1646{
1647 pgd_t *pgdp;
1648 pud_t *pudp;
1649 pmd_t *pmdp;
1650 pte_t *ptep;
1651 unsigned long mask = _PAGE_PADDR_4U;
1652
1653 if (tlb_type == hypervisor)
1654 mask = _PAGE_PADDR_4V;
1655
1656 if (addr >= PAGE_OFFSET)
1657 return addr & mask;
1658
1659 if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS))
1660 return prom_virt_to_phys(addr, NULL);
1661
1662 pgdp = pgd_offset_k(addr);
1663 pudp = pud_offset(pgdp, addr);
1664 pmdp = pmd_offset(pudp, addr);
1665 ptep = pte_offset_kernel(pmdp, addr);
1666
1667 return pte_val(*ptep) & mask;
1668}
1669
1670/* If not locked, zap it. */
1671void __flush_tlb_all(void)
1672{
1673 unsigned long pstate;
1674 int i;
1675
1676 __asm__ __volatile__("flushw\n\t"
1677 "rdpr %%pstate, %0\n\t"
1678 "wrpr %0, %1, %%pstate"
1679 : "=r" (pstate)
1680 : "i" (PSTATE_IE));
1681 if (tlb_type == spitfire) {
1682 for (i = 0; i < 64; i++) {
1683 /* Spitfire Errata #32 workaround */
1684 /* NOTE: Always runs on spitfire, so no
1685 * cheetah+ page size encodings.
1686 */
1687 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1688 "flush %%g6"
1689 : /* No outputs */
1690 : "r" (0),
1691 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1692
1693 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1694 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1695 "membar #Sync"
1696 : /* no outputs */
1697 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1698 spitfire_put_dtlb_data(i, 0x0UL);
1699 }
1700
1701 /* Spitfire Errata #32 workaround */
1702 /* NOTE: Always runs on spitfire, so no
1703 * cheetah+ page size encodings.
1704 */
1705 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1706 "flush %%g6"
1707 : /* No outputs */
1708 : "r" (0),
1709 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1710
1711 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1712 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1713 "membar #Sync"
1714 : /* no outputs */
1715 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1716 spitfire_put_itlb_data(i, 0x0UL);
1717 }
1718 }
1719 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1720 cheetah_flush_dtlb_all();
1721 cheetah_flush_itlb_all();
1722 }
1723 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1724 : : "r" (pstate));
1725}
kernel source for telekom puls (alcatel/mediatek)