Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* $Id: time.c,v 1.42 2002/01/23 14:33:55 davem Exp $ |
2 | * time.c: UltraSparc timer and TOD clock support. | |
3 | * | |
4 | * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) | |
6 | * | |
7 | * Based largely on code which is: | |
8 | * | |
9 | * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu) | |
10 | */ | |
11 | ||
1da177e4 LT |
12 | #include <linux/errno.h> |
13 | #include <linux/module.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/param.h> | |
17 | #include <linux/string.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/time.h> | |
21 | #include <linux/timex.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/mc146818rtc.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/profile.h> | |
27 | #include <linux/bcd.h> | |
28 | #include <linux/jiffies.h> | |
29 | #include <linux/cpufreq.h> | |
30 | #include <linux/percpu.h> | |
31 | #include <linux/profile.h> | |
8ba706a9 DM |
32 | #include <linux/miscdevice.h> |
33 | #include <linux/rtc.h> | |
777a4475 | 34 | #include <linux/kernel_stat.h> |
112f4871 DM |
35 | #include <linux/clockchips.h> |
36 | #include <linux/clocksource.h> | |
1da177e4 LT |
37 | |
38 | #include <asm/oplib.h> | |
39 | #include <asm/mostek.h> | |
40 | #include <asm/timer.h> | |
41 | #include <asm/irq.h> | |
42 | #include <asm/io.h> | |
ff0d2fc6 DM |
43 | #include <asm/prom.h> |
44 | #include <asm/of_device.h> | |
1da177e4 LT |
45 | #include <asm/starfire.h> |
46 | #include <asm/smp.h> | |
47 | #include <asm/sections.h> | |
48 | #include <asm/cpudata.h> | |
8ba706a9 | 49 | #include <asm/uaccess.h> |
07f8e5f3 | 50 | #include <asm/prom.h> |
63540ba3 | 51 | #include <asm/irq_regs.h> |
1da177e4 LT |
52 | |
53 | DEFINE_SPINLOCK(mostek_lock); | |
54 | DEFINE_SPINLOCK(rtc_lock); | |
ef0299bf | 55 | void __iomem *mstk48t02_regs = NULL; |
1da177e4 LT |
56 | #ifdef CONFIG_PCI |
57 | unsigned long ds1287_regs = 0UL; | |
d037e053 | 58 | static void __iomem *bq4802_regs; |
1da177e4 LT |
59 | #endif |
60 | ||
ef0299bf AV |
61 | static void __iomem *mstk48t08_regs; |
62 | static void __iomem *mstk48t59_regs; | |
1da177e4 LT |
63 | |
64 | static int set_rtc_mmss(unsigned long); | |
65 | ||
1da177e4 | 66 | #define TICK_PRIV_BIT (1UL << 63) |
112f4871 | 67 | #define TICKCMP_IRQ_BIT (1UL << 63) |
1da177e4 LT |
68 | |
69 | #ifdef CONFIG_SMP | |
70 | unsigned long profile_pc(struct pt_regs *regs) | |
71 | { | |
72 | unsigned long pc = instruction_pointer(regs); | |
73 | ||
74 | if (in_lock_functions(pc)) | |
75 | return regs->u_regs[UREG_RETPC]; | |
76 | return pc; | |
77 | } | |
78 | EXPORT_SYMBOL(profile_pc); | |
79 | #endif | |
80 | ||
81 | static void tick_disable_protection(void) | |
82 | { | |
83 | /* Set things up so user can access tick register for profiling | |
84 | * purposes. Also workaround BB_ERRATA_1 by doing a dummy | |
85 | * read back of %tick after writing it. | |
86 | */ | |
87 | __asm__ __volatile__( | |
88 | " ba,pt %%xcc, 1f\n" | |
89 | " nop\n" | |
90 | " .align 64\n" | |
91 | "1: rd %%tick, %%g2\n" | |
92 | " add %%g2, 6, %%g2\n" | |
93 | " andn %%g2, %0, %%g2\n" | |
94 | " wrpr %%g2, 0, %%tick\n" | |
95 | " rdpr %%tick, %%g0" | |
96 | : /* no outputs */ | |
97 | : "r" (TICK_PRIV_BIT) | |
98 | : "g2"); | |
99 | } | |
100 | ||
112f4871 | 101 | static void tick_disable_irq(void) |
1da177e4 | 102 | { |
1da177e4 | 103 | __asm__ __volatile__( |
1da177e4 | 104 | " ba,pt %%xcc, 1f\n" |
112f4871 | 105 | " nop\n" |
1da177e4 | 106 | " .align 64\n" |
112f4871 | 107 | "1: wr %0, 0x0, %%tick_cmpr\n" |
1da177e4 LT |
108 | " rd %%tick_cmpr, %%g0" |
109 | : /* no outputs */ | |
112f4871 DM |
110 | : "r" (TICKCMP_IRQ_BIT)); |
111 | } | |
112 | ||
113 | static void tick_init_tick(void) | |
114 | { | |
115 | tick_disable_protection(); | |
116 | tick_disable_irq(); | |
1da177e4 LT |
117 | } |
118 | ||
119 | static unsigned long tick_get_tick(void) | |
120 | { | |
121 | unsigned long ret; | |
122 | ||
123 | __asm__ __volatile__("rd %%tick, %0\n\t" | |
124 | "mov %0, %0" | |
125 | : "=r" (ret)); | |
126 | ||
127 | return ret & ~TICK_PRIV_BIT; | |
128 | } | |
129 | ||
112f4871 | 130 | static int tick_add_compare(unsigned long adj) |
1da177e4 | 131 | { |
112f4871 | 132 | unsigned long orig_tick, new_tick, new_compare; |
1da177e4 | 133 | |
112f4871 DM |
134 | __asm__ __volatile__("rd %%tick, %0" |
135 | : "=r" (orig_tick)); | |
1da177e4 | 136 | |
112f4871 | 137 | orig_tick &= ~TICKCMP_IRQ_BIT; |
1da177e4 LT |
138 | |
139 | /* Workaround for Spitfire Errata (#54 I think??), I discovered | |
140 | * this via Sun BugID 4008234, mentioned in Solaris-2.5.1 patch | |
141 | * number 103640. | |
142 | * | |
143 | * On Blackbird writes to %tick_cmpr can fail, the | |
144 | * workaround seems to be to execute the wr instruction | |
145 | * at the start of an I-cache line, and perform a dummy | |
146 | * read back from %tick_cmpr right after writing to it. -DaveM | |
147 | */ | |
112f4871 DM |
148 | __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" |
149 | " add %1, %2, %0\n\t" | |
1da177e4 LT |
150 | ".align 64\n" |
151 | "1:\n\t" | |
152 | "wr %0, 0, %%tick_cmpr\n\t" | |
112f4871 DM |
153 | "rd %%tick_cmpr, %%g0\n\t" |
154 | : "=r" (new_compare) | |
155 | : "r" (orig_tick), "r" (adj)); | |
156 | ||
157 | __asm__ __volatile__("rd %%tick, %0" | |
158 | : "=r" (new_tick)); | |
159 | new_tick &= ~TICKCMP_IRQ_BIT; | |
1da177e4 | 160 | |
112f4871 | 161 | return ((long)(new_tick - (orig_tick+adj))) > 0L; |
1da177e4 LT |
162 | } |
163 | ||
112f4871 | 164 | static unsigned long tick_add_tick(unsigned long adj) |
1da177e4 | 165 | { |
112f4871 | 166 | unsigned long new_tick; |
1da177e4 LT |
167 | |
168 | /* Also need to handle Blackbird bug here too. */ | |
169 | __asm__ __volatile__("rd %%tick, %0\n\t" | |
112f4871 | 170 | "add %0, %1, %0\n\t" |
1da177e4 | 171 | "wrpr %0, 0, %%tick\n\t" |
112f4871 DM |
172 | : "=&r" (new_tick) |
173 | : "r" (adj)); | |
1da177e4 LT |
174 | |
175 | return new_tick; | |
176 | } | |
177 | ||
d369ddd2 | 178 | static struct sparc64_tick_ops tick_operations __read_mostly = { |
112f4871 | 179 | .name = "tick", |
1da177e4 | 180 | .init_tick = tick_init_tick, |
112f4871 | 181 | .disable_irq = tick_disable_irq, |
1da177e4 | 182 | .get_tick = tick_get_tick, |
1da177e4 LT |
183 | .add_tick = tick_add_tick, |
184 | .add_compare = tick_add_compare, | |
185 | .softint_mask = 1UL << 0, | |
186 | }; | |
187 | ||
fc321495 DM |
188 | struct sparc64_tick_ops *tick_ops __read_mostly = &tick_operations; |
189 | ||
112f4871 DM |
190 | static void stick_disable_irq(void) |
191 | { | |
192 | __asm__ __volatile__( | |
193 | "wr %0, 0x0, %%asr25" | |
194 | : /* no outputs */ | |
195 | : "r" (TICKCMP_IRQ_BIT)); | |
196 | } | |
197 | ||
198 | static void stick_init_tick(void) | |
1da177e4 | 199 | { |
7aa62645 DM |
200 | /* Writes to the %tick and %stick register are not |
201 | * allowed on sun4v. The Hypervisor controls that | |
202 | * bit, per-strand. | |
203 | */ | |
204 | if (tlb_type != hypervisor) { | |
205 | tick_disable_protection(); | |
112f4871 | 206 | tick_disable_irq(); |
7aa62645 DM |
207 | |
208 | /* Let the user get at STICK too. */ | |
209 | __asm__ __volatile__( | |
210 | " rd %%asr24, %%g2\n" | |
211 | " andn %%g2, %0, %%g2\n" | |
212 | " wr %%g2, 0, %%asr24" | |
213 | : /* no outputs */ | |
214 | : "r" (TICK_PRIV_BIT) | |
215 | : "g1", "g2"); | |
216 | } | |
1da177e4 | 217 | |
112f4871 | 218 | stick_disable_irq(); |
1da177e4 LT |
219 | } |
220 | ||
221 | static unsigned long stick_get_tick(void) | |
222 | { | |
223 | unsigned long ret; | |
224 | ||
225 | __asm__ __volatile__("rd %%asr24, %0" | |
226 | : "=r" (ret)); | |
227 | ||
228 | return ret & ~TICK_PRIV_BIT; | |
229 | } | |
230 | ||
112f4871 | 231 | static unsigned long stick_add_tick(unsigned long adj) |
1da177e4 | 232 | { |
112f4871 | 233 | unsigned long new_tick; |
1da177e4 LT |
234 | |
235 | __asm__ __volatile__("rd %%asr24, %0\n\t" | |
112f4871 | 236 | "add %0, %1, %0\n\t" |
1da177e4 | 237 | "wr %0, 0, %%asr24\n\t" |
112f4871 DM |
238 | : "=&r" (new_tick) |
239 | : "r" (adj)); | |
1da177e4 LT |
240 | |
241 | return new_tick; | |
242 | } | |
243 | ||
112f4871 | 244 | static int stick_add_compare(unsigned long adj) |
1da177e4 | 245 | { |
112f4871 | 246 | unsigned long orig_tick, new_tick; |
1da177e4 | 247 | |
112f4871 DM |
248 | __asm__ __volatile__("rd %%asr24, %0" |
249 | : "=r" (orig_tick)); | |
250 | orig_tick &= ~TICKCMP_IRQ_BIT; | |
251 | ||
252 | __asm__ __volatile__("wr %0, 0, %%asr25" | |
253 | : /* no outputs */ | |
254 | : "r" (orig_tick + adj)); | |
255 | ||
256 | __asm__ __volatile__("rd %%asr24, %0" | |
257 | : "=r" (new_tick)); | |
258 | new_tick &= ~TICKCMP_IRQ_BIT; | |
1da177e4 | 259 | |
112f4871 | 260 | return ((long)(new_tick - (orig_tick+adj))) > 0L; |
1da177e4 LT |
261 | } |
262 | ||
d369ddd2 | 263 | static struct sparc64_tick_ops stick_operations __read_mostly = { |
112f4871 | 264 | .name = "stick", |
1da177e4 | 265 | .init_tick = stick_init_tick, |
112f4871 | 266 | .disable_irq = stick_disable_irq, |
1da177e4 | 267 | .get_tick = stick_get_tick, |
1da177e4 LT |
268 | .add_tick = stick_add_tick, |
269 | .add_compare = stick_add_compare, | |
270 | .softint_mask = 1UL << 16, | |
271 | }; | |
272 | ||
273 | /* On Hummingbird the STICK/STICK_CMPR register is implemented | |
274 | * in I/O space. There are two 64-bit registers each, the | |
275 | * first holds the low 32-bits of the value and the second holds | |
276 | * the high 32-bits. | |
277 | * | |
278 | * Since STICK is constantly updating, we have to access it carefully. | |
279 | * | |
280 | * The sequence we use to read is: | |
9eb3394b RM |
281 | * 1) read high |
282 | * 2) read low | |
283 | * 3) read high again, if it rolled re-read both low and high again. | |
1da177e4 LT |
284 | * |
285 | * Writing STICK safely is also tricky: | |
286 | * 1) write low to zero | |
287 | * 2) write high | |
288 | * 3) write low | |
289 | */ | |
290 | #define HBIRD_STICKCMP_ADDR 0x1fe0000f060UL | |
291 | #define HBIRD_STICK_ADDR 0x1fe0000f070UL | |
292 | ||
293 | static unsigned long __hbird_read_stick(void) | |
294 | { | |
295 | unsigned long ret, tmp1, tmp2, tmp3; | |
9eb3394b | 296 | unsigned long addr = HBIRD_STICK_ADDR+8; |
1da177e4 | 297 | |
9eb3394b RM |
298 | __asm__ __volatile__("ldxa [%1] %5, %2\n" |
299 | "1:\n\t" | |
1da177e4 | 300 | "sub %1, 0x8, %1\n\t" |
9eb3394b RM |
301 | "ldxa [%1] %5, %3\n\t" |
302 | "add %1, 0x8, %1\n\t" | |
1da177e4 LT |
303 | "ldxa [%1] %5, %4\n\t" |
304 | "cmp %4, %2\n\t" | |
9eb3394b RM |
305 | "bne,a,pn %%xcc, 1b\n\t" |
306 | " mov %4, %2\n\t" | |
307 | "sllx %4, 32, %4\n\t" | |
1da177e4 LT |
308 | "or %3, %4, %0\n\t" |
309 | : "=&r" (ret), "=&r" (addr), | |
310 | "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3) | |
311 | : "i" (ASI_PHYS_BYPASS_EC_E), "1" (addr)); | |
312 | ||
313 | return ret; | |
314 | } | |
315 | ||
1da177e4 LT |
316 | static void __hbird_write_stick(unsigned long val) |
317 | { | |
318 | unsigned long low = (val & 0xffffffffUL); | |
319 | unsigned long high = (val >> 32UL); | |
320 | unsigned long addr = HBIRD_STICK_ADDR; | |
321 | ||
322 | __asm__ __volatile__("stxa %%g0, [%0] %4\n\t" | |
323 | "add %0, 0x8, %0\n\t" | |
324 | "stxa %3, [%0] %4\n\t" | |
325 | "sub %0, 0x8, %0\n\t" | |
326 | "stxa %2, [%0] %4" | |
327 | : "=&r" (addr) | |
328 | : "0" (addr), "r" (low), "r" (high), | |
329 | "i" (ASI_PHYS_BYPASS_EC_E)); | |
330 | } | |
331 | ||
332 | static void __hbird_write_compare(unsigned long val) | |
333 | { | |
334 | unsigned long low = (val & 0xffffffffUL); | |
335 | unsigned long high = (val >> 32UL); | |
336 | unsigned long addr = HBIRD_STICKCMP_ADDR + 0x8UL; | |
337 | ||
338 | __asm__ __volatile__("stxa %3, [%0] %4\n\t" | |
339 | "sub %0, 0x8, %0\n\t" | |
340 | "stxa %2, [%0] %4" | |
341 | : "=&r" (addr) | |
342 | : "0" (addr), "r" (low), "r" (high), | |
343 | "i" (ASI_PHYS_BYPASS_EC_E)); | |
344 | } | |
345 | ||
112f4871 | 346 | static void hbtick_disable_irq(void) |
1da177e4 | 347 | { |
112f4871 DM |
348 | __hbird_write_compare(TICKCMP_IRQ_BIT); |
349 | } | |
1da177e4 | 350 | |
112f4871 DM |
351 | static void hbtick_init_tick(void) |
352 | { | |
1da177e4 LT |
353 | tick_disable_protection(); |
354 | ||
355 | /* XXX This seems to be necessary to 'jumpstart' Hummingbird | |
356 | * XXX into actually sending STICK interrupts. I think because | |
357 | * XXX of how we store %tick_cmpr in head.S this somehow resets the | |
358 | * XXX {TICK + STICK} interrupt mux. -DaveM | |
359 | */ | |
360 | __hbird_write_stick(__hbird_read_stick()); | |
361 | ||
112f4871 | 362 | hbtick_disable_irq(); |
1da177e4 LT |
363 | } |
364 | ||
365 | static unsigned long hbtick_get_tick(void) | |
366 | { | |
367 | return __hbird_read_stick() & ~TICK_PRIV_BIT; | |
368 | } | |
369 | ||
112f4871 | 370 | static unsigned long hbtick_add_tick(unsigned long adj) |
1da177e4 LT |
371 | { |
372 | unsigned long val; | |
373 | ||
374 | val = __hbird_read_stick() + adj; | |
375 | __hbird_write_stick(val); | |
376 | ||
1da177e4 LT |
377 | return val; |
378 | } | |
379 | ||
112f4871 | 380 | static int hbtick_add_compare(unsigned long adj) |
1da177e4 | 381 | { |
112f4871 DM |
382 | unsigned long val = __hbird_read_stick(); |
383 | unsigned long val2; | |
1da177e4 | 384 | |
112f4871 DM |
385 | val &= ~TICKCMP_IRQ_BIT; |
386 | val += adj; | |
1da177e4 LT |
387 | __hbird_write_compare(val); |
388 | ||
112f4871 DM |
389 | val2 = __hbird_read_stick() & ~TICKCMP_IRQ_BIT; |
390 | ||
391 | return ((long)(val2 - val)) > 0L; | |
1da177e4 LT |
392 | } |
393 | ||
d369ddd2 | 394 | static struct sparc64_tick_ops hbtick_operations __read_mostly = { |
112f4871 | 395 | .name = "hbtick", |
1da177e4 | 396 | .init_tick = hbtick_init_tick, |
112f4871 | 397 | .disable_irq = hbtick_disable_irq, |
1da177e4 | 398 | .get_tick = hbtick_get_tick, |
1da177e4 LT |
399 | .add_tick = hbtick_add_tick, |
400 | .add_compare = hbtick_add_compare, | |
401 | .softint_mask = 1UL << 0, | |
402 | }; | |
403 | ||
d369ddd2 | 404 | static unsigned long timer_ticks_per_nsec_quotient __read_mostly; |
1da177e4 LT |
405 | |
406 | #define TICK_SIZE (tick_nsec / 1000) | |
407 | ||
a58c9f3c DM |
408 | #define USEC_AFTER 500000 |
409 | #define USEC_BEFORE 500000 | |
410 | ||
411 | static void sync_cmos_clock(unsigned long dummy); | |
412 | ||
413 | static DEFINE_TIMER(sync_cmos_timer, sync_cmos_clock, 0, 0); | |
414 | ||
415 | static void sync_cmos_clock(unsigned long dummy) | |
1da177e4 | 416 | { |
a58c9f3c DM |
417 | struct timeval now, next; |
418 | int fail = 1; | |
419 | ||
420 | /* | |
421 | * If we have an externally synchronized Linux clock, then update | |
422 | * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be | |
423 | * called as close as possible to 500 ms before the new second starts. | |
424 | * This code is run on a timer. If the clock is set, that timer | |
425 | * may not expire at the correct time. Thus, we adjust... | |
426 | */ | |
427 | if (!ntp_synced()) | |
428 | /* | |
429 | * Not synced, exit, do not restart a timer (if one is | |
430 | * running, let it run out). | |
431 | */ | |
432 | return; | |
433 | ||
434 | do_gettimeofday(&now); | |
435 | if (now.tv_usec >= USEC_AFTER - ((unsigned) TICK_SIZE) / 2 && | |
436 | now.tv_usec <= USEC_BEFORE + ((unsigned) TICK_SIZE) / 2) | |
437 | fail = set_rtc_mmss(now.tv_sec); | |
438 | ||
439 | next.tv_usec = USEC_AFTER - now.tv_usec; | |
440 | if (next.tv_usec <= 0) | |
441 | next.tv_usec += USEC_PER_SEC; | |
442 | ||
443 | if (!fail) | |
444 | next.tv_sec = 659; | |
445 | else | |
446 | next.tv_sec = 0; | |
447 | ||
448 | if (next.tv_usec >= USEC_PER_SEC) { | |
449 | next.tv_sec++; | |
450 | next.tv_usec -= USEC_PER_SEC; | |
1da177e4 | 451 | } |
a58c9f3c DM |
452 | mod_timer(&sync_cmos_timer, jiffies + timeval_to_jiffies(&next)); |
453 | } | |
454 | ||
455 | void notify_arch_cmos_timer(void) | |
456 | { | |
457 | mod_timer(&sync_cmos_timer, jiffies + 1); | |
1da177e4 LT |
458 | } |
459 | ||
1da177e4 LT |
460 | /* Kick start a stopped clock (procedure from the Sun NVRAM/hostid FAQ). */ |
461 | static void __init kick_start_clock(void) | |
462 | { | |
ef0299bf | 463 | void __iomem *regs = mstk48t02_regs; |
1da177e4 LT |
464 | u8 sec, tmp; |
465 | int i, count; | |
466 | ||
467 | prom_printf("CLOCK: Clock was stopped. Kick start "); | |
468 | ||
469 | spin_lock_irq(&mostek_lock); | |
470 | ||
471 | /* Turn on the kick start bit to start the oscillator. */ | |
472 | tmp = mostek_read(regs + MOSTEK_CREG); | |
473 | tmp |= MSTK_CREG_WRITE; | |
474 | mostek_write(regs + MOSTEK_CREG, tmp); | |
475 | tmp = mostek_read(regs + MOSTEK_SEC); | |
476 | tmp &= ~MSTK_STOP; | |
477 | mostek_write(regs + MOSTEK_SEC, tmp); | |
478 | tmp = mostek_read(regs + MOSTEK_HOUR); | |
479 | tmp |= MSTK_KICK_START; | |
480 | mostek_write(regs + MOSTEK_HOUR, tmp); | |
481 | tmp = mostek_read(regs + MOSTEK_CREG); | |
482 | tmp &= ~MSTK_CREG_WRITE; | |
483 | mostek_write(regs + MOSTEK_CREG, tmp); | |
484 | ||
485 | spin_unlock_irq(&mostek_lock); | |
486 | ||
487 | /* Delay to allow the clock oscillator to start. */ | |
488 | sec = MSTK_REG_SEC(regs); | |
489 | for (i = 0; i < 3; i++) { | |
490 | while (sec == MSTK_REG_SEC(regs)) | |
491 | for (count = 0; count < 100000; count++) | |
492 | /* nothing */ ; | |
493 | prom_printf("."); | |
494 | sec = MSTK_REG_SEC(regs); | |
495 | } | |
496 | prom_printf("\n"); | |
497 | ||
498 | spin_lock_irq(&mostek_lock); | |
499 | ||
500 | /* Turn off kick start and set a "valid" time and date. */ | |
501 | tmp = mostek_read(regs + MOSTEK_CREG); | |
502 | tmp |= MSTK_CREG_WRITE; | |
503 | mostek_write(regs + MOSTEK_CREG, tmp); | |
504 | tmp = mostek_read(regs + MOSTEK_HOUR); | |
505 | tmp &= ~MSTK_KICK_START; | |
506 | mostek_write(regs + MOSTEK_HOUR, tmp); | |
507 | MSTK_SET_REG_SEC(regs,0); | |
508 | MSTK_SET_REG_MIN(regs,0); | |
509 | MSTK_SET_REG_HOUR(regs,0); | |
510 | MSTK_SET_REG_DOW(regs,5); | |
511 | MSTK_SET_REG_DOM(regs,1); | |
512 | MSTK_SET_REG_MONTH(regs,8); | |
513 | MSTK_SET_REG_YEAR(regs,1996 - MSTK_YEAR_ZERO); | |
514 | tmp = mostek_read(regs + MOSTEK_CREG); | |
515 | tmp &= ~MSTK_CREG_WRITE; | |
516 | mostek_write(regs + MOSTEK_CREG, tmp); | |
517 | ||
518 | spin_unlock_irq(&mostek_lock); | |
519 | ||
520 | /* Ensure the kick start bit is off. If it isn't, turn it off. */ | |
521 | while (mostek_read(regs + MOSTEK_HOUR) & MSTK_KICK_START) { | |
522 | prom_printf("CLOCK: Kick start still on!\n"); | |
523 | ||
524 | spin_lock_irq(&mostek_lock); | |
525 | ||
526 | tmp = mostek_read(regs + MOSTEK_CREG); | |
527 | tmp |= MSTK_CREG_WRITE; | |
528 | mostek_write(regs + MOSTEK_CREG, tmp); | |
529 | ||
530 | tmp = mostek_read(regs + MOSTEK_HOUR); | |
531 | tmp &= ~MSTK_KICK_START; | |
532 | mostek_write(regs + MOSTEK_HOUR, tmp); | |
533 | ||
534 | tmp = mostek_read(regs + MOSTEK_CREG); | |
535 | tmp &= ~MSTK_CREG_WRITE; | |
536 | mostek_write(regs + MOSTEK_CREG, tmp); | |
537 | ||
538 | spin_unlock_irq(&mostek_lock); | |
539 | } | |
540 | ||
541 | prom_printf("CLOCK: Kick start procedure successful.\n"); | |
542 | } | |
543 | ||
544 | /* Return nonzero if the clock chip battery is low. */ | |
545 | static int __init has_low_battery(void) | |
546 | { | |
ef0299bf | 547 | void __iomem *regs = mstk48t02_regs; |
1da177e4 LT |
548 | u8 data1, data2; |
549 | ||
550 | spin_lock_irq(&mostek_lock); | |
551 | ||
552 | data1 = mostek_read(regs + MOSTEK_EEPROM); /* Read some data. */ | |
553 | mostek_write(regs + MOSTEK_EEPROM, ~data1); /* Write back the complement. */ | |
554 | data2 = mostek_read(regs + MOSTEK_EEPROM); /* Read back the complement. */ | |
555 | mostek_write(regs + MOSTEK_EEPROM, data1); /* Restore original value. */ | |
556 | ||
557 | spin_unlock_irq(&mostek_lock); | |
558 | ||
559 | return (data1 == data2); /* Was the write blocked? */ | |
560 | } | |
561 | ||
562 | /* Probe for the real time clock chip. */ | |
563 | static void __init set_system_time(void) | |
564 | { | |
565 | unsigned int year, mon, day, hour, min, sec; | |
ef0299bf | 566 | void __iomem *mregs = mstk48t02_regs; |
1da177e4 LT |
567 | #ifdef CONFIG_PCI |
568 | unsigned long dregs = ds1287_regs; | |
d037e053 | 569 | void __iomem *bregs = bq4802_regs; |
1da177e4 LT |
570 | #else |
571 | unsigned long dregs = 0UL; | |
d037e053 | 572 | void __iomem *bregs = 0UL; |
1da177e4 LT |
573 | #endif |
574 | u8 tmp; | |
575 | ||
d037e053 | 576 | if (!mregs && !dregs && !bregs) { |
1da177e4 LT |
577 | prom_printf("Something wrong, clock regs not mapped yet.\n"); |
578 | prom_halt(); | |
579 | } | |
580 | ||
581 | if (mregs) { | |
582 | spin_lock_irq(&mostek_lock); | |
583 | ||
584 | /* Traditional Mostek chip. */ | |
585 | tmp = mostek_read(mregs + MOSTEK_CREG); | |
586 | tmp |= MSTK_CREG_READ; | |
587 | mostek_write(mregs + MOSTEK_CREG, tmp); | |
588 | ||
589 | sec = MSTK_REG_SEC(mregs); | |
590 | min = MSTK_REG_MIN(mregs); | |
591 | hour = MSTK_REG_HOUR(mregs); | |
592 | day = MSTK_REG_DOM(mregs); | |
593 | mon = MSTK_REG_MONTH(mregs); | |
594 | year = MSTK_CVT_YEAR( MSTK_REG_YEAR(mregs) ); | |
d037e053 DM |
595 | } else if (bregs) { |
596 | unsigned char val = readb(bregs + 0x0e); | |
597 | unsigned int century; | |
598 | ||
599 | /* BQ4802 RTC chip. */ | |
600 | ||
601 | writeb(val | 0x08, bregs + 0x0e); | |
602 | ||
603 | sec = readb(bregs + 0x00); | |
604 | min = readb(bregs + 0x02); | |
605 | hour = readb(bregs + 0x04); | |
606 | day = readb(bregs + 0x06); | |
607 | mon = readb(bregs + 0x09); | |
608 | year = readb(bregs + 0x0a); | |
609 | century = readb(bregs + 0x0f); | |
610 | ||
611 | writeb(val, bregs + 0x0e); | |
612 | ||
613 | BCD_TO_BIN(sec); | |
614 | BCD_TO_BIN(min); | |
615 | BCD_TO_BIN(hour); | |
616 | BCD_TO_BIN(day); | |
617 | BCD_TO_BIN(mon); | |
618 | BCD_TO_BIN(year); | |
619 | BCD_TO_BIN(century); | |
620 | ||
621 | year += (century * 100); | |
1da177e4 | 622 | } else { |
1da177e4 LT |
623 | /* Dallas 12887 RTC chip. */ |
624 | ||
1da177e4 LT |
625 | do { |
626 | sec = CMOS_READ(RTC_SECONDS); | |
627 | min = CMOS_READ(RTC_MINUTES); | |
628 | hour = CMOS_READ(RTC_HOURS); | |
629 | day = CMOS_READ(RTC_DAY_OF_MONTH); | |
630 | mon = CMOS_READ(RTC_MONTH); | |
631 | year = CMOS_READ(RTC_YEAR); | |
632 | } while (sec != CMOS_READ(RTC_SECONDS)); | |
3dedf53b | 633 | |
1da177e4 LT |
634 | if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { |
635 | BCD_TO_BIN(sec); | |
636 | BCD_TO_BIN(min); | |
637 | BCD_TO_BIN(hour); | |
638 | BCD_TO_BIN(day); | |
639 | BCD_TO_BIN(mon); | |
640 | BCD_TO_BIN(year); | |
641 | } | |
642 | if ((year += 1900) < 1970) | |
643 | year += 100; | |
644 | } | |
645 | ||
646 | xtime.tv_sec = mktime(year, mon, day, hour, min, sec); | |
647 | xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ); | |
648 | set_normalized_timespec(&wall_to_monotonic, | |
649 | -xtime.tv_sec, -xtime.tv_nsec); | |
650 | ||
651 | if (mregs) { | |
652 | tmp = mostek_read(mregs + MOSTEK_CREG); | |
653 | tmp &= ~MSTK_CREG_READ; | |
654 | mostek_write(mregs + MOSTEK_CREG, tmp); | |
655 | ||
656 | spin_unlock_irq(&mostek_lock); | |
657 | } | |
658 | } | |
659 | ||
4bdff414 DM |
660 | /* davem suggests we keep this within the 4M locked kernel image */ |
661 | static u32 starfire_get_time(void) | |
662 | { | |
663 | static char obp_gettod[32]; | |
664 | static u32 unix_tod; | |
665 | ||
666 | sprintf(obp_gettod, "h# %08x unix-gettod", | |
667 | (unsigned int) (long) &unix_tod); | |
668 | prom_feval(obp_gettod); | |
669 | ||
670 | return unix_tod; | |
671 | } | |
672 | ||
8ba706a9 DM |
673 | static int starfire_set_time(u32 val) |
674 | { | |
675 | /* Do nothing, time is set using the service processor | |
676 | * console on this platform. | |
677 | */ | |
678 | return 0; | |
679 | } | |
680 | ||
4bdff414 DM |
681 | static u32 hypervisor_get_time(void) |
682 | { | |
7db35f31 | 683 | unsigned long ret, time; |
4bdff414 DM |
684 | int retries = 10000; |
685 | ||
686 | retry: | |
7db35f31 DM |
687 | ret = sun4v_tod_get(&time); |
688 | if (ret == HV_EOK) | |
689 | return time; | |
690 | if (ret == HV_EWOULDBLOCK) { | |
4bdff414 DM |
691 | if (--retries > 0) { |
692 | udelay(100); | |
693 | goto retry; | |
694 | } | |
695 | printk(KERN_WARNING "SUN4V: tod_get() timed out.\n"); | |
696 | return 0; | |
697 | } | |
698 | printk(KERN_WARNING "SUN4V: tod_get() not supported.\n"); | |
699 | return 0; | |
700 | } | |
701 | ||
8ba706a9 DM |
702 | static int hypervisor_set_time(u32 secs) |
703 | { | |
7db35f31 | 704 | unsigned long ret; |
8ba706a9 DM |
705 | int retries = 10000; |
706 | ||
707 | retry: | |
7db35f31 DM |
708 | ret = sun4v_tod_set(secs); |
709 | if (ret == HV_EOK) | |
8ba706a9 | 710 | return 0; |
7db35f31 | 711 | if (ret == HV_EWOULDBLOCK) { |
8ba706a9 DM |
712 | if (--retries > 0) { |
713 | udelay(100); | |
714 | goto retry; | |
715 | } | |
716 | printk(KERN_WARNING "SUN4V: tod_set() timed out.\n"); | |
717 | return -EAGAIN; | |
718 | } | |
719 | printk(KERN_WARNING "SUN4V: tod_set() not supported.\n"); | |
720 | return -EOPNOTSUPP; | |
721 | } | |
722 | ||
6a23acf3 | 723 | static int __init clock_model_matches(const char *model) |
690c8fd3 DM |
724 | { |
725 | if (strcmp(model, "mk48t02") && | |
726 | strcmp(model, "mk48t08") && | |
727 | strcmp(model, "mk48t59") && | |
728 | strcmp(model, "m5819") && | |
729 | strcmp(model, "m5819p") && | |
730 | strcmp(model, "m5823") && | |
d037e053 DM |
731 | strcmp(model, "ds1287") && |
732 | strcmp(model, "bq4802")) | |
690c8fd3 DM |
733 | return 0; |
734 | ||
735 | return 1; | |
736 | } | |
737 | ||
ee5caf0e | 738 | static int __devinit clock_probe(struct of_device *op, const struct of_device_id *match) |
690c8fd3 | 739 | { |
ee5caf0e | 740 | struct device_node *dp = op->node; |
6a23acf3 | 741 | const char *model = of_get_property(dp, "model", NULL); |
d037e053 | 742 | const char *compat = of_get_property(dp, "compatible", NULL); |
ee5caf0e DM |
743 | unsigned long size, flags; |
744 | void __iomem *regs; | |
690c8fd3 | 745 | |
d037e053 DM |
746 | if (!model) |
747 | model = compat; | |
748 | ||
ee5caf0e DM |
749 | if (!model || !clock_model_matches(model)) |
750 | return -ENODEV; | |
690c8fd3 | 751 | |
91521485 DM |
752 | /* On an Enterprise system there can be multiple mostek clocks. |
753 | * We should only match the one that is on the central FHC bus. | |
754 | */ | |
c3a8b85f DM |
755 | if (!strcmp(dp->parent->name, "fhc") && |
756 | strcmp(dp->parent->parent->name, "central") != 0) | |
91521485 DM |
757 | return -ENODEV; |
758 | ||
ee5caf0e DM |
759 | size = (op->resource[0].end - op->resource[0].start) + 1; |
760 | regs = of_ioremap(&op->resource[0], 0, size, "clock"); | |
761 | if (!regs) | |
762 | return -ENOMEM; | |
690c8fd3 | 763 | |
7233589d | 764 | #ifdef CONFIG_PCI |
690c8fd3 DM |
765 | if (!strcmp(model, "ds1287") || |
766 | !strcmp(model, "m5819") || | |
767 | !strcmp(model, "m5819p") || | |
768 | !strcmp(model, "m5823")) { | |
ee5caf0e | 769 | ds1287_regs = (unsigned long) regs; |
d037e053 DM |
770 | } else if (!strcmp(model, "bq4802")) { |
771 | bq4802_regs = regs; | |
7233589d RD |
772 | } else |
773 | #endif | |
774 | if (model[5] == '0' && model[6] == '2') { | |
ee5caf0e DM |
775 | mstk48t02_regs = regs; |
776 | } else if(model[5] == '0' && model[6] == '8') { | |
777 | mstk48t08_regs = regs; | |
778 | mstk48t02_regs = mstk48t08_regs + MOSTEK_48T08_48T02; | |
690c8fd3 | 779 | } else { |
ee5caf0e | 780 | mstk48t59_regs = regs; |
690c8fd3 DM |
781 | mstk48t02_regs = mstk48t59_regs + MOSTEK_48T59_48T02; |
782 | } | |
690c8fd3 | 783 | |
ee5caf0e | 784 | printk(KERN_INFO "%s: Clock regs at %p\n", dp->full_name, regs); |
690c8fd3 | 785 | |
ee5caf0e | 786 | local_irq_save(flags); |
690c8fd3 | 787 | |
ee5caf0e DM |
788 | if (mstk48t02_regs != NULL) { |
789 | /* Report a low battery voltage condition. */ | |
790 | if (has_low_battery()) | |
791 | prom_printf("NVRAM: Low battery voltage!\n"); | |
690c8fd3 | 792 | |
ee5caf0e DM |
793 | /* Kick start the clock if it is completely stopped. */ |
794 | if (mostek_read(mstk48t02_regs + MOSTEK_SEC) & MSTK_STOP) | |
795 | kick_start_clock(); | |
690c8fd3 DM |
796 | } |
797 | ||
ee5caf0e DM |
798 | set_system_time(); |
799 | ||
800 | local_irq_restore(flags); | |
690c8fd3 DM |
801 | |
802 | return 0; | |
803 | } | |
690c8fd3 | 804 | |
ee5caf0e DM |
805 | static struct of_device_id clock_match[] = { |
806 | { | |
807 | .name = "eeprom", | |
808 | }, | |
809 | { | |
810 | .name = "rtc", | |
811 | }, | |
812 | {}, | |
813 | }; | |
690c8fd3 | 814 | |
ee5caf0e DM |
815 | static struct of_platform_driver clock_driver = { |
816 | .name = "clock", | |
817 | .match_table = clock_match, | |
818 | .probe = clock_probe, | |
819 | }; | |
690c8fd3 | 820 | |
ee5caf0e | 821 | static int __init clock_init(void) |
690c8fd3 | 822 | { |
1da177e4 | 823 | if (this_is_starfire) { |
4bdff414 DM |
824 | xtime.tv_sec = starfire_get_time(); |
825 | xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ); | |
826 | set_normalized_timespec(&wall_to_monotonic, | |
827 | -xtime.tv_sec, -xtime.tv_nsec); | |
ee5caf0e | 828 | return 0; |
4bdff414 DM |
829 | } |
830 | if (tlb_type == hypervisor) { | |
831 | xtime.tv_sec = hypervisor_get_time(); | |
1da177e4 LT |
832 | xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ); |
833 | set_normalized_timespec(&wall_to_monotonic, | |
834 | -xtime.tv_sec, -xtime.tv_nsec); | |
ee5caf0e | 835 | return 0; |
1da177e4 LT |
836 | } |
837 | ||
37b7754a | 838 | return of_register_driver(&clock_driver, &of_platform_bus_type); |
1da177e4 LT |
839 | } |
840 | ||
ee5caf0e DM |
841 | /* Must be after subsys_initcall() so that busses are probed. Must |
842 | * be before device_initcall() because things like the RTC driver | |
843 | * need to see the clock registers. | |
844 | */ | |
845 | fs_initcall(clock_init); | |
846 | ||
1da177e4 LT |
847 | /* This is gets the master TICK_INT timer going. */ |
848 | static unsigned long sparc64_init_timers(void) | |
849 | { | |
07f8e5f3 | 850 | struct device_node *dp; |
1da177e4 | 851 | unsigned long clock; |
1da177e4 | 852 | |
07f8e5f3 | 853 | dp = of_find_node_by_path("/"); |
1da177e4 LT |
854 | if (tlb_type == spitfire) { |
855 | unsigned long ver, manuf, impl; | |
856 | ||
857 | __asm__ __volatile__ ("rdpr %%ver, %0" | |
858 | : "=&r" (ver)); | |
859 | manuf = ((ver >> 48) & 0xffff); | |
860 | impl = ((ver >> 32) & 0xffff); | |
861 | if (manuf == 0x17 && impl == 0x13) { | |
862 | /* Hummingbird, aka Ultra-IIe */ | |
863 | tick_ops = &hbtick_operations; | |
5cbc3073 | 864 | clock = of_getintprop_default(dp, "stick-frequency", 0); |
1da177e4 LT |
865 | } else { |
866 | tick_ops = &tick_operations; | |
5cbc3073 | 867 | clock = local_cpu_data().clock_tick; |
1da177e4 LT |
868 | } |
869 | } else { | |
870 | tick_ops = &stick_operations; | |
5cbc3073 | 871 | clock = of_getintprop_default(dp, "stick-frequency", 0); |
1da177e4 | 872 | } |
1da177e4 | 873 | |
1da177e4 LT |
874 | return clock; |
875 | } | |
876 | ||
1da177e4 | 877 | struct freq_table { |
1da177e4 LT |
878 | unsigned long clock_tick_ref; |
879 | unsigned int ref_freq; | |
880 | }; | |
3763be32 | 881 | static DEFINE_PER_CPU(struct freq_table, sparc64_freq_table) = { 0, 0 }; |
1da177e4 LT |
882 | |
883 | unsigned long sparc64_get_clock_tick(unsigned int cpu) | |
884 | { | |
885 | struct freq_table *ft = &per_cpu(sparc64_freq_table, cpu); | |
886 | ||
887 | if (ft->clock_tick_ref) | |
888 | return ft->clock_tick_ref; | |
889 | return cpu_data(cpu).clock_tick; | |
890 | } | |
891 | ||
892 | #ifdef CONFIG_CPU_FREQ | |
893 | ||
894 | static int sparc64_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
895 | void *data) | |
896 | { | |
897 | struct cpufreq_freqs *freq = data; | |
898 | unsigned int cpu = freq->cpu; | |
899 | struct freq_table *ft = &per_cpu(sparc64_freq_table, cpu); | |
900 | ||
901 | if (!ft->ref_freq) { | |
902 | ft->ref_freq = freq->old; | |
1da177e4 LT |
903 | ft->clock_tick_ref = cpu_data(cpu).clock_tick; |
904 | } | |
905 | if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || | |
906 | (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) || | |
907 | (val == CPUFREQ_RESUMECHANGE)) { | |
1da177e4 LT |
908 | cpu_data(cpu).clock_tick = |
909 | cpufreq_scale(ft->clock_tick_ref, | |
910 | ft->ref_freq, | |
911 | freq->new); | |
912 | } | |
913 | ||
914 | return 0; | |
915 | } | |
916 | ||
917 | static struct notifier_block sparc64_cpufreq_notifier_block = { | |
918 | .notifier_call = sparc64_cpufreq_notifier | |
919 | }; | |
920 | ||
921 | #endif /* CONFIG_CPU_FREQ */ | |
922 | ||
112f4871 DM |
923 | static int sparc64_next_event(unsigned long delta, |
924 | struct clock_event_device *evt) | |
925 | { | |
d62c6f09 | 926 | return tick_ops->add_compare(delta) ? -ETIME : 0; |
112f4871 DM |
927 | } |
928 | ||
929 | static void sparc64_timer_setup(enum clock_event_mode mode, | |
930 | struct clock_event_device *evt) | |
931 | { | |
932 | switch (mode) { | |
933 | case CLOCK_EVT_MODE_ONESHOT: | |
934 | break; | |
935 | ||
936 | case CLOCK_EVT_MODE_SHUTDOWN: | |
937 | tick_ops->disable_irq(); | |
938 | break; | |
939 | ||
940 | case CLOCK_EVT_MODE_PERIODIC: | |
941 | case CLOCK_EVT_MODE_UNUSED: | |
942 | WARN_ON(1); | |
943 | break; | |
944 | }; | |
945 | } | |
946 | ||
947 | static struct clock_event_device sparc64_clockevent = { | |
948 | .features = CLOCK_EVT_FEAT_ONESHOT, | |
949 | .set_mode = sparc64_timer_setup, | |
950 | .set_next_event = sparc64_next_event, | |
951 | .rating = 100, | |
952 | .shift = 30, | |
953 | .irq = -1, | |
1da177e4 | 954 | }; |
112f4871 | 955 | static DEFINE_PER_CPU(struct clock_event_device, sparc64_events); |
1da177e4 | 956 | |
112f4871 | 957 | void timer_interrupt(int irq, struct pt_regs *regs) |
1da177e4 | 958 | { |
112f4871 DM |
959 | struct pt_regs *old_regs = set_irq_regs(regs); |
960 | unsigned long tick_mask = tick_ops->softint_mask; | |
961 | int cpu = smp_processor_id(); | |
962 | struct clock_event_device *evt = &per_cpu(sparc64_events, cpu); | |
963 | ||
964 | clear_softint(tick_mask); | |
965 | ||
966 | irq_enter(); | |
967 | ||
968 | kstat_this_cpu.irqs[0]++; | |
969 | ||
970 | if (unlikely(!evt->event_handler)) { | |
971 | printk(KERN_WARNING | |
972 | "Spurious SPARC64 timer interrupt on cpu %d\n", cpu); | |
973 | } else | |
974 | evt->event_handler(evt); | |
975 | ||
976 | irq_exit(); | |
977 | ||
978 | set_irq_regs(old_regs); | |
979 | } | |
1da177e4 | 980 | |
112f4871 DM |
981 | void __devinit setup_sparc64_timer(void) |
982 | { | |
983 | struct clock_event_device *sevt; | |
984 | unsigned long pstate; | |
1da177e4 | 985 | |
112f4871 DM |
986 | /* Guarantee that the following sequences execute |
987 | * uninterrupted. | |
1da177e4 | 988 | */ |
112f4871 DM |
989 | __asm__ __volatile__("rdpr %%pstate, %0\n\t" |
990 | "wrpr %0, %1, %%pstate" | |
991 | : "=r" (pstate) | |
992 | : "i" (PSTATE_IE)); | |
993 | ||
994 | tick_ops->init_tick(); | |
995 | ||
996 | /* Restore PSTATE_IE. */ | |
997 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
998 | : /* no outputs */ | |
999 | : "r" (pstate)); | |
1000 | ||
1001 | sevt = &__get_cpu_var(sparc64_events); | |
1002 | ||
1003 | memcpy(sevt, &sparc64_clockevent, sizeof(*sevt)); | |
1004 | sevt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
1005 | ||
1006 | clockevents_register_device(sevt); | |
1007 | } | |
1008 | ||
03983ab8 | 1009 | #define SPARC64_NSEC_PER_CYC_SHIFT 10UL |
112f4871 DM |
1010 | |
1011 | static struct clocksource clocksource_tick = { | |
1012 | .rating = 100, | |
1013 | .mask = CLOCKSOURCE_MASK(64), | |
1014 | .shift = 16, | |
1015 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
1016 | }; | |
1017 | ||
1018 | static void __init setup_clockevent_multiplier(unsigned long hz) | |
1019 | { | |
1020 | unsigned long mult, shift = 32; | |
1021 | ||
1022 | while (1) { | |
1023 | mult = div_sc(hz, NSEC_PER_SEC, shift); | |
1024 | if (mult && (mult >> 32UL) == 0UL) | |
1025 | break; | |
1026 | ||
1027 | shift--; | |
1028 | } | |
1029 | ||
1030 | sparc64_clockevent.shift = shift; | |
1031 | sparc64_clockevent.mult = mult; | |
1032 | } | |
1033 | ||
8b99cfb8 DM |
1034 | static unsigned long tb_ticks_per_usec __read_mostly; |
1035 | ||
1036 | void __delay(unsigned long loops) | |
1037 | { | |
1038 | unsigned long bclock, now; | |
1039 | ||
1040 | bclock = tick_ops->get_tick(); | |
1041 | do { | |
1042 | now = tick_ops->get_tick(); | |
1043 | } while ((now-bclock) < loops); | |
1044 | } | |
1045 | EXPORT_SYMBOL(__delay); | |
1046 | ||
1047 | void udelay(unsigned long usecs) | |
1048 | { | |
1049 | __delay(tb_ticks_per_usec * usecs); | |
1050 | } | |
1051 | EXPORT_SYMBOL(udelay); | |
1052 | ||
112f4871 DM |
1053 | void __init time_init(void) |
1054 | { | |
1055 | unsigned long clock = sparc64_init_timers(); | |
1da177e4 | 1056 | |
8b99cfb8 DM |
1057 | tb_ticks_per_usec = clock / USEC_PER_SEC; |
1058 | ||
1da177e4 | 1059 | timer_ticks_per_nsec_quotient = |
112f4871 DM |
1060 | clocksource_hz2mult(clock, SPARC64_NSEC_PER_CYC_SHIFT); |
1061 | ||
1062 | clocksource_tick.name = tick_ops->name; | |
1063 | clocksource_tick.mult = | |
1064 | clocksource_hz2mult(clock, | |
1065 | clocksource_tick.shift); | |
1066 | clocksource_tick.read = tick_ops->get_tick; | |
1067 | ||
1068 | printk("clocksource: mult[%x] shift[%d]\n", | |
1069 | clocksource_tick.mult, clocksource_tick.shift); | |
1070 | ||
1071 | clocksource_register(&clocksource_tick); | |
1072 | ||
1073 | sparc64_clockevent.name = tick_ops->name; | |
1074 | ||
1075 | setup_clockevent_multiplier(clock); | |
1076 | ||
1077 | sparc64_clockevent.max_delta_ns = | |
1078 | clockevent_delta2ns(0x7fffffffffffffff, &sparc64_clockevent); | |
1079 | sparc64_clockevent.min_delta_ns = | |
1080 | clockevent_delta2ns(0xF, &sparc64_clockevent); | |
1081 | ||
1082 | printk("clockevent: mult[%lx] shift[%d]\n", | |
1083 | sparc64_clockevent.mult, sparc64_clockevent.shift); | |
1084 | ||
1085 | setup_sparc64_timer(); | |
1da177e4 LT |
1086 | |
1087 | #ifdef CONFIG_CPU_FREQ | |
1088 | cpufreq_register_notifier(&sparc64_cpufreq_notifier_block, | |
1089 | CPUFREQ_TRANSITION_NOTIFIER); | |
1090 | #endif | |
1091 | } | |
1092 | ||
1093 | unsigned long long sched_clock(void) | |
1094 | { | |
1095 | unsigned long ticks = tick_ops->get_tick(); | |
1096 | ||
1097 | return (ticks * timer_ticks_per_nsec_quotient) | |
1098 | >> SPARC64_NSEC_PER_CYC_SHIFT; | |
1099 | } | |
1100 | ||
1101 | static int set_rtc_mmss(unsigned long nowtime) | |
1102 | { | |
1103 | int real_seconds, real_minutes, chip_minutes; | |
ef0299bf | 1104 | void __iomem *mregs = mstk48t02_regs; |
1da177e4 LT |
1105 | #ifdef CONFIG_PCI |
1106 | unsigned long dregs = ds1287_regs; | |
d037e053 | 1107 | void __iomem *bregs = bq4802_regs; |
1da177e4 LT |
1108 | #else |
1109 | unsigned long dregs = 0UL; | |
d037e053 | 1110 | void __iomem *bregs = 0UL; |
1da177e4 LT |
1111 | #endif |
1112 | unsigned long flags; | |
1113 | u8 tmp; | |
1114 | ||
1115 | /* | |
1116 | * Not having a register set can lead to trouble. | |
1117 | * Also starfire doesn't have a tod clock. | |
1118 | */ | |
d037e053 | 1119 | if (!mregs && !dregs & !bregs) |
1da177e4 LT |
1120 | return -1; |
1121 | ||
1122 | if (mregs) { | |
1123 | spin_lock_irqsave(&mostek_lock, flags); | |
1124 | ||
1125 | /* Read the current RTC minutes. */ | |
1126 | tmp = mostek_read(mregs + MOSTEK_CREG); | |
1127 | tmp |= MSTK_CREG_READ; | |
1128 | mostek_write(mregs + MOSTEK_CREG, tmp); | |
1129 | ||
1130 | chip_minutes = MSTK_REG_MIN(mregs); | |
1131 | ||
1132 | tmp = mostek_read(mregs + MOSTEK_CREG); | |
1133 | tmp &= ~MSTK_CREG_READ; | |
1134 | mostek_write(mregs + MOSTEK_CREG, tmp); | |
1135 | ||
1136 | /* | |
1137 | * since we're only adjusting minutes and seconds, | |
1138 | * don't interfere with hour overflow. This avoids | |
1139 | * messing with unknown time zones but requires your | |
1140 | * RTC not to be off by more than 15 minutes | |
1141 | */ | |
1142 | real_seconds = nowtime % 60; | |
1143 | real_minutes = nowtime / 60; | |
1144 | if (((abs(real_minutes - chip_minutes) + 15)/30) & 1) | |
1145 | real_minutes += 30; /* correct for half hour time zone */ | |
1146 | real_minutes %= 60; | |
1147 | ||
1148 | if (abs(real_minutes - chip_minutes) < 30) { | |
1149 | tmp = mostek_read(mregs + MOSTEK_CREG); | |
1150 | tmp |= MSTK_CREG_WRITE; | |
1151 | mostek_write(mregs + MOSTEK_CREG, tmp); | |
1152 | ||
1153 | MSTK_SET_REG_SEC(mregs,real_seconds); | |
1154 | MSTK_SET_REG_MIN(mregs,real_minutes); | |
1155 | ||
1156 | tmp = mostek_read(mregs + MOSTEK_CREG); | |
1157 | tmp &= ~MSTK_CREG_WRITE; | |
1158 | mostek_write(mregs + MOSTEK_CREG, tmp); | |
1159 | ||
1160 | spin_unlock_irqrestore(&mostek_lock, flags); | |
1161 | ||
1162 | return 0; | |
1163 | } else { | |
1164 | spin_unlock_irqrestore(&mostek_lock, flags); | |
1165 | ||
1166 | return -1; | |
1167 | } | |
d037e053 DM |
1168 | } else if (bregs) { |
1169 | int retval = 0; | |
1170 | unsigned char val = readb(bregs + 0x0e); | |
1171 | ||
1172 | /* BQ4802 RTC chip. */ | |
1173 | ||
1174 | writeb(val | 0x08, bregs + 0x0e); | |
1175 | ||
1176 | chip_minutes = readb(bregs + 0x02); | |
1177 | BCD_TO_BIN(chip_minutes); | |
1178 | real_seconds = nowtime % 60; | |
1179 | real_minutes = nowtime / 60; | |
1180 | if (((abs(real_minutes - chip_minutes) + 15)/30) & 1) | |
1181 | real_minutes += 30; | |
1182 | real_minutes %= 60; | |
1183 | ||
1184 | if (abs(real_minutes - chip_minutes) < 30) { | |
1185 | BIN_TO_BCD(real_seconds); | |
1186 | BIN_TO_BCD(real_minutes); | |
1187 | writeb(real_seconds, bregs + 0x00); | |
1188 | writeb(real_minutes, bregs + 0x02); | |
1189 | } else { | |
1190 | printk(KERN_WARNING | |
1191 | "set_rtc_mmss: can't update from %d to %d\n", | |
1192 | chip_minutes, real_minutes); | |
1193 | retval = -1; | |
1194 | } | |
1195 | ||
1196 | writeb(val, bregs + 0x0e); | |
1197 | ||
1198 | return retval; | |
1da177e4 LT |
1199 | } else { |
1200 | int retval = 0; | |
1201 | unsigned char save_control, save_freq_select; | |
1202 | ||
1203 | /* Stolen from arch/i386/kernel/time.c, see there for | |
1204 | * credits and descriptive comments. | |
1205 | */ | |
1206 | spin_lock_irqsave(&rtc_lock, flags); | |
1207 | save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */ | |
1208 | CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL); | |
1209 | ||
1210 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */ | |
1211 | CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT); | |
1212 | ||
1213 | chip_minutes = CMOS_READ(RTC_MINUTES); | |
1214 | if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) | |
1215 | BCD_TO_BIN(chip_minutes); | |
1216 | real_seconds = nowtime % 60; | |
1217 | real_minutes = nowtime / 60; | |
1218 | if (((abs(real_minutes - chip_minutes) + 15)/30) & 1) | |
1219 | real_minutes += 30; | |
1220 | real_minutes %= 60; | |
1221 | ||
1222 | if (abs(real_minutes - chip_minutes) < 30) { | |
1223 | if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { | |
1224 | BIN_TO_BCD(real_seconds); | |
1225 | BIN_TO_BCD(real_minutes); | |
1226 | } | |
1227 | CMOS_WRITE(real_seconds,RTC_SECONDS); | |
1228 | CMOS_WRITE(real_minutes,RTC_MINUTES); | |
1229 | } else { | |
1230 | printk(KERN_WARNING | |
1231 | "set_rtc_mmss: can't update from %d to %d\n", | |
1232 | chip_minutes, real_minutes); | |
1233 | retval = -1; | |
1234 | } | |
1235 | ||
1236 | CMOS_WRITE(save_control, RTC_CONTROL); | |
1237 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
1238 | spin_unlock_irqrestore(&rtc_lock, flags); | |
1239 | ||
1240 | return retval; | |
1241 | } | |
1242 | } | |
8ba706a9 DM |
1243 | |
1244 | #define RTC_IS_OPEN 0x01 /* means /dev/rtc is in use */ | |
1245 | static unsigned char mini_rtc_status; /* bitmapped status byte. */ | |
1246 | ||
8ba706a9 DM |
1247 | #define FEBRUARY 2 |
1248 | #define STARTOFTIME 1970 | |
1249 | #define SECDAY 86400L | |
1250 | #define SECYR (SECDAY * 365) | |
1251 | #define leapyear(year) ((year) % 4 == 0 && \ | |
1252 | ((year) % 100 != 0 || (year) % 400 == 0)) | |
1253 | #define days_in_year(a) (leapyear(a) ? 366 : 365) | |
1254 | #define days_in_month(a) (month_days[(a) - 1]) | |
1255 | ||
1256 | static int month_days[12] = { | |
1257 | 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 | |
1258 | }; | |
1259 | ||
1260 | /* | |
1261 | * This only works for the Gregorian calendar - i.e. after 1752 (in the UK) | |
1262 | */ | |
1263 | static void GregorianDay(struct rtc_time * tm) | |
1264 | { | |
1265 | int leapsToDate; | |
1266 | int lastYear; | |
1267 | int day; | |
1268 | int MonthOffset[] = { 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334 }; | |
1269 | ||
1270 | lastYear = tm->tm_year - 1; | |
1271 | ||
1272 | /* | |
1273 | * Number of leap corrections to apply up to end of last year | |
1274 | */ | |
1275 | leapsToDate = lastYear / 4 - lastYear / 100 + lastYear / 400; | |
1276 | ||
1277 | /* | |
1278 | * This year is a leap year if it is divisible by 4 except when it is | |
1279 | * divisible by 100 unless it is divisible by 400 | |
1280 | * | |
1281 | * e.g. 1904 was a leap year, 1900 was not, 1996 is, and 2000 was | |
1282 | */ | |
1283 | day = tm->tm_mon > 2 && leapyear(tm->tm_year); | |
1284 | ||
1285 | day += lastYear*365 + leapsToDate + MonthOffset[tm->tm_mon-1] + | |
1286 | tm->tm_mday; | |
1287 | ||
1288 | tm->tm_wday = day % 7; | |
1289 | } | |
1290 | ||
1291 | static void to_tm(int tim, struct rtc_time *tm) | |
1292 | { | |
1293 | register int i; | |
1294 | register long hms, day; | |
1295 | ||
1296 | day = tim / SECDAY; | |
1297 | hms = tim % SECDAY; | |
1298 | ||
1299 | /* Hours, minutes, seconds are easy */ | |
1300 | tm->tm_hour = hms / 3600; | |
1301 | tm->tm_min = (hms % 3600) / 60; | |
1302 | tm->tm_sec = (hms % 3600) % 60; | |
1303 | ||
1304 | /* Number of years in days */ | |
1305 | for (i = STARTOFTIME; day >= days_in_year(i); i++) | |
1306 | day -= days_in_year(i); | |
1307 | tm->tm_year = i; | |
1308 | ||
1309 | /* Number of months in days left */ | |
1310 | if (leapyear(tm->tm_year)) | |
1311 | days_in_month(FEBRUARY) = 29; | |
1312 | for (i = 1; day >= days_in_month(i); i++) | |
1313 | day -= days_in_month(i); | |
1314 | days_in_month(FEBRUARY) = 28; | |
1315 | tm->tm_mon = i; | |
1316 | ||
1317 | /* Days are what is left over (+1) from all that. */ | |
1318 | tm->tm_mday = day + 1; | |
1319 | ||
1320 | /* | |
1321 | * Determine the day of week | |
1322 | */ | |
1323 | GregorianDay(tm); | |
1324 | } | |
1325 | ||
1326 | /* Both Starfire and SUN4V give us seconds since Jan 1st, 1970, | |
1327 | * aka Unix time. So we have to convert to/from rtc_time. | |
1328 | */ | |
d037e053 | 1329 | static void starfire_get_rtc_time(struct rtc_time *time) |
8ba706a9 | 1330 | { |
d037e053 | 1331 | u32 seconds = starfire_get_time(); |
8ba706a9 | 1332 | |
d037e053 DM |
1333 | to_tm(seconds, time); |
1334 | time->tm_year -= 1900; | |
1335 | time->tm_mon -= 1; | |
1336 | } | |
1337 | ||
1338 | static int starfire_set_rtc_time(struct rtc_time *time) | |
1339 | { | |
1340 | u32 seconds = mktime(time->tm_year + 1900, time->tm_mon + 1, | |
1341 | time->tm_mday, time->tm_hour, | |
1342 | time->tm_min, time->tm_sec); | |
1343 | ||
1344 | return starfire_set_time(seconds); | |
1345 | } | |
1346 | ||
1347 | static void hypervisor_get_rtc_time(struct rtc_time *time) | |
1348 | { | |
1349 | u32 seconds = hypervisor_get_time(); | |
8ba706a9 DM |
1350 | |
1351 | to_tm(seconds, time); | |
c4f8ef77 DM |
1352 | time->tm_year -= 1900; |
1353 | time->tm_mon -= 1; | |
8ba706a9 DM |
1354 | } |
1355 | ||
d037e053 | 1356 | static int hypervisor_set_rtc_time(struct rtc_time *time) |
8ba706a9 DM |
1357 | { |
1358 | u32 seconds = mktime(time->tm_year + 1900, time->tm_mon + 1, | |
1359 | time->tm_mday, time->tm_hour, | |
1360 | time->tm_min, time->tm_sec); | |
d037e053 DM |
1361 | |
1362 | return hypervisor_set_time(seconds); | |
1363 | } | |
1364 | ||
7189859f | 1365 | #ifdef CONFIG_PCI |
d037e053 DM |
1366 | static void bq4802_get_rtc_time(struct rtc_time *time) |
1367 | { | |
1368 | unsigned char val = readb(bq4802_regs + 0x0e); | |
1369 | unsigned int century; | |
1370 | ||
1371 | writeb(val | 0x08, bq4802_regs + 0x0e); | |
1372 | ||
1373 | time->tm_sec = readb(bq4802_regs + 0x00); | |
1374 | time->tm_min = readb(bq4802_regs + 0x02); | |
1375 | time->tm_hour = readb(bq4802_regs + 0x04); | |
1376 | time->tm_mday = readb(bq4802_regs + 0x06); | |
1377 | time->tm_mon = readb(bq4802_regs + 0x09); | |
1378 | time->tm_year = readb(bq4802_regs + 0x0a); | |
1379 | time->tm_wday = readb(bq4802_regs + 0x08); | |
1380 | century = readb(bq4802_regs + 0x0f); | |
1381 | ||
1382 | writeb(val, bq4802_regs + 0x0e); | |
1383 | ||
1384 | BCD_TO_BIN(time->tm_sec); | |
1385 | BCD_TO_BIN(time->tm_min); | |
1386 | BCD_TO_BIN(time->tm_hour); | |
1387 | BCD_TO_BIN(time->tm_mday); | |
1388 | BCD_TO_BIN(time->tm_mon); | |
1389 | BCD_TO_BIN(time->tm_year); | |
1390 | BCD_TO_BIN(time->tm_wday); | |
1391 | BCD_TO_BIN(century); | |
1392 | ||
1393 | time->tm_year += (century * 100); | |
1394 | time->tm_year -= 1900; | |
1395 | ||
1396 | time->tm_mon--; | |
1397 | } | |
1398 | ||
1399 | static int bq4802_set_rtc_time(struct rtc_time *time) | |
1400 | { | |
1401 | unsigned char val = readb(bq4802_regs + 0x0e); | |
1402 | unsigned char sec, min, hrs, day, mon, yrs, century; | |
1403 | unsigned int year; | |
1404 | ||
1405 | year = time->tm_year + 1900; | |
1406 | century = year / 100; | |
1407 | yrs = year % 100; | |
1408 | ||
1409 | mon = time->tm_mon + 1; /* tm_mon starts at zero */ | |
1410 | day = time->tm_mday; | |
1411 | hrs = time->tm_hour; | |
1412 | min = time->tm_min; | |
1413 | sec = time->tm_sec; | |
1414 | ||
1415 | BIN_TO_BCD(sec); | |
1416 | BIN_TO_BCD(min); | |
1417 | BIN_TO_BCD(hrs); | |
1418 | BIN_TO_BCD(day); | |
1419 | BIN_TO_BCD(mon); | |
1420 | BIN_TO_BCD(yrs); | |
1421 | BIN_TO_BCD(century); | |
1422 | ||
1423 | writeb(val | 0x08, bq4802_regs + 0x0e); | |
1424 | ||
1425 | writeb(sec, bq4802_regs + 0x00); | |
1426 | writeb(min, bq4802_regs + 0x02); | |
1427 | writeb(hrs, bq4802_regs + 0x04); | |
1428 | writeb(day, bq4802_regs + 0x06); | |
1429 | writeb(mon, bq4802_regs + 0x09); | |
1430 | writeb(yrs, bq4802_regs + 0x0a); | |
1431 | writeb(century, bq4802_regs + 0x0f); | |
1432 | ||
1433 | writeb(val, bq4802_regs + 0x0e); | |
1434 | ||
1435 | return 0; | |
1436 | } | |
7189859f | 1437 | #endif /* CONFIG_PCI */ |
d037e053 DM |
1438 | |
1439 | struct mini_rtc_ops { | |
1440 | void (*get_rtc_time)(struct rtc_time *); | |
1441 | int (*set_rtc_time)(struct rtc_time *); | |
1442 | }; | |
1443 | ||
1444 | static struct mini_rtc_ops starfire_rtc_ops = { | |
1445 | .get_rtc_time = starfire_get_rtc_time, | |
1446 | .set_rtc_time = starfire_set_rtc_time, | |
1447 | }; | |
1448 | ||
1449 | static struct mini_rtc_ops hypervisor_rtc_ops = { | |
1450 | .get_rtc_time = hypervisor_get_rtc_time, | |
1451 | .set_rtc_time = hypervisor_set_rtc_time, | |
1452 | }; | |
1453 | ||
7189859f | 1454 | #ifdef CONFIG_PCI |
d037e053 DM |
1455 | static struct mini_rtc_ops bq4802_rtc_ops = { |
1456 | .get_rtc_time = bq4802_get_rtc_time, | |
1457 | .set_rtc_time = bq4802_set_rtc_time, | |
1458 | }; | |
7189859f | 1459 | #endif /* CONFIG_PCI */ |
d037e053 DM |
1460 | |
1461 | static struct mini_rtc_ops *mini_rtc_ops; | |
1462 | ||
1463 | static inline void mini_get_rtc_time(struct rtc_time *time) | |
1464 | { | |
1465 | unsigned long flags; | |
1466 | ||
1467 | spin_lock_irqsave(&rtc_lock, flags); | |
1468 | mini_rtc_ops->get_rtc_time(time); | |
1469 | spin_unlock_irqrestore(&rtc_lock, flags); | |
1470 | } | |
1471 | ||
1472 | static inline int mini_set_rtc_time(struct rtc_time *time) | |
1473 | { | |
8ba706a9 DM |
1474 | unsigned long flags; |
1475 | int err; | |
1476 | ||
1477 | spin_lock_irqsave(&rtc_lock, flags); | |
d037e053 | 1478 | err = mini_rtc_ops->set_rtc_time(time); |
8ba706a9 DM |
1479 | spin_unlock_irqrestore(&rtc_lock, flags); |
1480 | ||
1481 | return err; | |
1482 | } | |
1483 | ||
1484 | static int mini_rtc_ioctl(struct inode *inode, struct file *file, | |
1485 | unsigned int cmd, unsigned long arg) | |
1486 | { | |
1487 | struct rtc_time wtime; | |
1488 | void __user *argp = (void __user *)arg; | |
1489 | ||
1490 | switch (cmd) { | |
1491 | ||
1492 | case RTC_PLL_GET: | |
1493 | return -EINVAL; | |
1494 | ||
1495 | case RTC_PLL_SET: | |
1496 | return -EINVAL; | |
1497 | ||
1498 | case RTC_UIE_OFF: /* disable ints from RTC updates. */ | |
1499 | return 0; | |
1500 | ||
1501 | case RTC_UIE_ON: /* enable ints for RTC updates. */ | |
1502 | return -EINVAL; | |
1503 | ||
1504 | case RTC_RD_TIME: /* Read the time/date from RTC */ | |
1505 | /* this doesn't get week-day, who cares */ | |
1506 | memset(&wtime, 0, sizeof(wtime)); | |
1507 | mini_get_rtc_time(&wtime); | |
1508 | ||
1509 | return copy_to_user(argp, &wtime, sizeof(wtime)) ? -EFAULT : 0; | |
1510 | ||
1511 | case RTC_SET_TIME: /* Set the RTC */ | |
1512 | { | |
644923d4 | 1513 | int year, days; |
8ba706a9 DM |
1514 | |
1515 | if (!capable(CAP_SYS_TIME)) | |
1516 | return -EACCES; | |
1517 | ||
1518 | if (copy_from_user(&wtime, argp, sizeof(wtime))) | |
1519 | return -EFAULT; | |
1520 | ||
1521 | year = wtime.tm_year + 1900; | |
644923d4 TB |
1522 | days = month_days[wtime.tm_mon] + |
1523 | ((wtime.tm_mon == 1) && leapyear(year)); | |
8ba706a9 | 1524 | |
644923d4 TB |
1525 | if ((wtime.tm_mon < 0 || wtime.tm_mon > 11) || |
1526 | (wtime.tm_mday < 1)) | |
8ba706a9 DM |
1527 | return -EINVAL; |
1528 | ||
644923d4 | 1529 | if (wtime.tm_mday < 0 || wtime.tm_mday > days) |
8ba706a9 DM |
1530 | return -EINVAL; |
1531 | ||
1532 | if (wtime.tm_hour < 0 || wtime.tm_hour >= 24 || | |
1533 | wtime.tm_min < 0 || wtime.tm_min >= 60 || | |
1534 | wtime.tm_sec < 0 || wtime.tm_sec >= 60) | |
1535 | return -EINVAL; | |
1536 | ||
1537 | return mini_set_rtc_time(&wtime); | |
1538 | } | |
1539 | } | |
1540 | ||
1541 | return -EINVAL; | |
1542 | } | |
1543 | ||
1544 | static int mini_rtc_open(struct inode *inode, struct file *file) | |
1545 | { | |
1546 | if (mini_rtc_status & RTC_IS_OPEN) | |
1547 | return -EBUSY; | |
1548 | ||
1549 | mini_rtc_status |= RTC_IS_OPEN; | |
1550 | ||
1551 | return 0; | |
1552 | } | |
1553 | ||
1554 | static int mini_rtc_release(struct inode *inode, struct file *file) | |
1555 | { | |
1556 | mini_rtc_status &= ~RTC_IS_OPEN; | |
1557 | return 0; | |
1558 | } | |
1559 | ||
1560 | ||
5dfe4c96 | 1561 | static const struct file_operations mini_rtc_fops = { |
8ba706a9 DM |
1562 | .owner = THIS_MODULE, |
1563 | .ioctl = mini_rtc_ioctl, | |
1564 | .open = mini_rtc_open, | |
1565 | .release = mini_rtc_release, | |
1566 | }; | |
1567 | ||
1568 | static struct miscdevice rtc_mini_dev = | |
1569 | { | |
1570 | .minor = RTC_MINOR, | |
1571 | .name = "rtc", | |
1572 | .fops = &mini_rtc_fops, | |
1573 | }; | |
1574 | ||
1575 | static int __init rtc_mini_init(void) | |
1576 | { | |
1577 | int retval; | |
1578 | ||
d037e053 DM |
1579 | if (tlb_type == hypervisor) |
1580 | mini_rtc_ops = &hypervisor_rtc_ops; | |
1581 | else if (this_is_starfire) | |
1582 | mini_rtc_ops = &starfire_rtc_ops; | |
7189859f | 1583 | #ifdef CONFIG_PCI |
d037e053 DM |
1584 | else if (bq4802_regs) |
1585 | mini_rtc_ops = &bq4802_rtc_ops; | |
7189859f | 1586 | #endif /* CONFIG_PCI */ |
d037e053 | 1587 | else |
8ba706a9 DM |
1588 | return -ENODEV; |
1589 | ||
1590 | printk(KERN_INFO "Mini RTC Driver\n"); | |
1591 | ||
1592 | retval = misc_register(&rtc_mini_dev); | |
1593 | if (retval < 0) | |
1594 | return retval; | |
1595 | ||
1596 | return 0; | |
1597 | } | |
1598 | ||
1599 | static void __exit rtc_mini_exit(void) | |
1600 | { | |
1601 | misc_deregister(&rtc_mini_dev); | |
1602 | } | |
1603 | ||
1604 | ||
1605 | module_init(rtc_mini_init); | |
1606 | module_exit(rtc_mini_exit); |